1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright 2021 Google LLC. 4 * 5 * Driver for Semtech's SX9324 capacitive proximity/button solution. 6 * Based on SX9324 driver and copy of datasheet at: 7 * https://edit.wpgdadawant.com/uploads/news_file/program/2019/30184/tech_files/program_30184_suggest_other_file.pdf 8 */ 9 10#include <linux/acpi.h> 11#include <linux/bits.h> 12#include <linux/bitfield.h> 13#include <linux/delay.h> 14#include <linux/i2c.h> 15#include <linux/interrupt.h> 16#include <linux/kernel.h> 17#include <linux/log2.h> 18#include <linux/mod_devicetable.h> 19#include <linux/module.h> 20#include <linux/pm.h> 21#include <linux/property.h> 22#include <linux/regmap.h> 23 24#include <linux/iio/iio.h> 25 26#include "sx_common.h" 27 28/* Register definitions. */ 29#define SX9324_REG_IRQ_SRC SX_COMMON_REG_IRQ_SRC 30#define SX9324_REG_STAT0 0x01 31#define SX9324_REG_STAT1 0x02 32#define SX9324_REG_STAT2 0x03 33#define SX9324_REG_STAT2_COMPSTAT_MASK GENMASK(3, 0) 34#define SX9324_REG_STAT3 0x04 35#define SX9324_REG_IRQ_MSK 0x05 36#define SX9324_CONVDONE_IRQ BIT(3) 37#define SX9324_FAR_IRQ BIT(5) 38#define SX9324_CLOSE_IRQ BIT(6) 39#define SX9324_REG_IRQ_CFG0 0x06 40#define SX9324_REG_IRQ_CFG1 0x07 41#define SX9324_REG_IRQ_CFG1_FAILCOND 0x80 42#define SX9324_REG_IRQ_CFG2 0x08 43 44#define SX9324_REG_GNRL_CTRL0 0x10 45#define SX9324_REG_GNRL_CTRL0_SCANPERIOD_MASK GENMASK(4, 0) 46#define SX9324_REG_GNRL_CTRL0_SCANPERIOD_100MS 0x16 47#define SX9324_REG_GNRL_CTRL1 0x11 48#define SX9324_REG_GNRL_CTRL1_PHEN_MASK GENMASK(3, 0) 49#define SX9324_REG_GNRL_CTRL1_PAUSECTRL 0x20 50 51#define SX9324_REG_I2C_ADDR 0x14 52#define SX9324_REG_CLK_SPRD 0x15 53 54#define SX9324_REG_AFE_CTRL0 0x20 55#define SX9324_REG_AFE_CTRL0_RINT_SHIFT 6 56#define SX9324_REG_AFE_CTRL0_RINT_MASK \ 57 GENMASK(SX9324_REG_AFE_CTRL0_RINT_SHIFT + 1, \ 58 SX9324_REG_AFE_CTRL0_RINT_SHIFT) 59#define SX9324_REG_AFE_CTRL0_RINT_LOWEST 0x00 60#define SX9324_REG_AFE_CTRL0_CSIDLE_SHIFT 4 61#define SX9324_REG_AFE_CTRL0_CSIDLE_MASK \ 62 GENMASK(SX9324_REG_AFE_CTRL0_CSIDLE_SHIFT + 1, \ 63 SX9324_REG_AFE_CTRL0_CSIDLE_SHIFT) 64#define SX9324_REG_AFE_CTRL0_RINT_LOWEST 0x00 65#define SX9324_REG_AFE_CTRL1 0x21 66#define SX9324_REG_AFE_CTRL2 0x22 67#define SX9324_REG_AFE_CTRL3 0x23 68#define SX9324_REG_AFE_CTRL4 0x24 69#define SX9324_REG_AFE_CTRL4_FREQ_83_33HZ 0x40 70#define SX9324_REG_AFE_CTRL4_RESOLUTION_MASK GENMASK(2, 0) 71#define SX9324_REG_AFE_CTRL4_RES_100 0x04 72#define SX9324_REG_AFE_CTRL5 0x25 73#define SX9324_REG_AFE_CTRL6 0x26 74#define SX9324_REG_AFE_CTRL7 0x27 75#define SX9324_REG_AFE_PH0 0x28 76#define SX9324_REG_AFE_PH0_PIN_MASK(_pin) \ 77 GENMASK(2 * (_pin) + 1, 2 * (_pin)) 78 79#define SX9324_REG_AFE_PH1 0x29 80#define SX9324_REG_AFE_PH2 0x2a 81#define SX9324_REG_AFE_PH3 0x2b 82#define SX9324_REG_AFE_CTRL8 0x2c 83#define SX9324_REG_AFE_CTRL8_RESERVED 0x10 84#define SX9324_REG_AFE_CTRL8_RESFILTIN_4KOHM 0x02 85#define SX9324_REG_AFE_CTRL8_RESFILTIN_MASK GENMASK(3, 0) 86#define SX9324_REG_AFE_CTRL9 0x2d 87#define SX9324_REG_AFE_CTRL9_AGAIN_MASK GENMASK(3, 0) 88#define SX9324_REG_AFE_CTRL9_AGAIN_1 0x08 89 90#define SX9324_REG_PROX_CTRL0 0x30 91#define SX9324_REG_PROX_CTRL0_GAIN_MASK GENMASK(5, 3) 92#define SX9324_REG_PROX_CTRL0_GAIN_SHIFT 3 93#define SX9324_REG_PROX_CTRL0_GAIN_RSVD 0x0 94#define SX9324_REG_PROX_CTRL0_GAIN_1 0x1 95#define SX9324_REG_PROX_CTRL0_GAIN_8 0x4 96#define SX9324_REG_PROX_CTRL0_RAWFILT_MASK GENMASK(2, 0) 97#define SX9324_REG_PROX_CTRL0_RAWFILT_1P50 0x01 98#define SX9324_REG_PROX_CTRL1 0x31 99#define SX9324_REG_PROX_CTRL2 0x32 100#define SX9324_REG_PROX_CTRL2_AVGNEG_THRESH_16K 0x20 101#define SX9324_REG_PROX_CTRL3 0x33 102#define SX9324_REG_PROX_CTRL3_AVGDEB_2SAMPLES 0x40 103#define SX9324_REG_PROX_CTRL3_AVGPOS_THRESH_16K 0x20 104#define SX9324_REG_PROX_CTRL4 0x34 105#define SX9324_REG_PROX_CTRL4_AVGNEGFILT_MASK GENMASK(5, 3) 106#define SX9324_REG_PROX_CTRL4_AVGNEG_FILT_2 0x08 107#define SX9324_REG_PROX_CTRL4_AVGPOSFILT_MASK GENMASK(2, 0) 108#define SX9324_REG_PROX_CTRL4_AVGPOS_FILT_256 0x04 109#define SX9324_REG_PROX_CTRL5 0x35 110#define SX9324_REG_PROX_CTRL5_HYST_MASK GENMASK(5, 4) 111#define SX9324_REG_PROX_CTRL5_CLOSE_DEBOUNCE_MASK GENMASK(3, 2) 112#define SX9324_REG_PROX_CTRL5_FAR_DEBOUNCE_MASK GENMASK(1, 0) 113#define SX9324_REG_PROX_CTRL6 0x36 114#define SX9324_REG_PROX_CTRL6_PROXTHRESH_32 0x08 115#define SX9324_REG_PROX_CTRL7 0x37 116 117#define SX9324_REG_ADV_CTRL0 0x40 118#define SX9324_REG_ADV_CTRL1 0x41 119#define SX9324_REG_ADV_CTRL2 0x42 120#define SX9324_REG_ADV_CTRL3 0x43 121#define SX9324_REG_ADV_CTRL4 0x44 122#define SX9324_REG_ADV_CTRL5 0x45 123#define SX9324_REG_ADV_CTRL5_STARTUPSENS_MASK GENMASK(3, 2) 124#define SX9324_REG_ADV_CTRL5_STARTUP_SENSOR_1 0x04 125#define SX9324_REG_ADV_CTRL5_STARTUP_METHOD_1 0x01 126#define SX9324_REG_ADV_CTRL6 0x46 127#define SX9324_REG_ADV_CTRL7 0x47 128#define SX9324_REG_ADV_CTRL8 0x48 129#define SX9324_REG_ADV_CTRL9 0x49 130#define SX9324_REG_ADV_CTRL10 0x4a 131#define SX9324_REG_ADV_CTRL11 0x4b 132#define SX9324_REG_ADV_CTRL12 0x4c 133#define SX9324_REG_ADV_CTRL13 0x4d 134#define SX9324_REG_ADV_CTRL14 0x4e 135#define SX9324_REG_ADV_CTRL15 0x4f 136#define SX9324_REG_ADV_CTRL16 0x50 137#define SX9324_REG_ADV_CTRL17 0x51 138#define SX9324_REG_ADV_CTRL18 0x52 139#define SX9324_REG_ADV_CTRL19 0x53 140#define SX9324_REG_ADV_CTRL20 0x54 141#define SX9324_REG_ADV_CTRL19_HIGHT_FAILURE_THRESH_SATURATION 0xf0 142 143#define SX9324_REG_PHASE_SEL 0x60 144 145#define SX9324_REG_USEFUL_MSB 0x61 146#define SX9324_REG_USEFUL_LSB 0x62 147 148#define SX9324_REG_AVG_MSB 0x63 149#define SX9324_REG_AVG_LSB 0x64 150 151#define SX9324_REG_DIFF_MSB 0x65 152#define SX9324_REG_DIFF_LSB 0x66 153 154#define SX9324_REG_OFFSET_MSB 0x67 155#define SX9324_REG_OFFSET_LSB 0x68 156 157#define SX9324_REG_SAR_MSB 0x69 158#define SX9324_REG_SAR_LSB 0x6a 159 160#define SX9324_REG_RESET 0x9f 161/* Write this to REG_RESET to do a soft reset. */ 162#define SX9324_SOFT_RESET 0xde 163 164#define SX9324_REG_WHOAMI 0xfa 165#define SX9324_WHOAMI_VALUE 0x23 166 167#define SX9324_REG_REVISION 0xfe 168 169/* 4 channels, as defined in STAT0: PH0, PH1, PH2 and PH3. */ 170#define SX9324_NUM_CHANNELS 4 171/* 3 CS pins: CS0, CS1, CS2. */ 172#define SX9324_NUM_PINS 3 173 174static const char * const sx9324_cs_pin_usage[] = { "HZ", "MI", "DS", "GD" }; 175 176static ssize_t sx9324_phase_configuration_show(struct iio_dev *indio_dev, 177 uintptr_t private, 178 const struct iio_chan_spec *chan, 179 char *buf) 180{ 181 struct sx_common_data *data = iio_priv(indio_dev); 182 unsigned int val; 183 int i, ret, pin_idx; 184 size_t len = 0; 185 186 ret = regmap_read(data->regmap, SX9324_REG_AFE_PH0 + chan->channel, &val); 187 if (ret < 0) 188 return ret; 189 190 for (i = 0; i < SX9324_NUM_PINS; i++) { 191 pin_idx = (val & SX9324_REG_AFE_PH0_PIN_MASK(i)) >> (2 * i); 192 len += sysfs_emit_at(buf, len, "%s,", 193 sx9324_cs_pin_usage[pin_idx]); 194 } 195 buf[len - 1] = '\n'; 196 return len; 197} 198 199static const struct iio_chan_spec_ext_info sx9324_channel_ext_info[] = { 200 { 201 .name = "setup", 202 .shared = IIO_SEPARATE, 203 .read = sx9324_phase_configuration_show, 204 }, 205 {} 206}; 207 208#define SX9324_CHANNEL(idx) \ 209{ \ 210 .type = IIO_PROXIMITY, \ 211 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 212 BIT(IIO_CHAN_INFO_HARDWAREGAIN), \ 213 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 214 .info_mask_separate_available = \ 215 BIT(IIO_CHAN_INFO_HARDWAREGAIN), \ 216 .info_mask_shared_by_all_available = \ 217 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 218 .indexed = 1, \ 219 .channel = idx, \ 220 .address = SX9324_REG_DIFF_MSB, \ 221 .event_spec = sx_common_events, \ 222 .num_event_specs = ARRAY_SIZE(sx_common_events), \ 223 .scan_index = idx, \ 224 .scan_type = { \ 225 .sign = 's', \ 226 .realbits = 12, \ 227 .storagebits = 16, \ 228 .endianness = IIO_BE, \ 229 }, \ 230 .ext_info = sx9324_channel_ext_info, \ 231} 232 233static const struct iio_chan_spec sx9324_channels[] = { 234 SX9324_CHANNEL(0), /* Phase 0 */ 235 SX9324_CHANNEL(1), /* Phase 1 */ 236 SX9324_CHANNEL(2), /* Phase 2 */ 237 SX9324_CHANNEL(3), /* Phase 3 */ 238 IIO_CHAN_SOFT_TIMESTAMP(4), 239}; 240 241/* 242 * Each entry contains the integer part (val) and the fractional part, in micro 243 * seconds. It conforms to the IIO output IIO_VAL_INT_PLUS_MICRO. 244 */ 245static const struct { 246 int val; 247 int val2; 248} sx9324_samp_freq_table[] = { 249 { 1000, 0 }, /* 00000: Min (no idle time) */ 250 { 500, 0 }, /* 00001: 2 ms */ 251 { 250, 0 }, /* 00010: 4 ms */ 252 { 166, 666666 }, /* 00011: 6 ms */ 253 { 125, 0 }, /* 00100: 8 ms */ 254 { 100, 0 }, /* 00101: 10 ms */ 255 { 71, 428571 }, /* 00110: 14 ms */ 256 { 55, 555556 }, /* 00111: 18 ms */ 257 { 45, 454545 }, /* 01000: 22 ms */ 258 { 38, 461538 }, /* 01001: 26 ms */ 259 { 33, 333333 }, /* 01010: 30 ms */ 260 { 29, 411765 }, /* 01011: 34 ms */ 261 { 26, 315789 }, /* 01100: 38 ms */ 262 { 23, 809524 }, /* 01101: 42 ms */ 263 { 21, 739130 }, /* 01110: 46 ms */ 264 { 20, 0 }, /* 01111: 50 ms */ 265 { 17, 857143 }, /* 10000: 56 ms */ 266 { 16, 129032 }, /* 10001: 62 ms */ 267 { 14, 705882 }, /* 10010: 68 ms */ 268 { 13, 513514 }, /* 10011: 74 ms */ 269 { 12, 500000 }, /* 10100: 80 ms */ 270 { 11, 111111 }, /* 10101: 90 ms */ 271 { 10, 0 }, /* 10110: 100 ms (Typ.) */ 272 { 5, 0 }, /* 10111: 200 ms */ 273 { 3, 333333 }, /* 11000: 300 ms */ 274 { 2, 500000 }, /* 11001: 400 ms */ 275 { 1, 666667 }, /* 11010: 600 ms */ 276 { 1, 250000 }, /* 11011: 800 ms */ 277 { 1, 0 }, /* 11100: 1 s */ 278 { 0, 500000 }, /* 11101: 2 s */ 279 { 0, 333333 }, /* 11110: 3 s */ 280 { 0, 250000 }, /* 11111: 4 s */ 281}; 282 283static const unsigned int sx9324_scan_period_table[] = { 284 2, 15, 30, 45, 60, 90, 120, 200, 285 400, 600, 800, 1000, 2000, 3000, 4000, 5000, 286}; 287 288static const struct regmap_range sx9324_writable_reg_ranges[] = { 289 /* 290 * To set COMPSTAT for compensation, even if datasheet says register is 291 * RO. 292 */ 293 regmap_reg_range(SX9324_REG_STAT2, SX9324_REG_STAT2), 294 regmap_reg_range(SX9324_REG_IRQ_MSK, SX9324_REG_IRQ_CFG2), 295 regmap_reg_range(SX9324_REG_GNRL_CTRL0, SX9324_REG_GNRL_CTRL1), 296 /* Leave i2c and clock spreading as unavailable */ 297 regmap_reg_range(SX9324_REG_AFE_CTRL0, SX9324_REG_AFE_CTRL9), 298 regmap_reg_range(SX9324_REG_PROX_CTRL0, SX9324_REG_PROX_CTRL7), 299 regmap_reg_range(SX9324_REG_ADV_CTRL0, SX9324_REG_ADV_CTRL20), 300 regmap_reg_range(SX9324_REG_PHASE_SEL, SX9324_REG_PHASE_SEL), 301 regmap_reg_range(SX9324_REG_OFFSET_MSB, SX9324_REG_OFFSET_LSB), 302 regmap_reg_range(SX9324_REG_RESET, SX9324_REG_RESET), 303}; 304 305static const struct regmap_access_table sx9324_writeable_regs = { 306 .yes_ranges = sx9324_writable_reg_ranges, 307 .n_yes_ranges = ARRAY_SIZE(sx9324_writable_reg_ranges), 308}; 309 310/* 311 * All allocated registers are readable, so we just list unallocated 312 * ones. 313 */ 314static const struct regmap_range sx9324_non_readable_reg_ranges[] = { 315 regmap_reg_range(SX9324_REG_IRQ_CFG2 + 1, SX9324_REG_GNRL_CTRL0 - 1), 316 regmap_reg_range(SX9324_REG_GNRL_CTRL1 + 1, SX9324_REG_AFE_CTRL0 - 1), 317 regmap_reg_range(SX9324_REG_AFE_CTRL9 + 1, SX9324_REG_PROX_CTRL0 - 1), 318 regmap_reg_range(SX9324_REG_PROX_CTRL7 + 1, SX9324_REG_ADV_CTRL0 - 1), 319 regmap_reg_range(SX9324_REG_ADV_CTRL20 + 1, SX9324_REG_PHASE_SEL - 1), 320 regmap_reg_range(SX9324_REG_SAR_LSB + 1, SX9324_REG_RESET - 1), 321 regmap_reg_range(SX9324_REG_RESET + 1, SX9324_REG_WHOAMI - 1), 322 regmap_reg_range(SX9324_REG_WHOAMI + 1, SX9324_REG_REVISION - 1), 323}; 324 325static const struct regmap_access_table sx9324_readable_regs = { 326 .no_ranges = sx9324_non_readable_reg_ranges, 327 .n_no_ranges = ARRAY_SIZE(sx9324_non_readable_reg_ranges), 328}; 329 330static const struct regmap_range sx9324_volatile_reg_ranges[] = { 331 regmap_reg_range(SX9324_REG_IRQ_SRC, SX9324_REG_STAT3), 332 regmap_reg_range(SX9324_REG_USEFUL_MSB, SX9324_REG_DIFF_LSB), 333 regmap_reg_range(SX9324_REG_SAR_MSB, SX9324_REG_SAR_LSB), 334 regmap_reg_range(SX9324_REG_WHOAMI, SX9324_REG_WHOAMI), 335 regmap_reg_range(SX9324_REG_REVISION, SX9324_REG_REVISION), 336}; 337 338static const struct regmap_access_table sx9324_volatile_regs = { 339 .yes_ranges = sx9324_volatile_reg_ranges, 340 .n_yes_ranges = ARRAY_SIZE(sx9324_volatile_reg_ranges), 341}; 342 343static const struct regmap_config sx9324_regmap_config = { 344 .reg_bits = 8, 345 .val_bits = 8, 346 347 .max_register = SX9324_REG_REVISION, 348 .cache_type = REGCACHE_RBTREE, 349 350 .wr_table = &sx9324_writeable_regs, 351 .rd_table = &sx9324_readable_regs, 352 .volatile_table = &sx9324_volatile_regs, 353}; 354 355static int sx9324_read_prox_data(struct sx_common_data *data, 356 const struct iio_chan_spec *chan, 357 __be16 *val) 358{ 359 int ret; 360 361 ret = regmap_write(data->regmap, SX9324_REG_PHASE_SEL, chan->channel); 362 if (ret < 0) 363 return ret; 364 365 return regmap_bulk_read(data->regmap, chan->address, val, sizeof(*val)); 366} 367 368/* 369 * If we have no interrupt support, we have to wait for a scan period 370 * after enabling a channel to get a result. 371 */ 372static int sx9324_wait_for_sample(struct sx_common_data *data) 373{ 374 int ret; 375 unsigned int val; 376 377 ret = regmap_read(data->regmap, SX9324_REG_GNRL_CTRL0, &val); 378 if (ret < 0) 379 return ret; 380 val = FIELD_GET(SX9324_REG_GNRL_CTRL0_SCANPERIOD_MASK, val); 381 382 msleep(sx9324_scan_period_table[val]); 383 384 return 0; 385} 386 387static int sx9324_read_gain(struct sx_common_data *data, 388 const struct iio_chan_spec *chan, int *val) 389{ 390 unsigned int reg, regval; 391 int ret; 392 393 reg = SX9324_REG_PROX_CTRL0 + chan->channel / 2; 394 ret = regmap_read(data->regmap, reg, ®val); 395 if (ret) 396 return ret; 397 398 regval = FIELD_GET(SX9324_REG_PROX_CTRL0_GAIN_MASK, regval); 399 if (regval) 400 regval--; 401 else if (regval == SX9324_REG_PROX_CTRL0_GAIN_RSVD || 402 regval > SX9324_REG_PROX_CTRL0_GAIN_8) 403 return -EINVAL; 404 405 *val = 1 << regval; 406 407 return IIO_VAL_INT; 408} 409 410static int sx9324_read_samp_freq(struct sx_common_data *data, 411 int *val, int *val2) 412{ 413 int ret; 414 unsigned int regval; 415 416 ret = regmap_read(data->regmap, SX9324_REG_GNRL_CTRL0, ®val); 417 if (ret) 418 return ret; 419 420 regval = FIELD_GET(SX9324_REG_GNRL_CTRL0_SCANPERIOD_MASK, regval); 421 *val = sx9324_samp_freq_table[regval].val; 422 *val2 = sx9324_samp_freq_table[regval].val2; 423 424 return IIO_VAL_INT_PLUS_MICRO; 425} 426 427static int sx9324_read_raw(struct iio_dev *indio_dev, 428 const struct iio_chan_spec *chan, 429 int *val, int *val2, long mask) 430{ 431 struct sx_common_data *data = iio_priv(indio_dev); 432 int ret; 433 434 switch (mask) { 435 case IIO_CHAN_INFO_RAW: 436 ret = iio_device_claim_direct_mode(indio_dev); 437 if (ret) 438 return ret; 439 440 ret = sx_common_read_proximity(data, chan, val); 441 iio_device_release_direct_mode(indio_dev); 442 return ret; 443 case IIO_CHAN_INFO_HARDWAREGAIN: 444 ret = iio_device_claim_direct_mode(indio_dev); 445 if (ret) 446 return ret; 447 448 ret = sx9324_read_gain(data, chan, val); 449 iio_device_release_direct_mode(indio_dev); 450 return ret; 451 case IIO_CHAN_INFO_SAMP_FREQ: 452 return sx9324_read_samp_freq(data, val, val2); 453 default: 454 return -EINVAL; 455 } 456} 457 458static const int sx9324_gain_vals[] = { 1, 2, 4, 8 }; 459 460static int sx9324_read_avail(struct iio_dev *indio_dev, 461 struct iio_chan_spec const *chan, 462 const int **vals, int *type, int *length, 463 long mask) 464{ 465 if (chan->type != IIO_PROXIMITY) 466 return -EINVAL; 467 468 switch (mask) { 469 case IIO_CHAN_INFO_HARDWAREGAIN: 470 *type = IIO_VAL_INT; 471 *length = ARRAY_SIZE(sx9324_gain_vals); 472 *vals = sx9324_gain_vals; 473 return IIO_AVAIL_LIST; 474 case IIO_CHAN_INFO_SAMP_FREQ: 475 *type = IIO_VAL_INT_PLUS_MICRO; 476 *length = ARRAY_SIZE(sx9324_samp_freq_table) * 2; 477 *vals = (int *)sx9324_samp_freq_table; 478 return IIO_AVAIL_LIST; 479 default: 480 return -EINVAL; 481 } 482} 483 484static int sx9324_set_samp_freq(struct sx_common_data *data, 485 int val, int val2) 486{ 487 int i, ret; 488 489 for (i = 0; i < ARRAY_SIZE(sx9324_samp_freq_table); i++) 490 if (val == sx9324_samp_freq_table[i].val && 491 val2 == sx9324_samp_freq_table[i].val2) 492 break; 493 494 if (i == ARRAY_SIZE(sx9324_samp_freq_table)) 495 return -EINVAL; 496 497 mutex_lock(&data->mutex); 498 499 ret = regmap_update_bits(data->regmap, 500 SX9324_REG_GNRL_CTRL0, 501 SX9324_REG_GNRL_CTRL0_SCANPERIOD_MASK, i); 502 503 mutex_unlock(&data->mutex); 504 505 return ret; 506} 507 508static int sx9324_read_thresh(struct sx_common_data *data, 509 const struct iio_chan_spec *chan, int *val) 510{ 511 unsigned int regval; 512 unsigned int reg; 513 int ret; 514 515 /* 516 * TODO(gwendal): Depending on the phase function 517 * (proximity/table/body), retrieve the right threshold. 518 * For now, return the proximity threshold. 519 */ 520 reg = SX9324_REG_PROX_CTRL6 + chan->channel / 2; 521 ret = regmap_read(data->regmap, reg, ®val); 522 if (ret) 523 return ret; 524 525 if (regval <= 1) 526 *val = regval; 527 else 528 *val = (regval * regval) / 2; 529 530 return IIO_VAL_INT; 531} 532 533static int sx9324_read_hysteresis(struct sx_common_data *data, 534 const struct iio_chan_spec *chan, int *val) 535{ 536 unsigned int regval, pthresh; 537 int ret; 538 539 ret = sx9324_read_thresh(data, chan, &pthresh); 540 if (ret < 0) 541 return ret; 542 543 ret = regmap_read(data->regmap, SX9324_REG_PROX_CTRL5, ®val); 544 if (ret) 545 return ret; 546 547 regval = FIELD_GET(SX9324_REG_PROX_CTRL5_HYST_MASK, regval); 548 if (!regval) 549 *val = 0; 550 else 551 *val = pthresh >> (5 - regval); 552 553 return IIO_VAL_INT; 554} 555 556static int sx9324_read_far_debounce(struct sx_common_data *data, int *val) 557{ 558 unsigned int regval; 559 int ret; 560 561 ret = regmap_read(data->regmap, SX9324_REG_PROX_CTRL5, ®val); 562 if (ret) 563 return ret; 564 565 regval = FIELD_GET(SX9324_REG_PROX_CTRL5_FAR_DEBOUNCE_MASK, regval); 566 if (regval) 567 *val = 1 << regval; 568 else 569 *val = 0; 570 571 return IIO_VAL_INT; 572} 573 574static int sx9324_read_close_debounce(struct sx_common_data *data, int *val) 575{ 576 unsigned int regval; 577 int ret; 578 579 ret = regmap_read(data->regmap, SX9324_REG_PROX_CTRL5, ®val); 580 if (ret) 581 return ret; 582 583 regval = FIELD_GET(SX9324_REG_PROX_CTRL5_CLOSE_DEBOUNCE_MASK, regval); 584 if (regval) 585 *val = 1 << regval; 586 else 587 *val = 0; 588 589 return IIO_VAL_INT; 590} 591 592static int sx9324_read_event_val(struct iio_dev *indio_dev, 593 const struct iio_chan_spec *chan, 594 enum iio_event_type type, 595 enum iio_event_direction dir, 596 enum iio_event_info info, int *val, int *val2) 597{ 598 struct sx_common_data *data = iio_priv(indio_dev); 599 600 if (chan->type != IIO_PROXIMITY) 601 return -EINVAL; 602 603 switch (info) { 604 case IIO_EV_INFO_VALUE: 605 return sx9324_read_thresh(data, chan, val); 606 case IIO_EV_INFO_PERIOD: 607 switch (dir) { 608 case IIO_EV_DIR_RISING: 609 return sx9324_read_far_debounce(data, val); 610 case IIO_EV_DIR_FALLING: 611 return sx9324_read_close_debounce(data, val); 612 default: 613 return -EINVAL; 614 } 615 case IIO_EV_INFO_HYSTERESIS: 616 return sx9324_read_hysteresis(data, chan, val); 617 default: 618 return -EINVAL; 619 } 620} 621 622static int sx9324_write_thresh(struct sx_common_data *data, 623 const struct iio_chan_spec *chan, int _val) 624{ 625 unsigned int reg, val = _val; 626 int ret; 627 628 reg = SX9324_REG_PROX_CTRL6 + chan->channel / 2; 629 630 if (val >= 1) 631 val = int_sqrt(2 * val); 632 633 if (val > 0xff) 634 return -EINVAL; 635 636 mutex_lock(&data->mutex); 637 ret = regmap_write(data->regmap, reg, val); 638 mutex_unlock(&data->mutex); 639 640 return ret; 641} 642 643static int sx9324_write_hysteresis(struct sx_common_data *data, 644 const struct iio_chan_spec *chan, int _val) 645{ 646 unsigned int hyst, val = _val; 647 int ret, pthresh; 648 649 ret = sx9324_read_thresh(data, chan, &pthresh); 650 if (ret < 0) 651 return ret; 652 653 if (val == 0) 654 hyst = 0; 655 else if (val >= pthresh >> 2) 656 hyst = 3; 657 else if (val >= pthresh >> 3) 658 hyst = 2; 659 else if (val >= pthresh >> 4) 660 hyst = 1; 661 else 662 return -EINVAL; 663 664 hyst = FIELD_PREP(SX9324_REG_PROX_CTRL5_HYST_MASK, hyst); 665 mutex_lock(&data->mutex); 666 ret = regmap_update_bits(data->regmap, SX9324_REG_PROX_CTRL5, 667 SX9324_REG_PROX_CTRL5_HYST_MASK, hyst); 668 mutex_unlock(&data->mutex); 669 670 return ret; 671} 672 673static int sx9324_write_far_debounce(struct sx_common_data *data, int _val) 674{ 675 unsigned int regval, val = _val; 676 int ret; 677 678 if (val > 0) 679 val = ilog2(val); 680 if (!FIELD_FIT(SX9324_REG_PROX_CTRL5_FAR_DEBOUNCE_MASK, val)) 681 return -EINVAL; 682 683 regval = FIELD_PREP(SX9324_REG_PROX_CTRL5_FAR_DEBOUNCE_MASK, val); 684 685 mutex_lock(&data->mutex); 686 ret = regmap_update_bits(data->regmap, SX9324_REG_PROX_CTRL5, 687 SX9324_REG_PROX_CTRL5_FAR_DEBOUNCE_MASK, 688 regval); 689 mutex_unlock(&data->mutex); 690 691 return ret; 692} 693 694static int sx9324_write_close_debounce(struct sx_common_data *data, int _val) 695{ 696 unsigned int regval, val = _val; 697 int ret; 698 699 if (val > 0) 700 val = ilog2(val); 701 if (!FIELD_FIT(SX9324_REG_PROX_CTRL5_CLOSE_DEBOUNCE_MASK, val)) 702 return -EINVAL; 703 704 regval = FIELD_PREP(SX9324_REG_PROX_CTRL5_CLOSE_DEBOUNCE_MASK, val); 705 706 mutex_lock(&data->mutex); 707 ret = regmap_update_bits(data->regmap, SX9324_REG_PROX_CTRL5, 708 SX9324_REG_PROX_CTRL5_CLOSE_DEBOUNCE_MASK, 709 regval); 710 mutex_unlock(&data->mutex); 711 712 return ret; 713} 714 715static int sx9324_write_event_val(struct iio_dev *indio_dev, 716 const struct iio_chan_spec *chan, 717 enum iio_event_type type, 718 enum iio_event_direction dir, 719 enum iio_event_info info, int val, int val2) 720{ 721 struct sx_common_data *data = iio_priv(indio_dev); 722 723 if (chan->type != IIO_PROXIMITY) 724 return -EINVAL; 725 726 switch (info) { 727 case IIO_EV_INFO_VALUE: 728 return sx9324_write_thresh(data, chan, val); 729 case IIO_EV_INFO_PERIOD: 730 switch (dir) { 731 case IIO_EV_DIR_RISING: 732 return sx9324_write_far_debounce(data, val); 733 case IIO_EV_DIR_FALLING: 734 return sx9324_write_close_debounce(data, val); 735 default: 736 return -EINVAL; 737 } 738 case IIO_EV_INFO_HYSTERESIS: 739 return sx9324_write_hysteresis(data, chan, val); 740 default: 741 return -EINVAL; 742 } 743} 744 745static int sx9324_write_gain(struct sx_common_data *data, 746 const struct iio_chan_spec *chan, int val) 747{ 748 unsigned int gain, reg; 749 int ret; 750 751 reg = SX9324_REG_PROX_CTRL0 + chan->channel / 2; 752 753 gain = ilog2(val) + 1; 754 if (val <= 0 || gain > SX9324_REG_PROX_CTRL0_GAIN_8) 755 return -EINVAL; 756 757 gain = FIELD_PREP(SX9324_REG_PROX_CTRL0_GAIN_MASK, gain); 758 759 mutex_lock(&data->mutex); 760 ret = regmap_update_bits(data->regmap, reg, 761 SX9324_REG_PROX_CTRL0_GAIN_MASK, 762 gain); 763 mutex_unlock(&data->mutex); 764 765 return ret; 766} 767 768static int sx9324_write_raw(struct iio_dev *indio_dev, 769 const struct iio_chan_spec *chan, int val, int val2, 770 long mask) 771{ 772 struct sx_common_data *data = iio_priv(indio_dev); 773 774 switch (mask) { 775 case IIO_CHAN_INFO_SAMP_FREQ: 776 return sx9324_set_samp_freq(data, val, val2); 777 case IIO_CHAN_INFO_HARDWAREGAIN: 778 return sx9324_write_gain(data, chan, val); 779 default: 780 return -EINVAL; 781 } 782} 783 784static const struct sx_common_reg_default sx9324_default_regs[] = { 785 { SX9324_REG_IRQ_MSK, 0x00 }, 786 { SX9324_REG_IRQ_CFG0, 0x00, "irq_cfg0" }, 787 { SX9324_REG_IRQ_CFG1, SX9324_REG_IRQ_CFG1_FAILCOND, "irq_cfg1" }, 788 { SX9324_REG_IRQ_CFG2, 0x00, "irq_cfg2" }, 789 { SX9324_REG_GNRL_CTRL0, SX9324_REG_GNRL_CTRL0_SCANPERIOD_100MS, "gnrl_ctrl0" }, 790 /* 791 * The lower 4 bits should not be set as it enable sensors measurements. 792 * Turning the detection on before the configuration values are set to 793 * good values can cause the device to return erroneous readings. 794 */ 795 { SX9324_REG_GNRL_CTRL1, SX9324_REG_GNRL_CTRL1_PAUSECTRL, "gnrl_ctrl1" }, 796 797 { SX9324_REG_AFE_CTRL0, SX9324_REG_AFE_CTRL0_RINT_LOWEST, "afe_ctrl0" }, 798 { SX9324_REG_AFE_CTRL3, 0x00, "afe_ctrl3" }, 799 { SX9324_REG_AFE_CTRL4, SX9324_REG_AFE_CTRL4_FREQ_83_33HZ | 800 SX9324_REG_AFE_CTRL4_RES_100, "afe_ctrl4" }, 801 { SX9324_REG_AFE_CTRL6, 0x00, "afe_ctrl6" }, 802 { SX9324_REG_AFE_CTRL7, SX9324_REG_AFE_CTRL4_FREQ_83_33HZ | 803 SX9324_REG_AFE_CTRL4_RES_100, "afe_ctrl7" }, 804 805 /* TODO(gwendal): PHx use chip default or all grounded? */ 806 { SX9324_REG_AFE_PH0, 0x29, "afe_ph0" }, 807 { SX9324_REG_AFE_PH1, 0x26, "afe_ph1" }, 808 { SX9324_REG_AFE_PH2, 0x1a, "afe_ph2" }, 809 { SX9324_REG_AFE_PH3, 0x16, "afe_ph3" }, 810 811 { SX9324_REG_AFE_CTRL8, SX9324_REG_AFE_CTRL8_RESERVED | 812 SX9324_REG_AFE_CTRL8_RESFILTIN_4KOHM, "afe_ctrl8" }, 813 { SX9324_REG_AFE_CTRL9, SX9324_REG_AFE_CTRL9_AGAIN_1, "afe_ctrl9" }, 814 815 { SX9324_REG_PROX_CTRL0, 816 SX9324_REG_PROX_CTRL0_GAIN_1 << SX9324_REG_PROX_CTRL0_GAIN_SHIFT | 817 SX9324_REG_PROX_CTRL0_RAWFILT_1P50, "prox_ctrl0" }, 818 { SX9324_REG_PROX_CTRL1, 819 SX9324_REG_PROX_CTRL0_GAIN_1 << SX9324_REG_PROX_CTRL0_GAIN_SHIFT | 820 SX9324_REG_PROX_CTRL0_RAWFILT_1P50, "prox_ctrl1" }, 821 { SX9324_REG_PROX_CTRL2, SX9324_REG_PROX_CTRL2_AVGNEG_THRESH_16K, "prox_ctrl2" }, 822 { SX9324_REG_PROX_CTRL3, SX9324_REG_PROX_CTRL3_AVGDEB_2SAMPLES | 823 SX9324_REG_PROX_CTRL3_AVGPOS_THRESH_16K, "prox_ctrl3" }, 824 { SX9324_REG_PROX_CTRL4, SX9324_REG_PROX_CTRL4_AVGNEG_FILT_2 | 825 SX9324_REG_PROX_CTRL4_AVGPOS_FILT_256, "prox_ctrl4" }, 826 { SX9324_REG_PROX_CTRL5, 0x00, "prox_ctrl5" }, 827 { SX9324_REG_PROX_CTRL6, SX9324_REG_PROX_CTRL6_PROXTHRESH_32, "prox_ctrl6" }, 828 { SX9324_REG_PROX_CTRL7, SX9324_REG_PROX_CTRL6_PROXTHRESH_32, "prox_ctrl7" }, 829 { SX9324_REG_ADV_CTRL0, 0x00, "adv_ctrl0" }, 830 { SX9324_REG_ADV_CTRL1, 0x00, "adv_ctrl1" }, 831 { SX9324_REG_ADV_CTRL2, 0x00, "adv_ctrl2" }, 832 { SX9324_REG_ADV_CTRL3, 0x00, "adv_ctrl3" }, 833 { SX9324_REG_ADV_CTRL4, 0x00, "adv_ctrl4" }, 834 { SX9324_REG_ADV_CTRL5, SX9324_REG_ADV_CTRL5_STARTUP_SENSOR_1 | 835 SX9324_REG_ADV_CTRL5_STARTUP_METHOD_1, "adv_ctrl5" }, 836 { SX9324_REG_ADV_CTRL6, 0x00, "adv_ctrl6" }, 837 { SX9324_REG_ADV_CTRL7, 0x00, "adv_ctrl7" }, 838 { SX9324_REG_ADV_CTRL8, 0x00, "adv_ctrl8" }, 839 { SX9324_REG_ADV_CTRL9, 0x00, "adv_ctrl9" }, 840 /* Body/Table threshold */ 841 { SX9324_REG_ADV_CTRL10, 0x00, "adv_ctrl10" }, 842 { SX9324_REG_ADV_CTRL11, 0x00, "adv_ctrl11" }, 843 { SX9324_REG_ADV_CTRL12, 0x00, "adv_ctrl12" }, 844 /* TODO(gwendal): SAR currenly disabled */ 845 { SX9324_REG_ADV_CTRL13, 0x00, "adv_ctrl13" }, 846 { SX9324_REG_ADV_CTRL14, 0x00, "adv_ctrl14" }, 847 { SX9324_REG_ADV_CTRL15, 0x00, "adv_ctrl15" }, 848 { SX9324_REG_ADV_CTRL16, 0x00, "adv_ctrl16" }, 849 { SX9324_REG_ADV_CTRL17, 0x00, "adv_ctrl17" }, 850 { SX9324_REG_ADV_CTRL18, 0x00, "adv_ctrl18" }, 851 { SX9324_REG_ADV_CTRL19, 852 SX9324_REG_ADV_CTRL19_HIGHT_FAILURE_THRESH_SATURATION, "adv_ctrl19" }, 853 { SX9324_REG_ADV_CTRL20, 854 SX9324_REG_ADV_CTRL19_HIGHT_FAILURE_THRESH_SATURATION, "adv_ctrl20" }, 855}; 856 857/* Activate all channels and perform an initial compensation. */ 858static int sx9324_init_compensation(struct iio_dev *indio_dev) 859{ 860 struct sx_common_data *data = iio_priv(indio_dev); 861 unsigned int val; 862 int ret; 863 864 /* run the compensation phase on all channels */ 865 ret = regmap_update_bits(data->regmap, SX9324_REG_STAT2, 866 SX9324_REG_STAT2_COMPSTAT_MASK, 867 SX9324_REG_STAT2_COMPSTAT_MASK); 868 if (ret) 869 return ret; 870 871 return regmap_read_poll_timeout(data->regmap, SX9324_REG_STAT2, val, 872 !(val & SX9324_REG_STAT2_COMPSTAT_MASK), 873 20000, 2000000); 874} 875 876static const struct sx_common_reg_default * 877sx9324_get_default_reg(struct device *dev, int idx, 878 struct sx_common_reg_default *reg_def) 879{ 880 static const char * const sx9324_rints[] = { "lowest", "low", "high", 881 "highest" }; 882 static const char * const sx9324_csidle[] = { "hi-z", "hi-z", "gnd", 883 "vdd" }; 884#define SX9324_PIN_DEF "semtech,ph0-pin" 885#define SX9324_RESOLUTION_DEF "semtech,ph01-resolution" 886#define SX9324_PROXRAW_DEF "semtech,ph01-proxraw-strength" 887 unsigned int pin_defs[SX9324_NUM_PINS]; 888 char prop[] = SX9324_PROXRAW_DEF; 889 u32 start = 0, raw = 0, pos = 0; 890 int ret, count, ph, pin; 891 const char *res; 892 893 memcpy(reg_def, &sx9324_default_regs[idx], sizeof(*reg_def)); 894 895 sx_common_get_raw_register_config(dev, reg_def); 896 switch (reg_def->reg) { 897 case SX9324_REG_AFE_PH0: 898 case SX9324_REG_AFE_PH1: 899 case SX9324_REG_AFE_PH2: 900 case SX9324_REG_AFE_PH3: 901 ph = reg_def->reg - SX9324_REG_AFE_PH0; 902 snprintf(prop, ARRAY_SIZE(prop), "semtech,ph%d-pin", ph); 903 904 count = device_property_count_u32(dev, prop); 905 if (count != ARRAY_SIZE(pin_defs)) 906 break; 907 ret = device_property_read_u32_array(dev, prop, pin_defs, 908 ARRAY_SIZE(pin_defs)); 909 if (ret) 910 break; 911 912 for (pin = 0; pin < SX9324_NUM_PINS; pin++) 913 raw |= (pin_defs[pin] << (2 * pin)) & 914 SX9324_REG_AFE_PH0_PIN_MASK(pin); 915 reg_def->def = raw; 916 break; 917 case SX9324_REG_AFE_CTRL0: 918 ret = device_property_read_string(dev, 919 "semtech,cs-idle-sleep", &res); 920 if (!ret) 921 ret = match_string(sx9324_csidle, ARRAY_SIZE(sx9324_csidle), res); 922 if (ret >= 0) { 923 reg_def->def &= ~SX9324_REG_AFE_CTRL0_CSIDLE_MASK; 924 reg_def->def |= ret << SX9324_REG_AFE_CTRL0_CSIDLE_SHIFT; 925 } 926 927 ret = device_property_read_string(dev, 928 "semtech,int-comp-resistor", &res); 929 if (ret) 930 break; 931 ret = match_string(sx9324_rints, ARRAY_SIZE(sx9324_rints), res); 932 if (ret < 0) 933 break; 934 reg_def->def &= ~SX9324_REG_AFE_CTRL0_RINT_MASK; 935 reg_def->def |= ret << SX9324_REG_AFE_CTRL0_RINT_SHIFT; 936 break; 937 case SX9324_REG_AFE_CTRL4: 938 case SX9324_REG_AFE_CTRL7: 939 if (reg_def->reg == SX9324_REG_AFE_CTRL4) 940 strncpy(prop, "semtech,ph01-resolution", 941 ARRAY_SIZE(prop)); 942 else 943 strncpy(prop, "semtech,ph23-resolution", 944 ARRAY_SIZE(prop)); 945 946 ret = device_property_read_u32(dev, prop, &raw); 947 if (ret) 948 break; 949 950 raw = ilog2(raw) - 3; 951 952 reg_def->def &= ~SX9324_REG_AFE_CTRL4_RESOLUTION_MASK; 953 reg_def->def |= FIELD_PREP(SX9324_REG_AFE_CTRL4_RESOLUTION_MASK, 954 raw); 955 break; 956 case SX9324_REG_AFE_CTRL8: 957 ret = device_property_read_u32(dev, 958 "semtech,input-precharge-resistor-ohms", 959 &raw); 960 if (ret) 961 break; 962 963 reg_def->def &= ~SX9324_REG_AFE_CTRL8_RESFILTIN_MASK; 964 reg_def->def |= FIELD_PREP(SX9324_REG_AFE_CTRL8_RESFILTIN_MASK, 965 raw / 2000); 966 break; 967 968 case SX9324_REG_AFE_CTRL9: 969 ret = device_property_read_u32(dev, 970 "semtech,input-analog-gain", &raw); 971 if (ret) 972 break; 973 /* 974 * The analog gain has the following setting: 975 * +---------+----------------+----------------+ 976 * | dt(raw) | physical value | register value | 977 * +---------+----------------+----------------+ 978 * | 0 | x1.247 | 6 | 979 * | 1 | x1 | 8 | 980 * | 2 | x0.768 | 11 | 981 * | 3 | x0.552 | 15 | 982 * +---------+----------------+----------------+ 983 */ 984 reg_def->def &= ~SX9324_REG_AFE_CTRL9_AGAIN_MASK; 985 reg_def->def |= FIELD_PREP(SX9324_REG_AFE_CTRL9_AGAIN_MASK, 986 6 + raw * (raw + 3) / 2); 987 break; 988 989 case SX9324_REG_ADV_CTRL5: 990 ret = device_property_read_u32(dev, "semtech,startup-sensor", 991 &start); 992 if (ret) 993 break; 994 995 reg_def->def &= ~SX9324_REG_ADV_CTRL5_STARTUPSENS_MASK; 996 reg_def->def |= FIELD_PREP(SX9324_REG_ADV_CTRL5_STARTUPSENS_MASK, 997 start); 998 break; 999 case SX9324_REG_PROX_CTRL4: 1000 ret = device_property_read_u32(dev, "semtech,avg-pos-strength", 1001 &pos); 1002 if (ret) 1003 break; 1004 1005 /* Powers of 2, except for a gap between 16 and 64 */ 1006 raw = clamp(ilog2(pos), 3, 11) - (pos >= 32 ? 4 : 3); 1007 1008 reg_def->def &= ~SX9324_REG_PROX_CTRL4_AVGPOSFILT_MASK; 1009 reg_def->def |= FIELD_PREP(SX9324_REG_PROX_CTRL4_AVGPOSFILT_MASK, 1010 raw); 1011 break; 1012 case SX9324_REG_PROX_CTRL0: 1013 case SX9324_REG_PROX_CTRL1: 1014 if (reg_def->reg == SX9324_REG_PROX_CTRL0) 1015 strncpy(prop, "semtech,ph01-proxraw-strength", 1016 ARRAY_SIZE(prop)); 1017 else 1018 strncpy(prop, "semtech,ph23-proxraw-strength", 1019 ARRAY_SIZE(prop)); 1020 ret = device_property_read_u32(dev, prop, &raw); 1021 if (ret) 1022 break; 1023 1024 reg_def->def &= ~SX9324_REG_PROX_CTRL0_RAWFILT_MASK; 1025 reg_def->def |= FIELD_PREP(SX9324_REG_PROX_CTRL0_RAWFILT_MASK, 1026 raw); 1027 break; 1028 } 1029 return reg_def; 1030} 1031 1032static int sx9324_check_whoami(struct device *dev, 1033 struct iio_dev *indio_dev) 1034{ 1035 /* 1036 * Only one sensor for this driver. Assuming the device tree 1037 * is correct, just set the sensor name. 1038 */ 1039 indio_dev->name = "sx9324"; 1040 return 0; 1041} 1042 1043static const struct sx_common_chip_info sx9324_chip_info = { 1044 .reg_stat = SX9324_REG_STAT0, 1045 .reg_irq_msk = SX9324_REG_IRQ_MSK, 1046 .reg_enable_chan = SX9324_REG_GNRL_CTRL1, 1047 .reg_reset = SX9324_REG_RESET, 1048 1049 .mask_enable_chan = SX9324_REG_GNRL_CTRL1_PHEN_MASK, 1050 .irq_msk_offset = 3, 1051 .num_channels = SX9324_NUM_CHANNELS, 1052 .num_default_regs = ARRAY_SIZE(sx9324_default_regs), 1053 1054 .ops = { 1055 .read_prox_data = sx9324_read_prox_data, 1056 .check_whoami = sx9324_check_whoami, 1057 .init_compensation = sx9324_init_compensation, 1058 .wait_for_sample = sx9324_wait_for_sample, 1059 .get_default_reg = sx9324_get_default_reg, 1060 }, 1061 1062 .iio_channels = sx9324_channels, 1063 .num_iio_channels = ARRAY_SIZE(sx9324_channels), 1064 .iio_info = { 1065 .read_raw = sx9324_read_raw, 1066 .read_avail = sx9324_read_avail, 1067 .read_event_value = sx9324_read_event_val, 1068 .write_event_value = sx9324_write_event_val, 1069 .write_raw = sx9324_write_raw, 1070 .read_event_config = sx_common_read_event_config, 1071 .write_event_config = sx_common_write_event_config, 1072 }, 1073}; 1074 1075static int sx9324_probe(struct i2c_client *client) 1076{ 1077 return sx_common_probe(client, &sx9324_chip_info, &sx9324_regmap_config); 1078} 1079 1080static int sx9324_suspend(struct device *dev) 1081{ 1082 struct sx_common_data *data = iio_priv(dev_get_drvdata(dev)); 1083 unsigned int regval; 1084 int ret; 1085 1086 disable_irq_nosync(data->client->irq); 1087 1088 mutex_lock(&data->mutex); 1089 ret = regmap_read(data->regmap, SX9324_REG_GNRL_CTRL1, ®val); 1090 1091 data->suspend_ctrl = 1092 FIELD_GET(SX9324_REG_GNRL_CTRL1_PHEN_MASK, regval); 1093 1094 if (ret < 0) 1095 goto out; 1096 1097 /* Disable all phases, send the device to sleep. */ 1098 ret = regmap_write(data->regmap, SX9324_REG_GNRL_CTRL1, 0); 1099 1100out: 1101 mutex_unlock(&data->mutex); 1102 return ret; 1103} 1104 1105static int sx9324_resume(struct device *dev) 1106{ 1107 struct sx_common_data *data = iio_priv(dev_get_drvdata(dev)); 1108 int ret; 1109 1110 mutex_lock(&data->mutex); 1111 ret = regmap_write(data->regmap, SX9324_REG_GNRL_CTRL1, 1112 data->suspend_ctrl | SX9324_REG_GNRL_CTRL1_PAUSECTRL); 1113 mutex_unlock(&data->mutex); 1114 if (ret) 1115 return ret; 1116 1117 enable_irq(data->client->irq); 1118 return 0; 1119} 1120 1121static DEFINE_SIMPLE_DEV_PM_OPS(sx9324_pm_ops, sx9324_suspend, sx9324_resume); 1122 1123static const struct acpi_device_id sx9324_acpi_match[] = { 1124 { "STH9324", SX9324_WHOAMI_VALUE }, 1125 { } 1126}; 1127MODULE_DEVICE_TABLE(acpi, sx9324_acpi_match); 1128 1129static const struct of_device_id sx9324_of_match[] = { 1130 { .compatible = "semtech,sx9324", (void *)SX9324_WHOAMI_VALUE }, 1131 { } 1132}; 1133MODULE_DEVICE_TABLE(of, sx9324_of_match); 1134 1135static const struct i2c_device_id sx9324_id[] = { 1136 { "sx9324", SX9324_WHOAMI_VALUE }, 1137 { } 1138}; 1139MODULE_DEVICE_TABLE(i2c, sx9324_id); 1140 1141static struct i2c_driver sx9324_driver = { 1142 .driver = { 1143 .name = "sx9324", 1144 .acpi_match_table = sx9324_acpi_match, 1145 .of_match_table = sx9324_of_match, 1146 .pm = pm_sleep_ptr(&sx9324_pm_ops), 1147 1148 /* 1149 * Lots of i2c transfers in probe + over 200 ms waiting in 1150 * sx9324_init_compensation() mean a slow probe; prefer async 1151 * so we don't delay boot if we're builtin to the kernel. 1152 */ 1153 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 1154 }, 1155 .probe = sx9324_probe, 1156 .id_table = sx9324_id, 1157}; 1158module_i2c_driver(sx9324_driver); 1159 1160MODULE_AUTHOR("Gwendal Grignou <gwendal@chromium.org>"); 1161MODULE_DESCRIPTION("Driver for Semtech SX9324 proximity sensor"); 1162MODULE_LICENSE("GPL v2"); 1163MODULE_IMPORT_NS(SEMTECH_PROX); 1164