162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-only */
262306a36Sopenharmony_ci/*
362306a36Sopenharmony_ci * AD5592R / AD5593R Digital <-> Analog converters driver
462306a36Sopenharmony_ci *
562306a36Sopenharmony_ci * Copyright 2015-2016 Analog Devices Inc.
662306a36Sopenharmony_ci * Author: Paul Cercueil <paul.cercueil@analog.com>
762306a36Sopenharmony_ci */
862306a36Sopenharmony_ci
962306a36Sopenharmony_ci#ifndef __DRIVERS_IIO_DAC_AD5592R_BASE_H__
1062306a36Sopenharmony_ci#define __DRIVERS_IIO_DAC_AD5592R_BASE_H__
1162306a36Sopenharmony_ci
1262306a36Sopenharmony_ci#include <linux/types.h>
1362306a36Sopenharmony_ci#include <linux/cache.h>
1462306a36Sopenharmony_ci#include <linux/mutex.h>
1562306a36Sopenharmony_ci#include <linux/gpio/driver.h>
1662306a36Sopenharmony_ci
1762306a36Sopenharmony_ci#include <linux/iio/iio.h>
1862306a36Sopenharmony_ci
1962306a36Sopenharmony_cistruct device;
2062306a36Sopenharmony_cistruct ad5592r_state;
2162306a36Sopenharmony_ci
2262306a36Sopenharmony_cienum ad5592r_registers {
2362306a36Sopenharmony_ci	AD5592R_REG_NOOP		= 0x0,
2462306a36Sopenharmony_ci	AD5592R_REG_DAC_READBACK	= 0x1,
2562306a36Sopenharmony_ci	AD5592R_REG_ADC_SEQ		= 0x2,
2662306a36Sopenharmony_ci	AD5592R_REG_CTRL		= 0x3,
2762306a36Sopenharmony_ci	AD5592R_REG_ADC_EN		= 0x4,
2862306a36Sopenharmony_ci	AD5592R_REG_DAC_EN		= 0x5,
2962306a36Sopenharmony_ci	AD5592R_REG_PULLDOWN		= 0x6,
3062306a36Sopenharmony_ci	AD5592R_REG_LDAC		= 0x7,
3162306a36Sopenharmony_ci	AD5592R_REG_GPIO_OUT_EN		= 0x8,
3262306a36Sopenharmony_ci	AD5592R_REG_GPIO_SET		= 0x9,
3362306a36Sopenharmony_ci	AD5592R_REG_GPIO_IN_EN		= 0xA,
3462306a36Sopenharmony_ci	AD5592R_REG_PD			= 0xB,
3562306a36Sopenharmony_ci	AD5592R_REG_OPEN_DRAIN		= 0xC,
3662306a36Sopenharmony_ci	AD5592R_REG_TRISTATE		= 0xD,
3762306a36Sopenharmony_ci	AD5592R_REG_RESET		= 0xF,
3862306a36Sopenharmony_ci};
3962306a36Sopenharmony_ci
4062306a36Sopenharmony_ci#define AD5592R_REG_PD_EN_REF		BIT(9)
4162306a36Sopenharmony_ci#define AD5592R_REG_CTRL_ADC_RANGE	BIT(5)
4262306a36Sopenharmony_ci#define AD5592R_REG_CTRL_DAC_RANGE	BIT(4)
4362306a36Sopenharmony_ci
4462306a36Sopenharmony_cistruct ad5592r_rw_ops {
4562306a36Sopenharmony_ci	int (*write_dac)(struct ad5592r_state *st, unsigned chan, u16 value);
4662306a36Sopenharmony_ci	int (*read_adc)(struct ad5592r_state *st, unsigned chan, u16 *value);
4762306a36Sopenharmony_ci	int (*reg_write)(struct ad5592r_state *st, u8 reg, u16 value);
4862306a36Sopenharmony_ci	int (*reg_read)(struct ad5592r_state *st, u8 reg, u16 *value);
4962306a36Sopenharmony_ci	int (*gpio_read)(struct ad5592r_state *st, u8 *value);
5062306a36Sopenharmony_ci};
5162306a36Sopenharmony_ci
5262306a36Sopenharmony_cistruct ad5592r_state {
5362306a36Sopenharmony_ci	struct device *dev;
5462306a36Sopenharmony_ci	struct regulator *reg;
5562306a36Sopenharmony_ci	struct gpio_chip gpiochip;
5662306a36Sopenharmony_ci	struct mutex gpio_lock;	/* Protect cached gpio_out, gpio_val, etc. */
5762306a36Sopenharmony_ci	struct mutex lock;
5862306a36Sopenharmony_ci	unsigned int num_channels;
5962306a36Sopenharmony_ci	const struct ad5592r_rw_ops *ops;
6062306a36Sopenharmony_ci	int scale_avail[2][2];
6162306a36Sopenharmony_ci	u16 cached_dac[8];
6262306a36Sopenharmony_ci	u16 cached_gp_ctrl;
6362306a36Sopenharmony_ci	u8 channel_modes[8];
6462306a36Sopenharmony_ci	u8 channel_offstate[8];
6562306a36Sopenharmony_ci	u8 gpio_map;
6662306a36Sopenharmony_ci	u8 gpio_out;
6762306a36Sopenharmony_ci	u8 gpio_in;
6862306a36Sopenharmony_ci	u8 gpio_val;
6962306a36Sopenharmony_ci
7062306a36Sopenharmony_ci	__be16 spi_msg __aligned(IIO_DMA_MINALIGN);
7162306a36Sopenharmony_ci	__be16 spi_msg_nop;
7262306a36Sopenharmony_ci};
7362306a36Sopenharmony_ci
7462306a36Sopenharmony_ciint ad5592r_probe(struct device *dev, const char *name,
7562306a36Sopenharmony_ci		const struct ad5592r_rw_ops *ops);
7662306a36Sopenharmony_civoid ad5592r_remove(struct device *dev);
7762306a36Sopenharmony_ci
7862306a36Sopenharmony_ci#endif /* __DRIVERS_IIO_DAC_AD5592R_BASE_H__ */
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