1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * IIO driver for the Apex Embedded Systems STX104 4 * Copyright (C) 2016 William Breathitt Gray 5 */ 6#include <linux/bitfield.h> 7#include <linux/bits.h> 8#include <linux/device.h> 9#include <linux/err.h> 10#include <linux/gpio/regmap.h> 11#include <linux/iio/iio.h> 12#include <linux/iio/types.h> 13#include <linux/isa.h> 14#include <linux/kernel.h> 15#include <linux/limits.h> 16#include <linux/module.h> 17#include <linux/moduleparam.h> 18#include <linux/mutex.h> 19#include <linux/regmap.h> 20#include <linux/types.h> 21 22#define STX104_OUT_CHAN(chan) { \ 23 .type = IIO_VOLTAGE, \ 24 .channel = chan, \ 25 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 26 .indexed = 1, \ 27 .output = 1 \ 28} 29#define STX104_IN_CHAN(chan, diff) { \ 30 .type = IIO_VOLTAGE, \ 31 .channel = chan, \ 32 .channel2 = chan, \ 33 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_HARDWAREGAIN) | \ 34 BIT(IIO_CHAN_INFO_OFFSET) | BIT(IIO_CHAN_INFO_SCALE), \ 35 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 36 .indexed = 1, \ 37 .differential = diff \ 38} 39 40#define STX104_NUM_OUT_CHAN 2 41 42#define STX104_EXTENT 16 43 44static unsigned int base[max_num_isa_dev(STX104_EXTENT)]; 45static unsigned int num_stx104; 46module_param_hw_array(base, uint, ioport, &num_stx104, 0); 47MODULE_PARM_DESC(base, "Apex Embedded Systems STX104 base addresses"); 48 49#define STX104_AIO_BASE 0x0 50#define STX104_SOFTWARE_STROBE STX104_AIO_BASE 51#define STX104_ADC_DATA STX104_AIO_BASE 52#define STX104_ADC_CHANNEL (STX104_AIO_BASE + 0x2) 53#define STX104_DIO_REG (STX104_AIO_BASE + 0x3) 54#define STX104_DAC_BASE (STX104_AIO_BASE + 0x4) 55#define STX104_ADC_STATUS (STX104_AIO_BASE + 0x8) 56#define STX104_ADC_CONTROL (STX104_AIO_BASE + 0x9) 57#define STX104_ADC_CONFIGURATION (STX104_AIO_BASE + 0x11) 58 59#define STX104_AIO_DATA_STRIDE 2 60#define STX104_DAC_OFFSET(_channel) (STX104_DAC_BASE + STX104_AIO_DATA_STRIDE * (_channel)) 61 62/* ADC Channel */ 63#define STX104_FC GENMASK(3, 0) 64#define STX104_LC GENMASK(7, 4) 65#define STX104_SINGLE_CHANNEL(_channel) \ 66 (u8_encode_bits(_channel, STX104_FC) | u8_encode_bits(_channel, STX104_LC)) 67 68/* ADC Status */ 69#define STX104_SD BIT(5) 70#define STX104_CNV BIT(7) 71#define STX104_DIFFERENTIAL 1 72 73/* ADC Control */ 74#define STX104_ALSS GENMASK(1, 0) 75#define STX104_SOFTWARE_TRIGGER u8_encode_bits(0x0, STX104_ALSS) 76 77/* ADC Configuration */ 78#define STX104_GAIN GENMASK(1, 0) 79#define STX104_ADBU BIT(2) 80#define STX104_BIPOLAR 0 81#define STX104_GAIN_X1 0 82#define STX104_GAIN_X2 1 83#define STX104_GAIN_X4 2 84#define STX104_GAIN_X8 3 85 86/** 87 * struct stx104_iio - IIO device private data structure 88 * @lock: synchronization lock to prevent I/O race conditions 89 * @aio_data_map: Regmap for analog I/O data 90 * @aio_ctl_map: Regmap for analog I/O control 91 */ 92struct stx104_iio { 93 struct mutex lock; 94 struct regmap *aio_data_map; 95 struct regmap *aio_ctl_map; 96}; 97 98static const struct regmap_range aio_ctl_wr_ranges[] = { 99 regmap_reg_range(0x0, 0x0), regmap_reg_range(0x2, 0x2), regmap_reg_range(0x9, 0x9), 100 regmap_reg_range(0x11, 0x11), 101}; 102static const struct regmap_range aio_ctl_rd_ranges[] = { 103 regmap_reg_range(0x2, 0x2), regmap_reg_range(0x8, 0x9), regmap_reg_range(0x11, 0x11), 104}; 105static const struct regmap_range aio_ctl_volatile_ranges[] = { 106 regmap_reg_range(0x8, 0x8), 107}; 108static const struct regmap_access_table aio_ctl_wr_table = { 109 .yes_ranges = aio_ctl_wr_ranges, 110 .n_yes_ranges = ARRAY_SIZE(aio_ctl_wr_ranges), 111}; 112static const struct regmap_access_table aio_ctl_rd_table = { 113 .yes_ranges = aio_ctl_rd_ranges, 114 .n_yes_ranges = ARRAY_SIZE(aio_ctl_rd_ranges), 115}; 116static const struct regmap_access_table aio_ctl_volatile_table = { 117 .yes_ranges = aio_ctl_volatile_ranges, 118 .n_yes_ranges = ARRAY_SIZE(aio_ctl_volatile_ranges), 119}; 120 121static const struct regmap_config aio_ctl_regmap_config = { 122 .name = "aio_ctl", 123 .reg_bits = 8, 124 .reg_stride = 1, 125 .reg_base = STX104_AIO_BASE, 126 .val_bits = 8, 127 .io_port = true, 128 .wr_table = &aio_ctl_wr_table, 129 .rd_table = &aio_ctl_rd_table, 130 .volatile_table = &aio_ctl_volatile_table, 131 .cache_type = REGCACHE_FLAT, 132}; 133 134static const struct regmap_range aio_data_wr_ranges[] = { 135 regmap_reg_range(0x4, 0x6), 136}; 137static const struct regmap_range aio_data_rd_ranges[] = { 138 regmap_reg_range(0x0, 0x0), 139}; 140static const struct regmap_access_table aio_data_wr_table = { 141 .yes_ranges = aio_data_wr_ranges, 142 .n_yes_ranges = ARRAY_SIZE(aio_data_wr_ranges), 143}; 144static const struct regmap_access_table aio_data_rd_table = { 145 .yes_ranges = aio_data_rd_ranges, 146 .n_yes_ranges = ARRAY_SIZE(aio_data_rd_ranges), 147}; 148 149static const struct regmap_config aio_data_regmap_config = { 150 .name = "aio_data", 151 .reg_bits = 16, 152 .reg_stride = STX104_AIO_DATA_STRIDE, 153 .reg_base = STX104_AIO_BASE, 154 .val_bits = 16, 155 .io_port = true, 156 .wr_table = &aio_data_wr_table, 157 .rd_table = &aio_data_rd_table, 158 .volatile_table = &aio_data_rd_table, 159 .cache_type = REGCACHE_FLAT, 160}; 161 162static const struct regmap_config dio_regmap_config = { 163 .name = "dio", 164 .reg_bits = 8, 165 .reg_stride = 1, 166 .reg_base = STX104_DIO_REG, 167 .val_bits = 8, 168 .io_port = true, 169}; 170 171static int stx104_read_raw(struct iio_dev *indio_dev, 172 struct iio_chan_spec const *chan, int *val, int *val2, long mask) 173{ 174 struct stx104_iio *const priv = iio_priv(indio_dev); 175 int err; 176 unsigned int adc_config; 177 unsigned int value; 178 unsigned int adc_status; 179 180 switch (mask) { 181 case IIO_CHAN_INFO_HARDWAREGAIN: 182 err = regmap_read(priv->aio_ctl_map, STX104_ADC_CONFIGURATION, &adc_config); 183 if (err) 184 return err; 185 186 *val = BIT(u8_get_bits(adc_config, STX104_GAIN)); 187 return IIO_VAL_INT; 188 case IIO_CHAN_INFO_RAW: 189 if (chan->output) { 190 err = regmap_read(priv->aio_data_map, STX104_DAC_OFFSET(chan->channel), 191 &value); 192 if (err) 193 return err; 194 *val = value; 195 return IIO_VAL_INT; 196 } 197 198 mutex_lock(&priv->lock); 199 200 /* select ADC channel */ 201 err = regmap_write(priv->aio_ctl_map, STX104_ADC_CHANNEL, 202 STX104_SINGLE_CHANNEL(chan->channel)); 203 if (err) { 204 mutex_unlock(&priv->lock); 205 return err; 206 } 207 208 /* 209 * Trigger ADC sample capture by writing to the 8-bit Software Strobe Register and 210 * wait for completion; the conversion time range is 5 microseconds to 53.68 seconds 211 * in steps of 25 nanoseconds. The actual Analog Input Frame Timer time interval is 212 * calculated as: 213 * ai_time_frame_ns = ( AIFT + 1 ) * ( 25 nanoseconds ). 214 * Where 0 <= AIFT <= 2147483648. 215 */ 216 err = regmap_write(priv->aio_ctl_map, STX104_SOFTWARE_STROBE, 0); 217 if (err) { 218 mutex_unlock(&priv->lock); 219 return err; 220 } 221 err = regmap_read_poll_timeout(priv->aio_ctl_map, STX104_ADC_STATUS, adc_status, 222 !u8_get_bits(adc_status, STX104_CNV), 0, 53687092); 223 if (err) { 224 mutex_unlock(&priv->lock); 225 return err; 226 } 227 228 err = regmap_read(priv->aio_data_map, STX104_ADC_DATA, &value); 229 if (err) { 230 mutex_unlock(&priv->lock); 231 return err; 232 } 233 *val = value; 234 235 mutex_unlock(&priv->lock); 236 return IIO_VAL_INT; 237 case IIO_CHAN_INFO_OFFSET: 238 /* get ADC bipolar/unipolar configuration */ 239 err = regmap_read(priv->aio_ctl_map, STX104_ADC_CONFIGURATION, &adc_config); 240 if (err) 241 return err; 242 243 *val = (u8_get_bits(adc_config, STX104_ADBU) == STX104_BIPOLAR) ? -32768 : 0; 244 return IIO_VAL_INT; 245 case IIO_CHAN_INFO_SCALE: 246 /* get ADC bipolar/unipolar and gain configuration */ 247 err = regmap_read(priv->aio_ctl_map, STX104_ADC_CONFIGURATION, &adc_config); 248 if (err) 249 return err; 250 251 *val = 5; 252 *val2 = (u8_get_bits(adc_config, STX104_ADBU) == STX104_BIPOLAR) ? 14 : 15; 253 *val2 += u8_get_bits(adc_config, STX104_GAIN); 254 return IIO_VAL_FRACTIONAL_LOG2; 255 } 256 257 return -EINVAL; 258} 259 260static int stx104_write_raw(struct iio_dev *indio_dev, 261 struct iio_chan_spec const *chan, int val, int val2, long mask) 262{ 263 struct stx104_iio *const priv = iio_priv(indio_dev); 264 u8 gain; 265 266 switch (mask) { 267 case IIO_CHAN_INFO_HARDWAREGAIN: 268 /* Only four gain states (x1, x2, x4, x8) */ 269 switch (val) { 270 case 1: 271 gain = STX104_GAIN_X1; 272 break; 273 case 2: 274 gain = STX104_GAIN_X2; 275 break; 276 case 4: 277 gain = STX104_GAIN_X4; 278 break; 279 case 8: 280 gain = STX104_GAIN_X8; 281 break; 282 default: 283 return -EINVAL; 284 } 285 286 return regmap_write(priv->aio_ctl_map, STX104_ADC_CONFIGURATION, gain); 287 case IIO_CHAN_INFO_RAW: 288 if (!chan->output) 289 return -EINVAL; 290 291 if (val < 0 || val > U16_MAX) 292 return -EINVAL; 293 294 return regmap_write(priv->aio_data_map, STX104_DAC_OFFSET(chan->channel), val); 295 } 296 297 return -EINVAL; 298} 299 300static const struct iio_info stx104_info = { 301 .read_raw = stx104_read_raw, 302 .write_raw = stx104_write_raw 303}; 304 305/* single-ended input channels configuration */ 306static const struct iio_chan_spec stx104_channels_sing[] = { 307 STX104_OUT_CHAN(0), STX104_OUT_CHAN(1), 308 STX104_IN_CHAN(0, 0), STX104_IN_CHAN(1, 0), STX104_IN_CHAN(2, 0), 309 STX104_IN_CHAN(3, 0), STX104_IN_CHAN(4, 0), STX104_IN_CHAN(5, 0), 310 STX104_IN_CHAN(6, 0), STX104_IN_CHAN(7, 0), STX104_IN_CHAN(8, 0), 311 STX104_IN_CHAN(9, 0), STX104_IN_CHAN(10, 0), STX104_IN_CHAN(11, 0), 312 STX104_IN_CHAN(12, 0), STX104_IN_CHAN(13, 0), STX104_IN_CHAN(14, 0), 313 STX104_IN_CHAN(15, 0) 314}; 315/* differential input channels configuration */ 316static const struct iio_chan_spec stx104_channels_diff[] = { 317 STX104_OUT_CHAN(0), STX104_OUT_CHAN(1), 318 STX104_IN_CHAN(0, 1), STX104_IN_CHAN(1, 1), STX104_IN_CHAN(2, 1), 319 STX104_IN_CHAN(3, 1), STX104_IN_CHAN(4, 1), STX104_IN_CHAN(5, 1), 320 STX104_IN_CHAN(6, 1), STX104_IN_CHAN(7, 1) 321}; 322 323static int stx104_reg_mask_xlate(struct gpio_regmap *const gpio, const unsigned int base, 324 unsigned int offset, unsigned int *const reg, 325 unsigned int *const mask) 326{ 327 /* Output lines are located at same register bit offsets as input lines */ 328 if (offset >= 4) 329 offset -= 4; 330 331 *reg = base; 332 *mask = BIT(offset); 333 334 return 0; 335} 336 337#define STX104_NGPIO 8 338static const char *stx104_names[STX104_NGPIO] = { 339 "DIN0", "DIN1", "DIN2", "DIN3", "DOUT0", "DOUT1", "DOUT2", "DOUT3" 340}; 341 342static int stx104_init_hw(struct stx104_iio *const priv) 343{ 344 int err; 345 346 /* configure device for software trigger operation */ 347 err = regmap_write(priv->aio_ctl_map, STX104_ADC_CONTROL, STX104_SOFTWARE_TRIGGER); 348 if (err) 349 return err; 350 351 /* initialize gain setting to x1 */ 352 err = regmap_write(priv->aio_ctl_map, STX104_ADC_CONFIGURATION, STX104_GAIN_X1); 353 if (err) 354 return err; 355 356 /* initialize DAC outputs to 0V */ 357 err = regmap_write(priv->aio_data_map, STX104_DAC_BASE, 0); 358 if (err) 359 return err; 360 err = regmap_write(priv->aio_data_map, STX104_DAC_BASE + STX104_AIO_DATA_STRIDE, 0); 361 if (err) 362 return err; 363 364 return 0; 365} 366 367static int stx104_probe(struct device *dev, unsigned int id) 368{ 369 struct iio_dev *indio_dev; 370 struct stx104_iio *priv; 371 struct gpio_regmap_config gpio_config; 372 void __iomem *stx104_base; 373 struct regmap *aio_ctl_map; 374 struct regmap *aio_data_map; 375 struct regmap *dio_map; 376 int err; 377 unsigned int adc_status; 378 379 indio_dev = devm_iio_device_alloc(dev, sizeof(*priv)); 380 if (!indio_dev) 381 return -ENOMEM; 382 383 if (!devm_request_region(dev, base[id], STX104_EXTENT, 384 dev_name(dev))) { 385 dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n", 386 base[id], base[id] + STX104_EXTENT); 387 return -EBUSY; 388 } 389 390 stx104_base = devm_ioport_map(dev, base[id], STX104_EXTENT); 391 if (!stx104_base) 392 return -ENOMEM; 393 394 aio_ctl_map = devm_regmap_init_mmio(dev, stx104_base, &aio_ctl_regmap_config); 395 if (IS_ERR(aio_ctl_map)) 396 return dev_err_probe(dev, PTR_ERR(aio_ctl_map), 397 "Unable to initialize aio_ctl register map\n"); 398 399 aio_data_map = devm_regmap_init_mmio(dev, stx104_base, &aio_data_regmap_config); 400 if (IS_ERR(aio_data_map)) 401 return dev_err_probe(dev, PTR_ERR(aio_data_map), 402 "Unable to initialize aio_data register map\n"); 403 404 dio_map = devm_regmap_init_mmio(dev, stx104_base, &dio_regmap_config); 405 if (IS_ERR(dio_map)) 406 return dev_err_probe(dev, PTR_ERR(dio_map), 407 "Unable to initialize dio register map\n"); 408 409 priv = iio_priv(indio_dev); 410 priv->aio_ctl_map = aio_ctl_map; 411 priv->aio_data_map = aio_data_map; 412 413 indio_dev->info = &stx104_info; 414 indio_dev->modes = INDIO_DIRECT_MODE; 415 416 err = regmap_read(aio_ctl_map, STX104_ADC_STATUS, &adc_status); 417 if (err) 418 return err; 419 420 if (u8_get_bits(adc_status, STX104_SD) == STX104_DIFFERENTIAL) { 421 indio_dev->num_channels = ARRAY_SIZE(stx104_channels_diff); 422 indio_dev->channels = stx104_channels_diff; 423 } else { 424 indio_dev->num_channels = ARRAY_SIZE(stx104_channels_sing); 425 indio_dev->channels = stx104_channels_sing; 426 } 427 428 indio_dev->name = dev_name(dev); 429 430 mutex_init(&priv->lock); 431 432 err = stx104_init_hw(priv); 433 if (err) 434 return err; 435 436 err = devm_iio_device_register(dev, indio_dev); 437 if (err) 438 return err; 439 440 gpio_config = (struct gpio_regmap_config) { 441 .parent = dev, 442 .regmap = dio_map, 443 .ngpio = STX104_NGPIO, 444 .names = stx104_names, 445 .reg_dat_base = GPIO_REGMAP_ADDR(STX104_DIO_REG), 446 .reg_set_base = GPIO_REGMAP_ADDR(STX104_DIO_REG), 447 .ngpio_per_reg = STX104_NGPIO, 448 .reg_mask_xlate = stx104_reg_mask_xlate, 449 .drvdata = dio_map, 450 }; 451 452 return PTR_ERR_OR_ZERO(devm_gpio_regmap_register(dev, &gpio_config)); 453} 454 455static struct isa_driver stx104_driver = { 456 .probe = stx104_probe, 457 .driver = { 458 .name = "stx104" 459 }, 460}; 461 462module_isa_driver(stx104_driver, num_stx104); 463 464MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>"); 465MODULE_DESCRIPTION("Apex Embedded Systems STX104 IIO driver"); 466MODULE_LICENSE("GPL v2"); 467