1// SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * iio/adc/max1363.c 4 * Copyright (C) 2008-2010 Jonathan Cameron 5 * 6 * based on linux/drivers/i2c/chips/max123x 7 * Copyright (C) 2002-2004 Stefan Eletzhofer 8 * 9 * based on linux/drivers/acron/char/pcf8583.c 10 * Copyright (C) 2000 Russell King 11 * 12 * Driver for max1363 and similar chips. 13 */ 14 15#include <linux/interrupt.h> 16#include <linux/device.h> 17#include <linux/kernel.h> 18#include <linux/sysfs.h> 19#include <linux/list.h> 20#include <linux/i2c.h> 21#include <linux/regulator/consumer.h> 22#include <linux/slab.h> 23#include <linux/err.h> 24#include <linux/module.h> 25#include <linux/mod_devicetable.h> 26#include <linux/property.h> 27 28#include <linux/iio/iio.h> 29#include <linux/iio/sysfs.h> 30#include <linux/iio/events.h> 31#include <linux/iio/buffer.h> 32#include <linux/iio/kfifo_buf.h> 33#include <linux/iio/trigger_consumer.h> 34#include <linux/iio/triggered_buffer.h> 35 36#define MAX1363_SETUP_BYTE(a) ((a) | 0x80) 37 38/* There is a fair bit more defined here than currently 39 * used, but the intention is to support everything these 40 * chips do in the long run */ 41 42/* see data sheets */ 43/* max1363 and max1236, max1237, max1238, max1239 */ 44#define MAX1363_SETUP_AIN3_IS_AIN3_REF_IS_VDD 0x00 45#define MAX1363_SETUP_AIN3_IS_REF_EXT_TO_REF 0x20 46#define MAX1363_SETUP_AIN3_IS_AIN3_REF_IS_INT 0x40 47#define MAX1363_SETUP_AIN3_IS_REF_REF_IS_INT 0x60 48#define MAX1363_SETUP_POWER_UP_INT_REF 0x10 49#define MAX1363_SETUP_POWER_DOWN_INT_REF 0x00 50 51/* think about including max11600 etc - more settings */ 52#define MAX1363_SETUP_EXT_CLOCK 0x08 53#define MAX1363_SETUP_INT_CLOCK 0x00 54#define MAX1363_SETUP_UNIPOLAR 0x00 55#define MAX1363_SETUP_BIPOLAR 0x04 56#define MAX1363_SETUP_RESET 0x00 57#define MAX1363_SETUP_NORESET 0x02 58/* max1363 only - though don't care on others. 59 * For now monitor modes are not implemented as the relevant 60 * line is not connected on my test board. 61 * The definitions are here as I intend to add this soon. 62 */ 63#define MAX1363_SETUP_MONITOR_SETUP 0x01 64 65/* Specific to the max1363 */ 66#define MAX1363_MON_RESET_CHAN(a) (1 << ((a) + 4)) 67#define MAX1363_MON_INT_ENABLE 0x01 68 69/* defined for readability reasons */ 70/* All chips */ 71#define MAX1363_CONFIG_BYTE(a) ((a)) 72 73#define MAX1363_CONFIG_SE 0x01 74#define MAX1363_CONFIG_DE 0x00 75#define MAX1363_CONFIG_SCAN_TO_CS 0x00 76#define MAX1363_CONFIG_SCAN_SINGLE_8 0x20 77#define MAX1363_CONFIG_SCAN_MONITOR_MODE 0x40 78#define MAX1363_CONFIG_SCAN_SINGLE_1 0x60 79/* max123{6-9} only */ 80#define MAX1236_SCAN_MID_TO_CHANNEL 0x40 81 82/* max1363 only - merely part of channel selects or don't care for others */ 83#define MAX1363_CONFIG_EN_MON_MODE_READ 0x18 84 85#define MAX1363_CHANNEL_SEL(a) ((a) << 1) 86 87/* max1363 strictly 0x06 - but doesn't matter */ 88#define MAX1363_CHANNEL_SEL_MASK 0x1E 89#define MAX1363_SCAN_MASK 0x60 90#define MAX1363_SE_DE_MASK 0x01 91 92#define MAX1363_MAX_CHANNELS 25 93/** 94 * struct max1363_mode - scan mode information 95 * @conf: The corresponding value of the configuration register 96 * @modemask: Bit mask corresponding to channels enabled in this mode 97 */ 98struct max1363_mode { 99 int8_t conf; 100 DECLARE_BITMAP(modemask, MAX1363_MAX_CHANNELS); 101}; 102 103/* This must be maintained along side the max1363_mode_table in max1363_core */ 104enum max1363_modes { 105 /* Single read of a single channel */ 106 _s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7, _s8, _s9, _s10, _s11, 107 /* Differential single read */ 108 d0m1, d2m3, d4m5, d6m7, d8m9, d10m11, 109 d1m0, d3m2, d5m4, d7m6, d9m8, d11m10, 110 /* Scan to channel and mid to channel where overlapping */ 111 s0to1, s0to2, s2to3, s0to3, s0to4, s0to5, s0to6, 112 s6to7, s0to7, s6to8, s0to8, s6to9, 113 s0to9, s6to10, s0to10, s6to11, s0to11, 114 /* Differential scan to channel and mid to channel where overlapping */ 115 d0m1to2m3, d0m1to4m5, d0m1to6m7, d6m7to8m9, 116 d0m1to8m9, d6m7to10m11, d0m1to10m11, d1m0to3m2, 117 d1m0to5m4, d1m0to7m6, d7m6to9m8, d1m0to9m8, 118 d7m6to11m10, d1m0to11m10, 119}; 120 121/** 122 * struct max1363_chip_info - chip specifc information 123 * @info: iio core function callbacks structure 124 * @channels: channel specification 125 * @num_channels: number of channels 126 * @mode_list: array of available scan modes 127 * @default_mode: the scan mode in which the chip starts up 128 * @int_vref_mv: the internal reference voltage 129 * @num_modes: number of modes 130 * @bits: accuracy of the adc in bits 131 */ 132struct max1363_chip_info { 133 const struct iio_info *info; 134 const struct iio_chan_spec *channels; 135 int num_channels; 136 const enum max1363_modes *mode_list; 137 enum max1363_modes default_mode; 138 u16 int_vref_mv; 139 u8 num_modes; 140 u8 bits; 141}; 142 143/** 144 * struct max1363_state - driver instance specific data 145 * @client: i2c_client 146 * @setupbyte: cache of current device setup byte 147 * @configbyte: cache of current device config byte 148 * @chip_info: chip model specific constants, available modes, etc. 149 * @current_mode: the scan mode of this chip 150 * @requestedmask: a valid requested set of channels 151 * @lock: lock to ensure state is consistent 152 * @monitor_on: whether monitor mode is enabled 153 * @monitor_speed: parameter corresponding to device monitor speed setting 154 * @mask_high: bitmask for enabled high thresholds 155 * @mask_low: bitmask for enabled low thresholds 156 * @thresh_high: high threshold values 157 * @thresh_low: low threshold values 158 * @vref: Reference voltage regulator 159 * @vref_uv: Actual (external or internal) reference voltage 160 * @send: function used to send data to the chip 161 * @recv: function used to receive data from the chip 162 */ 163struct max1363_state { 164 struct i2c_client *client; 165 u8 setupbyte; 166 u8 configbyte; 167 const struct max1363_chip_info *chip_info; 168 const struct max1363_mode *current_mode; 169 u32 requestedmask; 170 struct mutex lock; 171 172 /* Using monitor modes and buffer at the same time is 173 currently not supported */ 174 bool monitor_on; 175 unsigned int monitor_speed:3; 176 u8 mask_high; 177 u8 mask_low; 178 /* 4x unipolar first then the fours bipolar ones */ 179 s16 thresh_high[8]; 180 s16 thresh_low[8]; 181 struct regulator *vref; 182 u32 vref_uv; 183 int (*send)(const struct i2c_client *client, 184 const char *buf, int count); 185 int (*recv)(const struct i2c_client *client, 186 char *buf, int count); 187}; 188 189#define MAX1363_MODE_SINGLE(_num, _mask) { \ 190 .conf = MAX1363_CHANNEL_SEL(_num) \ 191 | MAX1363_CONFIG_SCAN_SINGLE_1 \ 192 | MAX1363_CONFIG_SE, \ 193 .modemask[0] = _mask, \ 194 } 195 196#define MAX1363_MODE_SCAN_TO_CHANNEL(_num, _mask) { \ 197 .conf = MAX1363_CHANNEL_SEL(_num) \ 198 | MAX1363_CONFIG_SCAN_TO_CS \ 199 | MAX1363_CONFIG_SE, \ 200 .modemask[0] = _mask, \ 201 } 202 203/* note not available for max1363 hence naming */ 204#define MAX1236_MODE_SCAN_MID_TO_CHANNEL(_mid, _num, _mask) { \ 205 .conf = MAX1363_CHANNEL_SEL(_num) \ 206 | MAX1236_SCAN_MID_TO_CHANNEL \ 207 | MAX1363_CONFIG_SE, \ 208 .modemask[0] = _mask \ 209} 210 211#define MAX1363_MODE_DIFF_SINGLE(_nump, _numm, _mask) { \ 212 .conf = MAX1363_CHANNEL_SEL(_nump) \ 213 | MAX1363_CONFIG_SCAN_SINGLE_1 \ 214 | MAX1363_CONFIG_DE, \ 215 .modemask[0] = _mask \ 216 } 217 218/* Can't think how to automate naming so specify for now */ 219#define MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(_num, _numvals, _mask) { \ 220 .conf = MAX1363_CHANNEL_SEL(_num) \ 221 | MAX1363_CONFIG_SCAN_TO_CS \ 222 | MAX1363_CONFIG_DE, \ 223 .modemask[0] = _mask \ 224 } 225 226/* note only available for max1363 hence naming */ 227#define MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(_num, _numvals, _mask) { \ 228 .conf = MAX1363_CHANNEL_SEL(_num) \ 229 | MAX1236_SCAN_MID_TO_CHANNEL \ 230 | MAX1363_CONFIG_SE, \ 231 .modemask[0] = _mask \ 232} 233 234static const struct max1363_mode max1363_mode_table[] = { 235 /* All of the single channel options first */ 236 MAX1363_MODE_SINGLE(0, 1 << 0), 237 MAX1363_MODE_SINGLE(1, 1 << 1), 238 MAX1363_MODE_SINGLE(2, 1 << 2), 239 MAX1363_MODE_SINGLE(3, 1 << 3), 240 MAX1363_MODE_SINGLE(4, 1 << 4), 241 MAX1363_MODE_SINGLE(5, 1 << 5), 242 MAX1363_MODE_SINGLE(6, 1 << 6), 243 MAX1363_MODE_SINGLE(7, 1 << 7), 244 MAX1363_MODE_SINGLE(8, 1 << 8), 245 MAX1363_MODE_SINGLE(9, 1 << 9), 246 MAX1363_MODE_SINGLE(10, 1 << 10), 247 MAX1363_MODE_SINGLE(11, 1 << 11), 248 249 MAX1363_MODE_DIFF_SINGLE(0, 1, 1 << 12), 250 MAX1363_MODE_DIFF_SINGLE(2, 3, 1 << 13), 251 MAX1363_MODE_DIFF_SINGLE(4, 5, 1 << 14), 252 MAX1363_MODE_DIFF_SINGLE(6, 7, 1 << 15), 253 MAX1363_MODE_DIFF_SINGLE(8, 9, 1 << 16), 254 MAX1363_MODE_DIFF_SINGLE(10, 11, 1 << 17), 255 MAX1363_MODE_DIFF_SINGLE(1, 0, 1 << 18), 256 MAX1363_MODE_DIFF_SINGLE(3, 2, 1 << 19), 257 MAX1363_MODE_DIFF_SINGLE(5, 4, 1 << 20), 258 MAX1363_MODE_DIFF_SINGLE(7, 6, 1 << 21), 259 MAX1363_MODE_DIFF_SINGLE(9, 8, 1 << 22), 260 MAX1363_MODE_DIFF_SINGLE(11, 10, 1 << 23), 261 262 /* The multichannel scans next */ 263 MAX1363_MODE_SCAN_TO_CHANNEL(1, 0x003), 264 MAX1363_MODE_SCAN_TO_CHANNEL(2, 0x007), 265 MAX1236_MODE_SCAN_MID_TO_CHANNEL(2, 3, 0x00C), 266 MAX1363_MODE_SCAN_TO_CHANNEL(3, 0x00F), 267 MAX1363_MODE_SCAN_TO_CHANNEL(4, 0x01F), 268 MAX1363_MODE_SCAN_TO_CHANNEL(5, 0x03F), 269 MAX1363_MODE_SCAN_TO_CHANNEL(6, 0x07F), 270 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 7, 0x0C0), 271 MAX1363_MODE_SCAN_TO_CHANNEL(7, 0x0FF), 272 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 8, 0x1C0), 273 MAX1363_MODE_SCAN_TO_CHANNEL(8, 0x1FF), 274 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 9, 0x3C0), 275 MAX1363_MODE_SCAN_TO_CHANNEL(9, 0x3FF), 276 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 10, 0x7C0), 277 MAX1363_MODE_SCAN_TO_CHANNEL(10, 0x7FF), 278 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 11, 0xFC0), 279 MAX1363_MODE_SCAN_TO_CHANNEL(11, 0xFFF), 280 281 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(2, 2, 0x003000), 282 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(4, 3, 0x007000), 283 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(6, 4, 0x00F000), 284 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(8, 2, 0x018000), 285 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(8, 5, 0x01F000), 286 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(10, 3, 0x038000), 287 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(10, 6, 0x3F000), 288 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(3, 2, 0x0C0000), 289 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(5, 3, 0x1C0000), 290 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(7, 4, 0x3C0000), 291 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(9, 2, 0x600000), 292 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(9, 5, 0x7C0000), 293 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(11, 3, 0xE00000), 294 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(11, 6, 0xFC0000), 295}; 296 297static const struct max1363_mode 298*max1363_match_mode(const unsigned long *mask, 299 const struct max1363_chip_info *ci) 300{ 301 int i; 302 if (mask) 303 for (i = 0; i < ci->num_modes; i++) 304 if (bitmap_subset(mask, 305 max1363_mode_table[ci->mode_list[i]]. 306 modemask, 307 MAX1363_MAX_CHANNELS)) 308 return &max1363_mode_table[ci->mode_list[i]]; 309 return NULL; 310} 311 312static int max1363_smbus_send(const struct i2c_client *client, const char *buf, 313 int count) 314{ 315 int i, err; 316 317 for (i = err = 0; err == 0 && i < count; ++i) 318 err = i2c_smbus_write_byte(client, buf[i]); 319 320 return err ? err : count; 321} 322 323static int max1363_smbus_recv(const struct i2c_client *client, char *buf, 324 int count) 325{ 326 int i, ret; 327 328 for (i = 0; i < count; ++i) { 329 ret = i2c_smbus_read_byte(client); 330 if (ret < 0) 331 return ret; 332 buf[i] = ret; 333 } 334 335 return count; 336} 337 338static int max1363_write_basic_config(struct max1363_state *st) 339{ 340 u8 tx_buf[2] = { st->setupbyte, st->configbyte }; 341 342 return st->send(st->client, tx_buf, 2); 343} 344 345static int max1363_set_scan_mode(struct max1363_state *st) 346{ 347 st->configbyte &= ~(MAX1363_CHANNEL_SEL_MASK 348 | MAX1363_SCAN_MASK 349 | MAX1363_SE_DE_MASK); 350 st->configbyte |= st->current_mode->conf; 351 352 return max1363_write_basic_config(st); 353} 354 355static int max1363_read_single_chan(struct iio_dev *indio_dev, 356 struct iio_chan_spec const *chan, 357 int *val, 358 long m) 359{ 360 int ret = 0; 361 s32 data; 362 u8 rxbuf[2]; 363 struct max1363_state *st = iio_priv(indio_dev); 364 struct i2c_client *client = st->client; 365 366 ret = iio_device_claim_direct_mode(indio_dev); 367 if (ret) 368 return ret; 369 mutex_lock(&st->lock); 370 371 /* 372 * If monitor mode is enabled, the method for reading a single 373 * channel will have to be rather different and has not yet 374 * been implemented. 375 * 376 * Also, cannot read directly if buffered capture enabled. 377 */ 378 if (st->monitor_on) { 379 ret = -EBUSY; 380 goto error_ret; 381 } 382 383 /* Check to see if current scan mode is correct */ 384 if (st->current_mode != &max1363_mode_table[chan->address]) { 385 /* Update scan mode if needed */ 386 st->current_mode = &max1363_mode_table[chan->address]; 387 ret = max1363_set_scan_mode(st); 388 if (ret < 0) 389 goto error_ret; 390 } 391 if (st->chip_info->bits != 8) { 392 /* Get reading */ 393 data = st->recv(client, rxbuf, 2); 394 if (data < 0) { 395 ret = data; 396 goto error_ret; 397 } 398 data = (rxbuf[1] | rxbuf[0] << 8) & 399 ((1 << st->chip_info->bits) - 1); 400 } else { 401 /* Get reading */ 402 data = st->recv(client, rxbuf, 1); 403 if (data < 0) { 404 ret = data; 405 goto error_ret; 406 } 407 data = rxbuf[0]; 408 } 409 *val = data; 410 411error_ret: 412 mutex_unlock(&st->lock); 413 iio_device_release_direct_mode(indio_dev); 414 return ret; 415 416} 417 418static int max1363_read_raw(struct iio_dev *indio_dev, 419 struct iio_chan_spec const *chan, 420 int *val, 421 int *val2, 422 long m) 423{ 424 struct max1363_state *st = iio_priv(indio_dev); 425 int ret; 426 427 switch (m) { 428 case IIO_CHAN_INFO_RAW: 429 ret = max1363_read_single_chan(indio_dev, chan, val, m); 430 if (ret < 0) 431 return ret; 432 return IIO_VAL_INT; 433 case IIO_CHAN_INFO_SCALE: 434 *val = st->vref_uv / 1000; 435 *val2 = st->chip_info->bits; 436 return IIO_VAL_FRACTIONAL_LOG2; 437 default: 438 return -EINVAL; 439 } 440 return 0; 441} 442 443/* Applies to max1363 */ 444static const enum max1363_modes max1363_mode_list[] = { 445 _s0, _s1, _s2, _s3, 446 s0to1, s0to2, s0to3, 447 d0m1, d2m3, d1m0, d3m2, 448 d0m1to2m3, d1m0to3m2, 449}; 450 451static const struct iio_event_spec max1363_events[] = { 452 { 453 .type = IIO_EV_TYPE_THRESH, 454 .dir = IIO_EV_DIR_RISING, 455 .mask_separate = BIT(IIO_EV_INFO_VALUE) | 456 BIT(IIO_EV_INFO_ENABLE), 457 }, { 458 .type = IIO_EV_TYPE_THRESH, 459 .dir = IIO_EV_DIR_FALLING, 460 .mask_separate = BIT(IIO_EV_INFO_VALUE) | 461 BIT(IIO_EV_INFO_ENABLE), 462 }, 463}; 464 465#define MAX1363_CHAN_U(num, addr, si, bits, ev_spec, num_ev_spec) \ 466 { \ 467 .type = IIO_VOLTAGE, \ 468 .indexed = 1, \ 469 .channel = num, \ 470 .address = addr, \ 471 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 472 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 473 .datasheet_name = "AIN"#num, \ 474 .scan_type = { \ 475 .sign = 'u', \ 476 .realbits = bits, \ 477 .storagebits = (bits > 8) ? 16 : 8, \ 478 .endianness = IIO_BE, \ 479 }, \ 480 .scan_index = si, \ 481 .event_spec = ev_spec, \ 482 .num_event_specs = num_ev_spec, \ 483 } 484 485/* bipolar channel */ 486#define MAX1363_CHAN_B(num, num2, addr, si, bits, ev_spec, num_ev_spec) \ 487 { \ 488 .type = IIO_VOLTAGE, \ 489 .differential = 1, \ 490 .indexed = 1, \ 491 .channel = num, \ 492 .channel2 = num2, \ 493 .address = addr, \ 494 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 495 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 496 .datasheet_name = "AIN"#num"-AIN"#num2, \ 497 .scan_type = { \ 498 .sign = 's', \ 499 .realbits = bits, \ 500 .storagebits = (bits > 8) ? 16 : 8, \ 501 .endianness = IIO_BE, \ 502 }, \ 503 .scan_index = si, \ 504 .event_spec = ev_spec, \ 505 .num_event_specs = num_ev_spec, \ 506 } 507 508#define MAX1363_4X_CHANS(bits, ev_spec, num_ev_spec) { \ 509 MAX1363_CHAN_U(0, _s0, 0, bits, ev_spec, num_ev_spec), \ 510 MAX1363_CHAN_U(1, _s1, 1, bits, ev_spec, num_ev_spec), \ 511 MAX1363_CHAN_U(2, _s2, 2, bits, ev_spec, num_ev_spec), \ 512 MAX1363_CHAN_U(3, _s3, 3, bits, ev_spec, num_ev_spec), \ 513 MAX1363_CHAN_B(0, 1, d0m1, 4, bits, ev_spec, num_ev_spec), \ 514 MAX1363_CHAN_B(2, 3, d2m3, 5, bits, ev_spec, num_ev_spec), \ 515 MAX1363_CHAN_B(1, 0, d1m0, 6, bits, ev_spec, num_ev_spec), \ 516 MAX1363_CHAN_B(3, 2, d3m2, 7, bits, ev_spec, num_ev_spec), \ 517 IIO_CHAN_SOFT_TIMESTAMP(8) \ 518 } 519 520static const struct iio_chan_spec max1036_channels[] = 521 MAX1363_4X_CHANS(8, NULL, 0); 522static const struct iio_chan_spec max1136_channels[] = 523 MAX1363_4X_CHANS(10, NULL, 0); 524static const struct iio_chan_spec max1236_channels[] = 525 MAX1363_4X_CHANS(12, NULL, 0); 526static const struct iio_chan_spec max1361_channels[] = 527 MAX1363_4X_CHANS(10, max1363_events, ARRAY_SIZE(max1363_events)); 528static const struct iio_chan_spec max1363_channels[] = 529 MAX1363_4X_CHANS(12, max1363_events, ARRAY_SIZE(max1363_events)); 530 531/* Applies to max1236, max1237 */ 532static const enum max1363_modes max1236_mode_list[] = { 533 _s0, _s1, _s2, _s3, 534 s0to1, s0to2, s0to3, 535 d0m1, d2m3, d1m0, d3m2, 536 d0m1to2m3, d1m0to3m2, 537 s2to3, 538}; 539 540/* Applies to max1238, max1239 */ 541static const enum max1363_modes max1238_mode_list[] = { 542 _s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7, _s8, _s9, _s10, _s11, 543 s0to1, s0to2, s0to3, s0to4, s0to5, s0to6, 544 s0to7, s0to8, s0to9, s0to10, s0to11, 545 d0m1, d2m3, d4m5, d6m7, d8m9, d10m11, 546 d1m0, d3m2, d5m4, d7m6, d9m8, d11m10, 547 d0m1to2m3, d0m1to4m5, d0m1to6m7, d0m1to8m9, d0m1to10m11, 548 d1m0to3m2, d1m0to5m4, d1m0to7m6, d1m0to9m8, d1m0to11m10, 549 s6to7, s6to8, s6to9, s6to10, s6to11, 550 d6m7to8m9, d6m7to10m11, d7m6to9m8, d7m6to11m10, 551}; 552 553#define MAX1363_12X_CHANS(bits) { \ 554 MAX1363_CHAN_U(0, _s0, 0, bits, NULL, 0), \ 555 MAX1363_CHAN_U(1, _s1, 1, bits, NULL, 0), \ 556 MAX1363_CHAN_U(2, _s2, 2, bits, NULL, 0), \ 557 MAX1363_CHAN_U(3, _s3, 3, bits, NULL, 0), \ 558 MAX1363_CHAN_U(4, _s4, 4, bits, NULL, 0), \ 559 MAX1363_CHAN_U(5, _s5, 5, bits, NULL, 0), \ 560 MAX1363_CHAN_U(6, _s6, 6, bits, NULL, 0), \ 561 MAX1363_CHAN_U(7, _s7, 7, bits, NULL, 0), \ 562 MAX1363_CHAN_U(8, _s8, 8, bits, NULL, 0), \ 563 MAX1363_CHAN_U(9, _s9, 9, bits, NULL, 0), \ 564 MAX1363_CHAN_U(10, _s10, 10, bits, NULL, 0), \ 565 MAX1363_CHAN_U(11, _s11, 11, bits, NULL, 0), \ 566 MAX1363_CHAN_B(0, 1, d0m1, 12, bits, NULL, 0), \ 567 MAX1363_CHAN_B(2, 3, d2m3, 13, bits, NULL, 0), \ 568 MAX1363_CHAN_B(4, 5, d4m5, 14, bits, NULL, 0), \ 569 MAX1363_CHAN_B(6, 7, d6m7, 15, bits, NULL, 0), \ 570 MAX1363_CHAN_B(8, 9, d8m9, 16, bits, NULL, 0), \ 571 MAX1363_CHAN_B(10, 11, d10m11, 17, bits, NULL, 0), \ 572 MAX1363_CHAN_B(1, 0, d1m0, 18, bits, NULL, 0), \ 573 MAX1363_CHAN_B(3, 2, d3m2, 19, bits, NULL, 0), \ 574 MAX1363_CHAN_B(5, 4, d5m4, 20, bits, NULL, 0), \ 575 MAX1363_CHAN_B(7, 6, d7m6, 21, bits, NULL, 0), \ 576 MAX1363_CHAN_B(9, 8, d9m8, 22, bits, NULL, 0), \ 577 MAX1363_CHAN_B(11, 10, d11m10, 23, bits, NULL, 0), \ 578 IIO_CHAN_SOFT_TIMESTAMP(24) \ 579 } 580static const struct iio_chan_spec max1038_channels[] = MAX1363_12X_CHANS(8); 581static const struct iio_chan_spec max1138_channels[] = MAX1363_12X_CHANS(10); 582static const struct iio_chan_spec max1238_channels[] = MAX1363_12X_CHANS(12); 583 584static const enum max1363_modes max11607_mode_list[] = { 585 _s0, _s1, _s2, _s3, 586 s0to1, s0to2, s0to3, 587 s2to3, 588 d0m1, d2m3, d1m0, d3m2, 589 d0m1to2m3, d1m0to3m2, 590}; 591 592static const enum max1363_modes max11608_mode_list[] = { 593 _s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7, 594 s0to1, s0to2, s0to3, s0to4, s0to5, s0to6, s0to7, 595 s6to7, 596 d0m1, d2m3, d4m5, d6m7, 597 d1m0, d3m2, d5m4, d7m6, 598 d0m1to2m3, d0m1to4m5, d0m1to6m7, 599 d1m0to3m2, d1m0to5m4, d1m0to7m6, 600}; 601 602#define MAX1363_8X_CHANS(bits) { \ 603 MAX1363_CHAN_U(0, _s0, 0, bits, NULL, 0), \ 604 MAX1363_CHAN_U(1, _s1, 1, bits, NULL, 0), \ 605 MAX1363_CHAN_U(2, _s2, 2, bits, NULL, 0), \ 606 MAX1363_CHAN_U(3, _s3, 3, bits, NULL, 0), \ 607 MAX1363_CHAN_U(4, _s4, 4, bits, NULL, 0), \ 608 MAX1363_CHAN_U(5, _s5, 5, bits, NULL, 0), \ 609 MAX1363_CHAN_U(6, _s6, 6, bits, NULL, 0), \ 610 MAX1363_CHAN_U(7, _s7, 7, bits, NULL, 0), \ 611 MAX1363_CHAN_B(0, 1, d0m1, 8, bits, NULL, 0), \ 612 MAX1363_CHAN_B(2, 3, d2m3, 9, bits, NULL, 0), \ 613 MAX1363_CHAN_B(4, 5, d4m5, 10, bits, NULL, 0), \ 614 MAX1363_CHAN_B(6, 7, d6m7, 11, bits, NULL, 0), \ 615 MAX1363_CHAN_B(1, 0, d1m0, 12, bits, NULL, 0), \ 616 MAX1363_CHAN_B(3, 2, d3m2, 13, bits, NULL, 0), \ 617 MAX1363_CHAN_B(5, 4, d5m4, 14, bits, NULL, 0), \ 618 MAX1363_CHAN_B(7, 6, d7m6, 15, bits, NULL, 0), \ 619 IIO_CHAN_SOFT_TIMESTAMP(16) \ 620} 621static const struct iio_chan_spec max11602_channels[] = MAX1363_8X_CHANS(8); 622static const struct iio_chan_spec max11608_channels[] = MAX1363_8X_CHANS(10); 623static const struct iio_chan_spec max11614_channels[] = MAX1363_8X_CHANS(12); 624 625static const enum max1363_modes max11644_mode_list[] = { 626 _s0, _s1, s0to1, d0m1, d1m0, 627}; 628 629#define MAX1363_2X_CHANS(bits) { \ 630 MAX1363_CHAN_U(0, _s0, 0, bits, NULL, 0), \ 631 MAX1363_CHAN_U(1, _s1, 1, bits, NULL, 0), \ 632 MAX1363_CHAN_B(0, 1, d0m1, 2, bits, NULL, 0), \ 633 MAX1363_CHAN_B(1, 0, d1m0, 3, bits, NULL, 0), \ 634 IIO_CHAN_SOFT_TIMESTAMP(4) \ 635 } 636 637static const struct iio_chan_spec max11646_channels[] = MAX1363_2X_CHANS(10); 638static const struct iio_chan_spec max11644_channels[] = MAX1363_2X_CHANS(12); 639 640enum { max1361, 641 max1362, 642 max1363, 643 max1364, 644 max1036, 645 max1037, 646 max1038, 647 max1039, 648 max1136, 649 max1137, 650 max1138, 651 max1139, 652 max1236, 653 max1237, 654 max1238, 655 max1239, 656 max11600, 657 max11601, 658 max11602, 659 max11603, 660 max11604, 661 max11605, 662 max11606, 663 max11607, 664 max11608, 665 max11609, 666 max11610, 667 max11611, 668 max11612, 669 max11613, 670 max11614, 671 max11615, 672 max11616, 673 max11617, 674 max11644, 675 max11645, 676 max11646, 677 max11647 678}; 679 680static const int max1363_monitor_speeds[] = { 133000, 665000, 33300, 16600, 681 8300, 4200, 2000, 1000 }; 682 683static ssize_t max1363_monitor_show_freq(struct device *dev, 684 struct device_attribute *attr, 685 char *buf) 686{ 687 struct max1363_state *st = iio_priv(dev_to_iio_dev(dev)); 688 return sprintf(buf, "%d\n", max1363_monitor_speeds[st->monitor_speed]); 689} 690 691static ssize_t max1363_monitor_store_freq(struct device *dev, 692 struct device_attribute *attr, 693 const char *buf, 694 size_t len) 695{ 696 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 697 struct max1363_state *st = iio_priv(indio_dev); 698 int i, ret; 699 unsigned long val; 700 bool found = false; 701 702 ret = kstrtoul(buf, 10, &val); 703 if (ret) 704 return -EINVAL; 705 for (i = 0; i < ARRAY_SIZE(max1363_monitor_speeds); i++) 706 if (val == max1363_monitor_speeds[i]) { 707 found = true; 708 break; 709 } 710 if (!found) 711 return -EINVAL; 712 713 mutex_lock(&st->lock); 714 st->monitor_speed = i; 715 mutex_unlock(&st->lock); 716 717 return 0; 718} 719 720static IIO_DEV_ATTR_SAMP_FREQ(S_IRUGO | S_IWUSR, 721 max1363_monitor_show_freq, 722 max1363_monitor_store_freq); 723 724static IIO_CONST_ATTR(sampling_frequency_available, 725 "133000 665000 33300 16600 8300 4200 2000 1000"); 726 727static int max1363_read_thresh(struct iio_dev *indio_dev, 728 const struct iio_chan_spec *chan, enum iio_event_type type, 729 enum iio_event_direction dir, enum iio_event_info info, int *val, 730 int *val2) 731{ 732 struct max1363_state *st = iio_priv(indio_dev); 733 if (dir == IIO_EV_DIR_FALLING) 734 *val = st->thresh_low[chan->channel]; 735 else 736 *val = st->thresh_high[chan->channel]; 737 return IIO_VAL_INT; 738} 739 740static int max1363_write_thresh(struct iio_dev *indio_dev, 741 const struct iio_chan_spec *chan, enum iio_event_type type, 742 enum iio_event_direction dir, enum iio_event_info info, int val, 743 int val2) 744{ 745 struct max1363_state *st = iio_priv(indio_dev); 746 /* make it handle signed correctly as well */ 747 switch (st->chip_info->bits) { 748 case 10: 749 if (val > 0x3FF) 750 return -EINVAL; 751 break; 752 case 12: 753 if (val > 0xFFF) 754 return -EINVAL; 755 break; 756 } 757 758 switch (dir) { 759 case IIO_EV_DIR_FALLING: 760 st->thresh_low[chan->channel] = val; 761 break; 762 case IIO_EV_DIR_RISING: 763 st->thresh_high[chan->channel] = val; 764 break; 765 default: 766 return -EINVAL; 767 } 768 769 return 0; 770} 771 772static const u64 max1363_event_codes[] = { 773 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 0, 774 IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING), 775 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 1, 776 IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING), 777 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 2, 778 IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING), 779 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 3, 780 IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING), 781 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 0, 782 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING), 783 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 1, 784 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING), 785 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 2, 786 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING), 787 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 3, 788 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING), 789}; 790 791static irqreturn_t max1363_event_handler(int irq, void *private) 792{ 793 struct iio_dev *indio_dev = private; 794 struct max1363_state *st = iio_priv(indio_dev); 795 s64 timestamp = iio_get_time_ns(indio_dev); 796 unsigned long mask, loc; 797 u8 rx; 798 u8 tx[2] = { st->setupbyte, 799 MAX1363_MON_INT_ENABLE | (st->monitor_speed << 1) | 0xF0 }; 800 801 st->recv(st->client, &rx, 1); 802 mask = rx; 803 for_each_set_bit(loc, &mask, 8) 804 iio_push_event(indio_dev, max1363_event_codes[loc], timestamp); 805 st->send(st->client, tx, 2); 806 807 return IRQ_HANDLED; 808} 809 810static int max1363_read_event_config(struct iio_dev *indio_dev, 811 const struct iio_chan_spec *chan, enum iio_event_type type, 812 enum iio_event_direction dir) 813{ 814 struct max1363_state *st = iio_priv(indio_dev); 815 int val; 816 int number = chan->channel; 817 818 mutex_lock(&st->lock); 819 if (dir == IIO_EV_DIR_FALLING) 820 val = (1 << number) & st->mask_low; 821 else 822 val = (1 << number) & st->mask_high; 823 mutex_unlock(&st->lock); 824 825 return val; 826} 827 828static int max1363_monitor_mode_update(struct max1363_state *st, int enabled) 829{ 830 u8 *tx_buf; 831 int ret, i = 3, j; 832 unsigned long numelements; 833 int len; 834 const long *modemask; 835 836 if (!enabled) { 837 /* transition to buffered capture is not currently supported */ 838 st->setupbyte &= ~MAX1363_SETUP_MONITOR_SETUP; 839 st->configbyte &= ~MAX1363_SCAN_MASK; 840 st->monitor_on = false; 841 return max1363_write_basic_config(st); 842 } 843 844 /* Ensure we are in the relevant mode */ 845 st->setupbyte |= MAX1363_SETUP_MONITOR_SETUP; 846 st->configbyte &= ~(MAX1363_CHANNEL_SEL_MASK 847 | MAX1363_SCAN_MASK 848 | MAX1363_SE_DE_MASK); 849 st->configbyte |= MAX1363_CONFIG_SCAN_MONITOR_MODE; 850 if ((st->mask_low | st->mask_high) & 0x0F) { 851 st->configbyte |= max1363_mode_table[s0to3].conf; 852 modemask = max1363_mode_table[s0to3].modemask; 853 } else if ((st->mask_low | st->mask_high) & 0x30) { 854 st->configbyte |= max1363_mode_table[d0m1to2m3].conf; 855 modemask = max1363_mode_table[d0m1to2m3].modemask; 856 } else { 857 st->configbyte |= max1363_mode_table[d1m0to3m2].conf; 858 modemask = max1363_mode_table[d1m0to3m2].modemask; 859 } 860 numelements = bitmap_weight(modemask, MAX1363_MAX_CHANNELS); 861 len = 3 * numelements + 3; 862 tx_buf = kmalloc(len, GFP_KERNEL); 863 if (!tx_buf) { 864 ret = -ENOMEM; 865 goto error_ret; 866 } 867 tx_buf[0] = st->configbyte; 868 tx_buf[1] = st->setupbyte; 869 tx_buf[2] = (st->monitor_speed << 1); 870 871 /* 872 * So we need to do yet another bit of nefarious scan mode 873 * setup to match what we need. 874 */ 875 for (j = 0; j < 8; j++) 876 if (test_bit(j, modemask)) { 877 /* Establish the mode is in the scan */ 878 if (st->mask_low & (1 << j)) { 879 tx_buf[i] = (st->thresh_low[j] >> 4) & 0xFF; 880 tx_buf[i + 1] = (st->thresh_low[j] << 4) & 0xF0; 881 } else if (j < 4) { 882 tx_buf[i] = 0; 883 tx_buf[i + 1] = 0; 884 } else { 885 tx_buf[i] = 0x80; 886 tx_buf[i + 1] = 0; 887 } 888 if (st->mask_high & (1 << j)) { 889 tx_buf[i + 1] |= 890 (st->thresh_high[j] >> 8) & 0x0F; 891 tx_buf[i + 2] = st->thresh_high[j] & 0xFF; 892 } else if (j < 4) { 893 tx_buf[i + 1] |= 0x0F; 894 tx_buf[i + 2] = 0xFF; 895 } else { 896 tx_buf[i + 1] |= 0x07; 897 tx_buf[i + 2] = 0xFF; 898 } 899 i += 3; 900 } 901 902 903 ret = st->send(st->client, tx_buf, len); 904 if (ret < 0) 905 goto error_ret; 906 if (ret != len) { 907 ret = -EIO; 908 goto error_ret; 909 } 910 911 /* 912 * Now that we hopefully have sensible thresholds in place it is 913 * time to turn the interrupts on. 914 * It is unclear from the data sheet if this should be necessary 915 * (i.e. whether monitor mode setup is atomic) but it appears to 916 * be in practice. 917 */ 918 tx_buf[0] = st->setupbyte; 919 tx_buf[1] = MAX1363_MON_INT_ENABLE | (st->monitor_speed << 1) | 0xF0; 920 ret = st->send(st->client, tx_buf, 2); 921 if (ret < 0) 922 goto error_ret; 923 if (ret != 2) { 924 ret = -EIO; 925 goto error_ret; 926 } 927 ret = 0; 928 st->monitor_on = true; 929error_ret: 930 931 kfree(tx_buf); 932 933 return ret; 934} 935 936/* 937 * To keep this manageable we always use one of 3 scan modes. 938 * Scan 0...3, 0-1,2-3 and 1-0,3-2 939 */ 940 941static inline int __max1363_check_event_mask(int thismask, int checkmask) 942{ 943 int ret = 0; 944 /* Is it unipolar */ 945 if (thismask < 4) { 946 if (checkmask & ~0x0F) { 947 ret = -EBUSY; 948 goto error_ret; 949 } 950 } else if (thismask < 6) { 951 if (checkmask & ~0x30) { 952 ret = -EBUSY; 953 goto error_ret; 954 } 955 } else if (checkmask & ~0xC0) 956 ret = -EBUSY; 957error_ret: 958 return ret; 959} 960 961static int max1363_write_event_config(struct iio_dev *indio_dev, 962 const struct iio_chan_spec *chan, enum iio_event_type type, 963 enum iio_event_direction dir, int state) 964{ 965 int ret = 0; 966 struct max1363_state *st = iio_priv(indio_dev); 967 u16 unifiedmask; 968 int number = chan->channel; 969 970 ret = iio_device_claim_direct_mode(indio_dev); 971 if (ret) 972 return ret; 973 mutex_lock(&st->lock); 974 975 unifiedmask = st->mask_low | st->mask_high; 976 if (dir == IIO_EV_DIR_FALLING) { 977 978 if (state == 0) 979 st->mask_low &= ~(1 << number); 980 else { 981 ret = __max1363_check_event_mask((1 << number), 982 unifiedmask); 983 if (ret) 984 goto error_ret; 985 st->mask_low |= (1 << number); 986 } 987 } else { 988 if (state == 0) 989 st->mask_high &= ~(1 << number); 990 else { 991 ret = __max1363_check_event_mask((1 << number), 992 unifiedmask); 993 if (ret) 994 goto error_ret; 995 st->mask_high |= (1 << number); 996 } 997 } 998 999 max1363_monitor_mode_update(st, !!(st->mask_high | st->mask_low)); 1000error_ret: 1001 mutex_unlock(&st->lock); 1002 iio_device_release_direct_mode(indio_dev); 1003 1004 return ret; 1005} 1006 1007/* 1008 * As with scan_elements, only certain sets of these can 1009 * be combined. 1010 */ 1011static struct attribute *max1363_event_attributes[] = { 1012 &iio_dev_attr_sampling_frequency.dev_attr.attr, 1013 &iio_const_attr_sampling_frequency_available.dev_attr.attr, 1014 NULL, 1015}; 1016 1017static const struct attribute_group max1363_event_attribute_group = { 1018 .attrs = max1363_event_attributes, 1019}; 1020 1021static int max1363_update_scan_mode(struct iio_dev *indio_dev, 1022 const unsigned long *scan_mask) 1023{ 1024 struct max1363_state *st = iio_priv(indio_dev); 1025 1026 /* 1027 * Need to figure out the current mode based upon the requested 1028 * scan mask in iio_dev 1029 */ 1030 st->current_mode = max1363_match_mode(scan_mask, st->chip_info); 1031 if (!st->current_mode) 1032 return -EINVAL; 1033 max1363_set_scan_mode(st); 1034 return 0; 1035} 1036 1037static const struct iio_info max1238_info = { 1038 .read_raw = &max1363_read_raw, 1039 .update_scan_mode = &max1363_update_scan_mode, 1040}; 1041 1042static const struct iio_info max1363_info = { 1043 .read_event_value = &max1363_read_thresh, 1044 .write_event_value = &max1363_write_thresh, 1045 .read_event_config = &max1363_read_event_config, 1046 .write_event_config = &max1363_write_event_config, 1047 .read_raw = &max1363_read_raw, 1048 .update_scan_mode = &max1363_update_scan_mode, 1049 .event_attrs = &max1363_event_attribute_group, 1050}; 1051 1052/* max1363 and max1368 tested - rest from data sheet */ 1053static const struct max1363_chip_info max1363_chip_info_tbl[] = { 1054 [max1361] = { 1055 .bits = 10, 1056 .int_vref_mv = 2048, 1057 .mode_list = max1363_mode_list, 1058 .num_modes = ARRAY_SIZE(max1363_mode_list), 1059 .default_mode = s0to3, 1060 .channels = max1361_channels, 1061 .num_channels = ARRAY_SIZE(max1361_channels), 1062 .info = &max1363_info, 1063 }, 1064 [max1362] = { 1065 .bits = 10, 1066 .int_vref_mv = 4096, 1067 .mode_list = max1363_mode_list, 1068 .num_modes = ARRAY_SIZE(max1363_mode_list), 1069 .default_mode = s0to3, 1070 .channels = max1361_channels, 1071 .num_channels = ARRAY_SIZE(max1361_channels), 1072 .info = &max1363_info, 1073 }, 1074 [max1363] = { 1075 .bits = 12, 1076 .int_vref_mv = 2048, 1077 .mode_list = max1363_mode_list, 1078 .num_modes = ARRAY_SIZE(max1363_mode_list), 1079 .default_mode = s0to3, 1080 .channels = max1363_channels, 1081 .num_channels = ARRAY_SIZE(max1363_channels), 1082 .info = &max1363_info, 1083 }, 1084 [max1364] = { 1085 .bits = 12, 1086 .int_vref_mv = 4096, 1087 .mode_list = max1363_mode_list, 1088 .num_modes = ARRAY_SIZE(max1363_mode_list), 1089 .default_mode = s0to3, 1090 .channels = max1363_channels, 1091 .num_channels = ARRAY_SIZE(max1363_channels), 1092 .info = &max1363_info, 1093 }, 1094 [max1036] = { 1095 .bits = 8, 1096 .int_vref_mv = 4096, 1097 .mode_list = max1236_mode_list, 1098 .num_modes = ARRAY_SIZE(max1236_mode_list), 1099 .default_mode = s0to3, 1100 .info = &max1238_info, 1101 .channels = max1036_channels, 1102 .num_channels = ARRAY_SIZE(max1036_channels), 1103 }, 1104 [max1037] = { 1105 .bits = 8, 1106 .int_vref_mv = 2048, 1107 .mode_list = max1236_mode_list, 1108 .num_modes = ARRAY_SIZE(max1236_mode_list), 1109 .default_mode = s0to3, 1110 .info = &max1238_info, 1111 .channels = max1036_channels, 1112 .num_channels = ARRAY_SIZE(max1036_channels), 1113 }, 1114 [max1038] = { 1115 .bits = 8, 1116 .int_vref_mv = 4096, 1117 .mode_list = max1238_mode_list, 1118 .num_modes = ARRAY_SIZE(max1238_mode_list), 1119 .default_mode = s0to11, 1120 .info = &max1238_info, 1121 .channels = max1038_channels, 1122 .num_channels = ARRAY_SIZE(max1038_channels), 1123 }, 1124 [max1039] = { 1125 .bits = 8, 1126 .int_vref_mv = 2048, 1127 .mode_list = max1238_mode_list, 1128 .num_modes = ARRAY_SIZE(max1238_mode_list), 1129 .default_mode = s0to11, 1130 .info = &max1238_info, 1131 .channels = max1038_channels, 1132 .num_channels = ARRAY_SIZE(max1038_channels), 1133 }, 1134 [max1136] = { 1135 .bits = 10, 1136 .int_vref_mv = 4096, 1137 .mode_list = max1236_mode_list, 1138 .num_modes = ARRAY_SIZE(max1236_mode_list), 1139 .default_mode = s0to3, 1140 .info = &max1238_info, 1141 .channels = max1136_channels, 1142 .num_channels = ARRAY_SIZE(max1136_channels), 1143 }, 1144 [max1137] = { 1145 .bits = 10, 1146 .int_vref_mv = 2048, 1147 .mode_list = max1236_mode_list, 1148 .num_modes = ARRAY_SIZE(max1236_mode_list), 1149 .default_mode = s0to3, 1150 .info = &max1238_info, 1151 .channels = max1136_channels, 1152 .num_channels = ARRAY_SIZE(max1136_channels), 1153 }, 1154 [max1138] = { 1155 .bits = 10, 1156 .int_vref_mv = 4096, 1157 .mode_list = max1238_mode_list, 1158 .num_modes = ARRAY_SIZE(max1238_mode_list), 1159 .default_mode = s0to11, 1160 .info = &max1238_info, 1161 .channels = max1138_channels, 1162 .num_channels = ARRAY_SIZE(max1138_channels), 1163 }, 1164 [max1139] = { 1165 .bits = 10, 1166 .int_vref_mv = 2048, 1167 .mode_list = max1238_mode_list, 1168 .num_modes = ARRAY_SIZE(max1238_mode_list), 1169 .default_mode = s0to11, 1170 .info = &max1238_info, 1171 .channels = max1138_channels, 1172 .num_channels = ARRAY_SIZE(max1138_channels), 1173 }, 1174 [max1236] = { 1175 .bits = 12, 1176 .int_vref_mv = 4096, 1177 .mode_list = max1236_mode_list, 1178 .num_modes = ARRAY_SIZE(max1236_mode_list), 1179 .default_mode = s0to3, 1180 .info = &max1238_info, 1181 .channels = max1236_channels, 1182 .num_channels = ARRAY_SIZE(max1236_channels), 1183 }, 1184 [max1237] = { 1185 .bits = 12, 1186 .int_vref_mv = 2048, 1187 .mode_list = max1236_mode_list, 1188 .num_modes = ARRAY_SIZE(max1236_mode_list), 1189 .default_mode = s0to3, 1190 .info = &max1238_info, 1191 .channels = max1236_channels, 1192 .num_channels = ARRAY_SIZE(max1236_channels), 1193 }, 1194 [max1238] = { 1195 .bits = 12, 1196 .int_vref_mv = 4096, 1197 .mode_list = max1238_mode_list, 1198 .num_modes = ARRAY_SIZE(max1238_mode_list), 1199 .default_mode = s0to11, 1200 .info = &max1238_info, 1201 .channels = max1238_channels, 1202 .num_channels = ARRAY_SIZE(max1238_channels), 1203 }, 1204 [max1239] = { 1205 .bits = 12, 1206 .int_vref_mv = 2048, 1207 .mode_list = max1238_mode_list, 1208 .num_modes = ARRAY_SIZE(max1238_mode_list), 1209 .default_mode = s0to11, 1210 .info = &max1238_info, 1211 .channels = max1238_channels, 1212 .num_channels = ARRAY_SIZE(max1238_channels), 1213 }, 1214 [max11600] = { 1215 .bits = 8, 1216 .int_vref_mv = 4096, 1217 .mode_list = max11607_mode_list, 1218 .num_modes = ARRAY_SIZE(max11607_mode_list), 1219 .default_mode = s0to3, 1220 .info = &max1238_info, 1221 .channels = max1036_channels, 1222 .num_channels = ARRAY_SIZE(max1036_channels), 1223 }, 1224 [max11601] = { 1225 .bits = 8, 1226 .int_vref_mv = 2048, 1227 .mode_list = max11607_mode_list, 1228 .num_modes = ARRAY_SIZE(max11607_mode_list), 1229 .default_mode = s0to3, 1230 .info = &max1238_info, 1231 .channels = max1036_channels, 1232 .num_channels = ARRAY_SIZE(max1036_channels), 1233 }, 1234 [max11602] = { 1235 .bits = 8, 1236 .int_vref_mv = 4096, 1237 .mode_list = max11608_mode_list, 1238 .num_modes = ARRAY_SIZE(max11608_mode_list), 1239 .default_mode = s0to7, 1240 .info = &max1238_info, 1241 .channels = max11602_channels, 1242 .num_channels = ARRAY_SIZE(max11602_channels), 1243 }, 1244 [max11603] = { 1245 .bits = 8, 1246 .int_vref_mv = 2048, 1247 .mode_list = max11608_mode_list, 1248 .num_modes = ARRAY_SIZE(max11608_mode_list), 1249 .default_mode = s0to7, 1250 .info = &max1238_info, 1251 .channels = max11602_channels, 1252 .num_channels = ARRAY_SIZE(max11602_channels), 1253 }, 1254 [max11604] = { 1255 .bits = 8, 1256 .int_vref_mv = 4096, 1257 .mode_list = max1238_mode_list, 1258 .num_modes = ARRAY_SIZE(max1238_mode_list), 1259 .default_mode = s0to11, 1260 .info = &max1238_info, 1261 .channels = max1038_channels, 1262 .num_channels = ARRAY_SIZE(max1038_channels), 1263 }, 1264 [max11605] = { 1265 .bits = 8, 1266 .int_vref_mv = 2048, 1267 .mode_list = max1238_mode_list, 1268 .num_modes = ARRAY_SIZE(max1238_mode_list), 1269 .default_mode = s0to11, 1270 .info = &max1238_info, 1271 .channels = max1038_channels, 1272 .num_channels = ARRAY_SIZE(max1038_channels), 1273 }, 1274 [max11606] = { 1275 .bits = 10, 1276 .int_vref_mv = 4096, 1277 .mode_list = max11607_mode_list, 1278 .num_modes = ARRAY_SIZE(max11607_mode_list), 1279 .default_mode = s0to3, 1280 .info = &max1238_info, 1281 .channels = max1136_channels, 1282 .num_channels = ARRAY_SIZE(max1136_channels), 1283 }, 1284 [max11607] = { 1285 .bits = 10, 1286 .int_vref_mv = 2048, 1287 .mode_list = max11607_mode_list, 1288 .num_modes = ARRAY_SIZE(max11607_mode_list), 1289 .default_mode = s0to3, 1290 .info = &max1238_info, 1291 .channels = max1136_channels, 1292 .num_channels = ARRAY_SIZE(max1136_channels), 1293 }, 1294 [max11608] = { 1295 .bits = 10, 1296 .int_vref_mv = 4096, 1297 .mode_list = max11608_mode_list, 1298 .num_modes = ARRAY_SIZE(max11608_mode_list), 1299 .default_mode = s0to7, 1300 .info = &max1238_info, 1301 .channels = max11608_channels, 1302 .num_channels = ARRAY_SIZE(max11608_channels), 1303 }, 1304 [max11609] = { 1305 .bits = 10, 1306 .int_vref_mv = 2048, 1307 .mode_list = max11608_mode_list, 1308 .num_modes = ARRAY_SIZE(max11608_mode_list), 1309 .default_mode = s0to7, 1310 .info = &max1238_info, 1311 .channels = max11608_channels, 1312 .num_channels = ARRAY_SIZE(max11608_channels), 1313 }, 1314 [max11610] = { 1315 .bits = 10, 1316 .int_vref_mv = 4096, 1317 .mode_list = max1238_mode_list, 1318 .num_modes = ARRAY_SIZE(max1238_mode_list), 1319 .default_mode = s0to11, 1320 .info = &max1238_info, 1321 .channels = max1138_channels, 1322 .num_channels = ARRAY_SIZE(max1138_channels), 1323 }, 1324 [max11611] = { 1325 .bits = 10, 1326 .int_vref_mv = 2048, 1327 .mode_list = max1238_mode_list, 1328 .num_modes = ARRAY_SIZE(max1238_mode_list), 1329 .default_mode = s0to11, 1330 .info = &max1238_info, 1331 .channels = max1138_channels, 1332 .num_channels = ARRAY_SIZE(max1138_channels), 1333 }, 1334 [max11612] = { 1335 .bits = 12, 1336 .int_vref_mv = 4096, 1337 .mode_list = max11607_mode_list, 1338 .num_modes = ARRAY_SIZE(max11607_mode_list), 1339 .default_mode = s0to3, 1340 .info = &max1238_info, 1341 .channels = max1363_channels, 1342 .num_channels = ARRAY_SIZE(max1363_channels), 1343 }, 1344 [max11613] = { 1345 .bits = 12, 1346 .int_vref_mv = 2048, 1347 .mode_list = max11607_mode_list, 1348 .num_modes = ARRAY_SIZE(max11607_mode_list), 1349 .default_mode = s0to3, 1350 .info = &max1238_info, 1351 .channels = max1363_channels, 1352 .num_channels = ARRAY_SIZE(max1363_channels), 1353 }, 1354 [max11614] = { 1355 .bits = 12, 1356 .int_vref_mv = 4096, 1357 .mode_list = max11608_mode_list, 1358 .num_modes = ARRAY_SIZE(max11608_mode_list), 1359 .default_mode = s0to7, 1360 .info = &max1238_info, 1361 .channels = max11614_channels, 1362 .num_channels = ARRAY_SIZE(max11614_channels), 1363 }, 1364 [max11615] = { 1365 .bits = 12, 1366 .int_vref_mv = 2048, 1367 .mode_list = max11608_mode_list, 1368 .num_modes = ARRAY_SIZE(max11608_mode_list), 1369 .default_mode = s0to7, 1370 .info = &max1238_info, 1371 .channels = max11614_channels, 1372 .num_channels = ARRAY_SIZE(max11614_channels), 1373 }, 1374 [max11616] = { 1375 .bits = 12, 1376 .int_vref_mv = 4096, 1377 .mode_list = max1238_mode_list, 1378 .num_modes = ARRAY_SIZE(max1238_mode_list), 1379 .default_mode = s0to11, 1380 .info = &max1238_info, 1381 .channels = max1238_channels, 1382 .num_channels = ARRAY_SIZE(max1238_channels), 1383 }, 1384 [max11617] = { 1385 .bits = 12, 1386 .int_vref_mv = 2048, 1387 .mode_list = max1238_mode_list, 1388 .num_modes = ARRAY_SIZE(max1238_mode_list), 1389 .default_mode = s0to11, 1390 .info = &max1238_info, 1391 .channels = max1238_channels, 1392 .num_channels = ARRAY_SIZE(max1238_channels), 1393 }, 1394 [max11644] = { 1395 .bits = 12, 1396 .int_vref_mv = 4096, 1397 .mode_list = max11644_mode_list, 1398 .num_modes = ARRAY_SIZE(max11644_mode_list), 1399 .default_mode = s0to1, 1400 .info = &max1238_info, 1401 .channels = max11644_channels, 1402 .num_channels = ARRAY_SIZE(max11644_channels), 1403 }, 1404 [max11645] = { 1405 .bits = 12, 1406 .int_vref_mv = 2048, 1407 .mode_list = max11644_mode_list, 1408 .num_modes = ARRAY_SIZE(max11644_mode_list), 1409 .default_mode = s0to1, 1410 .info = &max1238_info, 1411 .channels = max11644_channels, 1412 .num_channels = ARRAY_SIZE(max11644_channels), 1413 }, 1414 [max11646] = { 1415 .bits = 10, 1416 .int_vref_mv = 4096, 1417 .mode_list = max11644_mode_list, 1418 .num_modes = ARRAY_SIZE(max11644_mode_list), 1419 .default_mode = s0to1, 1420 .info = &max1238_info, 1421 .channels = max11646_channels, 1422 .num_channels = ARRAY_SIZE(max11646_channels), 1423 }, 1424 [max11647] = { 1425 .bits = 10, 1426 .int_vref_mv = 2048, 1427 .mode_list = max11644_mode_list, 1428 .num_modes = ARRAY_SIZE(max11644_mode_list), 1429 .default_mode = s0to1, 1430 .info = &max1238_info, 1431 .channels = max11646_channels, 1432 .num_channels = ARRAY_SIZE(max11646_channels), 1433 }, 1434}; 1435 1436static int max1363_initial_setup(struct max1363_state *st) 1437{ 1438 st->setupbyte = MAX1363_SETUP_INT_CLOCK 1439 | MAX1363_SETUP_UNIPOLAR 1440 | MAX1363_SETUP_NORESET; 1441 1442 if (st->vref) 1443 st->setupbyte |= MAX1363_SETUP_AIN3_IS_REF_EXT_TO_REF; 1444 else 1445 st->setupbyte |= MAX1363_SETUP_POWER_UP_INT_REF 1446 | MAX1363_SETUP_AIN3_IS_AIN3_REF_IS_INT; 1447 1448 /* Set scan mode writes the config anyway so wait until then */ 1449 st->setupbyte = MAX1363_SETUP_BYTE(st->setupbyte); 1450 st->current_mode = &max1363_mode_table[st->chip_info->default_mode]; 1451 st->configbyte = MAX1363_CONFIG_BYTE(st->configbyte); 1452 1453 return max1363_set_scan_mode(st); 1454} 1455 1456static int max1363_alloc_scan_masks(struct iio_dev *indio_dev) 1457{ 1458 struct max1363_state *st = iio_priv(indio_dev); 1459 unsigned long *masks; 1460 int i; 1461 1462 masks = devm_kzalloc(&indio_dev->dev, 1463 array3_size(BITS_TO_LONGS(MAX1363_MAX_CHANNELS), 1464 sizeof(long), 1465 st->chip_info->num_modes + 1), 1466 GFP_KERNEL); 1467 if (!masks) 1468 return -ENOMEM; 1469 1470 for (i = 0; i < st->chip_info->num_modes; i++) 1471 bitmap_copy(masks + BITS_TO_LONGS(MAX1363_MAX_CHANNELS)*i, 1472 max1363_mode_table[st->chip_info->mode_list[i]] 1473 .modemask, MAX1363_MAX_CHANNELS); 1474 1475 indio_dev->available_scan_masks = masks; 1476 1477 return 0; 1478} 1479 1480static irqreturn_t max1363_trigger_handler(int irq, void *p) 1481{ 1482 struct iio_poll_func *pf = p; 1483 struct iio_dev *indio_dev = pf->indio_dev; 1484 struct max1363_state *st = iio_priv(indio_dev); 1485 __u8 *rxbuf; 1486 int b_sent; 1487 size_t d_size; 1488 unsigned long numvals = bitmap_weight(st->current_mode->modemask, 1489 MAX1363_MAX_CHANNELS); 1490 1491 /* Ensure the timestamp is 8 byte aligned */ 1492 if (st->chip_info->bits != 8) 1493 d_size = numvals*2; 1494 else 1495 d_size = numvals; 1496 if (indio_dev->scan_timestamp) { 1497 d_size += sizeof(s64); 1498 if (d_size % sizeof(s64)) 1499 d_size += sizeof(s64) - (d_size % sizeof(s64)); 1500 } 1501 /* Monitor mode prevents reading. Whilst not currently implemented 1502 * might as well have this test in here in the meantime as it does 1503 * no harm. 1504 */ 1505 if (numvals == 0) 1506 goto done; 1507 1508 rxbuf = kmalloc(d_size, GFP_KERNEL); 1509 if (rxbuf == NULL) 1510 goto done; 1511 if (st->chip_info->bits != 8) 1512 b_sent = st->recv(st->client, rxbuf, numvals * 2); 1513 else 1514 b_sent = st->recv(st->client, rxbuf, numvals); 1515 if (b_sent < 0) 1516 goto done_free; 1517 1518 iio_push_to_buffers_with_timestamp(indio_dev, rxbuf, 1519 iio_get_time_ns(indio_dev)); 1520 1521done_free: 1522 kfree(rxbuf); 1523done: 1524 iio_trigger_notify_done(indio_dev->trig); 1525 1526 return IRQ_HANDLED; 1527} 1528 1529#define MAX1363_COMPATIBLE(of_compatible, cfg) { \ 1530 .compatible = of_compatible, \ 1531 .data = &max1363_chip_info_tbl[cfg], \ 1532} 1533 1534static const struct of_device_id max1363_of_match[] = { 1535 MAX1363_COMPATIBLE("maxim,max1361", max1361), 1536 MAX1363_COMPATIBLE("maxim,max1362", max1362), 1537 MAX1363_COMPATIBLE("maxim,max1363", max1363), 1538 MAX1363_COMPATIBLE("maxim,max1364", max1364), 1539 MAX1363_COMPATIBLE("maxim,max1036", max1036), 1540 MAX1363_COMPATIBLE("maxim,max1037", max1037), 1541 MAX1363_COMPATIBLE("maxim,max1038", max1038), 1542 MAX1363_COMPATIBLE("maxim,max1039", max1039), 1543 MAX1363_COMPATIBLE("maxim,max1136", max1136), 1544 MAX1363_COMPATIBLE("maxim,max1137", max1137), 1545 MAX1363_COMPATIBLE("maxim,max1138", max1138), 1546 MAX1363_COMPATIBLE("maxim,max1139", max1139), 1547 MAX1363_COMPATIBLE("maxim,max1236", max1236), 1548 MAX1363_COMPATIBLE("maxim,max1237", max1237), 1549 MAX1363_COMPATIBLE("maxim,max1238", max1238), 1550 MAX1363_COMPATIBLE("maxim,max1239", max1239), 1551 MAX1363_COMPATIBLE("maxim,max11600", max11600), 1552 MAX1363_COMPATIBLE("maxim,max11601", max11601), 1553 MAX1363_COMPATIBLE("maxim,max11602", max11602), 1554 MAX1363_COMPATIBLE("maxim,max11603", max11603), 1555 MAX1363_COMPATIBLE("maxim,max11604", max11604), 1556 MAX1363_COMPATIBLE("maxim,max11605", max11605), 1557 MAX1363_COMPATIBLE("maxim,max11606", max11606), 1558 MAX1363_COMPATIBLE("maxim,max11607", max11607), 1559 MAX1363_COMPATIBLE("maxim,max11608", max11608), 1560 MAX1363_COMPATIBLE("maxim,max11609", max11609), 1561 MAX1363_COMPATIBLE("maxim,max11610", max11610), 1562 MAX1363_COMPATIBLE("maxim,max11611", max11611), 1563 MAX1363_COMPATIBLE("maxim,max11612", max11612), 1564 MAX1363_COMPATIBLE("maxim,max11613", max11613), 1565 MAX1363_COMPATIBLE("maxim,max11614", max11614), 1566 MAX1363_COMPATIBLE("maxim,max11615", max11615), 1567 MAX1363_COMPATIBLE("maxim,max11616", max11616), 1568 MAX1363_COMPATIBLE("maxim,max11617", max11617), 1569 MAX1363_COMPATIBLE("maxim,max11644", max11644), 1570 MAX1363_COMPATIBLE("maxim,max11645", max11645), 1571 MAX1363_COMPATIBLE("maxim,max11646", max11646), 1572 MAX1363_COMPATIBLE("maxim,max11647", max11647), 1573 { /* sentinel */ } 1574}; 1575MODULE_DEVICE_TABLE(of, max1363_of_match); 1576 1577static void max1363_reg_disable(void *reg) 1578{ 1579 regulator_disable(reg); 1580} 1581 1582static int max1363_probe(struct i2c_client *client) 1583{ 1584 const struct i2c_device_id *id = i2c_client_get_device_id(client); 1585 int ret; 1586 struct max1363_state *st; 1587 struct iio_dev *indio_dev; 1588 struct regulator *vref; 1589 1590 indio_dev = devm_iio_device_alloc(&client->dev, 1591 sizeof(struct max1363_state)); 1592 if (!indio_dev) 1593 return -ENOMEM; 1594 1595 st = iio_priv(indio_dev); 1596 1597 mutex_init(&st->lock); 1598 ret = devm_regulator_get_enable(&client->dev, "vcc"); 1599 if (ret) 1600 return ret; 1601 1602 st->chip_info = device_get_match_data(&client->dev); 1603 if (!st->chip_info) 1604 st->chip_info = &max1363_chip_info_tbl[id->driver_data]; 1605 st->client = client; 1606 1607 st->vref_uv = st->chip_info->int_vref_mv * 1000; 1608 vref = devm_regulator_get_optional(&client->dev, "vref"); 1609 if (!IS_ERR(vref)) { 1610 int vref_uv; 1611 1612 ret = regulator_enable(vref); 1613 if (ret) 1614 return ret; 1615 1616 ret = devm_add_action_or_reset(&client->dev, max1363_reg_disable, vref); 1617 if (ret) 1618 return ret; 1619 1620 st->vref = vref; 1621 vref_uv = regulator_get_voltage(vref); 1622 if (vref_uv <= 0) 1623 return -EINVAL; 1624 1625 st->vref_uv = vref_uv; 1626 } 1627 1628 if (i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) { 1629 st->send = i2c_master_send; 1630 st->recv = i2c_master_recv; 1631 } else if (i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE) 1632 && st->chip_info->bits == 8) { 1633 st->send = max1363_smbus_send; 1634 st->recv = max1363_smbus_recv; 1635 } else { 1636 return -EOPNOTSUPP; 1637 } 1638 1639 ret = max1363_alloc_scan_masks(indio_dev); 1640 if (ret) 1641 return ret; 1642 1643 indio_dev->name = id->name; 1644 indio_dev->channels = st->chip_info->channels; 1645 indio_dev->num_channels = st->chip_info->num_channels; 1646 indio_dev->info = st->chip_info->info; 1647 indio_dev->modes = INDIO_DIRECT_MODE; 1648 ret = max1363_initial_setup(st); 1649 if (ret < 0) 1650 return ret; 1651 1652 ret = devm_iio_triggered_buffer_setup(&client->dev, indio_dev, NULL, 1653 &max1363_trigger_handler, NULL); 1654 if (ret) 1655 return ret; 1656 1657 if (client->irq) { 1658 ret = devm_request_threaded_irq(&client->dev, st->client->irq, 1659 NULL, 1660 &max1363_event_handler, 1661 IRQF_TRIGGER_RISING | IRQF_ONESHOT, 1662 "max1363_event", 1663 indio_dev); 1664 1665 if (ret) 1666 return ret; 1667 } 1668 1669 return devm_iio_device_register(&client->dev, indio_dev); 1670} 1671 1672static const struct i2c_device_id max1363_id[] = { 1673 { "max1361", max1361 }, 1674 { "max1362", max1362 }, 1675 { "max1363", max1363 }, 1676 { "max1364", max1364 }, 1677 { "max1036", max1036 }, 1678 { "max1037", max1037 }, 1679 { "max1038", max1038 }, 1680 { "max1039", max1039 }, 1681 { "max1136", max1136 }, 1682 { "max1137", max1137 }, 1683 { "max1138", max1138 }, 1684 { "max1139", max1139 }, 1685 { "max1236", max1236 }, 1686 { "max1237", max1237 }, 1687 { "max1238", max1238 }, 1688 { "max1239", max1239 }, 1689 { "max11600", max11600 }, 1690 { "max11601", max11601 }, 1691 { "max11602", max11602 }, 1692 { "max11603", max11603 }, 1693 { "max11604", max11604 }, 1694 { "max11605", max11605 }, 1695 { "max11606", max11606 }, 1696 { "max11607", max11607 }, 1697 { "max11608", max11608 }, 1698 { "max11609", max11609 }, 1699 { "max11610", max11610 }, 1700 { "max11611", max11611 }, 1701 { "max11612", max11612 }, 1702 { "max11613", max11613 }, 1703 { "max11614", max11614 }, 1704 { "max11615", max11615 }, 1705 { "max11616", max11616 }, 1706 { "max11617", max11617 }, 1707 { "max11644", max11644 }, 1708 { "max11645", max11645 }, 1709 { "max11646", max11646 }, 1710 { "max11647", max11647 }, 1711 {} 1712}; 1713 1714MODULE_DEVICE_TABLE(i2c, max1363_id); 1715 1716static struct i2c_driver max1363_driver = { 1717 .driver = { 1718 .name = "max1363", 1719 .of_match_table = max1363_of_match, 1720 }, 1721 .probe = max1363_probe, 1722 .id_table = max1363_id, 1723}; 1724module_i2c_driver(max1363_driver); 1725 1726MODULE_AUTHOR("Jonathan Cameron <jic23@kernel.org>"); 1727MODULE_DESCRIPTION("Maxim 1363 ADC"); 1728MODULE_LICENSE("GPL v2"); 1729