1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * Driver for the ADC present in the Atmel AT91 evaluation boards. 4 * 5 * Copyright 2011 Free Electrons 6 */ 7 8#include <linux/bitmap.h> 9#include <linux/bitops.h> 10#include <linux/clk.h> 11#include <linux/err.h> 12#include <linux/io.h> 13#include <linux/input.h> 14#include <linux/interrupt.h> 15#include <linux/jiffies.h> 16#include <linux/kernel.h> 17#include <linux/module.h> 18#include <linux/of.h> 19#include <linux/platform_device.h> 20#include <linux/sched.h> 21#include <linux/slab.h> 22#include <linux/wait.h> 23 24#include <linux/iio/iio.h> 25#include <linux/iio/buffer.h> 26#include <linux/iio/trigger.h> 27#include <linux/iio/trigger_consumer.h> 28#include <linux/iio/triggered_buffer.h> 29#include <linux/pinctrl/consumer.h> 30 31/* Registers */ 32#define AT91_ADC_CR 0x00 /* Control Register */ 33#define AT91_ADC_SWRST (1 << 0) /* Software Reset */ 34#define AT91_ADC_START (1 << 1) /* Start Conversion */ 35 36#define AT91_ADC_MR 0x04 /* Mode Register */ 37#define AT91_ADC_TSAMOD (3 << 0) /* ADC mode */ 38#define AT91_ADC_TSAMOD_ADC_ONLY_MODE (0 << 0) /* ADC Mode */ 39#define AT91_ADC_TSAMOD_TS_ONLY_MODE (1 << 0) /* Touch Screen Only Mode */ 40#define AT91_ADC_TRGEN (1 << 0) /* Trigger Enable */ 41#define AT91_ADC_TRGSEL (7 << 1) /* Trigger Selection */ 42#define AT91_ADC_TRGSEL_TC0 (0 << 1) 43#define AT91_ADC_TRGSEL_TC1 (1 << 1) 44#define AT91_ADC_TRGSEL_TC2 (2 << 1) 45#define AT91_ADC_TRGSEL_EXTERNAL (6 << 1) 46#define AT91_ADC_LOWRES (1 << 4) /* Low Resolution */ 47#define AT91_ADC_SLEEP (1 << 5) /* Sleep Mode */ 48#define AT91_ADC_PENDET (1 << 6) /* Pen contact detection enable */ 49#define AT91_ADC_PRESCAL_9260 (0x3f << 8) /* Prescalar Rate Selection */ 50#define AT91_ADC_PRESCAL_9G45 (0xff << 8) 51#define AT91_ADC_PRESCAL_(x) ((x) << 8) 52#define AT91_ADC_STARTUP_9260 (0x1f << 16) /* Startup Up Time */ 53#define AT91_ADC_STARTUP_9G45 (0x7f << 16) 54#define AT91_ADC_STARTUP_9X5 (0xf << 16) 55#define AT91_ADC_STARTUP_(x) ((x) << 16) 56#define AT91_ADC_SHTIM (0xf << 24) /* Sample & Hold Time */ 57#define AT91_ADC_SHTIM_(x) ((x) << 24) 58#define AT91_ADC_PENDBC (0x0f << 28) /* Pen Debounce time */ 59#define AT91_ADC_PENDBC_(x) ((x) << 28) 60 61#define AT91_ADC_TSR 0x0C 62#define AT91_ADC_TSR_SHTIM (0xf << 24) /* Sample & Hold Time */ 63#define AT91_ADC_TSR_SHTIM_(x) ((x) << 24) 64 65#define AT91_ADC_CHER 0x10 /* Channel Enable Register */ 66#define AT91_ADC_CHDR 0x14 /* Channel Disable Register */ 67#define AT91_ADC_CHSR 0x18 /* Channel Status Register */ 68#define AT91_ADC_CH(n) (1 << (n)) /* Channel Number */ 69 70#define AT91_ADC_SR 0x1C /* Status Register */ 71#define AT91_ADC_EOC(n) (1 << (n)) /* End of Conversion on Channel N */ 72#define AT91_ADC_OVRE(n) (1 << ((n) + 8))/* Overrun Error on Channel N */ 73#define AT91_ADC_DRDY (1 << 16) /* Data Ready */ 74#define AT91_ADC_GOVRE (1 << 17) /* General Overrun Error */ 75#define AT91_ADC_ENDRX (1 << 18) /* End of RX Buffer */ 76#define AT91_ADC_RXFUFF (1 << 19) /* RX Buffer Full */ 77 78#define AT91_ADC_SR_9X5 0x30 /* Status Register for 9x5 */ 79#define AT91_ADC_SR_DRDY_9X5 (1 << 24) /* Data Ready */ 80 81#define AT91_ADC_LCDR 0x20 /* Last Converted Data Register */ 82#define AT91_ADC_LDATA (0x3ff) 83 84#define AT91_ADC_IER 0x24 /* Interrupt Enable Register */ 85#define AT91_ADC_IDR 0x28 /* Interrupt Disable Register */ 86#define AT91_ADC_IMR 0x2C /* Interrupt Mask Register */ 87#define AT91RL_ADC_IER_PEN (1 << 20) 88#define AT91RL_ADC_IER_NOPEN (1 << 21) 89#define AT91_ADC_IER_PEN (1 << 29) 90#define AT91_ADC_IER_NOPEN (1 << 30) 91#define AT91_ADC_IER_XRDY (1 << 20) 92#define AT91_ADC_IER_YRDY (1 << 21) 93#define AT91_ADC_IER_PRDY (1 << 22) 94#define AT91_ADC_ISR_PENS (1 << 31) 95 96#define AT91_ADC_CHR(n) (0x30 + ((n) * 4)) /* Channel Data Register N */ 97#define AT91_ADC_DATA (0x3ff) 98 99#define AT91_ADC_CDR0_9X5 (0x50) /* Channel Data Register 0 for 9X5 */ 100 101#define AT91_ADC_ACR 0x94 /* Analog Control Register */ 102#define AT91_ADC_ACR_PENDETSENS (0x3 << 0) /* pull-up resistor */ 103 104#define AT91_ADC_TSMR 0xB0 105#define AT91_ADC_TSMR_TSMODE (3 << 0) /* Touch Screen Mode */ 106#define AT91_ADC_TSMR_TSMODE_NONE (0 << 0) 107#define AT91_ADC_TSMR_TSMODE_4WIRE_NO_PRESS (1 << 0) 108#define AT91_ADC_TSMR_TSMODE_4WIRE_PRESS (2 << 0) 109#define AT91_ADC_TSMR_TSMODE_5WIRE (3 << 0) 110#define AT91_ADC_TSMR_TSAV (3 << 4) /* Averages samples */ 111#define AT91_ADC_TSMR_TSAV_(x) ((x) << 4) 112#define AT91_ADC_TSMR_SCTIM (0x0f << 16) /* Switch closure time */ 113#define AT91_ADC_TSMR_SCTIM_(x) ((x) << 16) 114#define AT91_ADC_TSMR_PENDBC (0x0f << 28) /* Pen Debounce time */ 115#define AT91_ADC_TSMR_PENDBC_(x) ((x) << 28) 116#define AT91_ADC_TSMR_NOTSDMA (1 << 22) /* No Touchscreen DMA */ 117#define AT91_ADC_TSMR_PENDET_DIS (0 << 24) /* Pen contact detection disable */ 118#define AT91_ADC_TSMR_PENDET_ENA (1 << 24) /* Pen contact detection enable */ 119 120#define AT91_ADC_TSXPOSR 0xB4 121#define AT91_ADC_TSYPOSR 0xB8 122#define AT91_ADC_TSPRESSR 0xBC 123 124#define AT91_ADC_TRGR_9260 AT91_ADC_MR 125#define AT91_ADC_TRGR_9G45 0x08 126#define AT91_ADC_TRGR_9X5 0xC0 127 128/* Trigger Register bit field */ 129#define AT91_ADC_TRGR_TRGPER (0xffff << 16) 130#define AT91_ADC_TRGR_TRGPER_(x) ((x) << 16) 131#define AT91_ADC_TRGR_TRGMOD (0x7 << 0) 132#define AT91_ADC_TRGR_NONE (0 << 0) 133#define AT91_ADC_TRGR_MOD_PERIOD_TRIG (5 << 0) 134 135#define AT91_ADC_CHAN(st, ch) \ 136 (st->registers->channel_base + (ch * 4)) 137#define at91_adc_readl(st, reg) \ 138 (readl_relaxed(st->reg_base + reg)) 139#define at91_adc_writel(st, reg, val) \ 140 (writel_relaxed(val, st->reg_base + reg)) 141 142#define DRIVER_NAME "at91_adc" 143#define MAX_POS_BITS 12 144 145#define TOUCH_SAMPLE_PERIOD_US 2000 /* 2ms */ 146#define TOUCH_PEN_DETECT_DEBOUNCE_US 200 147 148#define MAX_RLPOS_BITS 10 149#define TOUCH_SAMPLE_PERIOD_US_RL 10000 /* 10ms, the SoC can't keep up with 2ms */ 150#define TOUCH_SHTIM 0xa 151#define TOUCH_SCTIM_US 10 /* 10us for the Touchscreen Switches Closure Time */ 152 153enum atmel_adc_ts_type { 154 ATMEL_ADC_TOUCHSCREEN_NONE = 0, 155 ATMEL_ADC_TOUCHSCREEN_4WIRE = 4, 156 ATMEL_ADC_TOUCHSCREEN_5WIRE = 5, 157}; 158 159/** 160 * struct at91_adc_trigger - description of triggers 161 * @name: name of the trigger advertised to the user 162 * @value: value to set in the ADC's trigger setup register 163 * to enable the trigger 164 * @is_external: Does the trigger rely on an external pin? 165 */ 166struct at91_adc_trigger { 167 const char *name; 168 u8 value; 169 bool is_external; 170}; 171 172/** 173 * struct at91_adc_reg_desc - Various informations relative to registers 174 * @channel_base: Base offset for the channel data registers 175 * @drdy_mask: Mask of the DRDY field in the relevant registers 176 * (Interruptions registers mostly) 177 * @status_register: Offset of the Interrupt Status Register 178 * @trigger_register: Offset of the Trigger setup register 179 * @mr_prescal_mask: Mask of the PRESCAL field in the adc MR register 180 * @mr_startup_mask: Mask of the STARTUP field in the adc MR register 181 */ 182struct at91_adc_reg_desc { 183 u8 channel_base; 184 u32 drdy_mask; 185 u8 status_register; 186 u8 trigger_register; 187 u32 mr_prescal_mask; 188 u32 mr_startup_mask; 189}; 190 191struct at91_adc_caps { 192 bool has_ts; /* Support touch screen */ 193 bool has_tsmr; /* only at91sam9x5, sama5d3 have TSMR reg */ 194 /* 195 * Numbers of sampling data will be averaged. Can be 0~3. 196 * Hardware can average (2 ^ ts_filter_average) sample data. 197 */ 198 u8 ts_filter_average; 199 /* Pen Detection input pull-up resistor, can be 0~3 */ 200 u8 ts_pen_detect_sensitivity; 201 202 /* startup time calculate function */ 203 u32 (*calc_startup_ticks)(u32 startup_time, u32 adc_clk_khz); 204 205 u8 num_channels; 206 207 u8 low_res_bits; 208 u8 high_res_bits; 209 u32 trigger_number; 210 const struct at91_adc_trigger *triggers; 211 struct at91_adc_reg_desc registers; 212}; 213 214struct at91_adc_state { 215 struct clk *adc_clk; 216 u16 *buffer; 217 unsigned long channels_mask; 218 struct clk *clk; 219 bool done; 220 int irq; 221 u16 last_value; 222 int chnb; 223 struct mutex lock; 224 u8 num_channels; 225 void __iomem *reg_base; 226 const struct at91_adc_reg_desc *registers; 227 u32 startup_time; 228 u8 sample_hold_time; 229 bool sleep_mode; 230 struct iio_trigger **trig; 231 bool use_external; 232 u32 vref_mv; 233 u32 res; /* resolution used for convertions */ 234 wait_queue_head_t wq_data_avail; 235 const struct at91_adc_caps *caps; 236 237 /* 238 * Following ADC channels are shared by touchscreen: 239 * 240 * CH0 -- Touch screen XP/UL 241 * CH1 -- Touch screen XM/UR 242 * CH2 -- Touch screen YP/LL 243 * CH3 -- Touch screen YM/Sense 244 * CH4 -- Touch screen LR(5-wire only) 245 * 246 * The bitfields below represents the reserved channel in the 247 * touchscreen mode. 248 */ 249#define CHAN_MASK_TOUCHSCREEN_4WIRE (0xf << 0) 250#define CHAN_MASK_TOUCHSCREEN_5WIRE (0x1f << 0) 251 enum atmel_adc_ts_type touchscreen_type; 252 struct input_dev *ts_input; 253 254 u16 ts_sample_period_val; 255 u32 ts_pressure_threshold; 256 u16 ts_pendbc; 257 258 bool ts_bufferedmeasure; 259 u32 ts_prev_absx; 260 u32 ts_prev_absy; 261}; 262 263static irqreturn_t at91_adc_trigger_handler(int irq, void *p) 264{ 265 struct iio_poll_func *pf = p; 266 struct iio_dev *idev = pf->indio_dev; 267 struct at91_adc_state *st = iio_priv(idev); 268 struct iio_chan_spec const *chan; 269 int i, j = 0; 270 271 for (i = 0; i < idev->masklength; i++) { 272 if (!test_bit(i, idev->active_scan_mask)) 273 continue; 274 chan = idev->channels + i; 275 st->buffer[j] = at91_adc_readl(st, AT91_ADC_CHAN(st, chan->channel)); 276 j++; 277 } 278 279 iio_push_to_buffers_with_timestamp(idev, st->buffer, pf->timestamp); 280 281 iio_trigger_notify_done(idev->trig); 282 283 /* Needed to ACK the DRDY interruption */ 284 at91_adc_readl(st, AT91_ADC_LCDR); 285 286 enable_irq(st->irq); 287 288 return IRQ_HANDLED; 289} 290 291/* Handler for classic adc channel eoc trigger */ 292static void handle_adc_eoc_trigger(int irq, struct iio_dev *idev) 293{ 294 struct at91_adc_state *st = iio_priv(idev); 295 296 if (iio_buffer_enabled(idev)) { 297 disable_irq_nosync(irq); 298 iio_trigger_poll(idev->trig); 299 } else { 300 st->last_value = at91_adc_readl(st, AT91_ADC_CHAN(st, st->chnb)); 301 /* Needed to ACK the DRDY interruption */ 302 at91_adc_readl(st, AT91_ADC_LCDR); 303 st->done = true; 304 wake_up_interruptible(&st->wq_data_avail); 305 } 306} 307 308static int at91_ts_sample(struct iio_dev *idev) 309{ 310 struct at91_adc_state *st = iio_priv(idev); 311 unsigned int xscale, yscale, reg, z1, z2; 312 unsigned int x, y, pres, xpos, ypos; 313 unsigned int rxp = 1; 314 unsigned int factor = 1000; 315 316 unsigned int xyz_mask_bits = st->res; 317 unsigned int xyz_mask = (1 << xyz_mask_bits) - 1; 318 319 /* calculate position */ 320 /* x position = (x / xscale) * max, max = 2^MAX_POS_BITS - 1 */ 321 reg = at91_adc_readl(st, AT91_ADC_TSXPOSR); 322 xpos = reg & xyz_mask; 323 x = (xpos << MAX_POS_BITS) - xpos; 324 xscale = (reg >> 16) & xyz_mask; 325 if (xscale == 0) { 326 dev_err(&idev->dev, "Error: xscale == 0!\n"); 327 return -1; 328 } 329 x /= xscale; 330 331 /* y position = (y / yscale) * max, max = 2^MAX_POS_BITS - 1 */ 332 reg = at91_adc_readl(st, AT91_ADC_TSYPOSR); 333 ypos = reg & xyz_mask; 334 y = (ypos << MAX_POS_BITS) - ypos; 335 yscale = (reg >> 16) & xyz_mask; 336 if (yscale == 0) { 337 dev_err(&idev->dev, "Error: yscale == 0!\n"); 338 return -1; 339 } 340 y /= yscale; 341 342 /* calculate the pressure */ 343 reg = at91_adc_readl(st, AT91_ADC_TSPRESSR); 344 z1 = reg & xyz_mask; 345 z2 = (reg >> 16) & xyz_mask; 346 347 if (z1 != 0) 348 pres = rxp * (x * factor / 1024) * (z2 * factor / z1 - factor) 349 / factor; 350 else 351 pres = st->ts_pressure_threshold; /* no pen contacted */ 352 353 dev_dbg(&idev->dev, "xpos = %d, xscale = %d, ypos = %d, yscale = %d, z1 = %d, z2 = %d, press = %d\n", 354 xpos, xscale, ypos, yscale, z1, z2, pres); 355 356 if (pres < st->ts_pressure_threshold) { 357 dev_dbg(&idev->dev, "x = %d, y = %d, pressure = %d\n", 358 x, y, pres / factor); 359 input_report_abs(st->ts_input, ABS_X, x); 360 input_report_abs(st->ts_input, ABS_Y, y); 361 input_report_abs(st->ts_input, ABS_PRESSURE, pres); 362 input_report_key(st->ts_input, BTN_TOUCH, 1); 363 input_sync(st->ts_input); 364 } else { 365 dev_dbg(&idev->dev, "pressure too low: not reporting\n"); 366 } 367 368 return 0; 369} 370 371static irqreturn_t at91_adc_rl_interrupt(int irq, void *private) 372{ 373 struct iio_dev *idev = private; 374 struct at91_adc_state *st = iio_priv(idev); 375 u32 status = at91_adc_readl(st, st->registers->status_register); 376 unsigned int reg; 377 378 status &= at91_adc_readl(st, AT91_ADC_IMR); 379 if (status & GENMASK(st->num_channels - 1, 0)) 380 handle_adc_eoc_trigger(irq, idev); 381 382 if (status & AT91RL_ADC_IER_PEN) { 383 /* Disabling pen debounce is required to get a NOPEN irq */ 384 reg = at91_adc_readl(st, AT91_ADC_MR); 385 reg &= ~AT91_ADC_PENDBC; 386 at91_adc_writel(st, AT91_ADC_MR, reg); 387 388 at91_adc_writel(st, AT91_ADC_IDR, AT91RL_ADC_IER_PEN); 389 at91_adc_writel(st, AT91_ADC_IER, AT91RL_ADC_IER_NOPEN 390 | AT91_ADC_EOC(3)); 391 /* Set up period trigger for sampling */ 392 at91_adc_writel(st, st->registers->trigger_register, 393 AT91_ADC_TRGR_MOD_PERIOD_TRIG | 394 AT91_ADC_TRGR_TRGPER_(st->ts_sample_period_val)); 395 } else if (status & AT91RL_ADC_IER_NOPEN) { 396 reg = at91_adc_readl(st, AT91_ADC_MR); 397 reg |= AT91_ADC_PENDBC_(st->ts_pendbc) & AT91_ADC_PENDBC; 398 at91_adc_writel(st, AT91_ADC_MR, reg); 399 at91_adc_writel(st, st->registers->trigger_register, 400 AT91_ADC_TRGR_NONE); 401 402 at91_adc_writel(st, AT91_ADC_IDR, AT91RL_ADC_IER_NOPEN 403 | AT91_ADC_EOC(3)); 404 at91_adc_writel(st, AT91_ADC_IER, AT91RL_ADC_IER_PEN); 405 st->ts_bufferedmeasure = false; 406 input_report_key(st->ts_input, BTN_TOUCH, 0); 407 input_sync(st->ts_input); 408 } else if (status & AT91_ADC_EOC(3) && st->ts_input) { 409 /* Conversion finished and we've a touchscreen */ 410 if (st->ts_bufferedmeasure) { 411 /* 412 * Last measurement is always discarded, since it can 413 * be erroneous. 414 * Always report previous measurement 415 */ 416 input_report_abs(st->ts_input, ABS_X, st->ts_prev_absx); 417 input_report_abs(st->ts_input, ABS_Y, st->ts_prev_absy); 418 input_report_key(st->ts_input, BTN_TOUCH, 1); 419 input_sync(st->ts_input); 420 } else 421 st->ts_bufferedmeasure = true; 422 423 /* Now make new measurement */ 424 st->ts_prev_absx = at91_adc_readl(st, AT91_ADC_CHAN(st, 3)) 425 << MAX_RLPOS_BITS; 426 st->ts_prev_absx /= at91_adc_readl(st, AT91_ADC_CHAN(st, 2)); 427 428 st->ts_prev_absy = at91_adc_readl(st, AT91_ADC_CHAN(st, 1)) 429 << MAX_RLPOS_BITS; 430 st->ts_prev_absy /= at91_adc_readl(st, AT91_ADC_CHAN(st, 0)); 431 } 432 433 return IRQ_HANDLED; 434} 435 436static irqreturn_t at91_adc_9x5_interrupt(int irq, void *private) 437{ 438 struct iio_dev *idev = private; 439 struct at91_adc_state *st = iio_priv(idev); 440 u32 status = at91_adc_readl(st, st->registers->status_register); 441 const uint32_t ts_data_irq_mask = 442 AT91_ADC_IER_XRDY | 443 AT91_ADC_IER_YRDY | 444 AT91_ADC_IER_PRDY; 445 446 if (status & GENMASK(st->num_channels - 1, 0)) 447 handle_adc_eoc_trigger(irq, idev); 448 449 if (status & AT91_ADC_IER_PEN) { 450 at91_adc_writel(st, AT91_ADC_IDR, AT91_ADC_IER_PEN); 451 at91_adc_writel(st, AT91_ADC_IER, AT91_ADC_IER_NOPEN | 452 ts_data_irq_mask); 453 /* Set up period trigger for sampling */ 454 at91_adc_writel(st, st->registers->trigger_register, 455 AT91_ADC_TRGR_MOD_PERIOD_TRIG | 456 AT91_ADC_TRGR_TRGPER_(st->ts_sample_period_val)); 457 } else if (status & AT91_ADC_IER_NOPEN) { 458 at91_adc_writel(st, st->registers->trigger_register, 0); 459 at91_adc_writel(st, AT91_ADC_IDR, AT91_ADC_IER_NOPEN | 460 ts_data_irq_mask); 461 at91_adc_writel(st, AT91_ADC_IER, AT91_ADC_IER_PEN); 462 463 input_report_key(st->ts_input, BTN_TOUCH, 0); 464 input_sync(st->ts_input); 465 } else if ((status & ts_data_irq_mask) == ts_data_irq_mask) { 466 /* Now all touchscreen data is ready */ 467 468 if (status & AT91_ADC_ISR_PENS) { 469 /* validate data by pen contact */ 470 at91_ts_sample(idev); 471 } else { 472 /* triggered by event that is no pen contact, just read 473 * them to clean the interrupt and discard all. 474 */ 475 at91_adc_readl(st, AT91_ADC_TSXPOSR); 476 at91_adc_readl(st, AT91_ADC_TSYPOSR); 477 at91_adc_readl(st, AT91_ADC_TSPRESSR); 478 } 479 } 480 481 return IRQ_HANDLED; 482} 483 484static int at91_adc_channel_init(struct iio_dev *idev) 485{ 486 struct at91_adc_state *st = iio_priv(idev); 487 struct iio_chan_spec *chan_array, *timestamp; 488 int bit, idx = 0; 489 unsigned long rsvd_mask = 0; 490 491 /* If touchscreen is enable, then reserve the adc channels */ 492 if (st->touchscreen_type == ATMEL_ADC_TOUCHSCREEN_4WIRE) 493 rsvd_mask = CHAN_MASK_TOUCHSCREEN_4WIRE; 494 else if (st->touchscreen_type == ATMEL_ADC_TOUCHSCREEN_5WIRE) 495 rsvd_mask = CHAN_MASK_TOUCHSCREEN_5WIRE; 496 497 /* set up the channel mask to reserve touchscreen channels */ 498 st->channels_mask &= ~rsvd_mask; 499 500 idev->num_channels = bitmap_weight(&st->channels_mask, 501 st->num_channels) + 1; 502 503 chan_array = devm_kzalloc(&idev->dev, 504 ((idev->num_channels + 1) * 505 sizeof(struct iio_chan_spec)), 506 GFP_KERNEL); 507 508 if (!chan_array) 509 return -ENOMEM; 510 511 for_each_set_bit(bit, &st->channels_mask, st->num_channels) { 512 struct iio_chan_spec *chan = chan_array + idx; 513 514 chan->type = IIO_VOLTAGE; 515 chan->indexed = 1; 516 chan->channel = bit; 517 chan->scan_index = idx; 518 chan->scan_type.sign = 'u'; 519 chan->scan_type.realbits = st->res; 520 chan->scan_type.storagebits = 16; 521 chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE); 522 chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW); 523 idx++; 524 } 525 timestamp = chan_array + idx; 526 527 timestamp->type = IIO_TIMESTAMP; 528 timestamp->channel = -1; 529 timestamp->scan_index = idx; 530 timestamp->scan_type.sign = 's'; 531 timestamp->scan_type.realbits = 64; 532 timestamp->scan_type.storagebits = 64; 533 534 idev->channels = chan_array; 535 return idev->num_channels; 536} 537 538static int at91_adc_get_trigger_value_by_name(struct iio_dev *idev, 539 const struct at91_adc_trigger *triggers, 540 const char *trigger_name) 541{ 542 struct at91_adc_state *st = iio_priv(idev); 543 int i; 544 545 for (i = 0; i < st->caps->trigger_number; i++) { 546 char *name = kasprintf(GFP_KERNEL, 547 "%s-dev%d-%s", 548 idev->name, 549 iio_device_id(idev), 550 triggers[i].name); 551 if (!name) 552 return -ENOMEM; 553 554 if (strcmp(trigger_name, name) == 0) { 555 kfree(name); 556 if (triggers[i].value == 0) 557 return -EINVAL; 558 return triggers[i].value; 559 } 560 561 kfree(name); 562 } 563 564 return -EINVAL; 565} 566 567static int at91_adc_configure_trigger(struct iio_trigger *trig, bool state) 568{ 569 struct iio_dev *idev = iio_trigger_get_drvdata(trig); 570 struct at91_adc_state *st = iio_priv(idev); 571 const struct at91_adc_reg_desc *reg = st->registers; 572 u32 status = at91_adc_readl(st, reg->trigger_register); 573 int value; 574 u8 bit; 575 576 value = at91_adc_get_trigger_value_by_name(idev, 577 st->caps->triggers, 578 idev->trig->name); 579 if (value < 0) 580 return value; 581 582 if (state) { 583 st->buffer = kmalloc(idev->scan_bytes, GFP_KERNEL); 584 if (st->buffer == NULL) 585 return -ENOMEM; 586 587 at91_adc_writel(st, reg->trigger_register, 588 status | value); 589 590 for_each_set_bit(bit, idev->active_scan_mask, 591 st->num_channels) { 592 struct iio_chan_spec const *chan = idev->channels + bit; 593 at91_adc_writel(st, AT91_ADC_CHER, 594 AT91_ADC_CH(chan->channel)); 595 } 596 597 at91_adc_writel(st, AT91_ADC_IER, reg->drdy_mask); 598 599 } else { 600 at91_adc_writel(st, AT91_ADC_IDR, reg->drdy_mask); 601 602 at91_adc_writel(st, reg->trigger_register, 603 status & ~value); 604 605 for_each_set_bit(bit, idev->active_scan_mask, 606 st->num_channels) { 607 struct iio_chan_spec const *chan = idev->channels + bit; 608 at91_adc_writel(st, AT91_ADC_CHDR, 609 AT91_ADC_CH(chan->channel)); 610 } 611 kfree(st->buffer); 612 } 613 614 return 0; 615} 616 617static const struct iio_trigger_ops at91_adc_trigger_ops = { 618 .set_trigger_state = &at91_adc_configure_trigger, 619}; 620 621static struct iio_trigger *at91_adc_allocate_trigger(struct iio_dev *idev, 622 const struct at91_adc_trigger *trigger) 623{ 624 struct iio_trigger *trig; 625 int ret; 626 627 trig = iio_trigger_alloc(idev->dev.parent, "%s-dev%d-%s", idev->name, 628 iio_device_id(idev), trigger->name); 629 if (trig == NULL) 630 return NULL; 631 632 iio_trigger_set_drvdata(trig, idev); 633 trig->ops = &at91_adc_trigger_ops; 634 635 ret = iio_trigger_register(trig); 636 if (ret) { 637 iio_trigger_free(trig); 638 return NULL; 639 } 640 641 return trig; 642} 643 644static int at91_adc_trigger_init(struct iio_dev *idev) 645{ 646 struct at91_adc_state *st = iio_priv(idev); 647 int i, ret; 648 649 st->trig = devm_kcalloc(&idev->dev, 650 st->caps->trigger_number, sizeof(*st->trig), 651 GFP_KERNEL); 652 653 if (st->trig == NULL) { 654 ret = -ENOMEM; 655 goto error_ret; 656 } 657 658 for (i = 0; i < st->caps->trigger_number; i++) { 659 if (st->caps->triggers[i].is_external && !(st->use_external)) 660 continue; 661 662 st->trig[i] = at91_adc_allocate_trigger(idev, 663 st->caps->triggers + i); 664 if (st->trig[i] == NULL) { 665 dev_err(&idev->dev, 666 "Could not allocate trigger %d\n", i); 667 ret = -ENOMEM; 668 goto error_trigger; 669 } 670 } 671 672 return 0; 673 674error_trigger: 675 for (i--; i >= 0; i--) { 676 iio_trigger_unregister(st->trig[i]); 677 iio_trigger_free(st->trig[i]); 678 } 679error_ret: 680 return ret; 681} 682 683static void at91_adc_trigger_remove(struct iio_dev *idev) 684{ 685 struct at91_adc_state *st = iio_priv(idev); 686 int i; 687 688 for (i = 0; i < st->caps->trigger_number; i++) { 689 iio_trigger_unregister(st->trig[i]); 690 iio_trigger_free(st->trig[i]); 691 } 692} 693 694static int at91_adc_buffer_init(struct iio_dev *idev) 695{ 696 return iio_triggered_buffer_setup(idev, &iio_pollfunc_store_time, 697 &at91_adc_trigger_handler, NULL); 698} 699 700static void at91_adc_buffer_remove(struct iio_dev *idev) 701{ 702 iio_triggered_buffer_cleanup(idev); 703} 704 705static int at91_adc_read_raw(struct iio_dev *idev, 706 struct iio_chan_spec const *chan, 707 int *val, int *val2, long mask) 708{ 709 struct at91_adc_state *st = iio_priv(idev); 710 int ret; 711 712 switch (mask) { 713 case IIO_CHAN_INFO_RAW: 714 mutex_lock(&st->lock); 715 716 st->chnb = chan->channel; 717 at91_adc_writel(st, AT91_ADC_CHER, 718 AT91_ADC_CH(chan->channel)); 719 at91_adc_writel(st, AT91_ADC_IER, BIT(chan->channel)); 720 at91_adc_writel(st, AT91_ADC_CR, AT91_ADC_START); 721 722 ret = wait_event_interruptible_timeout(st->wq_data_avail, 723 st->done, 724 msecs_to_jiffies(1000)); 725 726 /* Disable interrupts, regardless if adc conversion was 727 * successful or not 728 */ 729 at91_adc_writel(st, AT91_ADC_CHDR, 730 AT91_ADC_CH(chan->channel)); 731 at91_adc_writel(st, AT91_ADC_IDR, BIT(chan->channel)); 732 733 if (ret > 0) { 734 /* a valid conversion took place */ 735 *val = st->last_value; 736 st->last_value = 0; 737 st->done = false; 738 ret = IIO_VAL_INT; 739 } else if (ret == 0) { 740 /* conversion timeout */ 741 dev_err(&idev->dev, "ADC Channel %d timeout.\n", 742 chan->channel); 743 ret = -ETIMEDOUT; 744 } 745 746 mutex_unlock(&st->lock); 747 return ret; 748 749 case IIO_CHAN_INFO_SCALE: 750 *val = st->vref_mv; 751 *val2 = chan->scan_type.realbits; 752 return IIO_VAL_FRACTIONAL_LOG2; 753 default: 754 break; 755 } 756 return -EINVAL; 757} 758 759 760static u32 calc_startup_ticks_9260(u32 startup_time, u32 adc_clk_khz) 761{ 762 /* 763 * Number of ticks needed to cover the startup time of the ADC 764 * as defined in the electrical characteristics of the board, 765 * divided by 8. The formula thus is : 766 * Startup Time = (ticks + 1) * 8 / ADC Clock 767 */ 768 return round_up((startup_time * adc_clk_khz / 1000) - 1, 8) / 8; 769} 770 771static u32 calc_startup_ticks_9x5(u32 startup_time, u32 adc_clk_khz) 772{ 773 /* 774 * For sama5d3x and at91sam9x5, the formula changes to: 775 * Startup Time = <lookup_table_value> / ADC Clock 776 */ 777 static const int startup_lookup[] = { 778 0, 8, 16, 24, 779 64, 80, 96, 112, 780 512, 576, 640, 704, 781 768, 832, 896, 960 782 }; 783 int i, size = ARRAY_SIZE(startup_lookup); 784 unsigned int ticks; 785 786 ticks = startup_time * adc_clk_khz / 1000; 787 for (i = 0; i < size; i++) 788 if (ticks < startup_lookup[i]) 789 break; 790 791 ticks = i; 792 if (ticks == size) 793 /* Reach the end of lookup table */ 794 ticks = size - 1; 795 796 return ticks; 797} 798 799static int at91_adc_probe_dt_ts(struct device_node *node, 800 struct at91_adc_state *st, struct device *dev) 801{ 802 int ret; 803 u32 prop; 804 805 ret = of_property_read_u32(node, "atmel,adc-ts-wires", &prop); 806 if (ret) { 807 dev_info(dev, "ADC Touch screen is disabled.\n"); 808 return 0; 809 } 810 811 switch (prop) { 812 case 4: 813 case 5: 814 st->touchscreen_type = prop; 815 break; 816 default: 817 dev_err(dev, "Unsupported number of touchscreen wires (%d). Should be 4 or 5.\n", prop); 818 return -EINVAL; 819 } 820 821 if (!st->caps->has_tsmr) 822 return 0; 823 prop = 0; 824 of_property_read_u32(node, "atmel,adc-ts-pressure-threshold", &prop); 825 st->ts_pressure_threshold = prop; 826 if (st->ts_pressure_threshold) { 827 return 0; 828 } else { 829 dev_err(dev, "Invalid pressure threshold for the touchscreen\n"); 830 return -EINVAL; 831 } 832} 833 834static const struct iio_info at91_adc_info = { 835 .read_raw = &at91_adc_read_raw, 836}; 837 838/* Touchscreen related functions */ 839static int atmel_ts_open(struct input_dev *dev) 840{ 841 struct at91_adc_state *st = input_get_drvdata(dev); 842 843 if (st->caps->has_tsmr) 844 at91_adc_writel(st, AT91_ADC_IER, AT91_ADC_IER_PEN); 845 else 846 at91_adc_writel(st, AT91_ADC_IER, AT91RL_ADC_IER_PEN); 847 return 0; 848} 849 850static void atmel_ts_close(struct input_dev *dev) 851{ 852 struct at91_adc_state *st = input_get_drvdata(dev); 853 854 if (st->caps->has_tsmr) 855 at91_adc_writel(st, AT91_ADC_IDR, AT91_ADC_IER_PEN); 856 else 857 at91_adc_writel(st, AT91_ADC_IDR, AT91RL_ADC_IER_PEN); 858} 859 860static int at91_ts_hw_init(struct iio_dev *idev, u32 adc_clk_khz) 861{ 862 struct at91_adc_state *st = iio_priv(idev); 863 u32 reg = 0; 864 u32 tssctim = 0; 865 int i = 0; 866 867 /* a Pen Detect Debounce Time is necessary for the ADC Touch to avoid 868 * pen detect noise. 869 * The formula is : Pen Detect Debounce Time = (2 ^ pendbc) / ADCClock 870 */ 871 st->ts_pendbc = round_up(TOUCH_PEN_DETECT_DEBOUNCE_US * adc_clk_khz / 872 1000, 1); 873 874 while (st->ts_pendbc >> ++i) 875 ; /* Empty! Find the shift offset */ 876 if (abs(st->ts_pendbc - (1 << i)) < abs(st->ts_pendbc - (1 << (i - 1)))) 877 st->ts_pendbc = i; 878 else 879 st->ts_pendbc = i - 1; 880 881 if (!st->caps->has_tsmr) { 882 reg = at91_adc_readl(st, AT91_ADC_MR); 883 reg |= AT91_ADC_TSAMOD_TS_ONLY_MODE | AT91_ADC_PENDET; 884 885 reg |= AT91_ADC_PENDBC_(st->ts_pendbc) & AT91_ADC_PENDBC; 886 at91_adc_writel(st, AT91_ADC_MR, reg); 887 888 reg = AT91_ADC_TSR_SHTIM_(TOUCH_SHTIM) & AT91_ADC_TSR_SHTIM; 889 at91_adc_writel(st, AT91_ADC_TSR, reg); 890 891 st->ts_sample_period_val = round_up((TOUCH_SAMPLE_PERIOD_US_RL * 892 adc_clk_khz / 1000) - 1, 1); 893 894 return 0; 895 } 896 897 /* Touchscreen Switches Closure time needed for allowing the value to 898 * stabilize. 899 * Switch Closure Time = (TSSCTIM * 4) ADCClock periods 900 */ 901 tssctim = DIV_ROUND_UP(TOUCH_SCTIM_US * adc_clk_khz / 1000, 4); 902 dev_dbg(&idev->dev, "adc_clk at: %d KHz, tssctim at: %d\n", 903 adc_clk_khz, tssctim); 904 905 if (st->touchscreen_type == ATMEL_ADC_TOUCHSCREEN_4WIRE) 906 reg = AT91_ADC_TSMR_TSMODE_4WIRE_PRESS; 907 else 908 reg = AT91_ADC_TSMR_TSMODE_5WIRE; 909 910 reg |= AT91_ADC_TSMR_SCTIM_(tssctim) & AT91_ADC_TSMR_SCTIM; 911 reg |= AT91_ADC_TSMR_TSAV_(st->caps->ts_filter_average) 912 & AT91_ADC_TSMR_TSAV; 913 reg |= AT91_ADC_TSMR_PENDBC_(st->ts_pendbc) & AT91_ADC_TSMR_PENDBC; 914 reg |= AT91_ADC_TSMR_NOTSDMA; 915 reg |= AT91_ADC_TSMR_PENDET_ENA; 916 reg |= 0x03 << 8; /* TSFREQ, needs to be bigger than TSAV */ 917 918 at91_adc_writel(st, AT91_ADC_TSMR, reg); 919 920 /* Change adc internal resistor value for better pen detection, 921 * default value is 100 kOhm. 922 * 0 = 200 kOhm, 1 = 150 kOhm, 2 = 100 kOhm, 3 = 50 kOhm 923 * option only available on ES2 and higher 924 */ 925 at91_adc_writel(st, AT91_ADC_ACR, st->caps->ts_pen_detect_sensitivity 926 & AT91_ADC_ACR_PENDETSENS); 927 928 /* Sample Period Time = (TRGPER + 1) / ADCClock */ 929 st->ts_sample_period_val = round_up((TOUCH_SAMPLE_PERIOD_US * 930 adc_clk_khz / 1000) - 1, 1); 931 932 return 0; 933} 934 935static int at91_ts_register(struct iio_dev *idev, 936 struct platform_device *pdev) 937{ 938 struct at91_adc_state *st = iio_priv(idev); 939 struct input_dev *input; 940 int ret; 941 942 input = input_allocate_device(); 943 if (!input) { 944 dev_err(&idev->dev, "Failed to allocate TS device!\n"); 945 return -ENOMEM; 946 } 947 948 input->name = DRIVER_NAME; 949 input->id.bustype = BUS_HOST; 950 input->dev.parent = &pdev->dev; 951 input->open = atmel_ts_open; 952 input->close = atmel_ts_close; 953 954 __set_bit(EV_ABS, input->evbit); 955 __set_bit(EV_KEY, input->evbit); 956 __set_bit(BTN_TOUCH, input->keybit); 957 if (st->caps->has_tsmr) { 958 input_set_abs_params(input, ABS_X, 0, (1 << MAX_POS_BITS) - 1, 959 0, 0); 960 input_set_abs_params(input, ABS_Y, 0, (1 << MAX_POS_BITS) - 1, 961 0, 0); 962 input_set_abs_params(input, ABS_PRESSURE, 0, 0xffffff, 0, 0); 963 } else { 964 if (st->touchscreen_type != ATMEL_ADC_TOUCHSCREEN_4WIRE) { 965 dev_err(&pdev->dev, 966 "This touchscreen controller only support 4 wires\n"); 967 ret = -EINVAL; 968 goto err; 969 } 970 971 input_set_abs_params(input, ABS_X, 0, (1 << MAX_RLPOS_BITS) - 1, 972 0, 0); 973 input_set_abs_params(input, ABS_Y, 0, (1 << MAX_RLPOS_BITS) - 1, 974 0, 0); 975 } 976 977 st->ts_input = input; 978 input_set_drvdata(input, st); 979 980 ret = input_register_device(input); 981 if (ret) 982 goto err; 983 984 return ret; 985 986err: 987 input_free_device(st->ts_input); 988 return ret; 989} 990 991static void at91_ts_unregister(struct at91_adc_state *st) 992{ 993 input_unregister_device(st->ts_input); 994} 995 996static int at91_adc_probe(struct platform_device *pdev) 997{ 998 unsigned int prsc, mstrclk, ticks, adc_clk, adc_clk_khz, shtim; 999 struct device_node *node = pdev->dev.of_node; 1000 int ret; 1001 struct iio_dev *idev; 1002 struct at91_adc_state *st; 1003 u32 reg, prop; 1004 char *s; 1005 1006 idev = devm_iio_device_alloc(&pdev->dev, sizeof(struct at91_adc_state)); 1007 if (!idev) 1008 return -ENOMEM; 1009 1010 st = iio_priv(idev); 1011 1012 st->caps = of_device_get_match_data(&pdev->dev); 1013 1014 st->use_external = of_property_read_bool(node, "atmel,adc-use-external-triggers"); 1015 1016 if (of_property_read_u32(node, "atmel,adc-channels-used", &prop)) { 1017 dev_err(&idev->dev, "Missing adc-channels-used property in the DT.\n"); 1018 return -EINVAL; 1019 } 1020 st->channels_mask = prop; 1021 1022 st->sleep_mode = of_property_read_bool(node, "atmel,adc-sleep-mode"); 1023 1024 if (of_property_read_u32(node, "atmel,adc-startup-time", &prop)) { 1025 dev_err(&idev->dev, "Missing adc-startup-time property in the DT.\n"); 1026 return -EINVAL; 1027 } 1028 st->startup_time = prop; 1029 1030 prop = 0; 1031 of_property_read_u32(node, "atmel,adc-sample-hold-time", &prop); 1032 st->sample_hold_time = prop; 1033 1034 if (of_property_read_u32(node, "atmel,adc-vref", &prop)) { 1035 dev_err(&idev->dev, "Missing adc-vref property in the DT.\n"); 1036 return -EINVAL; 1037 } 1038 st->vref_mv = prop; 1039 1040 st->res = st->caps->high_res_bits; 1041 if (st->caps->low_res_bits && 1042 !of_property_read_string(node, "atmel,adc-use-res", (const char **)&s) 1043 && !strcmp(s, "lowres")) 1044 st->res = st->caps->low_res_bits; 1045 1046 dev_info(&idev->dev, "Resolution used: %u bits\n", st->res); 1047 1048 st->registers = &st->caps->registers; 1049 st->num_channels = st->caps->num_channels; 1050 1051 /* Check if touchscreen is supported. */ 1052 if (st->caps->has_ts) { 1053 ret = at91_adc_probe_dt_ts(node, st, &idev->dev); 1054 if (ret) 1055 return ret; 1056 } 1057 1058 platform_set_drvdata(pdev, idev); 1059 1060 idev->name = dev_name(&pdev->dev); 1061 idev->modes = INDIO_DIRECT_MODE; 1062 idev->info = &at91_adc_info; 1063 1064 st->irq = platform_get_irq(pdev, 0); 1065 if (st->irq < 0) 1066 return -ENODEV; 1067 1068 st->reg_base = devm_platform_ioremap_resource(pdev, 0); 1069 if (IS_ERR(st->reg_base)) 1070 return PTR_ERR(st->reg_base); 1071 1072 1073 /* 1074 * Disable all IRQs before setting up the handler 1075 */ 1076 at91_adc_writel(st, AT91_ADC_CR, AT91_ADC_SWRST); 1077 at91_adc_writel(st, AT91_ADC_IDR, 0xFFFFFFFF); 1078 1079 if (st->caps->has_tsmr) 1080 ret = request_irq(st->irq, at91_adc_9x5_interrupt, 0, 1081 pdev->dev.driver->name, idev); 1082 else 1083 ret = request_irq(st->irq, at91_adc_rl_interrupt, 0, 1084 pdev->dev.driver->name, idev); 1085 if (ret) { 1086 dev_err(&pdev->dev, "Failed to allocate IRQ.\n"); 1087 return ret; 1088 } 1089 1090 st->clk = devm_clk_get(&pdev->dev, "adc_clk"); 1091 if (IS_ERR(st->clk)) { 1092 dev_err(&pdev->dev, "Failed to get the clock.\n"); 1093 ret = PTR_ERR(st->clk); 1094 goto error_free_irq; 1095 } 1096 1097 ret = clk_prepare_enable(st->clk); 1098 if (ret) { 1099 dev_err(&pdev->dev, 1100 "Could not prepare or enable the clock.\n"); 1101 goto error_free_irq; 1102 } 1103 1104 st->adc_clk = devm_clk_get(&pdev->dev, "adc_op_clk"); 1105 if (IS_ERR(st->adc_clk)) { 1106 dev_err(&pdev->dev, "Failed to get the ADC clock.\n"); 1107 ret = PTR_ERR(st->adc_clk); 1108 goto error_disable_clk; 1109 } 1110 1111 ret = clk_prepare_enable(st->adc_clk); 1112 if (ret) { 1113 dev_err(&pdev->dev, 1114 "Could not prepare or enable the ADC clock.\n"); 1115 goto error_disable_clk; 1116 } 1117 1118 /* 1119 * Prescaler rate computation using the formula from the Atmel's 1120 * datasheet : ADC Clock = MCK / ((Prescaler + 1) * 2), ADC Clock being 1121 * specified by the electrical characteristics of the board. 1122 */ 1123 mstrclk = clk_get_rate(st->clk); 1124 adc_clk = clk_get_rate(st->adc_clk); 1125 adc_clk_khz = adc_clk / 1000; 1126 1127 dev_dbg(&pdev->dev, "Master clock is set as: %d Hz, adc_clk should set as: %d Hz\n", 1128 mstrclk, adc_clk); 1129 1130 prsc = (mstrclk / (2 * adc_clk)) - 1; 1131 1132 if (!st->startup_time) { 1133 dev_err(&pdev->dev, "No startup time available.\n"); 1134 ret = -EINVAL; 1135 goto error_disable_adc_clk; 1136 } 1137 ticks = (*st->caps->calc_startup_ticks)(st->startup_time, adc_clk_khz); 1138 1139 /* 1140 * a minimal Sample and Hold Time is necessary for the ADC to guarantee 1141 * the best converted final value between two channels selection 1142 * The formula thus is : Sample and Hold Time = (shtim + 1) / ADCClock 1143 */ 1144 if (st->sample_hold_time > 0) 1145 shtim = round_up((st->sample_hold_time * adc_clk_khz / 1000) 1146 - 1, 1); 1147 else 1148 shtim = 0; 1149 1150 reg = AT91_ADC_PRESCAL_(prsc) & st->registers->mr_prescal_mask; 1151 reg |= AT91_ADC_STARTUP_(ticks) & st->registers->mr_startup_mask; 1152 if (st->res == st->caps->low_res_bits) 1153 reg |= AT91_ADC_LOWRES; 1154 if (st->sleep_mode) 1155 reg |= AT91_ADC_SLEEP; 1156 reg |= AT91_ADC_SHTIM_(shtim) & AT91_ADC_SHTIM; 1157 at91_adc_writel(st, AT91_ADC_MR, reg); 1158 1159 /* Setup the ADC channels available on the board */ 1160 ret = at91_adc_channel_init(idev); 1161 if (ret < 0) { 1162 dev_err(&pdev->dev, "Couldn't initialize the channels.\n"); 1163 goto error_disable_adc_clk; 1164 } 1165 1166 init_waitqueue_head(&st->wq_data_avail); 1167 mutex_init(&st->lock); 1168 1169 /* 1170 * Since touch screen will set trigger register as period trigger. So 1171 * when touch screen is enabled, then we have to disable hardware 1172 * trigger for classic adc. 1173 */ 1174 if (!st->touchscreen_type) { 1175 ret = at91_adc_buffer_init(idev); 1176 if (ret < 0) { 1177 dev_err(&pdev->dev, "Couldn't initialize the buffer.\n"); 1178 goto error_disable_adc_clk; 1179 } 1180 1181 ret = at91_adc_trigger_init(idev); 1182 if (ret < 0) { 1183 dev_err(&pdev->dev, "Couldn't setup the triggers.\n"); 1184 at91_adc_buffer_remove(idev); 1185 goto error_disable_adc_clk; 1186 } 1187 } else { 1188 ret = at91_ts_register(idev, pdev); 1189 if (ret) 1190 goto error_disable_adc_clk; 1191 1192 at91_ts_hw_init(idev, adc_clk_khz); 1193 } 1194 1195 ret = iio_device_register(idev); 1196 if (ret < 0) { 1197 dev_err(&pdev->dev, "Couldn't register the device.\n"); 1198 goto error_iio_device_register; 1199 } 1200 1201 return 0; 1202 1203error_iio_device_register: 1204 if (!st->touchscreen_type) { 1205 at91_adc_trigger_remove(idev); 1206 at91_adc_buffer_remove(idev); 1207 } else { 1208 at91_ts_unregister(st); 1209 } 1210error_disable_adc_clk: 1211 clk_disable_unprepare(st->adc_clk); 1212error_disable_clk: 1213 clk_disable_unprepare(st->clk); 1214error_free_irq: 1215 free_irq(st->irq, idev); 1216 return ret; 1217} 1218 1219static int at91_adc_remove(struct platform_device *pdev) 1220{ 1221 struct iio_dev *idev = platform_get_drvdata(pdev); 1222 struct at91_adc_state *st = iio_priv(idev); 1223 1224 iio_device_unregister(idev); 1225 if (!st->touchscreen_type) { 1226 at91_adc_trigger_remove(idev); 1227 at91_adc_buffer_remove(idev); 1228 } else { 1229 at91_ts_unregister(st); 1230 } 1231 clk_disable_unprepare(st->adc_clk); 1232 clk_disable_unprepare(st->clk); 1233 free_irq(st->irq, idev); 1234 1235 return 0; 1236} 1237 1238static int at91_adc_suspend(struct device *dev) 1239{ 1240 struct iio_dev *idev = dev_get_drvdata(dev); 1241 struct at91_adc_state *st = iio_priv(idev); 1242 1243 pinctrl_pm_select_sleep_state(dev); 1244 clk_disable_unprepare(st->clk); 1245 1246 return 0; 1247} 1248 1249static int at91_adc_resume(struct device *dev) 1250{ 1251 struct iio_dev *idev = dev_get_drvdata(dev); 1252 struct at91_adc_state *st = iio_priv(idev); 1253 1254 clk_prepare_enable(st->clk); 1255 pinctrl_pm_select_default_state(dev); 1256 1257 return 0; 1258} 1259 1260static DEFINE_SIMPLE_DEV_PM_OPS(at91_adc_pm_ops, at91_adc_suspend, 1261 at91_adc_resume); 1262 1263static const struct at91_adc_trigger at91sam9260_triggers[] = { 1264 { .name = "timer-counter-0", .value = 0x1 }, 1265 { .name = "timer-counter-1", .value = 0x3 }, 1266 { .name = "timer-counter-2", .value = 0x5 }, 1267 { .name = "external", .value = 0xd, .is_external = true }, 1268}; 1269 1270static struct at91_adc_caps at91sam9260_caps = { 1271 .calc_startup_ticks = calc_startup_ticks_9260, 1272 .num_channels = 4, 1273 .low_res_bits = 8, 1274 .high_res_bits = 10, 1275 .registers = { 1276 .channel_base = AT91_ADC_CHR(0), 1277 .drdy_mask = AT91_ADC_DRDY, 1278 .status_register = AT91_ADC_SR, 1279 .trigger_register = AT91_ADC_TRGR_9260, 1280 .mr_prescal_mask = AT91_ADC_PRESCAL_9260, 1281 .mr_startup_mask = AT91_ADC_STARTUP_9260, 1282 }, 1283 .triggers = at91sam9260_triggers, 1284 .trigger_number = ARRAY_SIZE(at91sam9260_triggers), 1285}; 1286 1287static const struct at91_adc_trigger at91sam9x5_triggers[] = { 1288 { .name = "external-rising", .value = 0x1, .is_external = true }, 1289 { .name = "external-falling", .value = 0x2, .is_external = true }, 1290 { .name = "external-any", .value = 0x3, .is_external = true }, 1291 { .name = "continuous", .value = 0x6 }, 1292}; 1293 1294static struct at91_adc_caps at91sam9rl_caps = { 1295 .has_ts = true, 1296 .calc_startup_ticks = calc_startup_ticks_9260, /* same as 9260 */ 1297 .num_channels = 6, 1298 .low_res_bits = 8, 1299 .high_res_bits = 10, 1300 .registers = { 1301 .channel_base = AT91_ADC_CHR(0), 1302 .drdy_mask = AT91_ADC_DRDY, 1303 .status_register = AT91_ADC_SR, 1304 .trigger_register = AT91_ADC_TRGR_9G45, 1305 .mr_prescal_mask = AT91_ADC_PRESCAL_9260, 1306 .mr_startup_mask = AT91_ADC_STARTUP_9G45, 1307 }, 1308 .triggers = at91sam9x5_triggers, 1309 .trigger_number = ARRAY_SIZE(at91sam9x5_triggers), 1310}; 1311 1312static struct at91_adc_caps at91sam9g45_caps = { 1313 .has_ts = true, 1314 .calc_startup_ticks = calc_startup_ticks_9260, /* same as 9260 */ 1315 .num_channels = 8, 1316 .low_res_bits = 8, 1317 .high_res_bits = 10, 1318 .registers = { 1319 .channel_base = AT91_ADC_CHR(0), 1320 .drdy_mask = AT91_ADC_DRDY, 1321 .status_register = AT91_ADC_SR, 1322 .trigger_register = AT91_ADC_TRGR_9G45, 1323 .mr_prescal_mask = AT91_ADC_PRESCAL_9G45, 1324 .mr_startup_mask = AT91_ADC_STARTUP_9G45, 1325 }, 1326 .triggers = at91sam9x5_triggers, 1327 .trigger_number = ARRAY_SIZE(at91sam9x5_triggers), 1328}; 1329 1330static struct at91_adc_caps at91sam9x5_caps = { 1331 .has_ts = true, 1332 .has_tsmr = true, 1333 .ts_filter_average = 3, 1334 .ts_pen_detect_sensitivity = 2, 1335 .calc_startup_ticks = calc_startup_ticks_9x5, 1336 .num_channels = 12, 1337 .low_res_bits = 8, 1338 .high_res_bits = 10, 1339 .registers = { 1340 .channel_base = AT91_ADC_CDR0_9X5, 1341 .drdy_mask = AT91_ADC_SR_DRDY_9X5, 1342 .status_register = AT91_ADC_SR_9X5, 1343 .trigger_register = AT91_ADC_TRGR_9X5, 1344 /* prescal mask is same as 9G45 */ 1345 .mr_prescal_mask = AT91_ADC_PRESCAL_9G45, 1346 .mr_startup_mask = AT91_ADC_STARTUP_9X5, 1347 }, 1348 .triggers = at91sam9x5_triggers, 1349 .trigger_number = ARRAY_SIZE(at91sam9x5_triggers), 1350}; 1351 1352static struct at91_adc_caps sama5d3_caps = { 1353 .has_ts = true, 1354 .has_tsmr = true, 1355 .ts_filter_average = 3, 1356 .ts_pen_detect_sensitivity = 2, 1357 .calc_startup_ticks = calc_startup_ticks_9x5, 1358 .num_channels = 12, 1359 .low_res_bits = 0, 1360 .high_res_bits = 12, 1361 .registers = { 1362 .channel_base = AT91_ADC_CDR0_9X5, 1363 .drdy_mask = AT91_ADC_SR_DRDY_9X5, 1364 .status_register = AT91_ADC_SR_9X5, 1365 .trigger_register = AT91_ADC_TRGR_9X5, 1366 .mr_prescal_mask = AT91_ADC_PRESCAL_9G45, 1367 .mr_startup_mask = AT91_ADC_STARTUP_9X5, 1368 }, 1369 .triggers = at91sam9x5_triggers, 1370 .trigger_number = ARRAY_SIZE(at91sam9x5_triggers), 1371}; 1372 1373static const struct of_device_id at91_adc_dt_ids[] = { 1374 { .compatible = "atmel,at91sam9260-adc", .data = &at91sam9260_caps }, 1375 { .compatible = "atmel,at91sam9rl-adc", .data = &at91sam9rl_caps }, 1376 { .compatible = "atmel,at91sam9g45-adc", .data = &at91sam9g45_caps }, 1377 { .compatible = "atmel,at91sam9x5-adc", .data = &at91sam9x5_caps }, 1378 { .compatible = "atmel,sama5d3-adc", .data = &sama5d3_caps }, 1379 {}, 1380}; 1381MODULE_DEVICE_TABLE(of, at91_adc_dt_ids); 1382 1383static struct platform_driver at91_adc_driver = { 1384 .probe = at91_adc_probe, 1385 .remove = at91_adc_remove, 1386 .driver = { 1387 .name = DRIVER_NAME, 1388 .of_match_table = at91_adc_dt_ids, 1389 .pm = pm_sleep_ptr(&at91_adc_pm_ops), 1390 }, 1391}; 1392 1393module_platform_driver(at91_adc_driver); 1394 1395MODULE_LICENSE("GPL"); 1396MODULE_DESCRIPTION("Atmel AT91 ADC Driver"); 1397MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>"); 1398