1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Analog Devices Generic AXI ADC IP core
4 * Link: https://wiki.analog.com/resources/fpga/docs/axi_adc_ip
5 *
6 * Copyright 2012-2020 Analog Devices Inc.
7 */
8
9#include <linux/bitfield.h>
10#include <linux/clk.h>
11#include <linux/io.h>
12#include <linux/delay.h>
13#include <linux/module.h>
14#include <linux/of.h>
15#include <linux/platform_device.h>
16#include <linux/property.h>
17#include <linux/slab.h>
18
19#include <linux/iio/iio.h>
20#include <linux/iio/sysfs.h>
21#include <linux/iio/buffer.h>
22#include <linux/iio/buffer-dmaengine.h>
23
24#include <linux/fpga/adi-axi-common.h>
25#include <linux/iio/adc/adi-axi-adc.h>
26
27/*
28 * Register definitions:
29 *   https://wiki.analog.com/resources/fpga/docs/axi_adc_ip#register_map
30 */
31
32/* ADC controls */
33
34#define ADI_AXI_REG_RSTN			0x0040
35#define   ADI_AXI_REG_RSTN_CE_N			BIT(2)
36#define   ADI_AXI_REG_RSTN_MMCM_RSTN		BIT(1)
37#define   ADI_AXI_REG_RSTN_RSTN			BIT(0)
38
39/* ADC Channel controls */
40
41#define ADI_AXI_REG_CHAN_CTRL(c)		(0x0400 + (c) * 0x40)
42#define   ADI_AXI_REG_CHAN_CTRL_LB_OWR		BIT(11)
43#define   ADI_AXI_REG_CHAN_CTRL_PN_SEL_OWR	BIT(10)
44#define   ADI_AXI_REG_CHAN_CTRL_IQCOR_EN	BIT(9)
45#define   ADI_AXI_REG_CHAN_CTRL_DCFILT_EN	BIT(8)
46#define   ADI_AXI_REG_CHAN_CTRL_FMT_SIGNEXT	BIT(6)
47#define   ADI_AXI_REG_CHAN_CTRL_FMT_TYPE	BIT(5)
48#define   ADI_AXI_REG_CHAN_CTRL_FMT_EN		BIT(4)
49#define   ADI_AXI_REG_CHAN_CTRL_PN_TYPE_OWR	BIT(1)
50#define   ADI_AXI_REG_CHAN_CTRL_ENABLE		BIT(0)
51
52#define ADI_AXI_REG_CHAN_CTRL_DEFAULTS		\
53	(ADI_AXI_REG_CHAN_CTRL_FMT_SIGNEXT |	\
54	 ADI_AXI_REG_CHAN_CTRL_FMT_EN |		\
55	 ADI_AXI_REG_CHAN_CTRL_ENABLE)
56
57struct adi_axi_adc_core_info {
58	unsigned int				version;
59};
60
61struct adi_axi_adc_state {
62	struct mutex				lock;
63
64	struct adi_axi_adc_client		*client;
65	void __iomem				*regs;
66};
67
68struct adi_axi_adc_client {
69	struct list_head			entry;
70	struct adi_axi_adc_conv			conv;
71	struct adi_axi_adc_state		*state;
72	struct device				*dev;
73	const struct adi_axi_adc_core_info	*info;
74};
75
76static LIST_HEAD(registered_clients);
77static DEFINE_MUTEX(registered_clients_lock);
78
79static struct adi_axi_adc_client *conv_to_client(struct adi_axi_adc_conv *conv)
80{
81	return container_of(conv, struct adi_axi_adc_client, conv);
82}
83
84void *adi_axi_adc_conv_priv(struct adi_axi_adc_conv *conv)
85{
86	struct adi_axi_adc_client *cl = conv_to_client(conv);
87
88	return (char *)cl + ALIGN(sizeof(struct adi_axi_adc_client),
89				  IIO_DMA_MINALIGN);
90}
91EXPORT_SYMBOL_NS_GPL(adi_axi_adc_conv_priv, IIO_ADI_AXI);
92
93static void adi_axi_adc_write(struct adi_axi_adc_state *st,
94			      unsigned int reg,
95			      unsigned int val)
96{
97	iowrite32(val, st->regs + reg);
98}
99
100static unsigned int adi_axi_adc_read(struct adi_axi_adc_state *st,
101				     unsigned int reg)
102{
103	return ioread32(st->regs + reg);
104}
105
106static int adi_axi_adc_config_dma_buffer(struct device *dev,
107					 struct iio_dev *indio_dev)
108{
109	const char *dma_name;
110
111	if (!device_property_present(dev, "dmas"))
112		return 0;
113
114	if (device_property_read_string(dev, "dma-names", &dma_name))
115		dma_name = "rx";
116
117	return devm_iio_dmaengine_buffer_setup(indio_dev->dev.parent,
118					       indio_dev, dma_name);
119}
120
121static int adi_axi_adc_read_raw(struct iio_dev *indio_dev,
122				struct iio_chan_spec const *chan,
123				int *val, int *val2, long mask)
124{
125	struct adi_axi_adc_state *st = iio_priv(indio_dev);
126	struct adi_axi_adc_conv *conv = &st->client->conv;
127
128	if (!conv->read_raw)
129		return -EOPNOTSUPP;
130
131	return conv->read_raw(conv, chan, val, val2, mask);
132}
133
134static int adi_axi_adc_write_raw(struct iio_dev *indio_dev,
135				 struct iio_chan_spec const *chan,
136				 int val, int val2, long mask)
137{
138	struct adi_axi_adc_state *st = iio_priv(indio_dev);
139	struct adi_axi_adc_conv *conv = &st->client->conv;
140
141	if (!conv->write_raw)
142		return -EOPNOTSUPP;
143
144	return conv->write_raw(conv, chan, val, val2, mask);
145}
146
147static int adi_axi_adc_read_avail(struct iio_dev *indio_dev,
148				  struct iio_chan_spec const *chan,
149				  const int **vals, int *type, int *length,
150				  long mask)
151{
152	struct adi_axi_adc_state *st = iio_priv(indio_dev);
153	struct adi_axi_adc_conv *conv = &st->client->conv;
154
155	if (!conv->read_avail)
156		return -EOPNOTSUPP;
157
158	return conv->read_avail(conv, chan, vals, type, length, mask);
159}
160
161static int adi_axi_adc_update_scan_mode(struct iio_dev *indio_dev,
162					const unsigned long *scan_mask)
163{
164	struct adi_axi_adc_state *st = iio_priv(indio_dev);
165	struct adi_axi_adc_conv *conv = &st->client->conv;
166	unsigned int i, ctrl;
167
168	for (i = 0; i < conv->chip_info->num_channels; i++) {
169		ctrl = adi_axi_adc_read(st, ADI_AXI_REG_CHAN_CTRL(i));
170
171		if (test_bit(i, scan_mask))
172			ctrl |= ADI_AXI_REG_CHAN_CTRL_ENABLE;
173		else
174			ctrl &= ~ADI_AXI_REG_CHAN_CTRL_ENABLE;
175
176		adi_axi_adc_write(st, ADI_AXI_REG_CHAN_CTRL(i), ctrl);
177	}
178
179	return 0;
180}
181
182static struct adi_axi_adc_conv *adi_axi_adc_conv_register(struct device *dev,
183							  size_t sizeof_priv)
184{
185	struct adi_axi_adc_client *cl;
186	size_t alloc_size;
187
188	alloc_size = ALIGN(sizeof(struct adi_axi_adc_client), IIO_DMA_MINALIGN);
189	if (sizeof_priv)
190		alloc_size += ALIGN(sizeof_priv, IIO_DMA_MINALIGN);
191
192	cl = kzalloc(alloc_size, GFP_KERNEL);
193	if (!cl)
194		return ERR_PTR(-ENOMEM);
195
196	mutex_lock(&registered_clients_lock);
197
198	cl->dev = get_device(dev);
199
200	list_add_tail(&cl->entry, &registered_clients);
201
202	mutex_unlock(&registered_clients_lock);
203
204	return &cl->conv;
205}
206
207static void adi_axi_adc_conv_unregister(struct adi_axi_adc_conv *conv)
208{
209	struct adi_axi_adc_client *cl = conv_to_client(conv);
210
211	mutex_lock(&registered_clients_lock);
212
213	list_del(&cl->entry);
214	put_device(cl->dev);
215
216	mutex_unlock(&registered_clients_lock);
217
218	kfree(cl);
219}
220
221static void devm_adi_axi_adc_conv_release(void *conv)
222{
223	adi_axi_adc_conv_unregister(conv);
224}
225
226struct adi_axi_adc_conv *devm_adi_axi_adc_conv_register(struct device *dev,
227							size_t sizeof_priv)
228{
229	struct adi_axi_adc_conv *conv;
230	int ret;
231
232	conv = adi_axi_adc_conv_register(dev, sizeof_priv);
233	if (IS_ERR(conv))
234		return conv;
235
236	ret = devm_add_action_or_reset(dev, devm_adi_axi_adc_conv_release,
237				       conv);
238	if (ret)
239		return ERR_PTR(ret);
240
241	return conv;
242}
243EXPORT_SYMBOL_NS_GPL(devm_adi_axi_adc_conv_register, IIO_ADI_AXI);
244
245static const struct iio_info adi_axi_adc_info = {
246	.read_raw = &adi_axi_adc_read_raw,
247	.write_raw = &adi_axi_adc_write_raw,
248	.update_scan_mode = &adi_axi_adc_update_scan_mode,
249	.read_avail = &adi_axi_adc_read_avail,
250};
251
252static const struct adi_axi_adc_core_info adi_axi_adc_10_0_a_info = {
253	.version = ADI_AXI_PCORE_VER(10, 0, 'a'),
254};
255
256static struct adi_axi_adc_client *adi_axi_adc_attach_client(struct device *dev)
257{
258	const struct adi_axi_adc_core_info *info;
259	struct adi_axi_adc_client *cl;
260	struct device_node *cln;
261
262	info = of_device_get_match_data(dev);
263	if (!info)
264		return ERR_PTR(-ENODEV);
265
266	cln = of_parse_phandle(dev->of_node, "adi,adc-dev", 0);
267	if (!cln) {
268		dev_err(dev, "No 'adi,adc-dev' node defined\n");
269		return ERR_PTR(-ENODEV);
270	}
271
272	mutex_lock(&registered_clients_lock);
273
274	list_for_each_entry(cl, &registered_clients, entry) {
275		if (!cl->dev)
276			continue;
277
278		if (cl->dev->of_node != cln)
279			continue;
280
281		if (!try_module_get(cl->dev->driver->owner)) {
282			mutex_unlock(&registered_clients_lock);
283			of_node_put(cln);
284			return ERR_PTR(-ENODEV);
285		}
286
287		get_device(cl->dev);
288		cl->info = info;
289		mutex_unlock(&registered_clients_lock);
290		of_node_put(cln);
291		return cl;
292	}
293
294	mutex_unlock(&registered_clients_lock);
295	of_node_put(cln);
296
297	return ERR_PTR(-EPROBE_DEFER);
298}
299
300static int adi_axi_adc_setup_channels(struct device *dev,
301				      struct adi_axi_adc_state *st)
302{
303	struct adi_axi_adc_conv *conv = &st->client->conv;
304	int i, ret;
305
306	if (conv->preenable_setup) {
307		ret = conv->preenable_setup(conv);
308		if (ret)
309			return ret;
310	}
311
312	for (i = 0; i < conv->chip_info->num_channels; i++) {
313		adi_axi_adc_write(st, ADI_AXI_REG_CHAN_CTRL(i),
314				  ADI_AXI_REG_CHAN_CTRL_DEFAULTS);
315	}
316
317	return 0;
318}
319
320static void axi_adc_reset(struct adi_axi_adc_state *st)
321{
322	adi_axi_adc_write(st, ADI_AXI_REG_RSTN, 0);
323	mdelay(10);
324	adi_axi_adc_write(st, ADI_AXI_REG_RSTN, ADI_AXI_REG_RSTN_MMCM_RSTN);
325	mdelay(10);
326	adi_axi_adc_write(st, ADI_AXI_REG_RSTN,
327			  ADI_AXI_REG_RSTN_RSTN | ADI_AXI_REG_RSTN_MMCM_RSTN);
328}
329
330static void adi_axi_adc_cleanup(void *data)
331{
332	struct adi_axi_adc_client *cl = data;
333
334	put_device(cl->dev);
335	module_put(cl->dev->driver->owner);
336}
337
338static int adi_axi_adc_probe(struct platform_device *pdev)
339{
340	struct adi_axi_adc_conv *conv;
341	struct iio_dev *indio_dev;
342	struct adi_axi_adc_client *cl;
343	struct adi_axi_adc_state *st;
344	unsigned int ver;
345	int ret;
346
347	cl = adi_axi_adc_attach_client(&pdev->dev);
348	if (IS_ERR(cl))
349		return PTR_ERR(cl);
350
351	ret = devm_add_action_or_reset(&pdev->dev, adi_axi_adc_cleanup, cl);
352	if (ret)
353		return ret;
354
355	indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*st));
356	if (indio_dev == NULL)
357		return -ENOMEM;
358
359	st = iio_priv(indio_dev);
360	st->client = cl;
361	cl->state = st;
362	mutex_init(&st->lock);
363
364	st->regs = devm_platform_ioremap_resource(pdev, 0);
365	if (IS_ERR(st->regs))
366		return PTR_ERR(st->regs);
367
368	conv = &st->client->conv;
369
370	axi_adc_reset(st);
371
372	ver = adi_axi_adc_read(st, ADI_AXI_REG_VERSION);
373
374	if (cl->info->version > ver) {
375		dev_err(&pdev->dev,
376			"IP core version is too old. Expected %d.%.2d.%c, Reported %d.%.2d.%c\n",
377			ADI_AXI_PCORE_VER_MAJOR(cl->info->version),
378			ADI_AXI_PCORE_VER_MINOR(cl->info->version),
379			ADI_AXI_PCORE_VER_PATCH(cl->info->version),
380			ADI_AXI_PCORE_VER_MAJOR(ver),
381			ADI_AXI_PCORE_VER_MINOR(ver),
382			ADI_AXI_PCORE_VER_PATCH(ver));
383		return -ENODEV;
384	}
385
386	indio_dev->info = &adi_axi_adc_info;
387	indio_dev->name = "adi-axi-adc";
388	indio_dev->modes = INDIO_DIRECT_MODE;
389	indio_dev->num_channels = conv->chip_info->num_channels;
390	indio_dev->channels = conv->chip_info->channels;
391
392	ret = adi_axi_adc_config_dma_buffer(&pdev->dev, indio_dev);
393	if (ret)
394		return ret;
395
396	ret = adi_axi_adc_setup_channels(&pdev->dev, st);
397	if (ret)
398		return ret;
399
400	ret = devm_iio_device_register(&pdev->dev, indio_dev);
401	if (ret)
402		return ret;
403
404	dev_info(&pdev->dev, "AXI ADC IP core (%d.%.2d.%c) probed\n",
405		 ADI_AXI_PCORE_VER_MAJOR(ver),
406		 ADI_AXI_PCORE_VER_MINOR(ver),
407		 ADI_AXI_PCORE_VER_PATCH(ver));
408
409	return 0;
410}
411
412/* Match table for of_platform binding */
413static const struct of_device_id adi_axi_adc_of_match[] = {
414	{ .compatible = "adi,axi-adc-10.0.a", .data = &adi_axi_adc_10_0_a_info },
415	{ /* end of list */ }
416};
417MODULE_DEVICE_TABLE(of, adi_axi_adc_of_match);
418
419static struct platform_driver adi_axi_adc_driver = {
420	.driver = {
421		.name = KBUILD_MODNAME,
422		.of_match_table = adi_axi_adc_of_match,
423	},
424	.probe = adi_axi_adc_probe,
425};
426module_platform_driver(adi_axi_adc_driver);
427
428MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
429MODULE_DESCRIPTION("Analog Devices Generic AXI ADC IP core driver");
430MODULE_LICENSE("GPL v2");
431