1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Analog Devices AD9467 SPI ADC driver 4 * 5 * Copyright 2012-2020 Analog Devices Inc. 6 */ 7#include <linux/cleanup.h> 8#include <linux/module.h> 9#include <linux/mutex.h> 10#include <linux/device.h> 11#include <linux/kernel.h> 12#include <linux/slab.h> 13#include <linux/spi/spi.h> 14#include <linux/err.h> 15#include <linux/delay.h> 16#include <linux/gpio/consumer.h> 17#include <linux/of.h> 18 19 20#include <linux/iio/iio.h> 21#include <linux/iio/sysfs.h> 22 23#include <linux/clk.h> 24 25#include <linux/iio/adc/adi-axi-adc.h> 26 27/* 28 * ADI High-Speed ADC common spi interface registers 29 * See Application-Note AN-877: 30 * https://www.analog.com/media/en/technical-documentation/application-notes/AN-877.pdf 31 */ 32 33#define AN877_ADC_REG_CHIP_PORT_CONF 0x00 34#define AN877_ADC_REG_CHIP_ID 0x01 35#define AN877_ADC_REG_CHIP_GRADE 0x02 36#define AN877_ADC_REG_CHAN_INDEX 0x05 37#define AN877_ADC_REG_TRANSFER 0xFF 38#define AN877_ADC_REG_MODES 0x08 39#define AN877_ADC_REG_TEST_IO 0x0D 40#define AN877_ADC_REG_ADC_INPUT 0x0F 41#define AN877_ADC_REG_OFFSET 0x10 42#define AN877_ADC_REG_OUTPUT_MODE 0x14 43#define AN877_ADC_REG_OUTPUT_ADJUST 0x15 44#define AN877_ADC_REG_OUTPUT_PHASE 0x16 45#define AN877_ADC_REG_OUTPUT_DELAY 0x17 46#define AN877_ADC_REG_VREF 0x18 47#define AN877_ADC_REG_ANALOG_INPUT 0x2C 48 49/* AN877_ADC_REG_TEST_IO */ 50#define AN877_ADC_TESTMODE_OFF 0x0 51#define AN877_ADC_TESTMODE_MIDSCALE_SHORT 0x1 52#define AN877_ADC_TESTMODE_POS_FULLSCALE 0x2 53#define AN877_ADC_TESTMODE_NEG_FULLSCALE 0x3 54#define AN877_ADC_TESTMODE_ALT_CHECKERBOARD 0x4 55#define AN877_ADC_TESTMODE_PN23_SEQ 0x5 56#define AN877_ADC_TESTMODE_PN9_SEQ 0x6 57#define AN877_ADC_TESTMODE_ONE_ZERO_TOGGLE 0x7 58#define AN877_ADC_TESTMODE_USER 0x8 59#define AN877_ADC_TESTMODE_BIT_TOGGLE 0x9 60#define AN877_ADC_TESTMODE_SYNC 0xA 61#define AN877_ADC_TESTMODE_ONE_BIT_HIGH 0xB 62#define AN877_ADC_TESTMODE_MIXED_BIT_FREQUENCY 0xC 63#define AN877_ADC_TESTMODE_RAMP 0xF 64 65/* AN877_ADC_REG_TRANSFER */ 66#define AN877_ADC_TRANSFER_SYNC 0x1 67 68/* AN877_ADC_REG_OUTPUT_MODE */ 69#define AN877_ADC_OUTPUT_MODE_OFFSET_BINARY 0x0 70#define AN877_ADC_OUTPUT_MODE_TWOS_COMPLEMENT 0x1 71#define AN877_ADC_OUTPUT_MODE_GRAY_CODE 0x2 72 73/* AN877_ADC_REG_OUTPUT_PHASE */ 74#define AN877_ADC_OUTPUT_EVEN_ODD_MODE_EN 0x20 75#define AN877_ADC_INVERT_DCO_CLK 0x80 76 77/* AN877_ADC_REG_OUTPUT_DELAY */ 78#define AN877_ADC_DCO_DELAY_ENABLE 0x80 79 80/* 81 * Analog Devices AD9265 16-Bit, 125/105/80 MSPS ADC 82 */ 83 84#define CHIPID_AD9265 0x64 85#define AD9265_DEF_OUTPUT_MODE 0x40 86#define AD9265_REG_VREF_MASK 0xC0 87 88/* 89 * Analog Devices AD9434 12-Bit, 370/500 MSPS ADC 90 */ 91 92#define CHIPID_AD9434 0x6A 93#define AD9434_DEF_OUTPUT_MODE 0x00 94#define AD9434_REG_VREF_MASK 0xC0 95 96/* 97 * Analog Devices AD9467 16-Bit, 200/250 MSPS ADC 98 */ 99 100#define CHIPID_AD9467 0x50 101#define AD9467_DEF_OUTPUT_MODE 0x08 102#define AD9467_REG_VREF_MASK 0x0F 103 104enum { 105 ID_AD9265, 106 ID_AD9434, 107 ID_AD9467, 108}; 109 110struct ad9467_chip_info { 111 struct adi_axi_adc_chip_info axi_adc_info; 112 unsigned int default_output_mode; 113 unsigned int vref_mask; 114}; 115 116#define to_ad9467_chip_info(_info) \ 117 container_of(_info, struct ad9467_chip_info, axi_adc_info) 118 119struct ad9467_state { 120 struct spi_device *spi; 121 struct clk *clk; 122 unsigned int output_mode; 123 unsigned int (*scales)[2]; 124 125 struct gpio_desc *pwrdown_gpio; 126 /* ensure consistent state obtained on multiple related accesses */ 127 struct mutex lock; 128}; 129 130static int ad9467_spi_read(struct spi_device *spi, unsigned int reg) 131{ 132 unsigned char tbuf[2], rbuf[1]; 133 int ret; 134 135 tbuf[0] = 0x80 | (reg >> 8); 136 tbuf[1] = reg & 0xFF; 137 138 ret = spi_write_then_read(spi, 139 tbuf, ARRAY_SIZE(tbuf), 140 rbuf, ARRAY_SIZE(rbuf)); 141 142 if (ret < 0) 143 return ret; 144 145 return rbuf[0]; 146} 147 148static int ad9467_spi_write(struct spi_device *spi, unsigned int reg, 149 unsigned int val) 150{ 151 unsigned char buf[3]; 152 153 buf[0] = reg >> 8; 154 buf[1] = reg & 0xFF; 155 buf[2] = val; 156 157 return spi_write(spi, buf, ARRAY_SIZE(buf)); 158} 159 160static int ad9467_reg_access(struct adi_axi_adc_conv *conv, unsigned int reg, 161 unsigned int writeval, unsigned int *readval) 162{ 163 struct ad9467_state *st = adi_axi_adc_conv_priv(conv); 164 struct spi_device *spi = st->spi; 165 int ret; 166 167 if (readval == NULL) { 168 guard(mutex)(&st->lock); 169 ret = ad9467_spi_write(spi, reg, writeval); 170 if (ret) 171 return ret; 172 return ad9467_spi_write(spi, AN877_ADC_REG_TRANSFER, 173 AN877_ADC_TRANSFER_SYNC); 174 } 175 176 ret = ad9467_spi_read(spi, reg); 177 if (ret < 0) 178 return ret; 179 *readval = ret; 180 181 return 0; 182} 183 184static const unsigned int ad9265_scale_table[][2] = { 185 {1250, 0x00}, {1500, 0x40}, {1750, 0x80}, {2000, 0xC0}, 186}; 187 188static const unsigned int ad9434_scale_table[][2] = { 189 {1600, 0x1C}, {1580, 0x1D}, {1550, 0x1E}, {1520, 0x1F}, {1500, 0x00}, 190 {1470, 0x01}, {1440, 0x02}, {1420, 0x03}, {1390, 0x04}, {1360, 0x05}, 191 {1340, 0x06}, {1310, 0x07}, {1280, 0x08}, {1260, 0x09}, {1230, 0x0A}, 192 {1200, 0x0B}, {1180, 0x0C}, 193}; 194 195static const unsigned int ad9467_scale_table[][2] = { 196 {2000, 0}, {2100, 6}, {2200, 7}, 197 {2300, 8}, {2400, 9}, {2500, 10}, 198}; 199 200static void __ad9467_get_scale(struct adi_axi_adc_conv *conv, int index, 201 unsigned int *val, unsigned int *val2) 202{ 203 const struct adi_axi_adc_chip_info *info = conv->chip_info; 204 const struct iio_chan_spec *chan = &info->channels[0]; 205 unsigned int tmp; 206 207 tmp = (info->scale_table[index][0] * 1000000ULL) >> 208 chan->scan_type.realbits; 209 *val = tmp / 1000000; 210 *val2 = tmp % 1000000; 211} 212 213#define AD9467_CHAN(_chan, _si, _bits, _sign) \ 214{ \ 215 .type = IIO_VOLTAGE, \ 216 .indexed = 1, \ 217 .channel = _chan, \ 218 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ 219 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 220 .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE), \ 221 .scan_index = _si, \ 222 .scan_type = { \ 223 .sign = _sign, \ 224 .realbits = _bits, \ 225 .storagebits = 16, \ 226 }, \ 227} 228 229static const struct iio_chan_spec ad9434_channels[] = { 230 AD9467_CHAN(0, 0, 12, 'S'), 231}; 232 233static const struct iio_chan_spec ad9467_channels[] = { 234 AD9467_CHAN(0, 0, 16, 'S'), 235}; 236 237static const struct ad9467_chip_info ad9467_chip_tbl[] = { 238 [ID_AD9265] = { 239 .axi_adc_info = { 240 .id = CHIPID_AD9265, 241 .max_rate = 125000000UL, 242 .scale_table = ad9265_scale_table, 243 .num_scales = ARRAY_SIZE(ad9265_scale_table), 244 .channels = ad9467_channels, 245 .num_channels = ARRAY_SIZE(ad9467_channels), 246 }, 247 .default_output_mode = AD9265_DEF_OUTPUT_MODE, 248 .vref_mask = AD9265_REG_VREF_MASK, 249 }, 250 [ID_AD9434] = { 251 .axi_adc_info = { 252 .id = CHIPID_AD9434, 253 .max_rate = 500000000UL, 254 .scale_table = ad9434_scale_table, 255 .num_scales = ARRAY_SIZE(ad9434_scale_table), 256 .channels = ad9434_channels, 257 .num_channels = ARRAY_SIZE(ad9434_channels), 258 }, 259 .default_output_mode = AD9434_DEF_OUTPUT_MODE, 260 .vref_mask = AD9434_REG_VREF_MASK, 261 }, 262 [ID_AD9467] = { 263 .axi_adc_info = { 264 .id = CHIPID_AD9467, 265 .max_rate = 250000000UL, 266 .scale_table = ad9467_scale_table, 267 .num_scales = ARRAY_SIZE(ad9467_scale_table), 268 .channels = ad9467_channels, 269 .num_channels = ARRAY_SIZE(ad9467_channels), 270 }, 271 .default_output_mode = AD9467_DEF_OUTPUT_MODE, 272 .vref_mask = AD9467_REG_VREF_MASK, 273 }, 274}; 275 276static int ad9467_get_scale(struct adi_axi_adc_conv *conv, int *val, int *val2) 277{ 278 const struct adi_axi_adc_chip_info *info = conv->chip_info; 279 const struct ad9467_chip_info *info1 = to_ad9467_chip_info(info); 280 struct ad9467_state *st = adi_axi_adc_conv_priv(conv); 281 unsigned int i, vref_val; 282 int ret; 283 284 ret = ad9467_spi_read(st->spi, AN877_ADC_REG_VREF); 285 if (ret < 0) 286 return ret; 287 288 vref_val = ret & info1->vref_mask; 289 290 for (i = 0; i < info->num_scales; i++) { 291 if (vref_val == info->scale_table[i][1]) 292 break; 293 } 294 295 if (i == info->num_scales) 296 return -ERANGE; 297 298 __ad9467_get_scale(conv, i, val, val2); 299 300 return IIO_VAL_INT_PLUS_MICRO; 301} 302 303static int ad9467_set_scale(struct adi_axi_adc_conv *conv, int val, int val2) 304{ 305 const struct adi_axi_adc_chip_info *info = conv->chip_info; 306 struct ad9467_state *st = adi_axi_adc_conv_priv(conv); 307 unsigned int scale_val[2]; 308 unsigned int i; 309 int ret; 310 311 if (val != 0) 312 return -EINVAL; 313 314 for (i = 0; i < info->num_scales; i++) { 315 __ad9467_get_scale(conv, i, &scale_val[0], &scale_val[1]); 316 if (scale_val[0] != val || scale_val[1] != val2) 317 continue; 318 319 guard(mutex)(&st->lock); 320 ret = ad9467_spi_write(st->spi, AN877_ADC_REG_VREF, 321 info->scale_table[i][1]); 322 if (ret < 0) 323 return ret; 324 325 return ad9467_spi_write(st->spi, AN877_ADC_REG_TRANSFER, 326 AN877_ADC_TRANSFER_SYNC); 327 } 328 329 return -EINVAL; 330} 331 332static int ad9467_read_raw(struct adi_axi_adc_conv *conv, 333 struct iio_chan_spec const *chan, 334 int *val, int *val2, long m) 335{ 336 struct ad9467_state *st = adi_axi_adc_conv_priv(conv); 337 338 switch (m) { 339 case IIO_CHAN_INFO_SCALE: 340 return ad9467_get_scale(conv, val, val2); 341 case IIO_CHAN_INFO_SAMP_FREQ: 342 *val = clk_get_rate(st->clk); 343 344 return IIO_VAL_INT; 345 default: 346 return -EINVAL; 347 } 348} 349 350static int ad9467_write_raw(struct adi_axi_adc_conv *conv, 351 struct iio_chan_spec const *chan, 352 int val, int val2, long mask) 353{ 354 const struct adi_axi_adc_chip_info *info = conv->chip_info; 355 struct ad9467_state *st = adi_axi_adc_conv_priv(conv); 356 long r_clk; 357 358 switch (mask) { 359 case IIO_CHAN_INFO_SCALE: 360 return ad9467_set_scale(conv, val, val2); 361 case IIO_CHAN_INFO_SAMP_FREQ: 362 r_clk = clk_round_rate(st->clk, val); 363 if (r_clk < 0 || r_clk > info->max_rate) { 364 dev_warn(&st->spi->dev, 365 "Error setting ADC sample rate %ld", r_clk); 366 return -EINVAL; 367 } 368 369 return clk_set_rate(st->clk, r_clk); 370 default: 371 return -EINVAL; 372 } 373} 374 375static int ad9467_read_avail(struct adi_axi_adc_conv *conv, 376 struct iio_chan_spec const *chan, 377 const int **vals, int *type, int *length, 378 long mask) 379{ 380 const struct adi_axi_adc_chip_info *info = conv->chip_info; 381 struct ad9467_state *st = adi_axi_adc_conv_priv(conv); 382 383 switch (mask) { 384 case IIO_CHAN_INFO_SCALE: 385 *vals = (const int *)st->scales; 386 *type = IIO_VAL_INT_PLUS_MICRO; 387 /* Values are stored in a 2D matrix */ 388 *length = info->num_scales * 2; 389 return IIO_AVAIL_LIST; 390 default: 391 return -EINVAL; 392 } 393} 394 395static int ad9467_outputmode_set(struct spi_device *spi, unsigned int mode) 396{ 397 int ret; 398 399 ret = ad9467_spi_write(spi, AN877_ADC_REG_OUTPUT_MODE, mode); 400 if (ret < 0) 401 return ret; 402 403 return ad9467_spi_write(spi, AN877_ADC_REG_TRANSFER, 404 AN877_ADC_TRANSFER_SYNC); 405} 406 407static int ad9467_scale_fill(struct adi_axi_adc_conv *conv) 408{ 409 const struct adi_axi_adc_chip_info *info = conv->chip_info; 410 struct ad9467_state *st = adi_axi_adc_conv_priv(conv); 411 unsigned int i, val1, val2; 412 413 st->scales = devm_kmalloc_array(&st->spi->dev, info->num_scales, 414 sizeof(*st->scales), GFP_KERNEL); 415 if (!st->scales) 416 return -ENOMEM; 417 418 for (i = 0; i < info->num_scales; i++) { 419 __ad9467_get_scale(conv, i, &val1, &val2); 420 st->scales[i][0] = val1; 421 st->scales[i][1] = val2; 422 } 423 424 return 0; 425} 426 427static int ad9467_preenable_setup(struct adi_axi_adc_conv *conv) 428{ 429 struct ad9467_state *st = adi_axi_adc_conv_priv(conv); 430 431 return ad9467_outputmode_set(st->spi, st->output_mode); 432} 433 434static int ad9467_reset(struct device *dev) 435{ 436 struct gpio_desc *gpio; 437 438 gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH); 439 if (IS_ERR_OR_NULL(gpio)) 440 return PTR_ERR_OR_ZERO(gpio); 441 442 fsleep(1); 443 gpiod_set_value_cansleep(gpio, 0); 444 fsleep(10 * USEC_PER_MSEC); 445 446 return 0; 447} 448 449static int ad9467_probe(struct spi_device *spi) 450{ 451 const struct ad9467_chip_info *info; 452 struct adi_axi_adc_conv *conv; 453 struct ad9467_state *st; 454 unsigned int id; 455 int ret; 456 457 info = of_device_get_match_data(&spi->dev); 458 if (!info) 459 info = (void *)spi_get_device_id(spi)->driver_data; 460 if (!info) 461 return -ENODEV; 462 463 conv = devm_adi_axi_adc_conv_register(&spi->dev, sizeof(*st)); 464 if (IS_ERR(conv)) 465 return PTR_ERR(conv); 466 467 st = adi_axi_adc_conv_priv(conv); 468 st->spi = spi; 469 470 st->clk = devm_clk_get_enabled(&spi->dev, "adc-clk"); 471 if (IS_ERR(st->clk)) 472 return PTR_ERR(st->clk); 473 474 st->pwrdown_gpio = devm_gpiod_get_optional(&spi->dev, "powerdown", 475 GPIOD_OUT_LOW); 476 if (IS_ERR(st->pwrdown_gpio)) 477 return PTR_ERR(st->pwrdown_gpio); 478 479 ret = ad9467_reset(&spi->dev); 480 if (ret) 481 return ret; 482 483 conv->chip_info = &info->axi_adc_info; 484 485 ret = ad9467_scale_fill(conv); 486 if (ret) 487 return ret; 488 489 id = ad9467_spi_read(spi, AN877_ADC_REG_CHIP_ID); 490 if (id != conv->chip_info->id) { 491 dev_err(&spi->dev, "Mismatch CHIP_ID, got 0x%X, expected 0x%X\n", 492 id, conv->chip_info->id); 493 return -ENODEV; 494 } 495 496 conv->reg_access = ad9467_reg_access; 497 conv->write_raw = ad9467_write_raw; 498 conv->read_raw = ad9467_read_raw; 499 conv->read_avail = ad9467_read_avail; 500 conv->preenable_setup = ad9467_preenable_setup; 501 502 st->output_mode = info->default_output_mode | 503 AN877_ADC_OUTPUT_MODE_TWOS_COMPLEMENT; 504 505 return 0; 506} 507 508static const struct of_device_id ad9467_of_match[] = { 509 { .compatible = "adi,ad9265", .data = &ad9467_chip_tbl[ID_AD9265], }, 510 { .compatible = "adi,ad9434", .data = &ad9467_chip_tbl[ID_AD9434], }, 511 { .compatible = "adi,ad9467", .data = &ad9467_chip_tbl[ID_AD9467], }, 512 {} 513}; 514MODULE_DEVICE_TABLE(of, ad9467_of_match); 515 516static const struct spi_device_id ad9467_ids[] = { 517 { "ad9265", (kernel_ulong_t)&ad9467_chip_tbl[ID_AD9265] }, 518 { "ad9434", (kernel_ulong_t)&ad9467_chip_tbl[ID_AD9434] }, 519 { "ad9467", (kernel_ulong_t)&ad9467_chip_tbl[ID_AD9467] }, 520 {} 521}; 522MODULE_DEVICE_TABLE(spi, ad9467_ids); 523 524static struct spi_driver ad9467_driver = { 525 .driver = { 526 .name = "ad9467", 527 .of_match_table = ad9467_of_match, 528 }, 529 .probe = ad9467_probe, 530 .id_table = ad9467_ids, 531}; 532module_spi_driver(ad9467_driver); 533 534MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>"); 535MODULE_DESCRIPTION("Analog Devices AD9467 ADC driver"); 536MODULE_LICENSE("GPL v2"); 537MODULE_IMPORT_NS(IIO_ADI_AXI); 538