1// SPDX-License-Identifier: GPL-2.0-or-later 2/* linux/drivers/i2c/busses/i2c-s3c2410.c 3 * 4 * Copyright (C) 2004,2005,2009 Simtec Electronics 5 * Ben Dooks <ben@simtec.co.uk> 6 * 7 * S3C2410 I2C Controller 8*/ 9 10#include <linux/kernel.h> 11#include <linux/module.h> 12 13#include <linux/i2c.h> 14#include <linux/init.h> 15#include <linux/time.h> 16#include <linux/interrupt.h> 17#include <linux/delay.h> 18#include <linux/errno.h> 19#include <linux/err.h> 20#include <linux/platform_device.h> 21#include <linux/pm_runtime.h> 22#include <linux/clk.h> 23#include <linux/cpufreq.h> 24#include <linux/slab.h> 25#include <linux/io.h> 26#include <linux/of.h> 27#include <linux/gpio/consumer.h> 28#include <linux/pinctrl/consumer.h> 29#include <linux/mfd/syscon.h> 30#include <linux/regmap.h> 31 32#include <asm/irq.h> 33 34#include <linux/platform_data/i2c-s3c2410.h> 35 36/* see s3c2410x user guide, v1.1, section 9 (p447) for more info */ 37 38#define S3C2410_IICCON 0x00 39#define S3C2410_IICSTAT 0x04 40#define S3C2410_IICADD 0x08 41#define S3C2410_IICDS 0x0C 42#define S3C2440_IICLC 0x10 43 44#define S3C2410_IICCON_ACKEN (1 << 7) 45#define S3C2410_IICCON_TXDIV_16 (0 << 6) 46#define S3C2410_IICCON_TXDIV_512 (1 << 6) 47#define S3C2410_IICCON_IRQEN (1 << 5) 48#define S3C2410_IICCON_IRQPEND (1 << 4) 49#define S3C2410_IICCON_SCALE(x) ((x) & 0xf) 50#define S3C2410_IICCON_SCALEMASK (0xf) 51 52#define S3C2410_IICSTAT_MASTER_RX (2 << 6) 53#define S3C2410_IICSTAT_MASTER_TX (3 << 6) 54#define S3C2410_IICSTAT_SLAVE_RX (0 << 6) 55#define S3C2410_IICSTAT_SLAVE_TX (1 << 6) 56#define S3C2410_IICSTAT_MODEMASK (3 << 6) 57 58#define S3C2410_IICSTAT_START (1 << 5) 59#define S3C2410_IICSTAT_BUSBUSY (1 << 5) 60#define S3C2410_IICSTAT_TXRXEN (1 << 4) 61#define S3C2410_IICSTAT_ARBITR (1 << 3) 62#define S3C2410_IICSTAT_ASSLAVE (1 << 2) 63#define S3C2410_IICSTAT_ADDR0 (1 << 1) 64#define S3C2410_IICSTAT_LASTBIT (1 << 0) 65 66#define S3C2410_IICLC_SDA_DELAY0 (0 << 0) 67#define S3C2410_IICLC_SDA_DELAY5 (1 << 0) 68#define S3C2410_IICLC_SDA_DELAY10 (2 << 0) 69#define S3C2410_IICLC_SDA_DELAY15 (3 << 0) 70#define S3C2410_IICLC_SDA_DELAY_MASK (3 << 0) 71 72#define S3C2410_IICLC_FILTER_ON (1 << 2) 73 74/* Treat S3C2410 as baseline hardware, anything else is supported via quirks */ 75#define QUIRK_S3C2440 (1 << 0) 76#define QUIRK_HDMIPHY (1 << 1) 77#define QUIRK_NO_GPIO (1 << 2) 78#define QUIRK_POLL (1 << 3) 79 80/* Max time to wait for bus to become idle after a xfer (in us) */ 81#define S3C2410_IDLE_TIMEOUT 5000 82 83/* Exynos5 Sysreg offset */ 84#define EXYNOS5_SYS_I2C_CFG 0x0234 85 86/* i2c controller state */ 87enum s3c24xx_i2c_state { 88 STATE_IDLE, 89 STATE_START, 90 STATE_READ, 91 STATE_WRITE, 92 STATE_STOP 93}; 94 95struct s3c24xx_i2c { 96 wait_queue_head_t wait; 97 kernel_ulong_t quirks; 98 99 struct i2c_msg *msg; 100 unsigned int msg_num; 101 unsigned int msg_idx; 102 unsigned int msg_ptr; 103 104 unsigned int tx_setup; 105 unsigned int irq; 106 107 enum s3c24xx_i2c_state state; 108 unsigned long clkrate; 109 110 void __iomem *regs; 111 struct clk *clk; 112 struct device *dev; 113 struct i2c_adapter adap; 114 115 struct s3c2410_platform_i2c *pdata; 116 struct gpio_desc *gpios[2]; 117 struct pinctrl *pctrl; 118 struct regmap *sysreg; 119 unsigned int sys_i2c_cfg; 120}; 121 122static const struct platform_device_id s3c24xx_driver_ids[] = { 123 { 124 .name = "s3c2410-i2c", 125 .driver_data = 0, 126 }, { 127 .name = "s3c2440-i2c", 128 .driver_data = QUIRK_S3C2440, 129 }, { 130 .name = "s3c2440-hdmiphy-i2c", 131 .driver_data = QUIRK_S3C2440 | QUIRK_HDMIPHY | QUIRK_NO_GPIO, 132 }, { }, 133}; 134MODULE_DEVICE_TABLE(platform, s3c24xx_driver_ids); 135 136static int i2c_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat); 137 138#ifdef CONFIG_OF 139static const struct of_device_id s3c24xx_i2c_match[] = { 140 { .compatible = "samsung,s3c2410-i2c", .data = (void *)0 }, 141 { .compatible = "samsung,s3c2440-i2c", .data = (void *)QUIRK_S3C2440 }, 142 { .compatible = "samsung,s3c2440-hdmiphy-i2c", 143 .data = (void *)(QUIRK_S3C2440 | QUIRK_HDMIPHY | QUIRK_NO_GPIO) }, 144 { .compatible = "samsung,exynos5-sata-phy-i2c", 145 .data = (void *)(QUIRK_S3C2440 | QUIRK_POLL | QUIRK_NO_GPIO) }, 146 {}, 147}; 148MODULE_DEVICE_TABLE(of, s3c24xx_i2c_match); 149#endif 150 151/* 152 * Get controller type either from device tree or platform device variant. 153 */ 154static inline kernel_ulong_t s3c24xx_get_device_quirks(struct platform_device *pdev) 155{ 156 if (pdev->dev.of_node) 157 return (kernel_ulong_t)of_device_get_match_data(&pdev->dev); 158 159 return platform_get_device_id(pdev)->driver_data; 160} 161 162/* 163 * Complete the message and wake up the caller, using the given return code, 164 * or zero to mean ok. 165 */ 166static inline void s3c24xx_i2c_master_complete(struct s3c24xx_i2c *i2c, int ret) 167{ 168 dev_dbg(i2c->dev, "master_complete %d\n", ret); 169 170 i2c->msg_ptr = 0; 171 i2c->msg = NULL; 172 i2c->msg_idx++; 173 i2c->msg_num = 0; 174 if (ret) 175 i2c->msg_idx = ret; 176 177 if (!(i2c->quirks & QUIRK_POLL)) 178 wake_up(&i2c->wait); 179} 180 181static inline void s3c24xx_i2c_disable_ack(struct s3c24xx_i2c *i2c) 182{ 183 unsigned long tmp; 184 185 tmp = readl(i2c->regs + S3C2410_IICCON); 186 writel(tmp & ~S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON); 187} 188 189static inline void s3c24xx_i2c_enable_ack(struct s3c24xx_i2c *i2c) 190{ 191 unsigned long tmp; 192 193 tmp = readl(i2c->regs + S3C2410_IICCON); 194 writel(tmp | S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON); 195} 196 197/* irq enable/disable functions */ 198static inline void s3c24xx_i2c_disable_irq(struct s3c24xx_i2c *i2c) 199{ 200 unsigned long tmp; 201 202 tmp = readl(i2c->regs + S3C2410_IICCON); 203 writel(tmp & ~S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON); 204} 205 206static inline void s3c24xx_i2c_enable_irq(struct s3c24xx_i2c *i2c) 207{ 208 unsigned long tmp; 209 210 tmp = readl(i2c->regs + S3C2410_IICCON); 211 writel(tmp | S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON); 212} 213 214static bool is_ack(struct s3c24xx_i2c *i2c) 215{ 216 int tries; 217 218 for (tries = 50; tries; --tries) { 219 unsigned long tmp = readl(i2c->regs + S3C2410_IICCON); 220 221 if (!(tmp & S3C2410_IICCON_ACKEN)) { 222 /* 223 * Wait a bit for the bus to stabilize, 224 * delay estimated experimentally. 225 */ 226 usleep_range(100, 200); 227 return true; 228 } 229 if (tmp & S3C2410_IICCON_IRQPEND) { 230 if (!(readl(i2c->regs + S3C2410_IICSTAT) 231 & S3C2410_IICSTAT_LASTBIT)) 232 return true; 233 } 234 usleep_range(1000, 2000); 235 } 236 dev_err(i2c->dev, "ack was not received\n"); 237 return false; 238} 239 240/* 241 * put the start of a message onto the bus 242 */ 243static void s3c24xx_i2c_message_start(struct s3c24xx_i2c *i2c, 244 struct i2c_msg *msg) 245{ 246 unsigned int addr = (msg->addr & 0x7f) << 1; 247 unsigned long stat; 248 unsigned long iiccon; 249 250 stat = 0; 251 stat |= S3C2410_IICSTAT_TXRXEN; 252 253 if (msg->flags & I2C_M_RD) { 254 stat |= S3C2410_IICSTAT_MASTER_RX; 255 addr |= 1; 256 } else 257 stat |= S3C2410_IICSTAT_MASTER_TX; 258 259 if (msg->flags & I2C_M_REV_DIR_ADDR) 260 addr ^= 1; 261 262 /* todo - check for whether ack wanted or not */ 263 s3c24xx_i2c_enable_ack(i2c); 264 265 iiccon = readl(i2c->regs + S3C2410_IICCON); 266 writel(stat, i2c->regs + S3C2410_IICSTAT); 267 268 dev_dbg(i2c->dev, "START: %08lx to IICSTAT, %02x to DS\n", stat, addr); 269 writeb(addr, i2c->regs + S3C2410_IICDS); 270 271 /* 272 * delay here to ensure the data byte has gotten onto the bus 273 * before the transaction is started 274 */ 275 ndelay(i2c->tx_setup); 276 277 dev_dbg(i2c->dev, "iiccon, %08lx\n", iiccon); 278 writel(iiccon, i2c->regs + S3C2410_IICCON); 279 280 stat |= S3C2410_IICSTAT_START; 281 writel(stat, i2c->regs + S3C2410_IICSTAT); 282} 283 284static inline void s3c24xx_i2c_stop(struct s3c24xx_i2c *i2c, int ret) 285{ 286 unsigned long iicstat = readl(i2c->regs + S3C2410_IICSTAT); 287 288 dev_dbg(i2c->dev, "STOP\n"); 289 290 /* 291 * The datasheet says that the STOP sequence should be: 292 * 1) I2CSTAT.5 = 0 - Clear BUSY (or 'generate STOP') 293 * 2) I2CCON.4 = 0 - Clear IRQPEND 294 * 3) Wait until the stop condition takes effect. 295 * 4*) I2CSTAT.4 = 0 - Clear TXRXEN 296 * 297 * Where, step "4*" is only for buses with the "HDMIPHY" quirk. 298 * 299 * However, after much experimentation, it appears that: 300 * a) normal buses automatically clear BUSY and transition from 301 * Master->Slave when they complete generating a STOP condition. 302 * Therefore, step (3) can be done in doxfer() by polling I2CCON.4 303 * after starting the STOP generation here. 304 * b) HDMIPHY bus does neither, so there is no way to do step 3. 305 * There is no indication when this bus has finished generating 306 * STOP. 307 * 308 * In fact, we have found that as soon as the IRQPEND bit is cleared in 309 * step 2, the HDMIPHY bus generates the STOP condition, and then 310 * immediately starts transferring another data byte, even though the 311 * bus is supposedly stopped. This is presumably because the bus is 312 * still in "Master" mode, and its BUSY bit is still set. 313 * 314 * To avoid these extra post-STOP transactions on HDMI phy devices, we 315 * just disable Serial Output on the bus (I2CSTAT.4 = 0) directly, 316 * instead of first generating a proper STOP condition. This should 317 * float SDA & SCK terminating the transfer. Subsequent transfers 318 * start with a proper START condition, and proceed normally. 319 * 320 * The HDMIPHY bus is an internal bus that always has exactly two 321 * devices, the host as Master and the HDMIPHY device as the slave. 322 * Skipping the STOP condition has been tested on this bus and works. 323 */ 324 if (i2c->quirks & QUIRK_HDMIPHY) { 325 /* Stop driving the I2C pins */ 326 iicstat &= ~S3C2410_IICSTAT_TXRXEN; 327 } else { 328 /* stop the transfer */ 329 iicstat &= ~S3C2410_IICSTAT_START; 330 } 331 writel(iicstat, i2c->regs + S3C2410_IICSTAT); 332 333 i2c->state = STATE_STOP; 334 335 s3c24xx_i2c_master_complete(i2c, ret); 336 s3c24xx_i2c_disable_irq(i2c); 337} 338 339/* 340 * helper functions to determine the current state in the set of 341 * messages we are sending 342 */ 343 344/* 345 * returns TRUE if the current message is the last in the set 346 */ 347static inline int is_lastmsg(struct s3c24xx_i2c *i2c) 348{ 349 return i2c->msg_idx >= (i2c->msg_num - 1); 350} 351 352/* 353 * returns TRUE if we this is the last byte in the current message 354 */ 355static inline int is_msglast(struct s3c24xx_i2c *i2c) 356{ 357 /* 358 * msg->len is always 1 for the first byte of smbus block read. 359 * Actual length will be read from slave. More bytes will be 360 * read according to the length then. 361 */ 362 if (i2c->msg->flags & I2C_M_RECV_LEN && i2c->msg->len == 1) 363 return 0; 364 365 return i2c->msg_ptr == i2c->msg->len-1; 366} 367 368/* 369 * returns TRUE if we reached the end of the current message 370 */ 371static inline int is_msgend(struct s3c24xx_i2c *i2c) 372{ 373 return i2c->msg_ptr >= i2c->msg->len; 374} 375 376/* 377 * process an interrupt and work out what to do 378 */ 379static int i2c_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat) 380{ 381 unsigned long tmp; 382 unsigned char byte; 383 int ret = 0; 384 385 switch (i2c->state) { 386 387 case STATE_IDLE: 388 dev_err(i2c->dev, "%s: called in STATE_IDLE\n", __func__); 389 goto out; 390 391 case STATE_STOP: 392 dev_err(i2c->dev, "%s: called in STATE_STOP\n", __func__); 393 s3c24xx_i2c_disable_irq(i2c); 394 goto out_ack; 395 396 case STATE_START: 397 /* 398 * last thing we did was send a start condition on the 399 * bus, or started a new i2c message 400 */ 401 if (iicstat & S3C2410_IICSTAT_LASTBIT && 402 !(i2c->msg->flags & I2C_M_IGNORE_NAK)) { 403 /* ack was not received... */ 404 dev_dbg(i2c->dev, "ack was not received\n"); 405 s3c24xx_i2c_stop(i2c, -ENXIO); 406 goto out_ack; 407 } 408 409 if (i2c->msg->flags & I2C_M_RD) 410 i2c->state = STATE_READ; 411 else 412 i2c->state = STATE_WRITE; 413 414 /* 415 * Terminate the transfer if there is nothing to do 416 * as this is used by the i2c probe to find devices. 417 */ 418 if (is_lastmsg(i2c) && i2c->msg->len == 0) { 419 s3c24xx_i2c_stop(i2c, 0); 420 goto out_ack; 421 } 422 423 if (i2c->state == STATE_READ) 424 goto prepare_read; 425 426 /* 427 * fall through to the write state, as we will need to 428 * send a byte as well 429 */ 430 fallthrough; 431 case STATE_WRITE: 432 /* 433 * we are writing data to the device... check for the 434 * end of the message, and if so, work out what to do 435 */ 436 if (!(i2c->msg->flags & I2C_M_IGNORE_NAK)) { 437 if (iicstat & S3C2410_IICSTAT_LASTBIT) { 438 dev_dbg(i2c->dev, "WRITE: No Ack\n"); 439 440 s3c24xx_i2c_stop(i2c, -ECONNREFUSED); 441 goto out_ack; 442 } 443 } 444 445 retry_write: 446 447 if (!is_msgend(i2c)) { 448 byte = i2c->msg->buf[i2c->msg_ptr++]; 449 writeb(byte, i2c->regs + S3C2410_IICDS); 450 451 /* 452 * delay after writing the byte to allow the 453 * data setup time on the bus, as writing the 454 * data to the register causes the first bit 455 * to appear on SDA, and SCL will change as 456 * soon as the interrupt is acknowledged 457 */ 458 ndelay(i2c->tx_setup); 459 460 } else if (!is_lastmsg(i2c)) { 461 /* we need to go to the next i2c message */ 462 463 dev_dbg(i2c->dev, "WRITE: Next Message\n"); 464 465 i2c->msg_ptr = 0; 466 i2c->msg_idx++; 467 i2c->msg++; 468 469 /* check to see if we need to do another message */ 470 if (i2c->msg->flags & I2C_M_NOSTART) { 471 472 if (i2c->msg->flags & I2C_M_RD) { 473 /* 474 * cannot do this, the controller 475 * forces us to send a new START 476 * when we change direction 477 */ 478 dev_dbg(i2c->dev, 479 "missing START before write->read\n"); 480 s3c24xx_i2c_stop(i2c, -EINVAL); 481 break; 482 } 483 484 goto retry_write; 485 } else { 486 /* send the new start */ 487 s3c24xx_i2c_message_start(i2c, i2c->msg); 488 i2c->state = STATE_START; 489 } 490 491 } else { 492 /* send stop */ 493 s3c24xx_i2c_stop(i2c, 0); 494 } 495 break; 496 497 case STATE_READ: 498 /* 499 * we have a byte of data in the data register, do 500 * something with it, and then work out whether we are 501 * going to do any more read/write 502 */ 503 byte = readb(i2c->regs + S3C2410_IICDS); 504 i2c->msg->buf[i2c->msg_ptr++] = byte; 505 506 /* Add actual length to read for smbus block read */ 507 if (i2c->msg->flags & I2C_M_RECV_LEN && i2c->msg->len == 1) 508 i2c->msg->len += byte; 509 prepare_read: 510 if (is_msglast(i2c)) { 511 /* last byte of buffer */ 512 513 if (is_lastmsg(i2c)) 514 s3c24xx_i2c_disable_ack(i2c); 515 516 } else if (is_msgend(i2c)) { 517 /* 518 * ok, we've read the entire buffer, see if there 519 * is anything else we need to do 520 */ 521 if (is_lastmsg(i2c)) { 522 /* last message, send stop and complete */ 523 dev_dbg(i2c->dev, "READ: Send Stop\n"); 524 525 s3c24xx_i2c_stop(i2c, 0); 526 } else { 527 /* go to the next transfer */ 528 dev_dbg(i2c->dev, "READ: Next Transfer\n"); 529 530 i2c->msg_ptr = 0; 531 i2c->msg_idx++; 532 i2c->msg++; 533 } 534 } 535 536 break; 537 } 538 539 /* acknowlegde the IRQ and get back on with the work */ 540 541 out_ack: 542 tmp = readl(i2c->regs + S3C2410_IICCON); 543 tmp &= ~S3C2410_IICCON_IRQPEND; 544 writel(tmp, i2c->regs + S3C2410_IICCON); 545 out: 546 return ret; 547} 548 549/* 550 * top level IRQ servicing routine 551 */ 552static irqreturn_t s3c24xx_i2c_irq(int irqno, void *dev_id) 553{ 554 struct s3c24xx_i2c *i2c = dev_id; 555 unsigned long status; 556 unsigned long tmp; 557 558 status = readl(i2c->regs + S3C2410_IICSTAT); 559 560 if (status & S3C2410_IICSTAT_ARBITR) { 561 /* deal with arbitration loss */ 562 dev_err(i2c->dev, "deal with arbitration loss\n"); 563 } 564 565 if (i2c->state == STATE_IDLE) { 566 dev_dbg(i2c->dev, "IRQ: error i2c->state == IDLE\n"); 567 568 tmp = readl(i2c->regs + S3C2410_IICCON); 569 tmp &= ~S3C2410_IICCON_IRQPEND; 570 writel(tmp, i2c->regs + S3C2410_IICCON); 571 goto out; 572 } 573 574 /* 575 * pretty much this leaves us with the fact that we've 576 * transmitted or received whatever byte we last sent 577 */ 578 i2c_s3c_irq_nextbyte(i2c, status); 579 580 out: 581 return IRQ_HANDLED; 582} 583 584/* 585 * Disable the bus so that we won't get any interrupts from now on, or try 586 * to drive any lines. This is the default state when we don't have 587 * anything to send/receive. 588 * 589 * If there is an event on the bus, or we have a pre-existing event at 590 * kernel boot time, we may not notice the event and the I2C controller 591 * will lock the bus with the I2C clock line low indefinitely. 592 */ 593static inline void s3c24xx_i2c_disable_bus(struct s3c24xx_i2c *i2c) 594{ 595 unsigned long tmp; 596 597 /* Stop driving the I2C pins */ 598 tmp = readl(i2c->regs + S3C2410_IICSTAT); 599 tmp &= ~S3C2410_IICSTAT_TXRXEN; 600 writel(tmp, i2c->regs + S3C2410_IICSTAT); 601 602 /* We don't expect any interrupts now, and don't want send acks */ 603 tmp = readl(i2c->regs + S3C2410_IICCON); 604 tmp &= ~(S3C2410_IICCON_IRQEN | S3C2410_IICCON_IRQPEND | 605 S3C2410_IICCON_ACKEN); 606 writel(tmp, i2c->regs + S3C2410_IICCON); 607} 608 609 610/* 611 * get the i2c bus for a master transaction 612 */ 613static int s3c24xx_i2c_set_master(struct s3c24xx_i2c *i2c) 614{ 615 unsigned long iicstat; 616 int timeout = 400; 617 618 while (timeout-- > 0) { 619 iicstat = readl(i2c->regs + S3C2410_IICSTAT); 620 621 if (!(iicstat & S3C2410_IICSTAT_BUSBUSY)) 622 return 0; 623 624 msleep(1); 625 } 626 627 return -ETIMEDOUT; 628} 629 630/* 631 * wait for the i2c bus to become idle. 632 */ 633static void s3c24xx_i2c_wait_idle(struct s3c24xx_i2c *i2c) 634{ 635 unsigned long iicstat; 636 ktime_t start, now; 637 unsigned long delay; 638 int spins; 639 640 /* ensure the stop has been through the bus */ 641 642 dev_dbg(i2c->dev, "waiting for bus idle\n"); 643 644 start = now = ktime_get(); 645 646 /* 647 * Most of the time, the bus is already idle within a few usec of the 648 * end of a transaction. However, really slow i2c devices can stretch 649 * the clock, delaying STOP generation. 650 * 651 * On slower SoCs this typically happens within a very small number of 652 * instructions so busy wait briefly to avoid scheduling overhead. 653 */ 654 spins = 3; 655 iicstat = readl(i2c->regs + S3C2410_IICSTAT); 656 while ((iicstat & S3C2410_IICSTAT_START) && --spins) { 657 cpu_relax(); 658 iicstat = readl(i2c->regs + S3C2410_IICSTAT); 659 } 660 661 /* 662 * If we do get an appreciable delay as a compromise between idle 663 * detection latency for the normal, fast case, and system load in the 664 * slow device case, use an exponential back off in the polling loop, 665 * up to 1/10th of the total timeout, then continue to poll at a 666 * constant rate up to the timeout. 667 */ 668 delay = 1; 669 while ((iicstat & S3C2410_IICSTAT_START) && 670 ktime_us_delta(now, start) < S3C2410_IDLE_TIMEOUT) { 671 usleep_range(delay, 2 * delay); 672 if (delay < S3C2410_IDLE_TIMEOUT / 10) 673 delay <<= 1; 674 now = ktime_get(); 675 iicstat = readl(i2c->regs + S3C2410_IICSTAT); 676 } 677 678 if (iicstat & S3C2410_IICSTAT_START) 679 dev_warn(i2c->dev, "timeout waiting for bus idle\n"); 680} 681 682/* 683 * this starts an i2c transfer 684 */ 685static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c, 686 struct i2c_msg *msgs, int num) 687{ 688 unsigned long timeout = 0; 689 int ret; 690 691 ret = s3c24xx_i2c_set_master(i2c); 692 if (ret != 0) { 693 dev_err(i2c->dev, "cannot get bus (error %d)\n", ret); 694 ret = -EAGAIN; 695 goto out; 696 } 697 698 i2c->msg = msgs; 699 i2c->msg_num = num; 700 i2c->msg_ptr = 0; 701 i2c->msg_idx = 0; 702 i2c->state = STATE_START; 703 704 s3c24xx_i2c_enable_irq(i2c); 705 s3c24xx_i2c_message_start(i2c, msgs); 706 707 if (i2c->quirks & QUIRK_POLL) { 708 while ((i2c->msg_num != 0) && is_ack(i2c)) { 709 unsigned long stat = readl(i2c->regs + S3C2410_IICSTAT); 710 711 i2c_s3c_irq_nextbyte(i2c, stat); 712 713 stat = readl(i2c->regs + S3C2410_IICSTAT); 714 if (stat & S3C2410_IICSTAT_ARBITR) 715 dev_err(i2c->dev, "deal with arbitration loss\n"); 716 } 717 } else { 718 timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5); 719 } 720 721 ret = i2c->msg_idx; 722 723 /* 724 * Having these next two as dev_err() makes life very 725 * noisy when doing an i2cdetect 726 */ 727 if (timeout == 0) 728 dev_dbg(i2c->dev, "timeout\n"); 729 else if (ret != num) 730 dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret); 731 732 /* For QUIRK_HDMIPHY, bus is already disabled */ 733 if (i2c->quirks & QUIRK_HDMIPHY) 734 goto out; 735 736 s3c24xx_i2c_wait_idle(i2c); 737 738 s3c24xx_i2c_disable_bus(i2c); 739 740 out: 741 i2c->state = STATE_IDLE; 742 743 return ret; 744} 745 746/* 747 * first port of call from the i2c bus code when an message needs 748 * transferring across the i2c bus. 749 */ 750static int s3c24xx_i2c_xfer(struct i2c_adapter *adap, 751 struct i2c_msg *msgs, int num) 752{ 753 struct s3c24xx_i2c *i2c = (struct s3c24xx_i2c *)adap->algo_data; 754 int retry; 755 int ret; 756 757 ret = clk_enable(i2c->clk); 758 if (ret) 759 return ret; 760 761 for (retry = 0; retry < adap->retries; retry++) { 762 763 ret = s3c24xx_i2c_doxfer(i2c, msgs, num); 764 765 if (ret != -EAGAIN) { 766 clk_disable(i2c->clk); 767 return ret; 768 } 769 770 dev_dbg(i2c->dev, "Retrying transmission (%d)\n", retry); 771 772 udelay(100); 773 } 774 775 clk_disable(i2c->clk); 776 return -EREMOTEIO; 777} 778 779/* declare our i2c functionality */ 780static u32 s3c24xx_i2c_func(struct i2c_adapter *adap) 781{ 782 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL_ALL | I2C_FUNC_NOSTART | 783 I2C_FUNC_PROTOCOL_MANGLING; 784} 785 786/* i2c bus registration info */ 787static const struct i2c_algorithm s3c24xx_i2c_algorithm = { 788 .master_xfer = s3c24xx_i2c_xfer, 789 .functionality = s3c24xx_i2c_func, 790}; 791 792/* 793 * return the divisor settings for a given frequency 794 */ 795static int s3c24xx_i2c_calcdivisor(unsigned long clkin, unsigned int wanted, 796 unsigned int *div1, unsigned int *divs) 797{ 798 unsigned int calc_divs = clkin / wanted; 799 unsigned int calc_div1; 800 801 if (calc_divs > (16*16)) 802 calc_div1 = 512; 803 else 804 calc_div1 = 16; 805 806 calc_divs += calc_div1-1; 807 calc_divs /= calc_div1; 808 809 if (calc_divs == 0) 810 calc_divs = 1; 811 if (calc_divs > 17) 812 calc_divs = 17; 813 814 *divs = calc_divs; 815 *div1 = calc_div1; 816 817 return clkin / (calc_divs * calc_div1); 818} 819 820/* 821 * work out a divisor for the user requested frequency setting, 822 * either by the requested frequency, or scanning the acceptable 823 * range of frequencies until something is found 824 */ 825static int s3c24xx_i2c_clockrate(struct s3c24xx_i2c *i2c, unsigned int *got) 826{ 827 struct s3c2410_platform_i2c *pdata = i2c->pdata; 828 unsigned long clkin = clk_get_rate(i2c->clk); 829 unsigned int divs, div1; 830 unsigned long target_frequency; 831 u32 iiccon; 832 int freq; 833 834 i2c->clkrate = clkin; 835 clkin /= 1000; /* clkin now in KHz */ 836 837 dev_dbg(i2c->dev, "pdata desired frequency %lu\n", pdata->frequency); 838 839 target_frequency = pdata->frequency ?: I2C_MAX_STANDARD_MODE_FREQ; 840 841 target_frequency /= 1000; /* Target frequency now in KHz */ 842 843 freq = s3c24xx_i2c_calcdivisor(clkin, target_frequency, &div1, &divs); 844 845 if (freq > target_frequency) { 846 dev_err(i2c->dev, 847 "Unable to achieve desired frequency %luKHz." \ 848 " Lowest achievable %dKHz\n", target_frequency, freq); 849 return -EINVAL; 850 } 851 852 *got = freq; 853 854 iiccon = readl(i2c->regs + S3C2410_IICCON); 855 iiccon &= ~(S3C2410_IICCON_SCALEMASK | S3C2410_IICCON_TXDIV_512); 856 iiccon |= (divs-1); 857 858 if (div1 == 512) 859 iiccon |= S3C2410_IICCON_TXDIV_512; 860 861 if (i2c->quirks & QUIRK_POLL) 862 iiccon |= S3C2410_IICCON_SCALE(2); 863 864 writel(iiccon, i2c->regs + S3C2410_IICCON); 865 866 if (i2c->quirks & QUIRK_S3C2440) { 867 unsigned long sda_delay; 868 869 if (pdata->sda_delay) { 870 sda_delay = clkin * pdata->sda_delay; 871 sda_delay = DIV_ROUND_UP(sda_delay, 1000000); 872 sda_delay = DIV_ROUND_UP(sda_delay, 5); 873 if (sda_delay > 3) 874 sda_delay = 3; 875 sda_delay |= S3C2410_IICLC_FILTER_ON; 876 } else 877 sda_delay = 0; 878 879 dev_dbg(i2c->dev, "IICLC=%08lx\n", sda_delay); 880 writel(sda_delay, i2c->regs + S3C2440_IICLC); 881 } 882 883 return 0; 884} 885 886#ifdef CONFIG_OF 887static int s3c24xx_i2c_parse_dt_gpio(struct s3c24xx_i2c *i2c) 888{ 889 int i; 890 891 if (i2c->quirks & QUIRK_NO_GPIO) 892 return 0; 893 894 for (i = 0; i < 2; i++) { 895 i2c->gpios[i] = devm_gpiod_get_index(i2c->dev, NULL, 896 i, GPIOD_ASIS); 897 if (IS_ERR(i2c->gpios[i])) { 898 dev_err(i2c->dev, "i2c gpio invalid at index %d\n", i); 899 return -EINVAL; 900 } 901 } 902 return 0; 903} 904 905#else 906static int s3c24xx_i2c_parse_dt_gpio(struct s3c24xx_i2c *i2c) 907{ 908 return 0; 909} 910#endif 911 912/* 913 * initialise the controller, set the IO lines and frequency 914 */ 915static int s3c24xx_i2c_init(struct s3c24xx_i2c *i2c) 916{ 917 struct s3c2410_platform_i2c *pdata; 918 unsigned int freq; 919 920 /* get the plafrom data */ 921 922 pdata = i2c->pdata; 923 924 /* write slave address */ 925 926 writeb(pdata->slave_addr, i2c->regs + S3C2410_IICADD); 927 928 dev_info(i2c->dev, "slave address 0x%02x\n", pdata->slave_addr); 929 930 writel(0, i2c->regs + S3C2410_IICCON); 931 writel(0, i2c->regs + S3C2410_IICSTAT); 932 933 /* we need to work out the divisors for the clock... */ 934 935 if (s3c24xx_i2c_clockrate(i2c, &freq) != 0) { 936 dev_err(i2c->dev, "cannot meet bus frequency required\n"); 937 return -EINVAL; 938 } 939 940 /* todo - check that the i2c lines aren't being dragged anywhere */ 941 942 dev_info(i2c->dev, "bus frequency set to %d KHz\n", freq); 943 dev_dbg(i2c->dev, "S3C2410_IICCON=0x%02x\n", 944 readl(i2c->regs + S3C2410_IICCON)); 945 946 return 0; 947} 948 949#ifdef CONFIG_OF 950/* 951 * Parse the device tree node and retreive the platform data. 952 */ 953static void 954s3c24xx_i2c_parse_dt(struct device_node *np, struct s3c24xx_i2c *i2c) 955{ 956 struct s3c2410_platform_i2c *pdata = i2c->pdata; 957 int id; 958 959 if (!np) 960 return; 961 962 pdata->bus_num = -1; /* i2c bus number is dynamically assigned */ 963 of_property_read_u32(np, "samsung,i2c-sda-delay", &pdata->sda_delay); 964 of_property_read_u32(np, "samsung,i2c-slave-addr", &pdata->slave_addr); 965 of_property_read_u32(np, "samsung,i2c-max-bus-freq", 966 (u32 *)&pdata->frequency); 967 /* 968 * Exynos5's legacy i2c controller and new high speed i2c 969 * controller have muxed interrupt sources. By default the 970 * interrupts for 4-channel HS-I2C controller are enabled. 971 * If nodes for first four channels of legacy i2c controller 972 * are available then re-configure the interrupts via the 973 * system register. 974 */ 975 id = of_alias_get_id(np, "i2c"); 976 i2c->sysreg = syscon_regmap_lookup_by_phandle(np, 977 "samsung,sysreg-phandle"); 978 if (IS_ERR(i2c->sysreg)) 979 return; 980 981 regmap_update_bits(i2c->sysreg, EXYNOS5_SYS_I2C_CFG, BIT(id), 0); 982} 983#else 984static void 985s3c24xx_i2c_parse_dt(struct device_node *np, struct s3c24xx_i2c *i2c) { } 986#endif 987 988static int s3c24xx_i2c_probe(struct platform_device *pdev) 989{ 990 struct s3c24xx_i2c *i2c; 991 struct s3c2410_platform_i2c *pdata = NULL; 992 struct resource *res; 993 int ret; 994 995 if (!pdev->dev.of_node) { 996 pdata = dev_get_platdata(&pdev->dev); 997 if (!pdata) { 998 dev_err(&pdev->dev, "no platform data\n"); 999 return -EINVAL; 1000 } 1001 } 1002 1003 i2c = devm_kzalloc(&pdev->dev, sizeof(struct s3c24xx_i2c), GFP_KERNEL); 1004 if (!i2c) 1005 return -ENOMEM; 1006 1007 i2c->pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); 1008 if (!i2c->pdata) 1009 return -ENOMEM; 1010 1011 i2c->quirks = s3c24xx_get_device_quirks(pdev); 1012 i2c->sysreg = ERR_PTR(-ENOENT); 1013 if (pdata) 1014 memcpy(i2c->pdata, pdata, sizeof(*pdata)); 1015 else 1016 s3c24xx_i2c_parse_dt(pdev->dev.of_node, i2c); 1017 1018 strscpy(i2c->adap.name, "s3c2410-i2c", sizeof(i2c->adap.name)); 1019 i2c->adap.owner = THIS_MODULE; 1020 i2c->adap.algo = &s3c24xx_i2c_algorithm; 1021 i2c->adap.retries = 2; 1022 i2c->adap.class = I2C_CLASS_DEPRECATED; 1023 i2c->tx_setup = 50; 1024 1025 init_waitqueue_head(&i2c->wait); 1026 1027 /* find the clock and enable it */ 1028 i2c->dev = &pdev->dev; 1029 i2c->clk = devm_clk_get(&pdev->dev, "i2c"); 1030 if (IS_ERR(i2c->clk)) { 1031 dev_err(&pdev->dev, "cannot get clock\n"); 1032 return -ENOENT; 1033 } 1034 1035 dev_dbg(&pdev->dev, "clock source %p\n", i2c->clk); 1036 1037 /* map the registers */ 1038 i2c->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1039 if (IS_ERR(i2c->regs)) 1040 return PTR_ERR(i2c->regs); 1041 1042 dev_dbg(&pdev->dev, "registers %p (%p)\n", 1043 i2c->regs, res); 1044 1045 /* setup info block for the i2c core */ 1046 i2c->adap.algo_data = i2c; 1047 i2c->adap.dev.parent = &pdev->dev; 1048 i2c->pctrl = devm_pinctrl_get_select_default(i2c->dev); 1049 1050 /* inititalise the i2c gpio lines */ 1051 if (i2c->pdata->cfg_gpio) 1052 i2c->pdata->cfg_gpio(to_platform_device(i2c->dev)); 1053 else if (IS_ERR(i2c->pctrl) && s3c24xx_i2c_parse_dt_gpio(i2c)) 1054 return -EINVAL; 1055 1056 /* initialise the i2c controller */ 1057 ret = clk_prepare_enable(i2c->clk); 1058 if (ret) { 1059 dev_err(&pdev->dev, "I2C clock enable failed\n"); 1060 return ret; 1061 } 1062 1063 ret = s3c24xx_i2c_init(i2c); 1064 clk_disable(i2c->clk); 1065 if (ret != 0) { 1066 dev_err(&pdev->dev, "I2C controller init failed\n"); 1067 clk_unprepare(i2c->clk); 1068 return ret; 1069 } 1070 1071 /* 1072 * find the IRQ for this unit (note, this relies on the init call to 1073 * ensure no current IRQs pending 1074 */ 1075 if (!(i2c->quirks & QUIRK_POLL)) { 1076 i2c->irq = ret = platform_get_irq(pdev, 0); 1077 if (ret < 0) { 1078 clk_unprepare(i2c->clk); 1079 return ret; 1080 } 1081 1082 ret = devm_request_irq(&pdev->dev, i2c->irq, s3c24xx_i2c_irq, 1083 0, dev_name(&pdev->dev), i2c); 1084 if (ret != 0) { 1085 dev_err(&pdev->dev, "cannot claim IRQ %d\n", i2c->irq); 1086 clk_unprepare(i2c->clk); 1087 return ret; 1088 } 1089 } 1090 1091 /* 1092 * Note, previous versions of the driver used i2c_add_adapter() 1093 * to add the bus at any number. We now pass the bus number via 1094 * the platform data, so if unset it will now default to always 1095 * being bus 0. 1096 */ 1097 i2c->adap.nr = i2c->pdata->bus_num; 1098 i2c->adap.dev.of_node = pdev->dev.of_node; 1099 1100 platform_set_drvdata(pdev, i2c); 1101 1102 pm_runtime_enable(&pdev->dev); 1103 1104 ret = i2c_add_numbered_adapter(&i2c->adap); 1105 if (ret < 0) { 1106 pm_runtime_disable(&pdev->dev); 1107 clk_unprepare(i2c->clk); 1108 return ret; 1109 } 1110 1111 dev_info(&pdev->dev, "%s: S3C I2C adapter\n", dev_name(&i2c->adap.dev)); 1112 return 0; 1113} 1114 1115static void s3c24xx_i2c_remove(struct platform_device *pdev) 1116{ 1117 struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev); 1118 1119 clk_unprepare(i2c->clk); 1120 1121 pm_runtime_disable(&pdev->dev); 1122 1123 i2c_del_adapter(&i2c->adap); 1124} 1125 1126static int s3c24xx_i2c_suspend_noirq(struct device *dev) 1127{ 1128 struct s3c24xx_i2c *i2c = dev_get_drvdata(dev); 1129 1130 i2c_mark_adapter_suspended(&i2c->adap); 1131 1132 if (!IS_ERR(i2c->sysreg)) 1133 regmap_read(i2c->sysreg, EXYNOS5_SYS_I2C_CFG, &i2c->sys_i2c_cfg); 1134 1135 return 0; 1136} 1137 1138static int s3c24xx_i2c_resume_noirq(struct device *dev) 1139{ 1140 struct s3c24xx_i2c *i2c = dev_get_drvdata(dev); 1141 int ret; 1142 1143 if (!IS_ERR(i2c->sysreg)) 1144 regmap_write(i2c->sysreg, EXYNOS5_SYS_I2C_CFG, i2c->sys_i2c_cfg); 1145 1146 ret = clk_enable(i2c->clk); 1147 if (ret) 1148 return ret; 1149 s3c24xx_i2c_init(i2c); 1150 clk_disable(i2c->clk); 1151 i2c_mark_adapter_resumed(&i2c->adap); 1152 1153 return 0; 1154} 1155 1156static const struct dev_pm_ops s3c24xx_i2c_dev_pm_ops = { 1157 NOIRQ_SYSTEM_SLEEP_PM_OPS(s3c24xx_i2c_suspend_noirq, 1158 s3c24xx_i2c_resume_noirq) 1159}; 1160 1161static struct platform_driver s3c24xx_i2c_driver = { 1162 .probe = s3c24xx_i2c_probe, 1163 .remove_new = s3c24xx_i2c_remove, 1164 .id_table = s3c24xx_driver_ids, 1165 .driver = { 1166 .name = "s3c-i2c", 1167 .pm = pm_sleep_ptr(&s3c24xx_i2c_dev_pm_ops), 1168 .of_match_table = of_match_ptr(s3c24xx_i2c_match), 1169 }, 1170}; 1171 1172static int __init i2c_adap_s3c_init(void) 1173{ 1174 return platform_driver_register(&s3c24xx_i2c_driver); 1175} 1176subsys_initcall(i2c_adap_s3c_init); 1177 1178static void __exit i2c_adap_s3c_exit(void) 1179{ 1180 platform_driver_unregister(&s3c24xx_i2c_driver); 1181} 1182module_exit(i2c_adap_s3c_exit); 1183 1184MODULE_DESCRIPTION("S3C24XX I2C Bus driver"); 1185MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>"); 1186MODULE_LICENSE("GPL"); 1187