1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl> and 4 Philip Edelbrock <phil@netroedge.com> 5 6*/ 7 8/* 9 Supports: 10 Intel PIIX4, 440MX 11 Serverworks OSB4, CSB5, CSB6, HT-1000, HT-1100 12 ATI IXP200, IXP300, IXP400, SB600, SB700/SP5100, SB800 13 AMD Hudson-2, ML, CZ 14 Hygon CZ 15 SMSC Victory66 16 17 Note: we assume there can only be one device, with one or more 18 SMBus interfaces. 19 The device can register multiple i2c_adapters (up to PIIX4_MAX_ADAPTERS). 20 For devices supporting multiple ports the i2c_adapter should provide 21 an i2c_algorithm to access them. 22*/ 23 24#include <linux/module.h> 25#include <linux/moduleparam.h> 26#include <linux/pci.h> 27#include <linux/kernel.h> 28#include <linux/delay.h> 29#include <linux/stddef.h> 30#include <linux/ioport.h> 31#include <linux/i2c.h> 32#include <linux/slab.h> 33#include <linux/dmi.h> 34#include <linux/acpi.h> 35#include <linux/io.h> 36 37 38/* PIIX4 SMBus address offsets */ 39#define SMBHSTSTS (0 + piix4_smba) 40#define SMBHSLVSTS (1 + piix4_smba) 41#define SMBHSTCNT (2 + piix4_smba) 42#define SMBHSTCMD (3 + piix4_smba) 43#define SMBHSTADD (4 + piix4_smba) 44#define SMBHSTDAT0 (5 + piix4_smba) 45#define SMBHSTDAT1 (6 + piix4_smba) 46#define SMBBLKDAT (7 + piix4_smba) 47#define SMBSLVCNT (8 + piix4_smba) 48#define SMBSHDWCMD (9 + piix4_smba) 49#define SMBSLVEVT (0xA + piix4_smba) 50#define SMBSLVDAT (0xC + piix4_smba) 51 52/* count for request_region */ 53#define SMBIOSIZE 9 54 55/* PCI Address Constants */ 56#define SMBBA 0x090 57#define SMBHSTCFG 0x0D2 58#define SMBSLVC 0x0D3 59#define SMBSHDW1 0x0D4 60#define SMBSHDW2 0x0D5 61#define SMBREV 0x0D6 62 63/* Other settings */ 64#define MAX_TIMEOUT 500 65#define ENABLE_INT9 0 66 67/* PIIX4 constants */ 68#define PIIX4_QUICK 0x00 69#define PIIX4_BYTE 0x04 70#define PIIX4_BYTE_DATA 0x08 71#define PIIX4_WORD_DATA 0x0C 72#define PIIX4_BLOCK_DATA 0x14 73 74/* Multi-port constants */ 75#define PIIX4_MAX_ADAPTERS 4 76#define HUDSON2_MAIN_PORTS 2 /* HUDSON2, KERNCZ reserves ports 3, 4 */ 77 78/* SB800 constants */ 79#define SB800_PIIX4_SMB_IDX 0xcd6 80#define SB800_PIIX4_SMB_MAP_SIZE 2 81 82#define KERNCZ_IMC_IDX 0x3e 83#define KERNCZ_IMC_DATA 0x3f 84 85/* 86 * SB800 port is selected by bits 2:1 of the smb_en register (0x2c) 87 * or the smb_sel register (0x2e), depending on bit 0 of register 0x2f. 88 * Hudson-2/Bolton port is always selected by bits 2:1 of register 0x2f. 89 */ 90#define SB800_PIIX4_PORT_IDX 0x2c 91#define SB800_PIIX4_PORT_IDX_ALT 0x2e 92#define SB800_PIIX4_PORT_IDX_SEL 0x2f 93#define SB800_PIIX4_PORT_IDX_MASK 0x06 94#define SB800_PIIX4_PORT_IDX_SHIFT 1 95 96/* On kerncz and Hudson2, SmBus0Sel is at bit 20:19 of PMx00 DecodeEn */ 97#define SB800_PIIX4_PORT_IDX_KERNCZ 0x02 98#define SB800_PIIX4_PORT_IDX_MASK_KERNCZ 0x18 99#define SB800_PIIX4_PORT_IDX_SHIFT_KERNCZ 3 100 101#define SB800_PIIX4_FCH_PM_ADDR 0xFED80300 102#define SB800_PIIX4_FCH_PM_SIZE 8 103 104/* insmod parameters */ 105 106/* If force is set to anything different from 0, we forcibly enable the 107 PIIX4. DANGEROUS! */ 108static int force; 109module_param (force, int, 0); 110MODULE_PARM_DESC(force, "Forcibly enable the PIIX4. DANGEROUS!"); 111 112/* If force_addr is set to anything different from 0, we forcibly enable 113 the PIIX4 at the given address. VERY DANGEROUS! */ 114static int force_addr; 115module_param_hw(force_addr, int, ioport, 0); 116MODULE_PARM_DESC(force_addr, 117 "Forcibly enable the PIIX4 at the given address. " 118 "EXTREMELY DANGEROUS!"); 119 120static int srvrworks_csb5_delay; 121static struct pci_driver piix4_driver; 122 123static const struct dmi_system_id piix4_dmi_blacklist[] = { 124 { 125 .ident = "Sapphire AM2RD790", 126 .matches = { 127 DMI_MATCH(DMI_BOARD_VENDOR, "SAPPHIRE Inc."), 128 DMI_MATCH(DMI_BOARD_NAME, "PC-AM2RD790"), 129 }, 130 }, 131 { 132 .ident = "DFI Lanparty UT 790FX", 133 .matches = { 134 DMI_MATCH(DMI_BOARD_VENDOR, "DFI Inc."), 135 DMI_MATCH(DMI_BOARD_NAME, "LP UT 790FX"), 136 }, 137 }, 138 { } 139}; 140 141/* The IBM entry is in a separate table because we only check it 142 on Intel-based systems */ 143static const struct dmi_system_id piix4_dmi_ibm[] = { 144 { 145 .ident = "IBM", 146 .matches = { DMI_MATCH(DMI_SYS_VENDOR, "IBM"), }, 147 }, 148 { }, 149}; 150 151/* 152 * SB800 globals 153 */ 154static u8 piix4_port_sel_sb800; 155static u8 piix4_port_mask_sb800; 156static u8 piix4_port_shift_sb800; 157static const char *piix4_main_port_names_sb800[PIIX4_MAX_ADAPTERS] = { 158 " port 0", " port 2", " port 3", " port 4" 159}; 160static const char *piix4_aux_port_name_sb800 = " port 1"; 161 162struct sb800_mmio_cfg { 163 void __iomem *addr; 164 bool use_mmio; 165}; 166 167struct i2c_piix4_adapdata { 168 unsigned short smba; 169 170 /* SB800 */ 171 bool sb800_main; 172 bool notify_imc; 173 u8 port; /* Port number, shifted */ 174 struct sb800_mmio_cfg mmio_cfg; 175}; 176 177static int piix4_sb800_region_request(struct device *dev, 178 struct sb800_mmio_cfg *mmio_cfg) 179{ 180 if (mmio_cfg->use_mmio) { 181 void __iomem *addr; 182 183 if (!request_mem_region_muxed(SB800_PIIX4_FCH_PM_ADDR, 184 SB800_PIIX4_FCH_PM_SIZE, 185 "sb800_piix4_smb")) { 186 dev_err(dev, 187 "SMBus base address memory region 0x%x already in use.\n", 188 SB800_PIIX4_FCH_PM_ADDR); 189 return -EBUSY; 190 } 191 192 addr = ioremap(SB800_PIIX4_FCH_PM_ADDR, 193 SB800_PIIX4_FCH_PM_SIZE); 194 if (!addr) { 195 release_mem_region(SB800_PIIX4_FCH_PM_ADDR, 196 SB800_PIIX4_FCH_PM_SIZE); 197 dev_err(dev, "SMBus base address mapping failed.\n"); 198 return -ENOMEM; 199 } 200 201 mmio_cfg->addr = addr; 202 203 return 0; 204 } 205 206 if (!request_muxed_region(SB800_PIIX4_SMB_IDX, SB800_PIIX4_SMB_MAP_SIZE, 207 "sb800_piix4_smb")) { 208 dev_err(dev, 209 "SMBus base address index region 0x%x already in use.\n", 210 SB800_PIIX4_SMB_IDX); 211 return -EBUSY; 212 } 213 214 return 0; 215} 216 217static void piix4_sb800_region_release(struct device *dev, 218 struct sb800_mmio_cfg *mmio_cfg) 219{ 220 if (mmio_cfg->use_mmio) { 221 iounmap(mmio_cfg->addr); 222 release_mem_region(SB800_PIIX4_FCH_PM_ADDR, 223 SB800_PIIX4_FCH_PM_SIZE); 224 return; 225 } 226 227 release_region(SB800_PIIX4_SMB_IDX, SB800_PIIX4_SMB_MAP_SIZE); 228} 229 230static bool piix4_sb800_use_mmio(struct pci_dev *PIIX4_dev) 231{ 232 /* 233 * cd6h/cd7h port I/O accesses can be disabled on AMD processors 234 * w/ SMBus PCI revision ID 0x51 or greater. MMIO is supported on 235 * the same processors and is the recommended access method. 236 */ 237 return (PIIX4_dev->vendor == PCI_VENDOR_ID_AMD && 238 PIIX4_dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS && 239 PIIX4_dev->revision >= 0x51); 240} 241 242static int piix4_setup(struct pci_dev *PIIX4_dev, 243 const struct pci_device_id *id) 244{ 245 unsigned char temp; 246 unsigned short piix4_smba; 247 248 if ((PIIX4_dev->vendor == PCI_VENDOR_ID_SERVERWORKS) && 249 (PIIX4_dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5)) 250 srvrworks_csb5_delay = 1; 251 252 /* On some motherboards, it was reported that accessing the SMBus 253 caused severe hardware problems */ 254 if (dmi_check_system(piix4_dmi_blacklist)) { 255 dev_err(&PIIX4_dev->dev, 256 "Accessing the SMBus on this system is unsafe!\n"); 257 return -EPERM; 258 } 259 260 /* Don't access SMBus on IBM systems which get corrupted eeproms */ 261 if (dmi_check_system(piix4_dmi_ibm) && 262 PIIX4_dev->vendor == PCI_VENDOR_ID_INTEL) { 263 dev_err(&PIIX4_dev->dev, "IBM system detected; this module " 264 "may corrupt your serial eeprom! Refusing to load " 265 "module!\n"); 266 return -EPERM; 267 } 268 269 /* Determine the address of the SMBus areas */ 270 if (force_addr) { 271 piix4_smba = force_addr & 0xfff0; 272 force = 0; 273 } else { 274 pci_read_config_word(PIIX4_dev, SMBBA, &piix4_smba); 275 piix4_smba &= 0xfff0; 276 if(piix4_smba == 0) { 277 dev_err(&PIIX4_dev->dev, "SMBus base address " 278 "uninitialized - upgrade BIOS or use " 279 "force_addr=0xaddr\n"); 280 return -ENODEV; 281 } 282 } 283 284 if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) 285 return -ENODEV; 286 287 if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) { 288 dev_err(&PIIX4_dev->dev, "SMBus region 0x%x already in use!\n", 289 piix4_smba); 290 return -EBUSY; 291 } 292 293 pci_read_config_byte(PIIX4_dev, SMBHSTCFG, &temp); 294 295 /* If force_addr is set, we program the new address here. Just to make 296 sure, we disable the PIIX4 first. */ 297 if (force_addr) { 298 pci_write_config_byte(PIIX4_dev, SMBHSTCFG, temp & 0xfe); 299 pci_write_config_word(PIIX4_dev, SMBBA, piix4_smba); 300 pci_write_config_byte(PIIX4_dev, SMBHSTCFG, temp | 0x01); 301 dev_info(&PIIX4_dev->dev, "WARNING: SMBus interface set to " 302 "new address %04x!\n", piix4_smba); 303 } else if ((temp & 1) == 0) { 304 if (force) { 305 /* This should never need to be done, but has been 306 * noted that many Dell machines have the SMBus 307 * interface on the PIIX4 disabled!? NOTE: This assumes 308 * I/O space and other allocations WERE done by the 309 * Bios! Don't complain if your hardware does weird 310 * things after enabling this. :') Check for Bios 311 * updates before resorting to this. 312 */ 313 pci_write_config_byte(PIIX4_dev, SMBHSTCFG, 314 temp | 1); 315 dev_notice(&PIIX4_dev->dev, 316 "WARNING: SMBus interface has been FORCEFULLY ENABLED!\n"); 317 } else { 318 dev_err(&PIIX4_dev->dev, 319 "SMBus Host Controller not enabled!\n"); 320 release_region(piix4_smba, SMBIOSIZE); 321 return -ENODEV; 322 } 323 } 324 325 if (((temp & 0x0E) == 8) || ((temp & 0x0E) == 2)) 326 dev_dbg(&PIIX4_dev->dev, "Using IRQ for SMBus\n"); 327 else if ((temp & 0x0E) == 0) 328 dev_dbg(&PIIX4_dev->dev, "Using SMI# for SMBus\n"); 329 else 330 dev_err(&PIIX4_dev->dev, "Illegal Interrupt configuration " 331 "(or code out of date)!\n"); 332 333 pci_read_config_byte(PIIX4_dev, SMBREV, &temp); 334 dev_info(&PIIX4_dev->dev, 335 "SMBus Host Controller at 0x%x, revision %d\n", 336 piix4_smba, temp); 337 338 return piix4_smba; 339} 340 341static int piix4_setup_sb800_smba(struct pci_dev *PIIX4_dev, 342 u8 smb_en, 343 u8 aux, 344 u8 *smb_en_status, 345 unsigned short *piix4_smba) 346{ 347 struct sb800_mmio_cfg mmio_cfg; 348 u8 smba_en_lo; 349 u8 smba_en_hi; 350 int retval; 351 352 mmio_cfg.use_mmio = piix4_sb800_use_mmio(PIIX4_dev); 353 retval = piix4_sb800_region_request(&PIIX4_dev->dev, &mmio_cfg); 354 if (retval) 355 return retval; 356 357 if (mmio_cfg.use_mmio) { 358 smba_en_lo = ioread8(mmio_cfg.addr); 359 smba_en_hi = ioread8(mmio_cfg.addr + 1); 360 } else { 361 outb_p(smb_en, SB800_PIIX4_SMB_IDX); 362 smba_en_lo = inb_p(SB800_PIIX4_SMB_IDX + 1); 363 outb_p(smb_en + 1, SB800_PIIX4_SMB_IDX); 364 smba_en_hi = inb_p(SB800_PIIX4_SMB_IDX + 1); 365 } 366 367 piix4_sb800_region_release(&PIIX4_dev->dev, &mmio_cfg); 368 369 if (!smb_en) { 370 *smb_en_status = smba_en_lo & 0x10; 371 *piix4_smba = smba_en_hi << 8; 372 if (aux) 373 *piix4_smba |= 0x20; 374 } else { 375 *smb_en_status = smba_en_lo & 0x01; 376 *piix4_smba = ((smba_en_hi << 8) | smba_en_lo) & 0xffe0; 377 } 378 379 if (!*smb_en_status) { 380 dev_err(&PIIX4_dev->dev, 381 "SMBus Host Controller not enabled!\n"); 382 return -ENODEV; 383 } 384 385 return 0; 386} 387 388static int piix4_setup_sb800(struct pci_dev *PIIX4_dev, 389 const struct pci_device_id *id, u8 aux) 390{ 391 unsigned short piix4_smba; 392 u8 smb_en, smb_en_status, port_sel; 393 u8 i2ccfg, i2ccfg_offset = 0x10; 394 struct sb800_mmio_cfg mmio_cfg; 395 int retval; 396 397 /* SB800 and later SMBus does not support forcing address */ 398 if (force || force_addr) { 399 dev_err(&PIIX4_dev->dev, "SMBus does not support " 400 "forcing address!\n"); 401 return -EINVAL; 402 } 403 404 /* Determine the address of the SMBus areas */ 405 if ((PIIX4_dev->vendor == PCI_VENDOR_ID_AMD && 406 PIIX4_dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS && 407 PIIX4_dev->revision >= 0x41) || 408 (PIIX4_dev->vendor == PCI_VENDOR_ID_AMD && 409 PIIX4_dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS && 410 PIIX4_dev->revision >= 0x49) || 411 (PIIX4_dev->vendor == PCI_VENDOR_ID_HYGON && 412 PIIX4_dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS)) 413 smb_en = 0x00; 414 else 415 smb_en = (aux) ? 0x28 : 0x2c; 416 417 retval = piix4_setup_sb800_smba(PIIX4_dev, smb_en, aux, &smb_en_status, 418 &piix4_smba); 419 420 if (retval) 421 return retval; 422 423 if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) 424 return -ENODEV; 425 426 if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) { 427 dev_err(&PIIX4_dev->dev, "SMBus region 0x%x already in use!\n", 428 piix4_smba); 429 return -EBUSY; 430 } 431 432 /* Aux SMBus does not support IRQ information */ 433 if (aux) { 434 dev_info(&PIIX4_dev->dev, 435 "Auxiliary SMBus Host Controller at 0x%x\n", 436 piix4_smba); 437 return piix4_smba; 438 } 439 440 /* Request the SMBus I2C bus config region */ 441 if (!request_region(piix4_smba + i2ccfg_offset, 1, "i2ccfg")) { 442 dev_err(&PIIX4_dev->dev, "SMBus I2C bus config region " 443 "0x%x already in use!\n", piix4_smba + i2ccfg_offset); 444 release_region(piix4_smba, SMBIOSIZE); 445 return -EBUSY; 446 } 447 i2ccfg = inb_p(piix4_smba + i2ccfg_offset); 448 release_region(piix4_smba + i2ccfg_offset, 1); 449 450 if (i2ccfg & 1) 451 dev_dbg(&PIIX4_dev->dev, "Using IRQ for SMBus\n"); 452 else 453 dev_dbg(&PIIX4_dev->dev, "Using SMI# for SMBus\n"); 454 455 dev_info(&PIIX4_dev->dev, 456 "SMBus Host Controller at 0x%x, revision %d\n", 457 piix4_smba, i2ccfg >> 4); 458 459 /* Find which register is used for port selection */ 460 if (PIIX4_dev->vendor == PCI_VENDOR_ID_AMD || 461 PIIX4_dev->vendor == PCI_VENDOR_ID_HYGON) { 462 if (PIIX4_dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS || 463 (PIIX4_dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS && 464 PIIX4_dev->revision >= 0x1F)) { 465 piix4_port_sel_sb800 = SB800_PIIX4_PORT_IDX_KERNCZ; 466 piix4_port_mask_sb800 = SB800_PIIX4_PORT_IDX_MASK_KERNCZ; 467 piix4_port_shift_sb800 = SB800_PIIX4_PORT_IDX_SHIFT_KERNCZ; 468 } else { 469 piix4_port_sel_sb800 = SB800_PIIX4_PORT_IDX_ALT; 470 piix4_port_mask_sb800 = SB800_PIIX4_PORT_IDX_MASK; 471 piix4_port_shift_sb800 = SB800_PIIX4_PORT_IDX_SHIFT; 472 } 473 } else { 474 mmio_cfg.use_mmio = piix4_sb800_use_mmio(PIIX4_dev); 475 retval = piix4_sb800_region_request(&PIIX4_dev->dev, &mmio_cfg); 476 if (retval) { 477 release_region(piix4_smba, SMBIOSIZE); 478 return retval; 479 } 480 481 outb_p(SB800_PIIX4_PORT_IDX_SEL, SB800_PIIX4_SMB_IDX); 482 port_sel = inb_p(SB800_PIIX4_SMB_IDX + 1); 483 piix4_port_sel_sb800 = (port_sel & 0x01) ? 484 SB800_PIIX4_PORT_IDX_ALT : 485 SB800_PIIX4_PORT_IDX; 486 piix4_port_mask_sb800 = SB800_PIIX4_PORT_IDX_MASK; 487 piix4_port_shift_sb800 = SB800_PIIX4_PORT_IDX_SHIFT; 488 piix4_sb800_region_release(&PIIX4_dev->dev, &mmio_cfg); 489 } 490 491 dev_info(&PIIX4_dev->dev, 492 "Using register 0x%02x for SMBus port selection\n", 493 (unsigned int)piix4_port_sel_sb800); 494 495 return piix4_smba; 496} 497 498static int piix4_setup_aux(struct pci_dev *PIIX4_dev, 499 const struct pci_device_id *id, 500 unsigned short base_reg_addr) 501{ 502 /* Set up auxiliary SMBus controllers found on some 503 * AMD chipsets e.g. SP5100 (SB700 derivative) */ 504 505 unsigned short piix4_smba; 506 507 /* Read address of auxiliary SMBus controller */ 508 pci_read_config_word(PIIX4_dev, base_reg_addr, &piix4_smba); 509 if ((piix4_smba & 1) == 0) { 510 dev_dbg(&PIIX4_dev->dev, 511 "Auxiliary SMBus controller not enabled\n"); 512 return -ENODEV; 513 } 514 515 piix4_smba &= 0xfff0; 516 if (piix4_smba == 0) { 517 dev_dbg(&PIIX4_dev->dev, 518 "Auxiliary SMBus base address uninitialized\n"); 519 return -ENODEV; 520 } 521 522 if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) 523 return -ENODEV; 524 525 if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) { 526 dev_err(&PIIX4_dev->dev, "Auxiliary SMBus region 0x%x " 527 "already in use!\n", piix4_smba); 528 return -EBUSY; 529 } 530 531 dev_info(&PIIX4_dev->dev, 532 "Auxiliary SMBus Host Controller at 0x%x\n", 533 piix4_smba); 534 535 return piix4_smba; 536} 537 538static int piix4_transaction(struct i2c_adapter *piix4_adapter) 539{ 540 struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(piix4_adapter); 541 unsigned short piix4_smba = adapdata->smba; 542 int temp; 543 int result = 0; 544 int timeout = 0; 545 546 dev_dbg(&piix4_adapter->dev, "Transaction (pre): CNT=%02x, CMD=%02x, " 547 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT), 548 inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0), 549 inb_p(SMBHSTDAT1)); 550 551 /* Make sure the SMBus host is ready to start transmitting */ 552 if ((temp = inb_p(SMBHSTSTS)) != 0x00) { 553 dev_dbg(&piix4_adapter->dev, "SMBus busy (%02x). " 554 "Resetting...\n", temp); 555 outb_p(temp, SMBHSTSTS); 556 if ((temp = inb_p(SMBHSTSTS)) != 0x00) { 557 dev_err(&piix4_adapter->dev, "Failed! (%02x)\n", temp); 558 return -EBUSY; 559 } else { 560 dev_dbg(&piix4_adapter->dev, "Successful!\n"); 561 } 562 } 563 564 /* start the transaction by setting bit 6 */ 565 outb_p(inb(SMBHSTCNT) | 0x040, SMBHSTCNT); 566 567 /* We will always wait for a fraction of a second! (See PIIX4 docs errata) */ 568 if (srvrworks_csb5_delay) /* Extra delay for SERVERWORKS_CSB5 */ 569 usleep_range(2000, 2100); 570 else 571 usleep_range(250, 500); 572 573 while ((++timeout < MAX_TIMEOUT) && 574 ((temp = inb_p(SMBHSTSTS)) & 0x01)) 575 usleep_range(250, 500); 576 577 /* If the SMBus is still busy, we give up */ 578 if (timeout == MAX_TIMEOUT) { 579 dev_err(&piix4_adapter->dev, "SMBus Timeout!\n"); 580 result = -ETIMEDOUT; 581 } 582 583 if (temp & 0x10) { 584 result = -EIO; 585 dev_err(&piix4_adapter->dev, "Error: Failed bus transaction\n"); 586 } 587 588 if (temp & 0x08) { 589 result = -EIO; 590 dev_dbg(&piix4_adapter->dev, "Bus collision! SMBus may be " 591 "locked until next hard reset. (sorry!)\n"); 592 /* Clock stops and slave is stuck in mid-transmission */ 593 } 594 595 if (temp & 0x04) { 596 result = -ENXIO; 597 dev_dbg(&piix4_adapter->dev, "Error: no response!\n"); 598 } 599 600 if (inb_p(SMBHSTSTS) != 0x00) 601 outb_p(inb(SMBHSTSTS), SMBHSTSTS); 602 603 if ((temp = inb_p(SMBHSTSTS)) != 0x00) { 604 dev_err(&piix4_adapter->dev, "Failed reset at end of " 605 "transaction (%02x)\n", temp); 606 } 607 dev_dbg(&piix4_adapter->dev, "Transaction (post): CNT=%02x, CMD=%02x, " 608 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT), 609 inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0), 610 inb_p(SMBHSTDAT1)); 611 return result; 612} 613 614/* Return negative errno on error. */ 615static s32 piix4_access(struct i2c_adapter * adap, u16 addr, 616 unsigned short flags, char read_write, 617 u8 command, int size, union i2c_smbus_data * data) 618{ 619 struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(adap); 620 unsigned short piix4_smba = adapdata->smba; 621 int i, len; 622 int status; 623 624 switch (size) { 625 case I2C_SMBUS_QUICK: 626 outb_p((addr << 1) | read_write, 627 SMBHSTADD); 628 size = PIIX4_QUICK; 629 break; 630 case I2C_SMBUS_BYTE: 631 outb_p((addr << 1) | read_write, 632 SMBHSTADD); 633 if (read_write == I2C_SMBUS_WRITE) 634 outb_p(command, SMBHSTCMD); 635 size = PIIX4_BYTE; 636 break; 637 case I2C_SMBUS_BYTE_DATA: 638 outb_p((addr << 1) | read_write, 639 SMBHSTADD); 640 outb_p(command, SMBHSTCMD); 641 if (read_write == I2C_SMBUS_WRITE) 642 outb_p(data->byte, SMBHSTDAT0); 643 size = PIIX4_BYTE_DATA; 644 break; 645 case I2C_SMBUS_WORD_DATA: 646 outb_p((addr << 1) | read_write, 647 SMBHSTADD); 648 outb_p(command, SMBHSTCMD); 649 if (read_write == I2C_SMBUS_WRITE) { 650 outb_p(data->word & 0xff, SMBHSTDAT0); 651 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1); 652 } 653 size = PIIX4_WORD_DATA; 654 break; 655 case I2C_SMBUS_BLOCK_DATA: 656 outb_p((addr << 1) | read_write, 657 SMBHSTADD); 658 outb_p(command, SMBHSTCMD); 659 if (read_write == I2C_SMBUS_WRITE) { 660 len = data->block[0]; 661 if (len == 0 || len > I2C_SMBUS_BLOCK_MAX) 662 return -EINVAL; 663 outb_p(len, SMBHSTDAT0); 664 inb_p(SMBHSTCNT); /* Reset SMBBLKDAT */ 665 for (i = 1; i <= len; i++) 666 outb_p(data->block[i], SMBBLKDAT); 667 } 668 size = PIIX4_BLOCK_DATA; 669 break; 670 default: 671 dev_warn(&adap->dev, "Unsupported transaction %d\n", size); 672 return -EOPNOTSUPP; 673 } 674 675 outb_p((size & 0x1C) + (ENABLE_INT9 & 1), SMBHSTCNT); 676 677 status = piix4_transaction(adap); 678 if (status) 679 return status; 680 681 if ((read_write == I2C_SMBUS_WRITE) || (size == PIIX4_QUICK)) 682 return 0; 683 684 685 switch (size) { 686 case PIIX4_BYTE: 687 case PIIX4_BYTE_DATA: 688 data->byte = inb_p(SMBHSTDAT0); 689 break; 690 case PIIX4_WORD_DATA: 691 data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8); 692 break; 693 case PIIX4_BLOCK_DATA: 694 data->block[0] = inb_p(SMBHSTDAT0); 695 if (data->block[0] == 0 || data->block[0] > I2C_SMBUS_BLOCK_MAX) 696 return -EPROTO; 697 inb_p(SMBHSTCNT); /* Reset SMBBLKDAT */ 698 for (i = 1; i <= data->block[0]; i++) 699 data->block[i] = inb_p(SMBBLKDAT); 700 break; 701 } 702 return 0; 703} 704 705static uint8_t piix4_imc_read(uint8_t idx) 706{ 707 outb_p(idx, KERNCZ_IMC_IDX); 708 return inb_p(KERNCZ_IMC_DATA); 709} 710 711static void piix4_imc_write(uint8_t idx, uint8_t value) 712{ 713 outb_p(idx, KERNCZ_IMC_IDX); 714 outb_p(value, KERNCZ_IMC_DATA); 715} 716 717static int piix4_imc_sleep(void) 718{ 719 int timeout = MAX_TIMEOUT; 720 721 if (!request_muxed_region(KERNCZ_IMC_IDX, 2, "smbus_kerncz_imc")) 722 return -EBUSY; 723 724 /* clear response register */ 725 piix4_imc_write(0x82, 0x00); 726 /* request ownership flag */ 727 piix4_imc_write(0x83, 0xB4); 728 /* kick off IMC Mailbox command 96 */ 729 piix4_imc_write(0x80, 0x96); 730 731 while (timeout--) { 732 if (piix4_imc_read(0x82) == 0xfa) { 733 release_region(KERNCZ_IMC_IDX, 2); 734 return 0; 735 } 736 usleep_range(1000, 2000); 737 } 738 739 release_region(KERNCZ_IMC_IDX, 2); 740 return -ETIMEDOUT; 741} 742 743static void piix4_imc_wakeup(void) 744{ 745 int timeout = MAX_TIMEOUT; 746 747 if (!request_muxed_region(KERNCZ_IMC_IDX, 2, "smbus_kerncz_imc")) 748 return; 749 750 /* clear response register */ 751 piix4_imc_write(0x82, 0x00); 752 /* release ownership flag */ 753 piix4_imc_write(0x83, 0xB5); 754 /* kick off IMC Mailbox command 96 */ 755 piix4_imc_write(0x80, 0x96); 756 757 while (timeout--) { 758 if (piix4_imc_read(0x82) == 0xfa) 759 break; 760 usleep_range(1000, 2000); 761 } 762 763 release_region(KERNCZ_IMC_IDX, 2); 764} 765 766static int piix4_sb800_port_sel(u8 port, struct sb800_mmio_cfg *mmio_cfg) 767{ 768 u8 smba_en_lo, val; 769 770 if (mmio_cfg->use_mmio) { 771 smba_en_lo = ioread8(mmio_cfg->addr + piix4_port_sel_sb800); 772 val = (smba_en_lo & ~piix4_port_mask_sb800) | port; 773 if (smba_en_lo != val) 774 iowrite8(val, mmio_cfg->addr + piix4_port_sel_sb800); 775 776 return (smba_en_lo & piix4_port_mask_sb800); 777 } 778 779 outb_p(piix4_port_sel_sb800, SB800_PIIX4_SMB_IDX); 780 smba_en_lo = inb_p(SB800_PIIX4_SMB_IDX + 1); 781 782 val = (smba_en_lo & ~piix4_port_mask_sb800) | port; 783 if (smba_en_lo != val) 784 outb_p(val, SB800_PIIX4_SMB_IDX + 1); 785 786 return (smba_en_lo & piix4_port_mask_sb800); 787} 788 789/* 790 * Handles access to multiple SMBus ports on the SB800. 791 * The port is selected by bits 2:1 of the smb_en register (0x2c). 792 * Returns negative errno on error. 793 * 794 * Note: The selected port must be returned to the initial selection to avoid 795 * problems on certain systems. 796 */ 797static s32 piix4_access_sb800(struct i2c_adapter *adap, u16 addr, 798 unsigned short flags, char read_write, 799 u8 command, int size, union i2c_smbus_data *data) 800{ 801 struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(adap); 802 unsigned short piix4_smba = adapdata->smba; 803 int retries = MAX_TIMEOUT; 804 int smbslvcnt; 805 u8 prev_port; 806 int retval; 807 808 retval = piix4_sb800_region_request(&adap->dev, &adapdata->mmio_cfg); 809 if (retval) 810 return retval; 811 812 /* Request the SMBUS semaphore, avoid conflicts with the IMC */ 813 smbslvcnt = inb_p(SMBSLVCNT); 814 do { 815 outb_p(smbslvcnt | 0x10, SMBSLVCNT); 816 817 /* Check the semaphore status */ 818 smbslvcnt = inb_p(SMBSLVCNT); 819 if (smbslvcnt & 0x10) 820 break; 821 822 usleep_range(1000, 2000); 823 } while (--retries); 824 /* SMBus is still owned by the IMC, we give up */ 825 if (!retries) { 826 retval = -EBUSY; 827 goto release; 828 } 829 830 /* 831 * Notify the IMC (Integrated Micro Controller) if required. 832 * Among other responsibilities, the IMC is in charge of monitoring 833 * the System fans and temperature sensors, and act accordingly. 834 * All this is done through SMBus and can/will collide 835 * with our transactions if they are long (BLOCK_DATA). 836 * Therefore we need to request the ownership flag during those 837 * transactions. 838 */ 839 if ((size == I2C_SMBUS_BLOCK_DATA) && adapdata->notify_imc) { 840 int ret; 841 842 ret = piix4_imc_sleep(); 843 switch (ret) { 844 case -EBUSY: 845 dev_warn(&adap->dev, 846 "IMC base address index region 0x%x already in use.\n", 847 KERNCZ_IMC_IDX); 848 break; 849 case -ETIMEDOUT: 850 dev_warn(&adap->dev, 851 "Failed to communicate with the IMC.\n"); 852 break; 853 default: 854 break; 855 } 856 857 /* If IMC communication fails do not retry */ 858 if (ret) { 859 dev_warn(&adap->dev, 860 "Continuing without IMC notification.\n"); 861 adapdata->notify_imc = false; 862 } 863 } 864 865 prev_port = piix4_sb800_port_sel(adapdata->port, &adapdata->mmio_cfg); 866 867 retval = piix4_access(adap, addr, flags, read_write, 868 command, size, data); 869 870 piix4_sb800_port_sel(prev_port, &adapdata->mmio_cfg); 871 872 /* Release the semaphore */ 873 outb_p(smbslvcnt | 0x20, SMBSLVCNT); 874 875 if ((size == I2C_SMBUS_BLOCK_DATA) && adapdata->notify_imc) 876 piix4_imc_wakeup(); 877 878release: 879 piix4_sb800_region_release(&adap->dev, &adapdata->mmio_cfg); 880 return retval; 881} 882 883static u32 piix4_func(struct i2c_adapter *adapter) 884{ 885 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | 886 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | 887 I2C_FUNC_SMBUS_BLOCK_DATA; 888} 889 890static const struct i2c_algorithm smbus_algorithm = { 891 .smbus_xfer = piix4_access, 892 .functionality = piix4_func, 893}; 894 895static const struct i2c_algorithm piix4_smbus_algorithm_sb800 = { 896 .smbus_xfer = piix4_access_sb800, 897 .functionality = piix4_func, 898}; 899 900static const struct pci_device_id piix4_ids[] = { 901 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3) }, 902 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3) }, 903 { PCI_DEVICE(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_3) }, 904 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP200_SMBUS) }, 905 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP300_SMBUS) }, 906 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS) }, 907 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS) }, 908 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SMBUS) }, 909 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_KERNCZ_SMBUS) }, 910 { PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_KERNCZ_SMBUS) }, 911 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, 912 PCI_DEVICE_ID_SERVERWORKS_OSB4) }, 913 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, 914 PCI_DEVICE_ID_SERVERWORKS_CSB5) }, 915 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, 916 PCI_DEVICE_ID_SERVERWORKS_CSB6) }, 917 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, 918 PCI_DEVICE_ID_SERVERWORKS_HT1000SB) }, 919 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, 920 PCI_DEVICE_ID_SERVERWORKS_HT1100LD) }, 921 { 0, } 922}; 923 924MODULE_DEVICE_TABLE (pci, piix4_ids); 925 926static struct i2c_adapter *piix4_main_adapters[PIIX4_MAX_ADAPTERS]; 927static struct i2c_adapter *piix4_aux_adapter; 928static int piix4_adapter_count; 929 930static int piix4_add_adapter(struct pci_dev *dev, unsigned short smba, 931 bool sb800_main, u8 port, bool notify_imc, 932 u8 hw_port_nr, const char *name, 933 struct i2c_adapter **padap) 934{ 935 struct i2c_adapter *adap; 936 struct i2c_piix4_adapdata *adapdata; 937 int retval; 938 939 adap = kzalloc(sizeof(*adap), GFP_KERNEL); 940 if (adap == NULL) { 941 release_region(smba, SMBIOSIZE); 942 return -ENOMEM; 943 } 944 945 adap->owner = THIS_MODULE; 946 adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD; 947 adap->algo = sb800_main ? &piix4_smbus_algorithm_sb800 948 : &smbus_algorithm; 949 950 adapdata = kzalloc(sizeof(*adapdata), GFP_KERNEL); 951 if (adapdata == NULL) { 952 kfree(adap); 953 release_region(smba, SMBIOSIZE); 954 return -ENOMEM; 955 } 956 957 adapdata->mmio_cfg.use_mmio = piix4_sb800_use_mmio(dev); 958 adapdata->smba = smba; 959 adapdata->sb800_main = sb800_main; 960 adapdata->port = port << piix4_port_shift_sb800; 961 adapdata->notify_imc = notify_imc; 962 963 /* set up the sysfs linkage to our parent device */ 964 adap->dev.parent = &dev->dev; 965 966 if (has_acpi_companion(&dev->dev)) { 967 acpi_preset_companion(&adap->dev, 968 ACPI_COMPANION(&dev->dev), 969 hw_port_nr); 970 } 971 972 snprintf(adap->name, sizeof(adap->name), 973 "SMBus PIIX4 adapter%s at %04x", name, smba); 974 975 i2c_set_adapdata(adap, adapdata); 976 977 retval = i2c_add_adapter(adap); 978 if (retval) { 979 kfree(adapdata); 980 kfree(adap); 981 release_region(smba, SMBIOSIZE); 982 return retval; 983 } 984 985 *padap = adap; 986 return 0; 987} 988 989static int piix4_add_adapters_sb800(struct pci_dev *dev, unsigned short smba, 990 bool notify_imc) 991{ 992 struct i2c_piix4_adapdata *adapdata; 993 int port; 994 int retval; 995 996 if (dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS || 997 (dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS && 998 dev->revision >= 0x1F)) { 999 piix4_adapter_count = HUDSON2_MAIN_PORTS; 1000 } else { 1001 piix4_adapter_count = PIIX4_MAX_ADAPTERS; 1002 } 1003 1004 for (port = 0; port < piix4_adapter_count; port++) { 1005 u8 hw_port_nr = port == 0 ? 0 : port + 1; 1006 1007 retval = piix4_add_adapter(dev, smba, true, port, notify_imc, 1008 hw_port_nr, 1009 piix4_main_port_names_sb800[port], 1010 &piix4_main_adapters[port]); 1011 if (retval < 0) 1012 goto error; 1013 } 1014 1015 return retval; 1016 1017error: 1018 dev_err(&dev->dev, 1019 "Error setting up SB800 adapters. Unregistering!\n"); 1020 while (--port >= 0) { 1021 adapdata = i2c_get_adapdata(piix4_main_adapters[port]); 1022 if (adapdata->smba) { 1023 i2c_del_adapter(piix4_main_adapters[port]); 1024 kfree(adapdata); 1025 kfree(piix4_main_adapters[port]); 1026 piix4_main_adapters[port] = NULL; 1027 } 1028 } 1029 1030 return retval; 1031} 1032 1033static int piix4_probe(struct pci_dev *dev, const struct pci_device_id *id) 1034{ 1035 int retval; 1036 bool is_sb800 = false; 1037 1038 if ((dev->vendor == PCI_VENDOR_ID_ATI && 1039 dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS && 1040 dev->revision >= 0x40) || 1041 dev->vendor == PCI_VENDOR_ID_AMD || 1042 dev->vendor == PCI_VENDOR_ID_HYGON) { 1043 bool notify_imc = false; 1044 is_sb800 = true; 1045 1046 if ((dev->vendor == PCI_VENDOR_ID_AMD || 1047 dev->vendor == PCI_VENDOR_ID_HYGON) && 1048 dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS) { 1049 u8 imc; 1050 1051 /* 1052 * Detect if IMC is active or not, this method is 1053 * described on coreboot's AMD IMC notes 1054 */ 1055 pci_bus_read_config_byte(dev->bus, PCI_DEVFN(0x14, 3), 1056 0x40, &imc); 1057 if (imc & 0x80) 1058 notify_imc = true; 1059 } 1060 1061 /* base address location etc changed in SB800 */ 1062 retval = piix4_setup_sb800(dev, id, 0); 1063 if (retval < 0) 1064 return retval; 1065 1066 /* 1067 * Try to register multiplexed main SMBus adapter, 1068 * give up if we can't 1069 */ 1070 retval = piix4_add_adapters_sb800(dev, retval, notify_imc); 1071 if (retval < 0) 1072 return retval; 1073 } else { 1074 retval = piix4_setup(dev, id); 1075 if (retval < 0) 1076 return retval; 1077 1078 /* Try to register main SMBus adapter, give up if we can't */ 1079 retval = piix4_add_adapter(dev, retval, false, 0, false, 0, 1080 "", &piix4_main_adapters[0]); 1081 if (retval < 0) 1082 return retval; 1083 piix4_adapter_count = 1; 1084 } 1085 1086 /* Check for auxiliary SMBus on some AMD chipsets */ 1087 retval = -ENODEV; 1088 1089 if (dev->vendor == PCI_VENDOR_ID_ATI && 1090 dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS) { 1091 if (dev->revision < 0x40) { 1092 retval = piix4_setup_aux(dev, id, 0x58); 1093 } else { 1094 /* SB800 added aux bus too */ 1095 retval = piix4_setup_sb800(dev, id, 1); 1096 } 1097 } 1098 1099 if (dev->vendor == PCI_VENDOR_ID_AMD && 1100 (dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS || 1101 dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS)) { 1102 retval = piix4_setup_sb800(dev, id, 1); 1103 } 1104 1105 if (retval > 0) { 1106 /* Try to add the aux adapter if it exists, 1107 * piix4_add_adapter will clean up if this fails */ 1108 piix4_add_adapter(dev, retval, false, 0, false, 1, 1109 is_sb800 ? piix4_aux_port_name_sb800 : "", 1110 &piix4_aux_adapter); 1111 } 1112 1113 return 0; 1114} 1115 1116static void piix4_adap_remove(struct i2c_adapter *adap) 1117{ 1118 struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(adap); 1119 1120 if (adapdata->smba) { 1121 i2c_del_adapter(adap); 1122 if (adapdata->port == (0 << piix4_port_shift_sb800)) 1123 release_region(adapdata->smba, SMBIOSIZE); 1124 kfree(adapdata); 1125 kfree(adap); 1126 } 1127} 1128 1129static void piix4_remove(struct pci_dev *dev) 1130{ 1131 int port = piix4_adapter_count; 1132 1133 while (--port >= 0) { 1134 if (piix4_main_adapters[port]) { 1135 piix4_adap_remove(piix4_main_adapters[port]); 1136 piix4_main_adapters[port] = NULL; 1137 } 1138 } 1139 1140 if (piix4_aux_adapter) { 1141 piix4_adap_remove(piix4_aux_adapter); 1142 piix4_aux_adapter = NULL; 1143 } 1144} 1145 1146static struct pci_driver piix4_driver = { 1147 .name = "piix4_smbus", 1148 .id_table = piix4_ids, 1149 .probe = piix4_probe, 1150 .remove = piix4_remove, 1151}; 1152 1153module_pci_driver(piix4_driver); 1154 1155MODULE_AUTHOR("Frodo Looijaard <frodol@dds.nl>"); 1156MODULE_AUTHOR("Philip Edelbrock <phil@netroedge.com>"); 1157MODULE_DESCRIPTION("PIIX4 SMBus driver"); 1158MODULE_LICENSE("GPL"); 1159