162306a36Sopenharmony_ci// SPDX-License-Identifier: GPL-2.0-or-later 262306a36Sopenharmony_ci/* 362306a36Sopenharmony_ci Copyright (c) 1999-2002 Merlin Hughes <merlin@merlin.org> 462306a36Sopenharmony_ci 562306a36Sopenharmony_ci Shamelessly ripped from i2c-piix4.c: 662306a36Sopenharmony_ci 762306a36Sopenharmony_ci Copyright (c) 1998, 1999 Frodo Looijaard <frodol@dds.nl> and 862306a36Sopenharmony_ci Philip Edelbrock <phil@netroedge.com> 962306a36Sopenharmony_ci 1062306a36Sopenharmony_ci*/ 1162306a36Sopenharmony_ci 1262306a36Sopenharmony_ci/* 1362306a36Sopenharmony_ci 2002-04-08: Added nForce support. (Csaba Halasz) 1462306a36Sopenharmony_ci 2002-10-03: Fixed nForce PnP I/O port. (Michael Steil) 1562306a36Sopenharmony_ci 2002-12-28: Rewritten into something that resembles a Linux driver (hch) 1662306a36Sopenharmony_ci 2003-11-29: Added back AMD8111 removed by the previous rewrite. 1762306a36Sopenharmony_ci (Philip Pokorny) 1862306a36Sopenharmony_ci*/ 1962306a36Sopenharmony_ci 2062306a36Sopenharmony_ci/* 2162306a36Sopenharmony_ci Supports AMD756, AMD766, AMD768, AMD8111 and nVidia nForce 2262306a36Sopenharmony_ci Note: we assume there can only be one device, with one SMBus interface. 2362306a36Sopenharmony_ci*/ 2462306a36Sopenharmony_ci 2562306a36Sopenharmony_ci#include <linux/module.h> 2662306a36Sopenharmony_ci#include <linux/pci.h> 2762306a36Sopenharmony_ci#include <linux/kernel.h> 2862306a36Sopenharmony_ci#include <linux/delay.h> 2962306a36Sopenharmony_ci#include <linux/stddef.h> 3062306a36Sopenharmony_ci#include <linux/ioport.h> 3162306a36Sopenharmony_ci#include <linux/i2c.h> 3262306a36Sopenharmony_ci#include <linux/acpi.h> 3362306a36Sopenharmony_ci#include <linux/io.h> 3462306a36Sopenharmony_ci 3562306a36Sopenharmony_ci/* AMD756 SMBus address offsets */ 3662306a36Sopenharmony_ci#define SMB_ADDR_OFFSET 0xE0 3762306a36Sopenharmony_ci#define SMB_IOSIZE 16 3862306a36Sopenharmony_ci#define SMB_GLOBAL_STATUS (0x0 + amd756_ioport) 3962306a36Sopenharmony_ci#define SMB_GLOBAL_ENABLE (0x2 + amd756_ioport) 4062306a36Sopenharmony_ci#define SMB_HOST_ADDRESS (0x4 + amd756_ioport) 4162306a36Sopenharmony_ci#define SMB_HOST_DATA (0x6 + amd756_ioport) 4262306a36Sopenharmony_ci#define SMB_HOST_COMMAND (0x8 + amd756_ioport) 4362306a36Sopenharmony_ci#define SMB_HOST_BLOCK_DATA (0x9 + amd756_ioport) 4462306a36Sopenharmony_ci#define SMB_HAS_DATA (0xA + amd756_ioport) 4562306a36Sopenharmony_ci#define SMB_HAS_DEVICE_ADDRESS (0xC + amd756_ioport) 4662306a36Sopenharmony_ci#define SMB_HAS_HOST_ADDRESS (0xE + amd756_ioport) 4762306a36Sopenharmony_ci#define SMB_SNOOP_ADDRESS (0xF + amd756_ioport) 4862306a36Sopenharmony_ci 4962306a36Sopenharmony_ci/* PCI Address Constants */ 5062306a36Sopenharmony_ci 5162306a36Sopenharmony_ci/* address of I/O space */ 5262306a36Sopenharmony_ci#define SMBBA 0x058 /* mh */ 5362306a36Sopenharmony_ci#define SMBBANFORCE 0x014 5462306a36Sopenharmony_ci 5562306a36Sopenharmony_ci/* general configuration */ 5662306a36Sopenharmony_ci#define SMBGCFG 0x041 /* mh */ 5762306a36Sopenharmony_ci 5862306a36Sopenharmony_ci/* silicon revision code */ 5962306a36Sopenharmony_ci#define SMBREV 0x008 6062306a36Sopenharmony_ci 6162306a36Sopenharmony_ci/* Other settings */ 6262306a36Sopenharmony_ci#define MAX_TIMEOUT 500 6362306a36Sopenharmony_ci 6462306a36Sopenharmony_ci/* AMD756 constants */ 6562306a36Sopenharmony_ci#define AMD756_QUICK 0x00 6662306a36Sopenharmony_ci#define AMD756_BYTE 0x01 6762306a36Sopenharmony_ci#define AMD756_BYTE_DATA 0x02 6862306a36Sopenharmony_ci#define AMD756_WORD_DATA 0x03 6962306a36Sopenharmony_ci#define AMD756_PROCESS_CALL 0x04 7062306a36Sopenharmony_ci#define AMD756_BLOCK_DATA 0x05 7162306a36Sopenharmony_ci 7262306a36Sopenharmony_cistatic struct pci_driver amd756_driver; 7362306a36Sopenharmony_cistatic unsigned short amd756_ioport; 7462306a36Sopenharmony_ci 7562306a36Sopenharmony_ci/* 7662306a36Sopenharmony_ci SMBUS event = I/O 28-29 bit 11 7762306a36Sopenharmony_ci see E0 for the status bits and enabled in E2 7862306a36Sopenharmony_ci 7962306a36Sopenharmony_ci*/ 8062306a36Sopenharmony_ci#define GS_ABRT_STS (1 << 0) 8162306a36Sopenharmony_ci#define GS_COL_STS (1 << 1) 8262306a36Sopenharmony_ci#define GS_PRERR_STS (1 << 2) 8362306a36Sopenharmony_ci#define GS_HST_STS (1 << 3) 8462306a36Sopenharmony_ci#define GS_HCYC_STS (1 << 4) 8562306a36Sopenharmony_ci#define GS_TO_STS (1 << 5) 8662306a36Sopenharmony_ci#define GS_SMB_STS (1 << 11) 8762306a36Sopenharmony_ci 8862306a36Sopenharmony_ci#define GS_CLEAR_STS (GS_ABRT_STS | GS_COL_STS | GS_PRERR_STS | \ 8962306a36Sopenharmony_ci GS_HCYC_STS | GS_TO_STS ) 9062306a36Sopenharmony_ci 9162306a36Sopenharmony_ci#define GE_CYC_TYPE_MASK (7) 9262306a36Sopenharmony_ci#define GE_HOST_STC (1 << 3) 9362306a36Sopenharmony_ci#define GE_ABORT (1 << 5) 9462306a36Sopenharmony_ci 9562306a36Sopenharmony_ci 9662306a36Sopenharmony_cistatic int amd756_transaction(struct i2c_adapter *adap) 9762306a36Sopenharmony_ci{ 9862306a36Sopenharmony_ci int temp; 9962306a36Sopenharmony_ci int result = 0; 10062306a36Sopenharmony_ci int timeout = 0; 10162306a36Sopenharmony_ci 10262306a36Sopenharmony_ci dev_dbg(&adap->dev, "Transaction (pre): GS=%04x, GE=%04x, ADD=%04x, " 10362306a36Sopenharmony_ci "DAT=%04x\n", inw_p(SMB_GLOBAL_STATUS), 10462306a36Sopenharmony_ci inw_p(SMB_GLOBAL_ENABLE), inw_p(SMB_HOST_ADDRESS), 10562306a36Sopenharmony_ci inb_p(SMB_HOST_DATA)); 10662306a36Sopenharmony_ci 10762306a36Sopenharmony_ci /* Make sure the SMBus host is ready to start transmitting */ 10862306a36Sopenharmony_ci if ((temp = inw_p(SMB_GLOBAL_STATUS)) & (GS_HST_STS | GS_SMB_STS)) { 10962306a36Sopenharmony_ci dev_dbg(&adap->dev, "SMBus busy (%04x). Waiting...\n", temp); 11062306a36Sopenharmony_ci do { 11162306a36Sopenharmony_ci msleep(1); 11262306a36Sopenharmony_ci temp = inw_p(SMB_GLOBAL_STATUS); 11362306a36Sopenharmony_ci } while ((temp & (GS_HST_STS | GS_SMB_STS)) && 11462306a36Sopenharmony_ci (timeout++ < MAX_TIMEOUT)); 11562306a36Sopenharmony_ci /* If the SMBus is still busy, we give up */ 11662306a36Sopenharmony_ci if (timeout > MAX_TIMEOUT) { 11762306a36Sopenharmony_ci dev_dbg(&adap->dev, "Busy wait timeout (%04x)\n", temp); 11862306a36Sopenharmony_ci goto abort; 11962306a36Sopenharmony_ci } 12062306a36Sopenharmony_ci timeout = 0; 12162306a36Sopenharmony_ci } 12262306a36Sopenharmony_ci 12362306a36Sopenharmony_ci /* start the transaction by setting the start bit */ 12462306a36Sopenharmony_ci outw_p(inw(SMB_GLOBAL_ENABLE) | GE_HOST_STC, SMB_GLOBAL_ENABLE); 12562306a36Sopenharmony_ci 12662306a36Sopenharmony_ci /* We will always wait for a fraction of a second! */ 12762306a36Sopenharmony_ci do { 12862306a36Sopenharmony_ci msleep(1); 12962306a36Sopenharmony_ci temp = inw_p(SMB_GLOBAL_STATUS); 13062306a36Sopenharmony_ci } while ((temp & GS_HST_STS) && (timeout++ < MAX_TIMEOUT)); 13162306a36Sopenharmony_ci 13262306a36Sopenharmony_ci /* If the SMBus is still busy, we give up */ 13362306a36Sopenharmony_ci if (timeout > MAX_TIMEOUT) { 13462306a36Sopenharmony_ci dev_dbg(&adap->dev, "Completion timeout!\n"); 13562306a36Sopenharmony_ci goto abort; 13662306a36Sopenharmony_ci } 13762306a36Sopenharmony_ci 13862306a36Sopenharmony_ci if (temp & GS_PRERR_STS) { 13962306a36Sopenharmony_ci result = -ENXIO; 14062306a36Sopenharmony_ci dev_dbg(&adap->dev, "SMBus Protocol error (no response)!\n"); 14162306a36Sopenharmony_ci } 14262306a36Sopenharmony_ci 14362306a36Sopenharmony_ci if (temp & GS_COL_STS) { 14462306a36Sopenharmony_ci result = -EIO; 14562306a36Sopenharmony_ci dev_warn(&adap->dev, "SMBus collision!\n"); 14662306a36Sopenharmony_ci } 14762306a36Sopenharmony_ci 14862306a36Sopenharmony_ci if (temp & GS_TO_STS) { 14962306a36Sopenharmony_ci result = -ETIMEDOUT; 15062306a36Sopenharmony_ci dev_dbg(&adap->dev, "SMBus protocol timeout!\n"); 15162306a36Sopenharmony_ci } 15262306a36Sopenharmony_ci 15362306a36Sopenharmony_ci if (temp & GS_HCYC_STS) 15462306a36Sopenharmony_ci dev_dbg(&adap->dev, "SMBus protocol success!\n"); 15562306a36Sopenharmony_ci 15662306a36Sopenharmony_ci outw_p(GS_CLEAR_STS, SMB_GLOBAL_STATUS); 15762306a36Sopenharmony_ci 15862306a36Sopenharmony_ci#ifdef DEBUG 15962306a36Sopenharmony_ci if (((temp = inw_p(SMB_GLOBAL_STATUS)) & GS_CLEAR_STS) != 0x00) { 16062306a36Sopenharmony_ci dev_dbg(&adap->dev, 16162306a36Sopenharmony_ci "Failed reset at end of transaction (%04x)\n", temp); 16262306a36Sopenharmony_ci } 16362306a36Sopenharmony_ci#endif 16462306a36Sopenharmony_ci 16562306a36Sopenharmony_ci dev_dbg(&adap->dev, 16662306a36Sopenharmony_ci "Transaction (post): GS=%04x, GE=%04x, ADD=%04x, DAT=%04x\n", 16762306a36Sopenharmony_ci inw_p(SMB_GLOBAL_STATUS), inw_p(SMB_GLOBAL_ENABLE), 16862306a36Sopenharmony_ci inw_p(SMB_HOST_ADDRESS), inb_p(SMB_HOST_DATA)); 16962306a36Sopenharmony_ci 17062306a36Sopenharmony_ci return result; 17162306a36Sopenharmony_ci 17262306a36Sopenharmony_ci abort: 17362306a36Sopenharmony_ci dev_warn(&adap->dev, "Sending abort\n"); 17462306a36Sopenharmony_ci outw_p(inw(SMB_GLOBAL_ENABLE) | GE_ABORT, SMB_GLOBAL_ENABLE); 17562306a36Sopenharmony_ci msleep(100); 17662306a36Sopenharmony_ci outw_p(GS_CLEAR_STS, SMB_GLOBAL_STATUS); 17762306a36Sopenharmony_ci return -EIO; 17862306a36Sopenharmony_ci} 17962306a36Sopenharmony_ci 18062306a36Sopenharmony_ci/* Return negative errno on error. */ 18162306a36Sopenharmony_cistatic s32 amd756_access(struct i2c_adapter * adap, u16 addr, 18262306a36Sopenharmony_ci unsigned short flags, char read_write, 18362306a36Sopenharmony_ci u8 command, int size, union i2c_smbus_data * data) 18462306a36Sopenharmony_ci{ 18562306a36Sopenharmony_ci int i, len; 18662306a36Sopenharmony_ci int status; 18762306a36Sopenharmony_ci 18862306a36Sopenharmony_ci switch (size) { 18962306a36Sopenharmony_ci case I2C_SMBUS_QUICK: 19062306a36Sopenharmony_ci outw_p(((addr & 0x7f) << 1) | (read_write & 0x01), 19162306a36Sopenharmony_ci SMB_HOST_ADDRESS); 19262306a36Sopenharmony_ci size = AMD756_QUICK; 19362306a36Sopenharmony_ci break; 19462306a36Sopenharmony_ci case I2C_SMBUS_BYTE: 19562306a36Sopenharmony_ci outw_p(((addr & 0x7f) << 1) | (read_write & 0x01), 19662306a36Sopenharmony_ci SMB_HOST_ADDRESS); 19762306a36Sopenharmony_ci if (read_write == I2C_SMBUS_WRITE) 19862306a36Sopenharmony_ci outb_p(command, SMB_HOST_DATA); 19962306a36Sopenharmony_ci size = AMD756_BYTE; 20062306a36Sopenharmony_ci break; 20162306a36Sopenharmony_ci case I2C_SMBUS_BYTE_DATA: 20262306a36Sopenharmony_ci outw_p(((addr & 0x7f) << 1) | (read_write & 0x01), 20362306a36Sopenharmony_ci SMB_HOST_ADDRESS); 20462306a36Sopenharmony_ci outb_p(command, SMB_HOST_COMMAND); 20562306a36Sopenharmony_ci if (read_write == I2C_SMBUS_WRITE) 20662306a36Sopenharmony_ci outw_p(data->byte, SMB_HOST_DATA); 20762306a36Sopenharmony_ci size = AMD756_BYTE_DATA; 20862306a36Sopenharmony_ci break; 20962306a36Sopenharmony_ci case I2C_SMBUS_WORD_DATA: 21062306a36Sopenharmony_ci outw_p(((addr & 0x7f) << 1) | (read_write & 0x01), 21162306a36Sopenharmony_ci SMB_HOST_ADDRESS); 21262306a36Sopenharmony_ci outb_p(command, SMB_HOST_COMMAND); 21362306a36Sopenharmony_ci if (read_write == I2C_SMBUS_WRITE) 21462306a36Sopenharmony_ci outw_p(data->word, SMB_HOST_DATA); /* TODO: endian???? */ 21562306a36Sopenharmony_ci size = AMD756_WORD_DATA; 21662306a36Sopenharmony_ci break; 21762306a36Sopenharmony_ci case I2C_SMBUS_BLOCK_DATA: 21862306a36Sopenharmony_ci outw_p(((addr & 0x7f) << 1) | (read_write & 0x01), 21962306a36Sopenharmony_ci SMB_HOST_ADDRESS); 22062306a36Sopenharmony_ci outb_p(command, SMB_HOST_COMMAND); 22162306a36Sopenharmony_ci if (read_write == I2C_SMBUS_WRITE) { 22262306a36Sopenharmony_ci len = data->block[0]; 22362306a36Sopenharmony_ci if (len < 0) 22462306a36Sopenharmony_ci len = 0; 22562306a36Sopenharmony_ci if (len > 32) 22662306a36Sopenharmony_ci len = 32; 22762306a36Sopenharmony_ci outw_p(len, SMB_HOST_DATA); 22862306a36Sopenharmony_ci /* i = inw_p(SMBHSTCNT); Reset SMBBLKDAT */ 22962306a36Sopenharmony_ci for (i = 1; i <= len; i++) 23062306a36Sopenharmony_ci outb_p(data->block[i], 23162306a36Sopenharmony_ci SMB_HOST_BLOCK_DATA); 23262306a36Sopenharmony_ci } 23362306a36Sopenharmony_ci size = AMD756_BLOCK_DATA; 23462306a36Sopenharmony_ci break; 23562306a36Sopenharmony_ci default: 23662306a36Sopenharmony_ci dev_warn(&adap->dev, "Unsupported transaction %d\n", size); 23762306a36Sopenharmony_ci return -EOPNOTSUPP; 23862306a36Sopenharmony_ci } 23962306a36Sopenharmony_ci 24062306a36Sopenharmony_ci /* How about enabling interrupts... */ 24162306a36Sopenharmony_ci outw_p(size & GE_CYC_TYPE_MASK, SMB_GLOBAL_ENABLE); 24262306a36Sopenharmony_ci 24362306a36Sopenharmony_ci status = amd756_transaction(adap); 24462306a36Sopenharmony_ci if (status) 24562306a36Sopenharmony_ci return status; 24662306a36Sopenharmony_ci 24762306a36Sopenharmony_ci if ((read_write == I2C_SMBUS_WRITE) || (size == AMD756_QUICK)) 24862306a36Sopenharmony_ci return 0; 24962306a36Sopenharmony_ci 25062306a36Sopenharmony_ci 25162306a36Sopenharmony_ci switch (size) { 25262306a36Sopenharmony_ci case AMD756_BYTE: 25362306a36Sopenharmony_ci data->byte = inw_p(SMB_HOST_DATA); 25462306a36Sopenharmony_ci break; 25562306a36Sopenharmony_ci case AMD756_BYTE_DATA: 25662306a36Sopenharmony_ci data->byte = inw_p(SMB_HOST_DATA); 25762306a36Sopenharmony_ci break; 25862306a36Sopenharmony_ci case AMD756_WORD_DATA: 25962306a36Sopenharmony_ci data->word = inw_p(SMB_HOST_DATA); /* TODO: endian???? */ 26062306a36Sopenharmony_ci break; 26162306a36Sopenharmony_ci case AMD756_BLOCK_DATA: 26262306a36Sopenharmony_ci data->block[0] = inw_p(SMB_HOST_DATA) & 0x3f; 26362306a36Sopenharmony_ci if(data->block[0] > 32) 26462306a36Sopenharmony_ci data->block[0] = 32; 26562306a36Sopenharmony_ci /* i = inw_p(SMBHSTCNT); Reset SMBBLKDAT */ 26662306a36Sopenharmony_ci for (i = 1; i <= data->block[0]; i++) 26762306a36Sopenharmony_ci data->block[i] = inb_p(SMB_HOST_BLOCK_DATA); 26862306a36Sopenharmony_ci break; 26962306a36Sopenharmony_ci } 27062306a36Sopenharmony_ci 27162306a36Sopenharmony_ci return 0; 27262306a36Sopenharmony_ci} 27362306a36Sopenharmony_ci 27462306a36Sopenharmony_cistatic u32 amd756_func(struct i2c_adapter *adapter) 27562306a36Sopenharmony_ci{ 27662306a36Sopenharmony_ci return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | 27762306a36Sopenharmony_ci I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | 27862306a36Sopenharmony_ci I2C_FUNC_SMBUS_BLOCK_DATA; 27962306a36Sopenharmony_ci} 28062306a36Sopenharmony_ci 28162306a36Sopenharmony_cistatic const struct i2c_algorithm smbus_algorithm = { 28262306a36Sopenharmony_ci .smbus_xfer = amd756_access, 28362306a36Sopenharmony_ci .functionality = amd756_func, 28462306a36Sopenharmony_ci}; 28562306a36Sopenharmony_ci 28662306a36Sopenharmony_cistruct i2c_adapter amd756_smbus = { 28762306a36Sopenharmony_ci .owner = THIS_MODULE, 28862306a36Sopenharmony_ci .class = I2C_CLASS_HWMON | I2C_CLASS_SPD, 28962306a36Sopenharmony_ci .algo = &smbus_algorithm, 29062306a36Sopenharmony_ci}; 29162306a36Sopenharmony_ci 29262306a36Sopenharmony_cienum chiptype { AMD756, AMD766, AMD768, NFORCE, AMD8111 }; 29362306a36Sopenharmony_cistatic const char* chipname[] = { 29462306a36Sopenharmony_ci "AMD756", "AMD766", "AMD768", 29562306a36Sopenharmony_ci "nVidia nForce", "AMD8111", 29662306a36Sopenharmony_ci}; 29762306a36Sopenharmony_ci 29862306a36Sopenharmony_cistatic const struct pci_device_id amd756_ids[] = { 29962306a36Sopenharmony_ci { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_740B), 30062306a36Sopenharmony_ci .driver_data = AMD756 }, 30162306a36Sopenharmony_ci { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7413), 30262306a36Sopenharmony_ci .driver_data = AMD766 }, 30362306a36Sopenharmony_ci { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_OPUS_7443), 30462306a36Sopenharmony_ci .driver_data = AMD768 }, 30562306a36Sopenharmony_ci { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS), 30662306a36Sopenharmony_ci .driver_data = AMD8111 }, 30762306a36Sopenharmony_ci { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_SMBUS), 30862306a36Sopenharmony_ci .driver_data = NFORCE }, 30962306a36Sopenharmony_ci { 0, } 31062306a36Sopenharmony_ci}; 31162306a36Sopenharmony_ci 31262306a36Sopenharmony_ciMODULE_DEVICE_TABLE (pci, amd756_ids); 31362306a36Sopenharmony_ci 31462306a36Sopenharmony_cistatic int amd756_probe(struct pci_dev *pdev, const struct pci_device_id *id) 31562306a36Sopenharmony_ci{ 31662306a36Sopenharmony_ci int nforce = (id->driver_data == NFORCE); 31762306a36Sopenharmony_ci int error; 31862306a36Sopenharmony_ci u8 temp; 31962306a36Sopenharmony_ci 32062306a36Sopenharmony_ci if (amd756_ioport) { 32162306a36Sopenharmony_ci dev_err(&pdev->dev, "Only one device supported " 32262306a36Sopenharmony_ci "(you have a strange motherboard, btw)\n"); 32362306a36Sopenharmony_ci return -ENODEV; 32462306a36Sopenharmony_ci } 32562306a36Sopenharmony_ci 32662306a36Sopenharmony_ci if (nforce) { 32762306a36Sopenharmony_ci if (PCI_FUNC(pdev->devfn) != 1) 32862306a36Sopenharmony_ci return -ENODEV; 32962306a36Sopenharmony_ci 33062306a36Sopenharmony_ci pci_read_config_word(pdev, SMBBANFORCE, &amd756_ioport); 33162306a36Sopenharmony_ci amd756_ioport &= 0xfffc; 33262306a36Sopenharmony_ci } else { /* amd */ 33362306a36Sopenharmony_ci if (PCI_FUNC(pdev->devfn) != 3) 33462306a36Sopenharmony_ci return -ENODEV; 33562306a36Sopenharmony_ci 33662306a36Sopenharmony_ci pci_read_config_byte(pdev, SMBGCFG, &temp); 33762306a36Sopenharmony_ci if ((temp & 128) == 0) { 33862306a36Sopenharmony_ci dev_err(&pdev->dev, 33962306a36Sopenharmony_ci "Error: SMBus controller I/O not enabled!\n"); 34062306a36Sopenharmony_ci return -ENODEV; 34162306a36Sopenharmony_ci } 34262306a36Sopenharmony_ci 34362306a36Sopenharmony_ci /* Determine the address of the SMBus areas */ 34462306a36Sopenharmony_ci /* Technically it is a dword but... */ 34562306a36Sopenharmony_ci pci_read_config_word(pdev, SMBBA, &amd756_ioport); 34662306a36Sopenharmony_ci amd756_ioport &= 0xff00; 34762306a36Sopenharmony_ci amd756_ioport += SMB_ADDR_OFFSET; 34862306a36Sopenharmony_ci } 34962306a36Sopenharmony_ci 35062306a36Sopenharmony_ci error = acpi_check_region(amd756_ioport, SMB_IOSIZE, 35162306a36Sopenharmony_ci amd756_driver.name); 35262306a36Sopenharmony_ci if (error) 35362306a36Sopenharmony_ci return -ENODEV; 35462306a36Sopenharmony_ci 35562306a36Sopenharmony_ci if (!request_region(amd756_ioport, SMB_IOSIZE, amd756_driver.name)) { 35662306a36Sopenharmony_ci dev_err(&pdev->dev, "SMB region 0x%x already in use!\n", 35762306a36Sopenharmony_ci amd756_ioport); 35862306a36Sopenharmony_ci return -ENODEV; 35962306a36Sopenharmony_ci } 36062306a36Sopenharmony_ci 36162306a36Sopenharmony_ci pci_read_config_byte(pdev, SMBREV, &temp); 36262306a36Sopenharmony_ci dev_dbg(&pdev->dev, "SMBREV = 0x%X\n", temp); 36362306a36Sopenharmony_ci dev_dbg(&pdev->dev, "AMD756_smba = 0x%X\n", amd756_ioport); 36462306a36Sopenharmony_ci 36562306a36Sopenharmony_ci /* set up the sysfs linkage to our parent device */ 36662306a36Sopenharmony_ci amd756_smbus.dev.parent = &pdev->dev; 36762306a36Sopenharmony_ci 36862306a36Sopenharmony_ci snprintf(amd756_smbus.name, sizeof(amd756_smbus.name), 36962306a36Sopenharmony_ci "SMBus %s adapter at %04x", chipname[id->driver_data], 37062306a36Sopenharmony_ci amd756_ioport); 37162306a36Sopenharmony_ci 37262306a36Sopenharmony_ci error = i2c_add_adapter(&amd756_smbus); 37362306a36Sopenharmony_ci if (error) 37462306a36Sopenharmony_ci goto out_err; 37562306a36Sopenharmony_ci 37662306a36Sopenharmony_ci return 0; 37762306a36Sopenharmony_ci 37862306a36Sopenharmony_ci out_err: 37962306a36Sopenharmony_ci release_region(amd756_ioport, SMB_IOSIZE); 38062306a36Sopenharmony_ci return error; 38162306a36Sopenharmony_ci} 38262306a36Sopenharmony_ci 38362306a36Sopenharmony_cistatic void amd756_remove(struct pci_dev *dev) 38462306a36Sopenharmony_ci{ 38562306a36Sopenharmony_ci i2c_del_adapter(&amd756_smbus); 38662306a36Sopenharmony_ci release_region(amd756_ioport, SMB_IOSIZE); 38762306a36Sopenharmony_ci} 38862306a36Sopenharmony_ci 38962306a36Sopenharmony_cistatic struct pci_driver amd756_driver = { 39062306a36Sopenharmony_ci .name = "amd756_smbus", 39162306a36Sopenharmony_ci .id_table = amd756_ids, 39262306a36Sopenharmony_ci .probe = amd756_probe, 39362306a36Sopenharmony_ci .remove = amd756_remove, 39462306a36Sopenharmony_ci}; 39562306a36Sopenharmony_ci 39662306a36Sopenharmony_cimodule_pci_driver(amd756_driver); 39762306a36Sopenharmony_ci 39862306a36Sopenharmony_ciMODULE_AUTHOR("Merlin Hughes <merlin@merlin.org>"); 39962306a36Sopenharmony_ciMODULE_DESCRIPTION("AMD756/766/768/8111 and nVidia nForce SMBus driver"); 40062306a36Sopenharmony_ciMODULE_LICENSE("GPL"); 40162306a36Sopenharmony_ci 40262306a36Sopenharmony_ciEXPORT_SYMBOL(amd756_smbus); 403