1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (c) 2021-2022 NVIDIA Corporation 4 * 5 * Author: Dipen Patel <dipenp@nvidia.com> 6 */ 7 8#include <linux/err.h> 9#include <linux/io.h> 10#include <linux/module.h> 11#include <linux/slab.h> 12#include <linux/stat.h> 13#include <linux/interrupt.h> 14#include <linux/of.h> 15#include <linux/platform_device.h> 16#include <linux/hte.h> 17#include <linux/uaccess.h> 18#include <linux/gpio/driver.h> 19#include <linux/gpio/consumer.h> 20 21#define HTE_SUSPEND 0 22 23/* HTE source clock TSC is 31.25MHz */ 24#define HTE_TS_CLK_RATE_HZ 31250000ULL 25#define HTE_CLK_RATE_NS 32 26#define HTE_TS_NS_SHIFT __builtin_ctz(HTE_CLK_RATE_NS) 27 28#define NV_AON_SLICE_INVALID -1 29#define NV_LINES_IN_SLICE 32 30 31/* AON HTE line map For slice 1 */ 32#define NV_AON_HTE_SLICE1_IRQ_GPIO_28 12 33#define NV_AON_HTE_SLICE1_IRQ_GPIO_29 13 34 35/* AON HTE line map For slice 2 */ 36#define NV_AON_HTE_SLICE2_IRQ_GPIO_0 0 37#define NV_AON_HTE_SLICE2_IRQ_GPIO_1 1 38#define NV_AON_HTE_SLICE2_IRQ_GPIO_2 2 39#define NV_AON_HTE_SLICE2_IRQ_GPIO_3 3 40#define NV_AON_HTE_SLICE2_IRQ_GPIO_4 4 41#define NV_AON_HTE_SLICE2_IRQ_GPIO_5 5 42#define NV_AON_HTE_SLICE2_IRQ_GPIO_6 6 43#define NV_AON_HTE_SLICE2_IRQ_GPIO_7 7 44#define NV_AON_HTE_SLICE2_IRQ_GPIO_8 8 45#define NV_AON_HTE_SLICE2_IRQ_GPIO_9 9 46#define NV_AON_HTE_SLICE2_IRQ_GPIO_10 10 47#define NV_AON_HTE_SLICE2_IRQ_GPIO_11 11 48#define NV_AON_HTE_SLICE2_IRQ_GPIO_12 12 49#define NV_AON_HTE_SLICE2_IRQ_GPIO_13 13 50#define NV_AON_HTE_SLICE2_IRQ_GPIO_14 14 51#define NV_AON_HTE_SLICE2_IRQ_GPIO_15 15 52#define NV_AON_HTE_SLICE2_IRQ_GPIO_16 16 53#define NV_AON_HTE_SLICE2_IRQ_GPIO_17 17 54#define NV_AON_HTE_SLICE2_IRQ_GPIO_18 18 55#define NV_AON_HTE_SLICE2_IRQ_GPIO_19 19 56#define NV_AON_HTE_SLICE2_IRQ_GPIO_20 20 57#define NV_AON_HTE_SLICE2_IRQ_GPIO_21 21 58#define NV_AON_HTE_SLICE2_IRQ_GPIO_22 22 59#define NV_AON_HTE_SLICE2_IRQ_GPIO_23 23 60#define NV_AON_HTE_SLICE2_IRQ_GPIO_24 24 61#define NV_AON_HTE_SLICE2_IRQ_GPIO_25 25 62#define NV_AON_HTE_SLICE2_IRQ_GPIO_26 26 63#define NV_AON_HTE_SLICE2_IRQ_GPIO_27 27 64#define NV_AON_HTE_SLICE2_IRQ_GPIO_28 28 65#define NV_AON_HTE_SLICE2_IRQ_GPIO_29 29 66#define NV_AON_HTE_SLICE2_IRQ_GPIO_30 30 67#define NV_AON_HTE_SLICE2_IRQ_GPIO_31 31 68 69#define HTE_TECTRL 0x0 70#define HTE_TETSCH 0x4 71#define HTE_TETSCL 0x8 72#define HTE_TESRC 0xC 73#define HTE_TECCV 0x10 74#define HTE_TEPCV 0x14 75#define HTE_TECMD 0x1C 76#define HTE_TESTATUS 0x20 77#define HTE_SLICE0_TETEN 0x40 78#define HTE_SLICE1_TETEN 0x60 79 80#define HTE_SLICE_SIZE (HTE_SLICE1_TETEN - HTE_SLICE0_TETEN) 81 82#define HTE_TECTRL_ENABLE_ENABLE 0x1 83 84#define HTE_TECTRL_OCCU_SHIFT 0x8 85#define HTE_TECTRL_INTR_SHIFT 0x1 86#define HTE_TECTRL_INTR_ENABLE 0x1 87 88#define HTE_TESRC_SLICE_SHIFT 16 89#define HTE_TESRC_SLICE_DEFAULT_MASK 0xFF 90 91#define HTE_TECMD_CMD_POP 0x1 92 93#define HTE_TESTATUS_OCCUPANCY_SHIFT 8 94#define HTE_TESTATUS_OCCUPANCY_MASK 0xFF 95 96enum tegra_hte_type { 97 HTE_TEGRA_TYPE_GPIO = 1U << 0, 98 HTE_TEGRA_TYPE_LIC = 1U << 1, 99}; 100 101struct hte_slices { 102 u32 r_val; 103 unsigned long flags; 104 /* to prevent lines mapped to same slice updating its register */ 105 spinlock_t s_lock; 106}; 107 108struct tegra_hte_line_mapped { 109 int slice; 110 u32 bit_index; 111}; 112 113struct tegra_hte_line_data { 114 unsigned long flags; 115 void *data; 116}; 117 118struct tegra_hte_data { 119 enum tegra_hte_type type; 120 u32 slices; 121 u32 map_sz; 122 u32 sec_map_sz; 123 const struct tegra_hte_line_mapped *map; 124 const struct tegra_hte_line_mapped *sec_map; 125}; 126 127struct tegra_hte_soc { 128 int hte_irq; 129 u32 itr_thrshld; 130 u32 conf_rval; 131 struct hte_slices *sl; 132 const struct tegra_hte_data *prov_data; 133 struct tegra_hte_line_data *line_data; 134 struct hte_chip *chip; 135 struct gpio_chip *c; 136 void __iomem *regs; 137}; 138 139static const struct tegra_hte_line_mapped tegra194_aon_gpio_map[] = { 140 /* gpio, slice, bit_index */ 141 /* AA port */ 142 [0] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_11}, 143 [1] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_10}, 144 [2] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_9}, 145 [3] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_8}, 146 [4] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_7}, 147 [5] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_6}, 148 [6] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_5}, 149 [7] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_4}, 150 /* BB port */ 151 [8] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_3}, 152 [9] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_2}, 153 [10] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_1}, 154 [11] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_0}, 155 /* CC port */ 156 [12] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_22}, 157 [13] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_21}, 158 [14] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_20}, 159 [15] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_19}, 160 [16] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_18}, 161 [17] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_17}, 162 [18] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_16}, 163 [19] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_15}, 164 /* DD port */ 165 [20] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_14}, 166 [21] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_13}, 167 [22] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_12}, 168 /* EE port */ 169 [23] = {1, NV_AON_HTE_SLICE1_IRQ_GPIO_29}, 170 [24] = {1, NV_AON_HTE_SLICE1_IRQ_GPIO_28}, 171 [25] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_27}, 172 [26] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_26}, 173 [27] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_25}, 174 [28] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_24}, 175 [29] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_23}, 176}; 177 178static const struct tegra_hte_line_mapped tegra194_aon_gpio_sec_map[] = { 179 /* gpio, slice, bit_index */ 180 /* AA port */ 181 [0] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_11}, 182 [1] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_10}, 183 [2] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_9}, 184 [3] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_8}, 185 [4] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_7}, 186 [5] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_6}, 187 [6] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_5}, 188 [7] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_4}, 189 /* BB port */ 190 [8] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_3}, 191 [9] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_2}, 192 [10] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_1}, 193 [11] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_0}, 194 [12] = {NV_AON_SLICE_INVALID, 0}, 195 [13] = {NV_AON_SLICE_INVALID, 0}, 196 [14] = {NV_AON_SLICE_INVALID, 0}, 197 [15] = {NV_AON_SLICE_INVALID, 0}, 198 /* CC port */ 199 [16] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_22}, 200 [17] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_21}, 201 [18] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_20}, 202 [19] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_19}, 203 [20] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_18}, 204 [21] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_17}, 205 [22] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_16}, 206 [23] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_15}, 207 /* DD port */ 208 [24] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_14}, 209 [25] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_13}, 210 [26] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_12}, 211 [27] = {NV_AON_SLICE_INVALID, 0}, 212 [28] = {NV_AON_SLICE_INVALID, 0}, 213 [29] = {NV_AON_SLICE_INVALID, 0}, 214 [30] = {NV_AON_SLICE_INVALID, 0}, 215 [31] = {NV_AON_SLICE_INVALID, 0}, 216 /* EE port */ 217 [32] = {1, NV_AON_HTE_SLICE1_IRQ_GPIO_29}, 218 [33] = {1, NV_AON_HTE_SLICE1_IRQ_GPIO_28}, 219 [34] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_27}, 220 [35] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_26}, 221 [36] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_25}, 222 [37] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_24}, 223 [38] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_23}, 224 [39] = {NV_AON_SLICE_INVALID, 0}, 225}; 226 227static const struct tegra_hte_line_mapped tegra234_aon_gpio_map[] = { 228 /* gpio, slice, bit_index */ 229 /* AA port */ 230 [0] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_11}, 231 [1] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_10}, 232 [2] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_9}, 233 [3] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_8}, 234 [4] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_7}, 235 [5] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_6}, 236 [6] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_5}, 237 [7] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_4}, 238 /* BB port */ 239 [8] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_3}, 240 [9] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_2}, 241 [10] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_1}, 242 [11] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_0}, 243 /* CC port */ 244 [12] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_22}, 245 [13] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_21}, 246 [14] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_20}, 247 [15] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_19}, 248 [16] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_18}, 249 [17] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_17}, 250 [18] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_16}, 251 [19] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_15}, 252 /* DD port */ 253 [20] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_14}, 254 [21] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_13}, 255 [22] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_12}, 256 /* EE port */ 257 [23] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_31}, 258 [24] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_30}, 259 [25] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_29}, 260 [26] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_28}, 261 [27] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_27}, 262 [28] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_26}, 263 [29] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_25}, 264 [30] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_24}, 265 /* GG port */ 266 [31] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_23}, 267}; 268 269static const struct tegra_hte_line_mapped tegra234_aon_gpio_sec_map[] = { 270 /* gpio, slice, bit_index */ 271 /* AA port */ 272 [0] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_11}, 273 [1] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_10}, 274 [2] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_9}, 275 [3] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_8}, 276 [4] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_7}, 277 [5] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_6}, 278 [6] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_5}, 279 [7] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_4}, 280 /* BB port */ 281 [8] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_3}, 282 [9] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_2}, 283 [10] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_1}, 284 [11] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_0}, 285 [12] = {NV_AON_SLICE_INVALID, 0}, 286 [13] = {NV_AON_SLICE_INVALID, 0}, 287 [14] = {NV_AON_SLICE_INVALID, 0}, 288 [15] = {NV_AON_SLICE_INVALID, 0}, 289 /* CC port */ 290 [16] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_22}, 291 [17] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_21}, 292 [18] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_20}, 293 [19] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_19}, 294 [20] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_18}, 295 [21] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_17}, 296 [22] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_16}, 297 [23] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_15}, 298 /* DD port */ 299 [24] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_14}, 300 [25] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_13}, 301 [26] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_12}, 302 [27] = {NV_AON_SLICE_INVALID, 0}, 303 [28] = {NV_AON_SLICE_INVALID, 0}, 304 [29] = {NV_AON_SLICE_INVALID, 0}, 305 [30] = {NV_AON_SLICE_INVALID, 0}, 306 [31] = {NV_AON_SLICE_INVALID, 0}, 307 /* EE port */ 308 [32] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_31}, 309 [33] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_30}, 310 [34] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_29}, 311 [35] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_28}, 312 [36] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_27}, 313 [37] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_26}, 314 [38] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_25}, 315 [39] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_24}, 316 /* GG port */ 317 [40] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_23}, 318}; 319 320static const struct tegra_hte_data t194_aon_hte = { 321 .map_sz = ARRAY_SIZE(tegra194_aon_gpio_map), 322 .map = tegra194_aon_gpio_map, 323 .sec_map_sz = ARRAY_SIZE(tegra194_aon_gpio_sec_map), 324 .sec_map = tegra194_aon_gpio_sec_map, 325 .type = HTE_TEGRA_TYPE_GPIO, 326 .slices = 3, 327}; 328 329static const struct tegra_hte_data t234_aon_hte = { 330 .map_sz = ARRAY_SIZE(tegra234_aon_gpio_map), 331 .map = tegra234_aon_gpio_map, 332 .sec_map_sz = ARRAY_SIZE(tegra234_aon_gpio_sec_map), 333 .sec_map = tegra234_aon_gpio_sec_map, 334 .type = HTE_TEGRA_TYPE_GPIO, 335 .slices = 3, 336}; 337 338static const struct tegra_hte_data t194_lic_hte = { 339 .map_sz = 0, 340 .map = NULL, 341 .type = HTE_TEGRA_TYPE_LIC, 342 .slices = 11, 343}; 344 345static const struct tegra_hte_data t234_lic_hte = { 346 .map_sz = 0, 347 .map = NULL, 348 .type = HTE_TEGRA_TYPE_LIC, 349 .slices = 17, 350}; 351 352static inline u32 tegra_hte_readl(struct tegra_hte_soc *hte, u32 reg) 353{ 354 return readl(hte->regs + reg); 355} 356 357static inline void tegra_hte_writel(struct tegra_hte_soc *hte, u32 reg, 358 u32 val) 359{ 360 writel(val, hte->regs + reg); 361} 362 363static int tegra_hte_map_to_line_id(u32 eid, 364 const struct tegra_hte_line_mapped *m, 365 u32 map_sz, u32 *mapped) 366{ 367 368 if (m) { 369 if (eid >= map_sz) 370 return -EINVAL; 371 if (m[eid].slice == NV_AON_SLICE_INVALID) 372 return -EINVAL; 373 374 *mapped = (m[eid].slice << 5) + m[eid].bit_index; 375 } else { 376 *mapped = eid; 377 } 378 379 return 0; 380} 381 382static int tegra_hte_line_xlate(struct hte_chip *gc, 383 const struct of_phandle_args *args, 384 struct hte_ts_desc *desc, u32 *xlated_id) 385{ 386 int ret = 0; 387 u32 line_id; 388 struct tegra_hte_soc *gs; 389 const struct tegra_hte_line_mapped *map = NULL; 390 u32 map_sz = 0; 391 392 if (!gc || !desc || !xlated_id) 393 return -EINVAL; 394 395 if (args) { 396 if (gc->of_hte_n_cells < 1) 397 return -EINVAL; 398 399 if (args->args_count != gc->of_hte_n_cells) 400 return -EINVAL; 401 402 desc->attr.line_id = args->args[0]; 403 } 404 405 gs = gc->data; 406 if (!gs || !gs->prov_data) 407 return -EINVAL; 408 409 /* 410 * 411 * There are two paths GPIO consumers can take as follows: 412 * 1) The consumer (gpiolib-cdev for example) which uses GPIO global 413 * number which gets assigned run time. 414 * 2) The consumer passing GPIO from the DT which is assigned 415 * statically for example by using TEGRA194_AON_GPIO gpio DT binding. 416 * 417 * The code below addresses both the consumer use cases and maps into 418 * HTE/GTE namespace. 419 */ 420 if (gs->prov_data->type == HTE_TEGRA_TYPE_GPIO && !args) { 421 line_id = desc->attr.line_id - gs->c->base; 422 map = gs->prov_data->map; 423 map_sz = gs->prov_data->map_sz; 424 } else if (gs->prov_data->type == HTE_TEGRA_TYPE_GPIO && args) { 425 line_id = desc->attr.line_id; 426 map = gs->prov_data->sec_map; 427 map_sz = gs->prov_data->sec_map_sz; 428 } else { 429 line_id = desc->attr.line_id; 430 } 431 432 ret = tegra_hte_map_to_line_id(line_id, map, map_sz, xlated_id); 433 if (ret < 0) { 434 dev_err(gc->dev, "line_id:%u mapping failed\n", 435 desc->attr.line_id); 436 return ret; 437 } 438 439 if (*xlated_id > gc->nlines) 440 return -EINVAL; 441 442 dev_dbg(gc->dev, "requested id:%u, xlated id:%u\n", 443 desc->attr.line_id, *xlated_id); 444 445 return 0; 446} 447 448static int tegra_hte_line_xlate_plat(struct hte_chip *gc, 449 struct hte_ts_desc *desc, u32 *xlated_id) 450{ 451 return tegra_hte_line_xlate(gc, NULL, desc, xlated_id); 452} 453 454static int tegra_hte_en_dis_common(struct hte_chip *chip, u32 line_id, bool en) 455{ 456 u32 slice, sl_bit_shift, line_bit, val, reg; 457 struct tegra_hte_soc *gs; 458 459 sl_bit_shift = __builtin_ctz(HTE_SLICE_SIZE); 460 461 if (!chip) 462 return -EINVAL; 463 464 gs = chip->data; 465 466 if (line_id > chip->nlines) { 467 dev_err(chip->dev, 468 "line id: %u is not supported by this controller\n", 469 line_id); 470 return -EINVAL; 471 } 472 473 slice = line_id >> sl_bit_shift; 474 line_bit = line_id & (HTE_SLICE_SIZE - 1); 475 reg = (slice << sl_bit_shift) + HTE_SLICE0_TETEN; 476 477 spin_lock(&gs->sl[slice].s_lock); 478 479 if (test_bit(HTE_SUSPEND, &gs->sl[slice].flags)) { 480 spin_unlock(&gs->sl[slice].s_lock); 481 dev_dbg(chip->dev, "device suspended"); 482 return -EBUSY; 483 } 484 485 val = tegra_hte_readl(gs, reg); 486 if (en) 487 val = val | (1 << line_bit); 488 else 489 val = val & (~(1 << line_bit)); 490 tegra_hte_writel(gs, reg, val); 491 492 spin_unlock(&gs->sl[slice].s_lock); 493 494 dev_dbg(chip->dev, "line: %u, slice %u, line_bit %u, reg:0x%x\n", 495 line_id, slice, line_bit, reg); 496 497 return 0; 498} 499 500static int tegra_hte_enable(struct hte_chip *chip, u32 line_id) 501{ 502 if (!chip) 503 return -EINVAL; 504 505 return tegra_hte_en_dis_common(chip, line_id, true); 506} 507 508static int tegra_hte_disable(struct hte_chip *chip, u32 line_id) 509{ 510 if (!chip) 511 return -EINVAL; 512 513 return tegra_hte_en_dis_common(chip, line_id, false); 514} 515 516static int tegra_hte_request(struct hte_chip *chip, struct hte_ts_desc *desc, 517 u32 line_id) 518{ 519 int ret; 520 struct tegra_hte_soc *gs; 521 struct hte_line_attr *attr; 522 523 if (!chip || !chip->data || !desc) 524 return -EINVAL; 525 526 gs = chip->data; 527 attr = &desc->attr; 528 529 if (gs->prov_data->type == HTE_TEGRA_TYPE_GPIO) { 530 if (!attr->line_data) 531 return -EINVAL; 532 533 ret = gpiod_enable_hw_timestamp_ns(attr->line_data, 534 attr->edge_flags); 535 if (ret) 536 return ret; 537 538 gs->line_data[line_id].data = attr->line_data; 539 gs->line_data[line_id].flags = attr->edge_flags; 540 } 541 542 return tegra_hte_en_dis_common(chip, line_id, true); 543} 544 545static int tegra_hte_release(struct hte_chip *chip, struct hte_ts_desc *desc, 546 u32 line_id) 547{ 548 struct tegra_hte_soc *gs; 549 struct hte_line_attr *attr; 550 int ret; 551 552 if (!chip || !chip->data || !desc) 553 return -EINVAL; 554 555 gs = chip->data; 556 attr = &desc->attr; 557 558 if (gs->prov_data->type == HTE_TEGRA_TYPE_GPIO) { 559 ret = gpiod_disable_hw_timestamp_ns(attr->line_data, 560 gs->line_data[line_id].flags); 561 if (ret) 562 return ret; 563 564 gs->line_data[line_id].data = NULL; 565 gs->line_data[line_id].flags = 0; 566 } 567 568 return tegra_hte_en_dis_common(chip, line_id, false); 569} 570 571static int tegra_hte_clk_src_info(struct hte_chip *chip, 572 struct hte_clk_info *ci) 573{ 574 (void)chip; 575 576 if (!ci) 577 return -EINVAL; 578 579 ci->hz = HTE_TS_CLK_RATE_HZ; 580 ci->type = CLOCK_MONOTONIC; 581 582 return 0; 583} 584 585static int tegra_hte_get_level(struct tegra_hte_soc *gs, u32 line_id) 586{ 587 struct gpio_desc *desc; 588 589 if (gs->prov_data->type == HTE_TEGRA_TYPE_GPIO) { 590 desc = gs->line_data[line_id].data; 591 if (desc) 592 return gpiod_get_raw_value(desc); 593 } 594 595 return -1; 596} 597 598static void tegra_hte_read_fifo(struct tegra_hte_soc *gs) 599{ 600 u32 tsh, tsl, src, pv, cv, acv, slice, bit_index, line_id; 601 u64 tsc; 602 struct hte_ts_data el; 603 604 while ((tegra_hte_readl(gs, HTE_TESTATUS) >> 605 HTE_TESTATUS_OCCUPANCY_SHIFT) & 606 HTE_TESTATUS_OCCUPANCY_MASK) { 607 tsh = tegra_hte_readl(gs, HTE_TETSCH); 608 tsl = tegra_hte_readl(gs, HTE_TETSCL); 609 tsc = (((u64)tsh << 32) | tsl); 610 611 src = tegra_hte_readl(gs, HTE_TESRC); 612 slice = (src >> HTE_TESRC_SLICE_SHIFT) & 613 HTE_TESRC_SLICE_DEFAULT_MASK; 614 615 pv = tegra_hte_readl(gs, HTE_TEPCV); 616 cv = tegra_hte_readl(gs, HTE_TECCV); 617 acv = pv ^ cv; 618 while (acv) { 619 bit_index = __builtin_ctz(acv); 620 line_id = bit_index + (slice << 5); 621 el.tsc = tsc << HTE_TS_NS_SHIFT; 622 el.raw_level = tegra_hte_get_level(gs, line_id); 623 hte_push_ts_ns(gs->chip, line_id, &el); 624 acv &= ~BIT(bit_index); 625 } 626 tegra_hte_writel(gs, HTE_TECMD, HTE_TECMD_CMD_POP); 627 } 628} 629 630static irqreturn_t tegra_hte_isr(int irq, void *dev_id) 631{ 632 struct tegra_hte_soc *gs = dev_id; 633 (void)irq; 634 635 tegra_hte_read_fifo(gs); 636 637 return IRQ_HANDLED; 638} 639 640static bool tegra_hte_match_from_linedata(const struct hte_chip *chip, 641 const struct hte_ts_desc *hdesc) 642{ 643 struct tegra_hte_soc *hte_dev = chip->data; 644 645 if (!hte_dev || (hte_dev->prov_data->type != HTE_TEGRA_TYPE_GPIO)) 646 return false; 647 648 return hte_dev->c == gpiod_to_chip(hdesc->attr.line_data); 649} 650 651static const struct of_device_id tegra_hte_of_match[] = { 652 { .compatible = "nvidia,tegra194-gte-lic", .data = &t194_lic_hte}, 653 { .compatible = "nvidia,tegra194-gte-aon", .data = &t194_aon_hte}, 654 { .compatible = "nvidia,tegra234-gte-lic", .data = &t234_lic_hte}, 655 { .compatible = "nvidia,tegra234-gte-aon", .data = &t234_aon_hte}, 656 { } 657}; 658MODULE_DEVICE_TABLE(of, tegra_hte_of_match); 659 660static const struct hte_ops g_ops = { 661 .request = tegra_hte_request, 662 .release = tegra_hte_release, 663 .enable = tegra_hte_enable, 664 .disable = tegra_hte_disable, 665 .get_clk_src_info = tegra_hte_clk_src_info, 666}; 667 668static void tegra_gte_disable(void *data) 669{ 670 struct platform_device *pdev = data; 671 struct tegra_hte_soc *gs = dev_get_drvdata(&pdev->dev); 672 673 tegra_hte_writel(gs, HTE_TECTRL, 0); 674} 675 676static int tegra_get_gpiochip_from_name(struct gpio_chip *chip, void *data) 677{ 678 return !strcmp(chip->label, data); 679} 680 681static int tegra_gpiochip_match(struct gpio_chip *chip, void *data) 682{ 683 return chip->fwnode == of_node_to_fwnode(data); 684} 685 686static int tegra_hte_probe(struct platform_device *pdev) 687{ 688 int ret; 689 u32 i, slices, val = 0; 690 u32 nlines; 691 struct device *dev; 692 struct tegra_hte_soc *hte_dev; 693 struct hte_chip *gc; 694 struct device_node *gpio_ctrl; 695 696 dev = &pdev->dev; 697 698 hte_dev = devm_kzalloc(dev, sizeof(*hte_dev), GFP_KERNEL); 699 if (!hte_dev) 700 return -ENOMEM; 701 702 gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL); 703 if (!gc) 704 return -ENOMEM; 705 706 dev_set_drvdata(&pdev->dev, hte_dev); 707 hte_dev->prov_data = of_device_get_match_data(&pdev->dev); 708 709 ret = of_property_read_u32(dev->of_node, "nvidia,slices", &slices); 710 if (ret != 0) 711 slices = hte_dev->prov_data->slices; 712 713 dev_dbg(dev, "slices:%d\n", slices); 714 nlines = slices << 5; 715 716 hte_dev->regs = devm_platform_ioremap_resource(pdev, 0); 717 if (IS_ERR(hte_dev->regs)) 718 return PTR_ERR(hte_dev->regs); 719 720 ret = of_property_read_u32(dev->of_node, "nvidia,int-threshold", 721 &hte_dev->itr_thrshld); 722 if (ret != 0) 723 hte_dev->itr_thrshld = 1; 724 725 hte_dev->sl = devm_kcalloc(dev, slices, sizeof(*hte_dev->sl), 726 GFP_KERNEL); 727 if (!hte_dev->sl) 728 return -ENOMEM; 729 730 ret = platform_get_irq(pdev, 0); 731 if (ret < 0) { 732 dev_err_probe(dev, ret, "failed to get irq\n"); 733 return ret; 734 } 735 hte_dev->hte_irq = ret; 736 ret = devm_request_irq(dev, hte_dev->hte_irq, tegra_hte_isr, 0, 737 dev_name(dev), hte_dev); 738 if (ret < 0) { 739 dev_err(dev, "request irq failed.\n"); 740 return ret; 741 } 742 743 gc->nlines = nlines; 744 gc->ops = &g_ops; 745 gc->dev = dev; 746 gc->data = hte_dev; 747 gc->xlate_of = tegra_hte_line_xlate; 748 gc->xlate_plat = tegra_hte_line_xlate_plat; 749 gc->of_hte_n_cells = 1; 750 751 if (hte_dev->prov_data && 752 hte_dev->prov_data->type == HTE_TEGRA_TYPE_GPIO) { 753 hte_dev->line_data = devm_kcalloc(dev, nlines, 754 sizeof(*hte_dev->line_data), 755 GFP_KERNEL); 756 if (!hte_dev->line_data) 757 return -ENOMEM; 758 759 gc->match_from_linedata = tegra_hte_match_from_linedata; 760 761 if (of_device_is_compatible(dev->of_node, 762 "nvidia,tegra194-gte-aon")) { 763 hte_dev->c = gpiochip_find("tegra194-gpio-aon", 764 tegra_get_gpiochip_from_name); 765 } else { 766 gpio_ctrl = of_parse_phandle(dev->of_node, 767 "nvidia,gpio-controller", 768 0); 769 if (!gpio_ctrl) { 770 dev_err(dev, 771 "gpio controller node not found\n"); 772 return -ENODEV; 773 } 774 775 hte_dev->c = gpiochip_find(gpio_ctrl, 776 tegra_gpiochip_match); 777 of_node_put(gpio_ctrl); 778 } 779 780 if (!hte_dev->c) 781 return dev_err_probe(dev, -EPROBE_DEFER, 782 "wait for gpio controller\n"); 783 } 784 785 hte_dev->chip = gc; 786 787 ret = devm_hte_register_chip(hte_dev->chip); 788 if (ret) { 789 dev_err(gc->dev, "hte chip register failed"); 790 return ret; 791 } 792 793 for (i = 0; i < slices; i++) { 794 hte_dev->sl[i].flags = 0; 795 spin_lock_init(&hte_dev->sl[i].s_lock); 796 } 797 798 val = HTE_TECTRL_ENABLE_ENABLE | 799 (HTE_TECTRL_INTR_ENABLE << HTE_TECTRL_INTR_SHIFT) | 800 (hte_dev->itr_thrshld << HTE_TECTRL_OCCU_SHIFT); 801 tegra_hte_writel(hte_dev, HTE_TECTRL, val); 802 803 ret = devm_add_action_or_reset(&pdev->dev, tegra_gte_disable, pdev); 804 if (ret) 805 return ret; 806 807 dev_dbg(gc->dev, "lines: %d, slices:%d", gc->nlines, slices); 808 809 return 0; 810} 811 812static int __maybe_unused tegra_hte_resume_early(struct device *dev) 813{ 814 u32 i; 815 struct tegra_hte_soc *gs = dev_get_drvdata(dev); 816 u32 slices = gs->chip->nlines / NV_LINES_IN_SLICE; 817 u32 sl_bit_shift = __builtin_ctz(HTE_SLICE_SIZE); 818 819 tegra_hte_writel(gs, HTE_TECTRL, gs->conf_rval); 820 821 for (i = 0; i < slices; i++) { 822 spin_lock(&gs->sl[i].s_lock); 823 tegra_hte_writel(gs, 824 ((i << sl_bit_shift) + HTE_SLICE0_TETEN), 825 gs->sl[i].r_val); 826 clear_bit(HTE_SUSPEND, &gs->sl[i].flags); 827 spin_unlock(&gs->sl[i].s_lock); 828 } 829 830 return 0; 831} 832 833static int __maybe_unused tegra_hte_suspend_late(struct device *dev) 834{ 835 u32 i; 836 struct tegra_hte_soc *gs = dev_get_drvdata(dev); 837 u32 slices = gs->chip->nlines / NV_LINES_IN_SLICE; 838 u32 sl_bit_shift = __builtin_ctz(HTE_SLICE_SIZE); 839 840 gs->conf_rval = tegra_hte_readl(gs, HTE_TECTRL); 841 for (i = 0; i < slices; i++) { 842 spin_lock(&gs->sl[i].s_lock); 843 gs->sl[i].r_val = tegra_hte_readl(gs, 844 ((i << sl_bit_shift) + HTE_SLICE0_TETEN)); 845 set_bit(HTE_SUSPEND, &gs->sl[i].flags); 846 spin_unlock(&gs->sl[i].s_lock); 847 } 848 849 return 0; 850} 851 852static const struct dev_pm_ops tegra_hte_pm = { 853 SET_LATE_SYSTEM_SLEEP_PM_OPS(tegra_hte_suspend_late, 854 tegra_hte_resume_early) 855}; 856 857static struct platform_driver tegra_hte_driver = { 858 .probe = tegra_hte_probe, 859 .driver = { 860 .name = "tegra_hte", 861 .pm = &tegra_hte_pm, 862 .of_match_table = tegra_hte_of_match, 863 }, 864}; 865 866module_platform_driver(tegra_hte_driver); 867 868MODULE_AUTHOR("Dipen Patel <dipenp@nvidia.com>"); 869MODULE_DESCRIPTION("NVIDIA Tegra HTE (Hardware Timestamping Engine) driver"); 870MODULE_LICENSE("GPL"); 871