1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de>
4 * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
5 */
6#ifndef __IPU_PRV_H__
7#define __IPU_PRV_H__
8
9struct ipu_soc;
10
11#include <linux/io.h>
12#include <linux/types.h>
13#include <linux/device.h>
14#include <linux/clk.h>
15#include <linux/platform_device.h>
16
17#include <video/imx-ipu-v3.h>
18
19#define IPU_MCU_T_DEFAULT	8
20#define IPU_CM_IDMAC_REG_OFS	0x00008000
21#define IPU_CM_IC_REG_OFS	0x00020000
22#define IPU_CM_IRT_REG_OFS	0x00028000
23#define IPU_CM_CSI0_REG_OFS	0x00030000
24#define IPU_CM_CSI1_REG_OFS	0x00038000
25#define IPU_CM_SMFC_REG_OFS	0x00050000
26#define IPU_CM_DC_REG_OFS	0x00058000
27#define IPU_CM_DMFC_REG_OFS	0x00060000
28
29/* Register addresses */
30/* IPU Common registers */
31#define IPU_CM_REG(offset)	(offset)
32
33#define IPU_CONF			IPU_CM_REG(0)
34
35#define IPU_SRM_PRI1			IPU_CM_REG(0x00a0)
36#define IPU_SRM_PRI2			IPU_CM_REG(0x00a4)
37#define IPU_FS_PROC_FLOW1		IPU_CM_REG(0x00a8)
38#define IPU_FS_PROC_FLOW2		IPU_CM_REG(0x00ac)
39#define IPU_FS_PROC_FLOW3		IPU_CM_REG(0x00b0)
40#define IPU_FS_DISP_FLOW1		IPU_CM_REG(0x00b4)
41#define IPU_FS_DISP_FLOW2		IPU_CM_REG(0x00b8)
42#define IPU_SKIP			IPU_CM_REG(0x00bc)
43#define IPU_DISP_ALT_CONF		IPU_CM_REG(0x00c0)
44#define IPU_DISP_GEN			IPU_CM_REG(0x00c4)
45#define IPU_DISP_ALT1			IPU_CM_REG(0x00c8)
46#define IPU_DISP_ALT2			IPU_CM_REG(0x00cc)
47#define IPU_DISP_ALT3			IPU_CM_REG(0x00d0)
48#define IPU_DISP_ALT4			IPU_CM_REG(0x00d4)
49#define IPU_SNOOP			IPU_CM_REG(0x00d8)
50#define IPU_MEM_RST			IPU_CM_REG(0x00dc)
51#define IPU_PM				IPU_CM_REG(0x00e0)
52#define IPU_GPR				IPU_CM_REG(0x00e4)
53#define IPU_CHA_DB_MODE_SEL(ch)		IPU_CM_REG(0x0150 + 4 * ((ch) / 32))
54#define IPU_ALT_CHA_DB_MODE_SEL(ch)	IPU_CM_REG(0x0168 + 4 * ((ch) / 32))
55#define IPU_CHA_CUR_BUF(ch)		IPU_CM_REG(0x023C + 4 * ((ch) / 32))
56#define IPU_ALT_CUR_BUF0		IPU_CM_REG(0x0244)
57#define IPU_ALT_CUR_BUF1		IPU_CM_REG(0x0248)
58#define IPU_SRM_STAT			IPU_CM_REG(0x024C)
59#define IPU_PROC_TASK_STAT		IPU_CM_REG(0x0250)
60#define IPU_DISP_TASK_STAT		IPU_CM_REG(0x0254)
61#define IPU_CHA_BUF0_RDY(ch)		IPU_CM_REG(0x0268 + 4 * ((ch) / 32))
62#define IPU_CHA_BUF1_RDY(ch)		IPU_CM_REG(0x0270 + 4 * ((ch) / 32))
63#define IPU_CHA_BUF2_RDY(ch)		IPU_CM_REG(0x0288 + 4 * ((ch) / 32))
64#define IPU_ALT_CHA_BUF0_RDY(ch)	IPU_CM_REG(0x0278 + 4 * ((ch) / 32))
65#define IPU_ALT_CHA_BUF1_RDY(ch)	IPU_CM_REG(0x0280 + 4 * ((ch) / 32))
66
67#define IPU_INT_CTRL(n)		IPU_CM_REG(0x003C + 4 * (n))
68#define IPU_INT_STAT(n)		IPU_CM_REG(0x0200 + 4 * (n))
69
70/* SRM_PRI2 */
71#define DP_S_SRM_MODE_MASK		(0x3 << 3)
72#define DP_S_SRM_MODE_NOW		(0x3 << 3)
73#define DP_S_SRM_MODE_NEXT_FRAME	(0x1 << 3)
74
75/* FS_PROC_FLOW1 */
76#define FS_PRPENC_ROT_SRC_SEL_MASK	(0xf << 0)
77#define FS_PRPENC_ROT_SRC_SEL_ENC		(0x7 << 0)
78#define FS_PRPVF_ROT_SRC_SEL_MASK	(0xf << 8)
79#define FS_PRPVF_ROT_SRC_SEL_VF			(0x8 << 8)
80#define FS_PP_SRC_SEL_MASK		(0xf << 12)
81#define FS_PP_ROT_SRC_SEL_MASK		(0xf << 16)
82#define FS_PP_ROT_SRC_SEL_PP			(0x5 << 16)
83#define FS_VDI1_SRC_SEL_MASK		(0x3 << 20)
84#define FS_VDI3_SRC_SEL_MASK		(0x3 << 20)
85#define FS_PRP_SRC_SEL_MASK		(0xf << 24)
86#define FS_VDI_SRC_SEL_MASK		(0x3 << 28)
87#define FS_VDI_SRC_SEL_CSI_DIRECT		(0x1 << 28)
88#define FS_VDI_SRC_SEL_VDOA			(0x2 << 28)
89
90/* FS_PROC_FLOW2 */
91#define FS_PRP_ENC_DEST_SEL_MASK	(0xf << 0)
92#define FS_PRP_ENC_DEST_SEL_IRT_ENC		(0x1 << 0)
93#define FS_PRPVF_DEST_SEL_MASK		(0xf << 4)
94#define FS_PRPVF_DEST_SEL_IRT_VF		(0x1 << 4)
95#define FS_PRPVF_ROT_DEST_SEL_MASK	(0xf << 8)
96#define FS_PP_DEST_SEL_MASK		(0xf << 12)
97#define FS_PP_DEST_SEL_IRT_PP			(0x3 << 12)
98#define FS_PP_ROT_DEST_SEL_MASK		(0xf << 16)
99#define FS_PRPENC_ROT_DEST_SEL_MASK	(0xf << 20)
100#define FS_PRP_DEST_SEL_MASK		(0xf << 24)
101
102#define IPU_DI0_COUNTER_RELEASE			(1 << 24)
103#define IPU_DI1_COUNTER_RELEASE			(1 << 25)
104
105#define IPU_IDMAC_REG(offset)	(offset)
106
107#define IDMAC_CONF			IPU_IDMAC_REG(0x0000)
108#define IDMAC_CHA_EN(ch)		IPU_IDMAC_REG(0x0004 + 4 * ((ch) / 32))
109#define IDMAC_SEP_ALPHA			IPU_IDMAC_REG(0x000c)
110#define IDMAC_ALT_SEP_ALPHA		IPU_IDMAC_REG(0x0010)
111#define IDMAC_CHA_PRI(ch)		IPU_IDMAC_REG(0x0014 + 4 * ((ch) / 32))
112#define IDMAC_WM_EN(ch)			IPU_IDMAC_REG(0x001c + 4 * ((ch) / 32))
113#define IDMAC_CH_LOCK_EN_1		IPU_IDMAC_REG(0x0024)
114#define IDMAC_CH_LOCK_EN_2		IPU_IDMAC_REG(0x0028)
115#define IDMAC_SUB_ADDR_0		IPU_IDMAC_REG(0x002c)
116#define IDMAC_SUB_ADDR_1		IPU_IDMAC_REG(0x0030)
117#define IDMAC_SUB_ADDR_2		IPU_IDMAC_REG(0x0034)
118#define IDMAC_BAND_EN(ch)		IPU_IDMAC_REG(0x0040 + 4 * ((ch) / 32))
119#define IDMAC_CHA_BUSY(ch)		IPU_IDMAC_REG(0x0100 + 4 * ((ch) / 32))
120
121#define IPU_NUM_IRQS	(32 * 15)
122
123enum ipu_modules {
124	IPU_CONF_CSI0_EN		= (1 << 0),
125	IPU_CONF_CSI1_EN		= (1 << 1),
126	IPU_CONF_IC_EN			= (1 << 2),
127	IPU_CONF_ROT_EN			= (1 << 3),
128	IPU_CONF_ISP_EN			= (1 << 4),
129	IPU_CONF_DP_EN			= (1 << 5),
130	IPU_CONF_DI0_EN			= (1 << 6),
131	IPU_CONF_DI1_EN			= (1 << 7),
132	IPU_CONF_SMFC_EN		= (1 << 8),
133	IPU_CONF_DC_EN			= (1 << 9),
134	IPU_CONF_DMFC_EN		= (1 << 10),
135
136	IPU_CONF_VDI_EN			= (1 << 12),
137
138	IPU_CONF_IDMAC_DIS		= (1 << 22),
139
140	IPU_CONF_IC_DMFC_SEL		= (1 << 25),
141	IPU_CONF_IC_DMFC_SYNC		= (1 << 26),
142	IPU_CONF_VDI_DMFC_SYNC		= (1 << 27),
143
144	IPU_CONF_CSI0_DATA_SOURCE	= (1 << 28),
145	IPU_CONF_CSI1_DATA_SOURCE	= (1 << 29),
146	IPU_CONF_IC_INPUT		= (1 << 30),
147	IPU_CONF_CSI_SEL		= (1 << 31),
148};
149
150struct ipuv3_channel {
151	unsigned int num;
152	struct ipu_soc *ipu;
153	struct list_head list;
154};
155
156struct ipu_cpmem;
157struct ipu_csi;
158struct ipu_dc_priv;
159struct ipu_dmfc_priv;
160struct ipu_di;
161struct ipu_ic_priv;
162struct ipu_vdi;
163struct ipu_image_convert_priv;
164struct ipu_smfc_priv;
165struct ipu_pre;
166struct ipu_prg;
167
168struct ipu_devtype;
169
170struct ipu_soc {
171	struct device		*dev;
172	const struct ipu_devtype	*devtype;
173	enum ipuv3_type		ipu_type;
174	spinlock_t		lock;
175	struct mutex		channel_lock;
176	struct list_head	channels;
177
178	void __iomem		*cm_reg;
179	void __iomem		*idmac_reg;
180
181	int			id;
182	int			usecount;
183
184	struct clk		*clk;
185
186	int			irq_sync;
187	int			irq_err;
188	struct irq_domain	*domain;
189
190	struct ipu_cpmem	*cpmem_priv;
191	struct ipu_dc_priv	*dc_priv;
192	struct ipu_dp_priv	*dp_priv;
193	struct ipu_dmfc_priv	*dmfc_priv;
194	struct ipu_di		*di_priv[2];
195	struct ipu_csi		*csi_priv[2];
196	struct ipu_ic_priv	*ic_priv;
197	struct ipu_vdi          *vdi_priv;
198	struct ipu_image_convert_priv *image_convert_priv;
199	struct ipu_smfc_priv	*smfc_priv;
200	struct ipu_prg		*prg_priv;
201};
202
203static inline u32 ipu_idmac_read(struct ipu_soc *ipu, unsigned offset)
204{
205	return readl(ipu->idmac_reg + offset);
206}
207
208static inline void ipu_idmac_write(struct ipu_soc *ipu, u32 value,
209				   unsigned offset)
210{
211	writel(value, ipu->idmac_reg + offset);
212}
213
214void ipu_srm_dp_update(struct ipu_soc *ipu, bool sync);
215
216int ipu_module_enable(struct ipu_soc *ipu, u32 mask);
217int ipu_module_disable(struct ipu_soc *ipu, u32 mask);
218
219bool ipu_idmac_channel_busy(struct ipu_soc *ipu, unsigned int chno);
220
221int ipu_csi_init(struct ipu_soc *ipu, struct device *dev, int id,
222		 unsigned long base, u32 module, struct clk *clk_ipu);
223void ipu_csi_exit(struct ipu_soc *ipu, int id);
224
225int ipu_ic_init(struct ipu_soc *ipu, struct device *dev,
226		unsigned long base, unsigned long tpmem_base);
227void ipu_ic_exit(struct ipu_soc *ipu);
228
229int ipu_vdi_init(struct ipu_soc *ipu, struct device *dev,
230		 unsigned long base, u32 module);
231void ipu_vdi_exit(struct ipu_soc *ipu);
232
233int ipu_image_convert_init(struct ipu_soc *ipu, struct device *dev);
234void ipu_image_convert_exit(struct ipu_soc *ipu);
235
236int ipu_di_init(struct ipu_soc *ipu, struct device *dev, int id,
237		unsigned long base, u32 module, struct clk *ipu_clk);
238void ipu_di_exit(struct ipu_soc *ipu, int id);
239
240int ipu_dmfc_init(struct ipu_soc *ipu, struct device *dev, unsigned long base,
241		struct clk *ipu_clk);
242void ipu_dmfc_exit(struct ipu_soc *ipu);
243
244int ipu_dp_init(struct ipu_soc *ipu, struct device *dev, unsigned long base);
245void ipu_dp_exit(struct ipu_soc *ipu);
246
247int ipu_dc_init(struct ipu_soc *ipu, struct device *dev, unsigned long base,
248		unsigned long template_base);
249void ipu_dc_exit(struct ipu_soc *ipu);
250
251int ipu_cpmem_init(struct ipu_soc *ipu, struct device *dev, unsigned long base);
252void ipu_cpmem_exit(struct ipu_soc *ipu);
253
254int ipu_smfc_init(struct ipu_soc *ipu, struct device *dev, unsigned long base);
255void ipu_smfc_exit(struct ipu_soc *ipu);
256
257struct ipu_pre *ipu_pre_lookup_by_phandle(struct device *dev, const char *name,
258					  int index);
259int ipu_pre_get_available_count(void);
260int ipu_pre_get(struct ipu_pre *pre);
261void ipu_pre_put(struct ipu_pre *pre);
262u32 ipu_pre_get_baddr(struct ipu_pre *pre);
263void ipu_pre_configure(struct ipu_pre *pre, unsigned int width,
264		       unsigned int height, unsigned int stride, u32 format,
265		       uint64_t modifier, unsigned int bufaddr);
266void ipu_pre_update(struct ipu_pre *pre, unsigned int bufaddr);
267bool ipu_pre_update_pending(struct ipu_pre *pre);
268
269struct ipu_prg *ipu_prg_lookup_by_phandle(struct device *dev, const char *name,
270					  int ipu_id);
271
272extern struct platform_driver ipu_pre_drv;
273extern struct platform_driver ipu_prg_drv;
274
275#endif				/* __IPU_PRV_H__ */
276