1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (C) 2013 NVIDIA Corporation 4 */ 5 6#include <linux/clk.h> 7#include <linux/debugfs.h> 8#include <linux/delay.h> 9#include <linux/host1x.h> 10#include <linux/module.h> 11#include <linux/of.h> 12#include <linux/of_platform.h> 13#include <linux/platform_device.h> 14#include <linux/pm_runtime.h> 15#include <linux/regulator/consumer.h> 16#include <linux/reset.h> 17 18#include <video/mipi_display.h> 19 20#include <drm/drm_atomic_helper.h> 21#include <drm/drm_debugfs.h> 22#include <drm/drm_file.h> 23#include <drm/drm_mipi_dsi.h> 24#include <drm/drm_panel.h> 25#include <drm/drm_simple_kms_helper.h> 26 27#include "dc.h" 28#include "drm.h" 29#include "dsi.h" 30#include "mipi-phy.h" 31#include "trace.h" 32 33struct tegra_dsi_state { 34 struct drm_connector_state base; 35 36 struct mipi_dphy_timing timing; 37 unsigned long period; 38 39 unsigned int vrefresh; 40 unsigned int lanes; 41 unsigned long pclk; 42 unsigned long bclk; 43 44 enum tegra_dsi_format format; 45 unsigned int mul; 46 unsigned int div; 47}; 48 49static inline struct tegra_dsi_state * 50to_dsi_state(struct drm_connector_state *state) 51{ 52 return container_of(state, struct tegra_dsi_state, base); 53} 54 55struct tegra_dsi { 56 struct host1x_client client; 57 struct tegra_output output; 58 struct device *dev; 59 60 void __iomem *regs; 61 62 struct reset_control *rst; 63 struct clk *clk_parent; 64 struct clk *clk_lp; 65 struct clk *clk; 66 67 struct drm_info_list *debugfs_files; 68 69 unsigned long flags; 70 enum mipi_dsi_pixel_format format; 71 unsigned int lanes; 72 73 struct tegra_mipi_device *mipi; 74 struct mipi_dsi_host host; 75 76 struct regulator *vdd; 77 78 unsigned int video_fifo_depth; 79 unsigned int host_fifo_depth; 80 81 /* for ganged-mode support */ 82 struct tegra_dsi *master; 83 struct tegra_dsi *slave; 84}; 85 86static inline struct tegra_dsi * 87host1x_client_to_dsi(struct host1x_client *client) 88{ 89 return container_of(client, struct tegra_dsi, client); 90} 91 92static inline struct tegra_dsi *host_to_tegra(struct mipi_dsi_host *host) 93{ 94 return container_of(host, struct tegra_dsi, host); 95} 96 97static inline struct tegra_dsi *to_dsi(struct tegra_output *output) 98{ 99 return container_of(output, struct tegra_dsi, output); 100} 101 102static struct tegra_dsi_state *tegra_dsi_get_state(struct tegra_dsi *dsi) 103{ 104 return to_dsi_state(dsi->output.connector.state); 105} 106 107static inline u32 tegra_dsi_readl(struct tegra_dsi *dsi, unsigned int offset) 108{ 109 u32 value = readl(dsi->regs + (offset << 2)); 110 111 trace_dsi_readl(dsi->dev, offset, value); 112 113 return value; 114} 115 116static inline void tegra_dsi_writel(struct tegra_dsi *dsi, u32 value, 117 unsigned int offset) 118{ 119 trace_dsi_writel(dsi->dev, offset, value); 120 writel(value, dsi->regs + (offset << 2)); 121} 122 123#define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name } 124 125static const struct debugfs_reg32 tegra_dsi_regs[] = { 126 DEBUGFS_REG32(DSI_INCR_SYNCPT), 127 DEBUGFS_REG32(DSI_INCR_SYNCPT_CONTROL), 128 DEBUGFS_REG32(DSI_INCR_SYNCPT_ERROR), 129 DEBUGFS_REG32(DSI_CTXSW), 130 DEBUGFS_REG32(DSI_RD_DATA), 131 DEBUGFS_REG32(DSI_WR_DATA), 132 DEBUGFS_REG32(DSI_POWER_CONTROL), 133 DEBUGFS_REG32(DSI_INT_ENABLE), 134 DEBUGFS_REG32(DSI_INT_STATUS), 135 DEBUGFS_REG32(DSI_INT_MASK), 136 DEBUGFS_REG32(DSI_HOST_CONTROL), 137 DEBUGFS_REG32(DSI_CONTROL), 138 DEBUGFS_REG32(DSI_SOL_DELAY), 139 DEBUGFS_REG32(DSI_MAX_THRESHOLD), 140 DEBUGFS_REG32(DSI_TRIGGER), 141 DEBUGFS_REG32(DSI_TX_CRC), 142 DEBUGFS_REG32(DSI_STATUS), 143 DEBUGFS_REG32(DSI_INIT_SEQ_CONTROL), 144 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_0), 145 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_1), 146 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_2), 147 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_3), 148 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_4), 149 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_5), 150 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_6), 151 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_7), 152 DEBUGFS_REG32(DSI_PKT_SEQ_0_LO), 153 DEBUGFS_REG32(DSI_PKT_SEQ_0_HI), 154 DEBUGFS_REG32(DSI_PKT_SEQ_1_LO), 155 DEBUGFS_REG32(DSI_PKT_SEQ_1_HI), 156 DEBUGFS_REG32(DSI_PKT_SEQ_2_LO), 157 DEBUGFS_REG32(DSI_PKT_SEQ_2_HI), 158 DEBUGFS_REG32(DSI_PKT_SEQ_3_LO), 159 DEBUGFS_REG32(DSI_PKT_SEQ_3_HI), 160 DEBUGFS_REG32(DSI_PKT_SEQ_4_LO), 161 DEBUGFS_REG32(DSI_PKT_SEQ_4_HI), 162 DEBUGFS_REG32(DSI_PKT_SEQ_5_LO), 163 DEBUGFS_REG32(DSI_PKT_SEQ_5_HI), 164 DEBUGFS_REG32(DSI_DCS_CMDS), 165 DEBUGFS_REG32(DSI_PKT_LEN_0_1), 166 DEBUGFS_REG32(DSI_PKT_LEN_2_3), 167 DEBUGFS_REG32(DSI_PKT_LEN_4_5), 168 DEBUGFS_REG32(DSI_PKT_LEN_6_7), 169 DEBUGFS_REG32(DSI_PHY_TIMING_0), 170 DEBUGFS_REG32(DSI_PHY_TIMING_1), 171 DEBUGFS_REG32(DSI_PHY_TIMING_2), 172 DEBUGFS_REG32(DSI_BTA_TIMING), 173 DEBUGFS_REG32(DSI_TIMEOUT_0), 174 DEBUGFS_REG32(DSI_TIMEOUT_1), 175 DEBUGFS_REG32(DSI_TO_TALLY), 176 DEBUGFS_REG32(DSI_PAD_CONTROL_0), 177 DEBUGFS_REG32(DSI_PAD_CONTROL_CD), 178 DEBUGFS_REG32(DSI_PAD_CD_STATUS), 179 DEBUGFS_REG32(DSI_VIDEO_MODE_CONTROL), 180 DEBUGFS_REG32(DSI_PAD_CONTROL_1), 181 DEBUGFS_REG32(DSI_PAD_CONTROL_2), 182 DEBUGFS_REG32(DSI_PAD_CONTROL_3), 183 DEBUGFS_REG32(DSI_PAD_CONTROL_4), 184 DEBUGFS_REG32(DSI_GANGED_MODE_CONTROL), 185 DEBUGFS_REG32(DSI_GANGED_MODE_START), 186 DEBUGFS_REG32(DSI_GANGED_MODE_SIZE), 187 DEBUGFS_REG32(DSI_RAW_DATA_BYTE_COUNT), 188 DEBUGFS_REG32(DSI_ULTRA_LOW_POWER_CONTROL), 189 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_8), 190 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_9), 191 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_10), 192 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_11), 193 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_12), 194 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_13), 195 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_14), 196 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_15), 197}; 198 199static int tegra_dsi_show_regs(struct seq_file *s, void *data) 200{ 201 struct drm_info_node *node = s->private; 202 struct tegra_dsi *dsi = node->info_ent->data; 203 struct drm_crtc *crtc = dsi->output.encoder.crtc; 204 struct drm_device *drm = node->minor->dev; 205 unsigned int i; 206 int err = 0; 207 208 drm_modeset_lock_all(drm); 209 210 if (!crtc || !crtc->state->active) { 211 err = -EBUSY; 212 goto unlock; 213 } 214 215 for (i = 0; i < ARRAY_SIZE(tegra_dsi_regs); i++) { 216 unsigned int offset = tegra_dsi_regs[i].offset; 217 218 seq_printf(s, "%-32s %#05x %08x\n", tegra_dsi_regs[i].name, 219 offset, tegra_dsi_readl(dsi, offset)); 220 } 221 222unlock: 223 drm_modeset_unlock_all(drm); 224 return err; 225} 226 227static struct drm_info_list debugfs_files[] = { 228 { "regs", tegra_dsi_show_regs, 0, NULL }, 229}; 230 231static int tegra_dsi_late_register(struct drm_connector *connector) 232{ 233 struct tegra_output *output = connector_to_output(connector); 234 unsigned int i, count = ARRAY_SIZE(debugfs_files); 235 struct drm_minor *minor = connector->dev->primary; 236 struct dentry *root = connector->debugfs_entry; 237 struct tegra_dsi *dsi = to_dsi(output); 238 239 dsi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), 240 GFP_KERNEL); 241 if (!dsi->debugfs_files) 242 return -ENOMEM; 243 244 for (i = 0; i < count; i++) 245 dsi->debugfs_files[i].data = dsi; 246 247 drm_debugfs_create_files(dsi->debugfs_files, count, root, minor); 248 249 return 0; 250} 251 252static void tegra_dsi_early_unregister(struct drm_connector *connector) 253{ 254 struct tegra_output *output = connector_to_output(connector); 255 unsigned int count = ARRAY_SIZE(debugfs_files); 256 struct tegra_dsi *dsi = to_dsi(output); 257 258 drm_debugfs_remove_files(dsi->debugfs_files, count, 259 connector->dev->primary); 260 kfree(dsi->debugfs_files); 261 dsi->debugfs_files = NULL; 262} 263 264#define PKT_ID0(id) ((((id) & 0x3f) << 3) | (1 << 9)) 265#define PKT_LEN0(len) (((len) & 0x07) << 0) 266#define PKT_ID1(id) ((((id) & 0x3f) << 13) | (1 << 19)) 267#define PKT_LEN1(len) (((len) & 0x07) << 10) 268#define PKT_ID2(id) ((((id) & 0x3f) << 23) | (1 << 29)) 269#define PKT_LEN2(len) (((len) & 0x07) << 20) 270 271#define PKT_LP (1 << 30) 272#define NUM_PKT_SEQ 12 273 274/* 275 * non-burst mode with sync pulses 276 */ 277static const u32 pkt_seq_video_non_burst_sync_pulses[NUM_PKT_SEQ] = { 278 [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) | 279 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) | 280 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) | 281 PKT_LP, 282 [ 1] = 0, 283 [ 2] = PKT_ID0(MIPI_DSI_V_SYNC_END) | PKT_LEN0(0) | 284 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) | 285 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) | 286 PKT_LP, 287 [ 3] = 0, 288 [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | 289 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) | 290 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) | 291 PKT_LP, 292 [ 5] = 0, 293 [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | 294 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) | 295 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0), 296 [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) | 297 PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) | 298 PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4), 299 [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | 300 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) | 301 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) | 302 PKT_LP, 303 [ 9] = 0, 304 [10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | 305 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) | 306 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0), 307 [11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) | 308 PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) | 309 PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4), 310}; 311 312/* 313 * non-burst mode with sync events 314 */ 315static const u32 pkt_seq_video_non_burst_sync_events[NUM_PKT_SEQ] = { 316 [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) | 317 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) | 318 PKT_LP, 319 [ 1] = 0, 320 [ 2] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | 321 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) | 322 PKT_LP, 323 [ 3] = 0, 324 [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | 325 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) | 326 PKT_LP, 327 [ 5] = 0, 328 [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | 329 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) | 330 PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3), 331 [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4), 332 [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | 333 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) | 334 PKT_LP, 335 [ 9] = 0, 336 [10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | 337 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) | 338 PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3), 339 [11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4), 340}; 341 342static const u32 pkt_seq_command_mode[NUM_PKT_SEQ] = { 343 [ 0] = 0, 344 [ 1] = 0, 345 [ 2] = 0, 346 [ 3] = 0, 347 [ 4] = 0, 348 [ 5] = 0, 349 [ 6] = PKT_ID0(MIPI_DSI_DCS_LONG_WRITE) | PKT_LEN0(3) | PKT_LP, 350 [ 7] = 0, 351 [ 8] = 0, 352 [ 9] = 0, 353 [10] = PKT_ID0(MIPI_DSI_DCS_LONG_WRITE) | PKT_LEN0(5) | PKT_LP, 354 [11] = 0, 355}; 356 357static void tegra_dsi_set_phy_timing(struct tegra_dsi *dsi, 358 unsigned long period, 359 const struct mipi_dphy_timing *timing) 360{ 361 u32 value; 362 363 value = DSI_TIMING_FIELD(timing->hsexit, period, 1) << 24 | 364 DSI_TIMING_FIELD(timing->hstrail, period, 0) << 16 | 365 DSI_TIMING_FIELD(timing->hszero, period, 3) << 8 | 366 DSI_TIMING_FIELD(timing->hsprepare, period, 1); 367 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_0); 368 369 value = DSI_TIMING_FIELD(timing->clktrail, period, 1) << 24 | 370 DSI_TIMING_FIELD(timing->clkpost, period, 1) << 16 | 371 DSI_TIMING_FIELD(timing->clkzero, period, 1) << 8 | 372 DSI_TIMING_FIELD(timing->lpx, period, 1); 373 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_1); 374 375 value = DSI_TIMING_FIELD(timing->clkprepare, period, 1) << 16 | 376 DSI_TIMING_FIELD(timing->clkpre, period, 1) << 8 | 377 DSI_TIMING_FIELD(0xff * period, period, 0) << 0; 378 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_2); 379 380 value = DSI_TIMING_FIELD(timing->taget, period, 1) << 16 | 381 DSI_TIMING_FIELD(timing->tasure, period, 1) << 8 | 382 DSI_TIMING_FIELD(timing->tago, period, 1); 383 tegra_dsi_writel(dsi, value, DSI_BTA_TIMING); 384 385 if (dsi->slave) 386 tegra_dsi_set_phy_timing(dsi->slave, period, timing); 387} 388 389static int tegra_dsi_get_muldiv(enum mipi_dsi_pixel_format format, 390 unsigned int *mulp, unsigned int *divp) 391{ 392 switch (format) { 393 case MIPI_DSI_FMT_RGB666_PACKED: 394 case MIPI_DSI_FMT_RGB888: 395 *mulp = 3; 396 *divp = 1; 397 break; 398 399 case MIPI_DSI_FMT_RGB565: 400 *mulp = 2; 401 *divp = 1; 402 break; 403 404 case MIPI_DSI_FMT_RGB666: 405 *mulp = 9; 406 *divp = 4; 407 break; 408 409 default: 410 return -EINVAL; 411 } 412 413 return 0; 414} 415 416static int tegra_dsi_get_format(enum mipi_dsi_pixel_format format, 417 enum tegra_dsi_format *fmt) 418{ 419 switch (format) { 420 case MIPI_DSI_FMT_RGB888: 421 *fmt = TEGRA_DSI_FORMAT_24P; 422 break; 423 424 case MIPI_DSI_FMT_RGB666: 425 *fmt = TEGRA_DSI_FORMAT_18NP; 426 break; 427 428 case MIPI_DSI_FMT_RGB666_PACKED: 429 *fmt = TEGRA_DSI_FORMAT_18P; 430 break; 431 432 case MIPI_DSI_FMT_RGB565: 433 *fmt = TEGRA_DSI_FORMAT_16P; 434 break; 435 436 default: 437 return -EINVAL; 438 } 439 440 return 0; 441} 442 443static void tegra_dsi_ganged_enable(struct tegra_dsi *dsi, unsigned int start, 444 unsigned int size) 445{ 446 u32 value; 447 448 tegra_dsi_writel(dsi, start, DSI_GANGED_MODE_START); 449 tegra_dsi_writel(dsi, size << 16 | size, DSI_GANGED_MODE_SIZE); 450 451 value = DSI_GANGED_MODE_CONTROL_ENABLE; 452 tegra_dsi_writel(dsi, value, DSI_GANGED_MODE_CONTROL); 453} 454 455static void tegra_dsi_enable(struct tegra_dsi *dsi) 456{ 457 u32 value; 458 459 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL); 460 value |= DSI_POWER_CONTROL_ENABLE; 461 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL); 462 463 if (dsi->slave) 464 tegra_dsi_enable(dsi->slave); 465} 466 467static unsigned int tegra_dsi_get_lanes(struct tegra_dsi *dsi) 468{ 469 if (dsi->master) 470 return dsi->master->lanes + dsi->lanes; 471 472 if (dsi->slave) 473 return dsi->lanes + dsi->slave->lanes; 474 475 return dsi->lanes; 476} 477 478static void tegra_dsi_configure(struct tegra_dsi *dsi, unsigned int pipe, 479 const struct drm_display_mode *mode) 480{ 481 unsigned int hact, hsw, hbp, hfp, i, mul, div; 482 struct tegra_dsi_state *state; 483 const u32 *pkt_seq; 484 u32 value; 485 486 /* XXX: pass in state into this function? */ 487 if (dsi->master) 488 state = tegra_dsi_get_state(dsi->master); 489 else 490 state = tegra_dsi_get_state(dsi); 491 492 mul = state->mul; 493 div = state->div; 494 495 if (dsi->flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) { 496 DRM_DEBUG_KMS("Non-burst video mode with sync pulses\n"); 497 pkt_seq = pkt_seq_video_non_burst_sync_pulses; 498 } else if (dsi->flags & MIPI_DSI_MODE_VIDEO) { 499 DRM_DEBUG_KMS("Non-burst video mode with sync events\n"); 500 pkt_seq = pkt_seq_video_non_burst_sync_events; 501 } else { 502 DRM_DEBUG_KMS("Command mode\n"); 503 pkt_seq = pkt_seq_command_mode; 504 } 505 506 value = DSI_CONTROL_CHANNEL(0) | 507 DSI_CONTROL_FORMAT(state->format) | 508 DSI_CONTROL_LANES(dsi->lanes - 1) | 509 DSI_CONTROL_SOURCE(pipe); 510 tegra_dsi_writel(dsi, value, DSI_CONTROL); 511 512 tegra_dsi_writel(dsi, dsi->video_fifo_depth, DSI_MAX_THRESHOLD); 513 514 value = DSI_HOST_CONTROL_HS; 515 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL); 516 517 value = tegra_dsi_readl(dsi, DSI_CONTROL); 518 519 if (dsi->flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) 520 value |= DSI_CONTROL_HS_CLK_CTRL; 521 522 value &= ~DSI_CONTROL_TX_TRIG(3); 523 524 /* enable DCS commands for command mode */ 525 if (dsi->flags & MIPI_DSI_MODE_VIDEO) 526 value &= ~DSI_CONTROL_DCS_ENABLE; 527 else 528 value |= DSI_CONTROL_DCS_ENABLE; 529 530 value |= DSI_CONTROL_VIDEO_ENABLE; 531 value &= ~DSI_CONTROL_HOST_ENABLE; 532 tegra_dsi_writel(dsi, value, DSI_CONTROL); 533 534 for (i = 0; i < NUM_PKT_SEQ; i++) 535 tegra_dsi_writel(dsi, pkt_seq[i], DSI_PKT_SEQ_0_LO + i); 536 537 if (dsi->flags & MIPI_DSI_MODE_VIDEO) { 538 /* horizontal active pixels */ 539 hact = mode->hdisplay * mul / div; 540 541 /* horizontal sync width */ 542 hsw = (mode->hsync_end - mode->hsync_start) * mul / div; 543 544 /* horizontal back porch */ 545 hbp = (mode->htotal - mode->hsync_end) * mul / div; 546 547 if ((dsi->flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) == 0) 548 hbp += hsw; 549 550 /* horizontal front porch */ 551 hfp = (mode->hsync_start - mode->hdisplay) * mul / div; 552 553 /* subtract packet overhead */ 554 hsw -= 10; 555 hbp -= 14; 556 hfp -= 8; 557 558 tegra_dsi_writel(dsi, hsw << 16 | 0, DSI_PKT_LEN_0_1); 559 tegra_dsi_writel(dsi, hact << 16 | hbp, DSI_PKT_LEN_2_3); 560 tegra_dsi_writel(dsi, hfp, DSI_PKT_LEN_4_5); 561 tegra_dsi_writel(dsi, 0x0f0f << 16, DSI_PKT_LEN_6_7); 562 563 /* set SOL delay (for non-burst mode only) */ 564 tegra_dsi_writel(dsi, 8 * mul / div, DSI_SOL_DELAY); 565 566 /* TODO: implement ganged mode */ 567 } else { 568 u16 bytes; 569 570 if (dsi->master || dsi->slave) { 571 /* 572 * For ganged mode, assume symmetric left-right mode. 573 */ 574 bytes = 1 + (mode->hdisplay / 2) * mul / div; 575 } else { 576 /* 1 byte (DCS command) + pixel data */ 577 bytes = 1 + mode->hdisplay * mul / div; 578 } 579 580 tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_0_1); 581 tegra_dsi_writel(dsi, bytes << 16, DSI_PKT_LEN_2_3); 582 tegra_dsi_writel(dsi, bytes << 16, DSI_PKT_LEN_4_5); 583 tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_6_7); 584 585 value = MIPI_DCS_WRITE_MEMORY_START << 8 | 586 MIPI_DCS_WRITE_MEMORY_CONTINUE; 587 tegra_dsi_writel(dsi, value, DSI_DCS_CMDS); 588 589 /* set SOL delay */ 590 if (dsi->master || dsi->slave) { 591 unsigned long delay, bclk, bclk_ganged; 592 unsigned int lanes = state->lanes; 593 594 /* SOL to valid, valid to FIFO and FIFO write delay */ 595 delay = 4 + 4 + 2; 596 delay = DIV_ROUND_UP(delay * mul, div * lanes); 597 /* FIFO read delay */ 598 delay = delay + 6; 599 600 bclk = DIV_ROUND_UP(mode->htotal * mul, div * lanes); 601 bclk_ganged = DIV_ROUND_UP(bclk * lanes / 2, lanes); 602 value = bclk - bclk_ganged + delay + 20; 603 } else { 604 /* TODO: revisit for non-ganged mode */ 605 value = 8 * mul / div; 606 } 607 608 tegra_dsi_writel(dsi, value, DSI_SOL_DELAY); 609 } 610 611 if (dsi->slave) { 612 tegra_dsi_configure(dsi->slave, pipe, mode); 613 614 /* 615 * TODO: Support modes other than symmetrical left-right 616 * split. 617 */ 618 tegra_dsi_ganged_enable(dsi, 0, mode->hdisplay / 2); 619 tegra_dsi_ganged_enable(dsi->slave, mode->hdisplay / 2, 620 mode->hdisplay / 2); 621 } 622} 623 624static int tegra_dsi_wait_idle(struct tegra_dsi *dsi, unsigned long timeout) 625{ 626 u32 value; 627 628 timeout = jiffies + msecs_to_jiffies(timeout); 629 630 while (time_before(jiffies, timeout)) { 631 value = tegra_dsi_readl(dsi, DSI_STATUS); 632 if (value & DSI_STATUS_IDLE) 633 return 0; 634 635 usleep_range(1000, 2000); 636 } 637 638 return -ETIMEDOUT; 639} 640 641static void tegra_dsi_video_disable(struct tegra_dsi *dsi) 642{ 643 u32 value; 644 645 value = tegra_dsi_readl(dsi, DSI_CONTROL); 646 value &= ~DSI_CONTROL_VIDEO_ENABLE; 647 tegra_dsi_writel(dsi, value, DSI_CONTROL); 648 649 if (dsi->slave) 650 tegra_dsi_video_disable(dsi->slave); 651} 652 653static void tegra_dsi_ganged_disable(struct tegra_dsi *dsi) 654{ 655 tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_START); 656 tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_SIZE); 657 tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_CONTROL); 658} 659 660static int tegra_dsi_pad_enable(struct tegra_dsi *dsi) 661{ 662 u32 value; 663 664 value = DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0); 665 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0); 666 667 return 0; 668} 669 670static int tegra_dsi_pad_calibrate(struct tegra_dsi *dsi) 671{ 672 u32 value; 673 int err; 674 675 /* 676 * XXX Is this still needed? The module reset is deasserted right 677 * before this function is called. 678 */ 679 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_0); 680 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_1); 681 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_2); 682 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_3); 683 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_4); 684 685 /* start calibration */ 686 tegra_dsi_pad_enable(dsi); 687 688 value = DSI_PAD_SLEW_UP(0x7) | DSI_PAD_SLEW_DN(0x7) | 689 DSI_PAD_LP_UP(0x1) | DSI_PAD_LP_DN(0x1) | 690 DSI_PAD_OUT_CLK(0x0); 691 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_2); 692 693 value = DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) | 694 DSI_PAD_PREEMP_PD(0x03) | DSI_PAD_PREEMP_PU(0x3); 695 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_3); 696 697 err = tegra_mipi_start_calibration(dsi->mipi); 698 if (err < 0) 699 return err; 700 701 return tegra_mipi_finish_calibration(dsi->mipi); 702} 703 704static void tegra_dsi_set_timeout(struct tegra_dsi *dsi, unsigned long bclk, 705 unsigned int vrefresh) 706{ 707 unsigned int timeout; 708 u32 value; 709 710 /* one frame high-speed transmission timeout */ 711 timeout = (bclk / vrefresh) / 512; 712 value = DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(timeout); 713 tegra_dsi_writel(dsi, value, DSI_TIMEOUT_0); 714 715 /* 2 ms peripheral timeout for panel */ 716 timeout = 2 * bclk / 512 * 1000; 717 value = DSI_TIMEOUT_PR(timeout) | DSI_TIMEOUT_TA(0x2000); 718 tegra_dsi_writel(dsi, value, DSI_TIMEOUT_1); 719 720 value = DSI_TALLY_TA(0) | DSI_TALLY_LRX(0) | DSI_TALLY_HTX(0); 721 tegra_dsi_writel(dsi, value, DSI_TO_TALLY); 722 723 if (dsi->slave) 724 tegra_dsi_set_timeout(dsi->slave, bclk, vrefresh); 725} 726 727static void tegra_dsi_disable(struct tegra_dsi *dsi) 728{ 729 u32 value; 730 731 if (dsi->slave) { 732 tegra_dsi_ganged_disable(dsi->slave); 733 tegra_dsi_ganged_disable(dsi); 734 } 735 736 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL); 737 value &= ~DSI_POWER_CONTROL_ENABLE; 738 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL); 739 740 if (dsi->slave) 741 tegra_dsi_disable(dsi->slave); 742 743 usleep_range(5000, 10000); 744} 745 746static void tegra_dsi_soft_reset(struct tegra_dsi *dsi) 747{ 748 u32 value; 749 750 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL); 751 value &= ~DSI_POWER_CONTROL_ENABLE; 752 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL); 753 754 usleep_range(300, 1000); 755 756 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL); 757 value |= DSI_POWER_CONTROL_ENABLE; 758 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL); 759 760 usleep_range(300, 1000); 761 762 value = tegra_dsi_readl(dsi, DSI_TRIGGER); 763 if (value) 764 tegra_dsi_writel(dsi, 0, DSI_TRIGGER); 765 766 if (dsi->slave) 767 tegra_dsi_soft_reset(dsi->slave); 768} 769 770static void tegra_dsi_connector_reset(struct drm_connector *connector) 771{ 772 struct tegra_dsi_state *state = kzalloc(sizeof(*state), GFP_KERNEL); 773 774 if (!state) 775 return; 776 777 if (connector->state) { 778 __drm_atomic_helper_connector_destroy_state(connector->state); 779 kfree(connector->state); 780 } 781 782 __drm_atomic_helper_connector_reset(connector, &state->base); 783} 784 785static struct drm_connector_state * 786tegra_dsi_connector_duplicate_state(struct drm_connector *connector) 787{ 788 struct tegra_dsi_state *state = to_dsi_state(connector->state); 789 struct tegra_dsi_state *copy; 790 791 copy = kmemdup(state, sizeof(*state), GFP_KERNEL); 792 if (!copy) 793 return NULL; 794 795 __drm_atomic_helper_connector_duplicate_state(connector, 796 ©->base); 797 798 return ©->base; 799} 800 801static const struct drm_connector_funcs tegra_dsi_connector_funcs = { 802 .reset = tegra_dsi_connector_reset, 803 .detect = tegra_output_connector_detect, 804 .fill_modes = drm_helper_probe_single_connector_modes, 805 .destroy = tegra_output_connector_destroy, 806 .atomic_duplicate_state = tegra_dsi_connector_duplicate_state, 807 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 808 .late_register = tegra_dsi_late_register, 809 .early_unregister = tegra_dsi_early_unregister, 810}; 811 812static enum drm_mode_status 813tegra_dsi_connector_mode_valid(struct drm_connector *connector, 814 struct drm_display_mode *mode) 815{ 816 return MODE_OK; 817} 818 819static const struct drm_connector_helper_funcs tegra_dsi_connector_helper_funcs = { 820 .get_modes = tegra_output_connector_get_modes, 821 .mode_valid = tegra_dsi_connector_mode_valid, 822}; 823 824static void tegra_dsi_unprepare(struct tegra_dsi *dsi) 825{ 826 int err; 827 828 if (dsi->slave) 829 tegra_dsi_unprepare(dsi->slave); 830 831 err = tegra_mipi_disable(dsi->mipi); 832 if (err < 0) 833 dev_err(dsi->dev, "failed to disable MIPI calibration: %d\n", 834 err); 835 836 err = host1x_client_suspend(&dsi->client); 837 if (err < 0) 838 dev_err(dsi->dev, "failed to suspend: %d\n", err); 839} 840 841static void tegra_dsi_encoder_disable(struct drm_encoder *encoder) 842{ 843 struct tegra_output *output = encoder_to_output(encoder); 844 struct tegra_dc *dc = to_tegra_dc(encoder->crtc); 845 struct tegra_dsi *dsi = to_dsi(output); 846 u32 value; 847 int err; 848 849 if (output->panel) 850 drm_panel_disable(output->panel); 851 852 tegra_dsi_video_disable(dsi); 853 854 /* 855 * The following accesses registers of the display controller, so make 856 * sure it's only executed when the output is attached to one. 857 */ 858 if (dc) { 859 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 860 value &= ~DSI_ENABLE; 861 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 862 863 tegra_dc_commit(dc); 864 } 865 866 err = tegra_dsi_wait_idle(dsi, 100); 867 if (err < 0) 868 dev_dbg(dsi->dev, "failed to idle DSI: %d\n", err); 869 870 tegra_dsi_soft_reset(dsi); 871 872 if (output->panel) 873 drm_panel_unprepare(output->panel); 874 875 tegra_dsi_disable(dsi); 876 877 tegra_dsi_unprepare(dsi); 878} 879 880static int tegra_dsi_prepare(struct tegra_dsi *dsi) 881{ 882 int err; 883 884 err = host1x_client_resume(&dsi->client); 885 if (err < 0) { 886 dev_err(dsi->dev, "failed to resume: %d\n", err); 887 return err; 888 } 889 890 err = tegra_mipi_enable(dsi->mipi); 891 if (err < 0) 892 dev_err(dsi->dev, "failed to enable MIPI calibration: %d\n", 893 err); 894 895 err = tegra_dsi_pad_calibrate(dsi); 896 if (err < 0) 897 dev_err(dsi->dev, "MIPI calibration failed: %d\n", err); 898 899 if (dsi->slave) 900 tegra_dsi_prepare(dsi->slave); 901 902 return 0; 903} 904 905static void tegra_dsi_encoder_enable(struct drm_encoder *encoder) 906{ 907 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; 908 struct tegra_output *output = encoder_to_output(encoder); 909 struct tegra_dc *dc = to_tegra_dc(encoder->crtc); 910 struct tegra_dsi *dsi = to_dsi(output); 911 struct tegra_dsi_state *state; 912 u32 value; 913 int err; 914 915 /* If the bootloader enabled DSI it needs to be disabled 916 * in order for the panel initialization commands to be 917 * properly sent. 918 */ 919 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL); 920 921 if (value & DSI_POWER_CONTROL_ENABLE) 922 tegra_dsi_disable(dsi); 923 924 err = tegra_dsi_prepare(dsi); 925 if (err < 0) { 926 dev_err(dsi->dev, "failed to prepare: %d\n", err); 927 return; 928 } 929 930 state = tegra_dsi_get_state(dsi); 931 932 tegra_dsi_set_timeout(dsi, state->bclk, state->vrefresh); 933 934 /* 935 * The D-PHY timing fields are expressed in byte-clock cycles, so 936 * multiply the period by 8. 937 */ 938 tegra_dsi_set_phy_timing(dsi, state->period * 8, &state->timing); 939 940 if (output->panel) 941 drm_panel_prepare(output->panel); 942 943 tegra_dsi_configure(dsi, dc->pipe, mode); 944 945 /* enable display controller */ 946 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 947 value |= DSI_ENABLE; 948 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 949 950 tegra_dc_commit(dc); 951 952 /* enable DSI controller */ 953 tegra_dsi_enable(dsi); 954 955 if (output->panel) 956 drm_panel_enable(output->panel); 957} 958 959static int 960tegra_dsi_encoder_atomic_check(struct drm_encoder *encoder, 961 struct drm_crtc_state *crtc_state, 962 struct drm_connector_state *conn_state) 963{ 964 struct tegra_output *output = encoder_to_output(encoder); 965 struct tegra_dsi_state *state = to_dsi_state(conn_state); 966 struct tegra_dc *dc = to_tegra_dc(conn_state->crtc); 967 struct tegra_dsi *dsi = to_dsi(output); 968 unsigned int scdiv; 969 unsigned long plld; 970 int err; 971 972 state->pclk = crtc_state->mode.clock * 1000; 973 974 err = tegra_dsi_get_muldiv(dsi->format, &state->mul, &state->div); 975 if (err < 0) 976 return err; 977 978 state->lanes = tegra_dsi_get_lanes(dsi); 979 980 err = tegra_dsi_get_format(dsi->format, &state->format); 981 if (err < 0) 982 return err; 983 984 state->vrefresh = drm_mode_vrefresh(&crtc_state->mode); 985 986 /* compute byte clock */ 987 state->bclk = (state->pclk * state->mul) / (state->div * state->lanes); 988 989 DRM_DEBUG_KMS("mul: %u, div: %u, lanes: %u\n", state->mul, state->div, 990 state->lanes); 991 DRM_DEBUG_KMS("format: %u, vrefresh: %u\n", state->format, 992 state->vrefresh); 993 DRM_DEBUG_KMS("bclk: %lu\n", state->bclk); 994 995 /* 996 * Compute bit clock and round up to the next MHz. 997 */ 998 plld = DIV_ROUND_UP(state->bclk * 8, USEC_PER_SEC) * USEC_PER_SEC; 999 state->period = DIV_ROUND_CLOSEST(NSEC_PER_SEC, plld); 1000 1001 err = mipi_dphy_timing_get_default(&state->timing, state->period); 1002 if (err < 0) 1003 return err; 1004 1005 err = mipi_dphy_timing_validate(&state->timing, state->period); 1006 if (err < 0) { 1007 dev_err(dsi->dev, "failed to validate D-PHY timing: %d\n", err); 1008 return err; 1009 } 1010 1011 /* 1012 * We divide the frequency by two here, but we make up for that by 1013 * setting the shift clock divider (further below) to half of the 1014 * correct value. 1015 */ 1016 plld /= 2; 1017 1018 /* 1019 * Derive pixel clock from bit clock using the shift clock divider. 1020 * Note that this is only half of what we would expect, but we need 1021 * that to make up for the fact that we divided the bit clock by a 1022 * factor of two above. 1023 * 1024 * It's not clear exactly why this is necessary, but the display is 1025 * not working properly otherwise. Perhaps the PLLs cannot generate 1026 * frequencies sufficiently high. 1027 */ 1028 scdiv = ((8 * state->mul) / (state->div * state->lanes)) - 2; 1029 1030 err = tegra_dc_state_setup_clock(dc, crtc_state, dsi->clk_parent, 1031 plld, scdiv); 1032 if (err < 0) { 1033 dev_err(output->dev, "failed to setup CRTC state: %d\n", err); 1034 return err; 1035 } 1036 1037 return err; 1038} 1039 1040static const struct drm_encoder_helper_funcs tegra_dsi_encoder_helper_funcs = { 1041 .disable = tegra_dsi_encoder_disable, 1042 .enable = tegra_dsi_encoder_enable, 1043 .atomic_check = tegra_dsi_encoder_atomic_check, 1044}; 1045 1046static int tegra_dsi_init(struct host1x_client *client) 1047{ 1048 struct drm_device *drm = dev_get_drvdata(client->host); 1049 struct tegra_dsi *dsi = host1x_client_to_dsi(client); 1050 int err; 1051 1052 /* Gangsters must not register their own outputs. */ 1053 if (!dsi->master) { 1054 dsi->output.dev = client->dev; 1055 1056 drm_connector_init(drm, &dsi->output.connector, 1057 &tegra_dsi_connector_funcs, 1058 DRM_MODE_CONNECTOR_DSI); 1059 drm_connector_helper_add(&dsi->output.connector, 1060 &tegra_dsi_connector_helper_funcs); 1061 dsi->output.connector.dpms = DRM_MODE_DPMS_OFF; 1062 1063 drm_simple_encoder_init(drm, &dsi->output.encoder, 1064 DRM_MODE_ENCODER_DSI); 1065 drm_encoder_helper_add(&dsi->output.encoder, 1066 &tegra_dsi_encoder_helper_funcs); 1067 1068 drm_connector_attach_encoder(&dsi->output.connector, 1069 &dsi->output.encoder); 1070 drm_connector_register(&dsi->output.connector); 1071 1072 err = tegra_output_init(drm, &dsi->output); 1073 if (err < 0) 1074 dev_err(dsi->dev, "failed to initialize output: %d\n", 1075 err); 1076 1077 dsi->output.encoder.possible_crtcs = 0x3; 1078 } 1079 1080 return 0; 1081} 1082 1083static int tegra_dsi_exit(struct host1x_client *client) 1084{ 1085 struct tegra_dsi *dsi = host1x_client_to_dsi(client); 1086 1087 tegra_output_exit(&dsi->output); 1088 1089 return 0; 1090} 1091 1092static int tegra_dsi_runtime_suspend(struct host1x_client *client) 1093{ 1094 struct tegra_dsi *dsi = host1x_client_to_dsi(client); 1095 struct device *dev = client->dev; 1096 int err; 1097 1098 if (dsi->rst) { 1099 err = reset_control_assert(dsi->rst); 1100 if (err < 0) { 1101 dev_err(dev, "failed to assert reset: %d\n", err); 1102 return err; 1103 } 1104 } 1105 1106 usleep_range(1000, 2000); 1107 1108 clk_disable_unprepare(dsi->clk_lp); 1109 clk_disable_unprepare(dsi->clk); 1110 1111 regulator_disable(dsi->vdd); 1112 pm_runtime_put_sync(dev); 1113 1114 return 0; 1115} 1116 1117static int tegra_dsi_runtime_resume(struct host1x_client *client) 1118{ 1119 struct tegra_dsi *dsi = host1x_client_to_dsi(client); 1120 struct device *dev = client->dev; 1121 int err; 1122 1123 err = pm_runtime_resume_and_get(dev); 1124 if (err < 0) { 1125 dev_err(dev, "failed to get runtime PM: %d\n", err); 1126 return err; 1127 } 1128 1129 err = regulator_enable(dsi->vdd); 1130 if (err < 0) { 1131 dev_err(dev, "failed to enable VDD supply: %d\n", err); 1132 goto put_rpm; 1133 } 1134 1135 err = clk_prepare_enable(dsi->clk); 1136 if (err < 0) { 1137 dev_err(dev, "cannot enable DSI clock: %d\n", err); 1138 goto disable_vdd; 1139 } 1140 1141 err = clk_prepare_enable(dsi->clk_lp); 1142 if (err < 0) { 1143 dev_err(dev, "cannot enable low-power clock: %d\n", err); 1144 goto disable_clk; 1145 } 1146 1147 usleep_range(1000, 2000); 1148 1149 if (dsi->rst) { 1150 err = reset_control_deassert(dsi->rst); 1151 if (err < 0) { 1152 dev_err(dev, "cannot assert reset: %d\n", err); 1153 goto disable_clk_lp; 1154 } 1155 } 1156 1157 return 0; 1158 1159disable_clk_lp: 1160 clk_disable_unprepare(dsi->clk_lp); 1161disable_clk: 1162 clk_disable_unprepare(dsi->clk); 1163disable_vdd: 1164 regulator_disable(dsi->vdd); 1165put_rpm: 1166 pm_runtime_put_sync(dev); 1167 return err; 1168} 1169 1170static const struct host1x_client_ops dsi_client_ops = { 1171 .init = tegra_dsi_init, 1172 .exit = tegra_dsi_exit, 1173 .suspend = tegra_dsi_runtime_suspend, 1174 .resume = tegra_dsi_runtime_resume, 1175}; 1176 1177static int tegra_dsi_setup_clocks(struct tegra_dsi *dsi) 1178{ 1179 struct clk *parent; 1180 int err; 1181 1182 parent = clk_get_parent(dsi->clk); 1183 if (!parent) 1184 return -EINVAL; 1185 1186 err = clk_set_parent(parent, dsi->clk_parent); 1187 if (err < 0) 1188 return err; 1189 1190 return 0; 1191} 1192 1193static const char * const error_report[16] = { 1194 "SoT Error", 1195 "SoT Sync Error", 1196 "EoT Sync Error", 1197 "Escape Mode Entry Command Error", 1198 "Low-Power Transmit Sync Error", 1199 "Peripheral Timeout Error", 1200 "False Control Error", 1201 "Contention Detected", 1202 "ECC Error, single-bit", 1203 "ECC Error, multi-bit", 1204 "Checksum Error", 1205 "DSI Data Type Not Recognized", 1206 "DSI VC ID Invalid", 1207 "Invalid Transmission Length", 1208 "Reserved", 1209 "DSI Protocol Violation", 1210}; 1211 1212static ssize_t tegra_dsi_read_response(struct tegra_dsi *dsi, 1213 const struct mipi_dsi_msg *msg, 1214 size_t count) 1215{ 1216 u8 *rx = msg->rx_buf; 1217 unsigned int i, j, k; 1218 size_t size = 0; 1219 u16 errors; 1220 u32 value; 1221 1222 /* read and parse packet header */ 1223 value = tegra_dsi_readl(dsi, DSI_RD_DATA); 1224 1225 switch (value & 0x3f) { 1226 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT: 1227 errors = (value >> 8) & 0xffff; 1228 dev_dbg(dsi->dev, "Acknowledge and error report: %04x\n", 1229 errors); 1230 for (i = 0; i < ARRAY_SIZE(error_report); i++) 1231 if (errors & BIT(i)) 1232 dev_dbg(dsi->dev, " %2u: %s\n", i, 1233 error_report[i]); 1234 break; 1235 1236 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE: 1237 rx[0] = (value >> 8) & 0xff; 1238 size = 1; 1239 break; 1240 1241 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE: 1242 rx[0] = (value >> 8) & 0xff; 1243 rx[1] = (value >> 16) & 0xff; 1244 size = 2; 1245 break; 1246 1247 case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE: 1248 size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff); 1249 break; 1250 1251 case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE: 1252 size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff); 1253 break; 1254 1255 default: 1256 dev_err(dsi->dev, "unhandled response type: %02x\n", 1257 value & 0x3f); 1258 return -EPROTO; 1259 } 1260 1261 size = min(size, msg->rx_len); 1262 1263 if (msg->rx_buf && size > 0) { 1264 for (i = 0, j = 0; i < count - 1; i++, j += 4) { 1265 u8 *rx = msg->rx_buf + j; 1266 1267 value = tegra_dsi_readl(dsi, DSI_RD_DATA); 1268 1269 for (k = 0; k < 4 && (j + k) < msg->rx_len; k++) 1270 rx[j + k] = (value >> (k << 3)) & 0xff; 1271 } 1272 } 1273 1274 return size; 1275} 1276 1277static int tegra_dsi_transmit(struct tegra_dsi *dsi, unsigned long timeout) 1278{ 1279 tegra_dsi_writel(dsi, DSI_TRIGGER_HOST, DSI_TRIGGER); 1280 1281 timeout = jiffies + msecs_to_jiffies(timeout); 1282 1283 while (time_before(jiffies, timeout)) { 1284 u32 value = tegra_dsi_readl(dsi, DSI_TRIGGER); 1285 if ((value & DSI_TRIGGER_HOST) == 0) 1286 return 0; 1287 1288 usleep_range(1000, 2000); 1289 } 1290 1291 DRM_DEBUG_KMS("timeout waiting for transmission to complete\n"); 1292 return -ETIMEDOUT; 1293} 1294 1295static int tegra_dsi_wait_for_response(struct tegra_dsi *dsi, 1296 unsigned long timeout) 1297{ 1298 timeout = jiffies + msecs_to_jiffies(250); 1299 1300 while (time_before(jiffies, timeout)) { 1301 u32 value = tegra_dsi_readl(dsi, DSI_STATUS); 1302 u8 count = value & 0x1f; 1303 1304 if (count > 0) 1305 return count; 1306 1307 usleep_range(1000, 2000); 1308 } 1309 1310 DRM_DEBUG_KMS("peripheral returned no data\n"); 1311 return -ETIMEDOUT; 1312} 1313 1314static void tegra_dsi_writesl(struct tegra_dsi *dsi, unsigned long offset, 1315 const void *buffer, size_t size) 1316{ 1317 const u8 *buf = buffer; 1318 size_t i, j; 1319 u32 value; 1320 1321 for (j = 0; j < size; j += 4) { 1322 value = 0; 1323 1324 for (i = 0; i < 4 && j + i < size; i++) 1325 value |= buf[j + i] << (i << 3); 1326 1327 tegra_dsi_writel(dsi, value, DSI_WR_DATA); 1328 } 1329} 1330 1331static ssize_t tegra_dsi_host_transfer(struct mipi_dsi_host *host, 1332 const struct mipi_dsi_msg *msg) 1333{ 1334 struct tegra_dsi *dsi = host_to_tegra(host); 1335 struct mipi_dsi_packet packet; 1336 const u8 *header; 1337 size_t count; 1338 ssize_t err; 1339 u32 value; 1340 1341 err = mipi_dsi_create_packet(&packet, msg); 1342 if (err < 0) 1343 return err; 1344 1345 header = packet.header; 1346 1347 /* maximum FIFO depth is 1920 words */ 1348 if (packet.size > dsi->video_fifo_depth * 4) 1349 return -ENOSPC; 1350 1351 /* reset underflow/overflow flags */ 1352 value = tegra_dsi_readl(dsi, DSI_STATUS); 1353 if (value & (DSI_STATUS_UNDERFLOW | DSI_STATUS_OVERFLOW)) { 1354 value = DSI_HOST_CONTROL_FIFO_RESET; 1355 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL); 1356 usleep_range(10, 20); 1357 } 1358 1359 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL); 1360 value |= DSI_POWER_CONTROL_ENABLE; 1361 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL); 1362 1363 usleep_range(5000, 10000); 1364 1365 value = DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST | 1366 DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC; 1367 1368 if ((msg->flags & MIPI_DSI_MSG_USE_LPM) == 0) 1369 value |= DSI_HOST_CONTROL_HS; 1370 1371 /* 1372 * The host FIFO has a maximum of 64 words, so larger transmissions 1373 * need to use the video FIFO. 1374 */ 1375 if (packet.size > dsi->host_fifo_depth * 4) 1376 value |= DSI_HOST_CONTROL_FIFO_SEL; 1377 1378 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL); 1379 1380 /* 1381 * For reads and messages with explicitly requested ACK, generate a 1382 * BTA sequence after the transmission of the packet. 1383 */ 1384 if ((msg->flags & MIPI_DSI_MSG_REQ_ACK) || 1385 (msg->rx_buf && msg->rx_len > 0)) { 1386 value = tegra_dsi_readl(dsi, DSI_HOST_CONTROL); 1387 value |= DSI_HOST_CONTROL_PKT_BTA; 1388 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL); 1389 } 1390 1391 value = DSI_CONTROL_LANES(0) | DSI_CONTROL_HOST_ENABLE; 1392 tegra_dsi_writel(dsi, value, DSI_CONTROL); 1393 1394 /* write packet header, ECC is generated by hardware */ 1395 value = header[2] << 16 | header[1] << 8 | header[0]; 1396 tegra_dsi_writel(dsi, value, DSI_WR_DATA); 1397 1398 /* write payload (if any) */ 1399 if (packet.payload_length > 0) 1400 tegra_dsi_writesl(dsi, DSI_WR_DATA, packet.payload, 1401 packet.payload_length); 1402 1403 err = tegra_dsi_transmit(dsi, 250); 1404 if (err < 0) 1405 return err; 1406 1407 if ((msg->flags & MIPI_DSI_MSG_REQ_ACK) || 1408 (msg->rx_buf && msg->rx_len > 0)) { 1409 err = tegra_dsi_wait_for_response(dsi, 250); 1410 if (err < 0) 1411 return err; 1412 1413 count = err; 1414 1415 value = tegra_dsi_readl(dsi, DSI_RD_DATA); 1416 switch (value) { 1417 case 0x84: 1418 /* 1419 dev_dbg(dsi->dev, "ACK\n"); 1420 */ 1421 break; 1422 1423 case 0x87: 1424 /* 1425 dev_dbg(dsi->dev, "ESCAPE\n"); 1426 */ 1427 break; 1428 1429 default: 1430 dev_err(dsi->dev, "unknown status: %08x\n", value); 1431 break; 1432 } 1433 1434 if (count > 1) { 1435 err = tegra_dsi_read_response(dsi, msg, count); 1436 if (err < 0) 1437 dev_err(dsi->dev, 1438 "failed to parse response: %zd\n", 1439 err); 1440 else { 1441 /* 1442 * For read commands, return the number of 1443 * bytes returned by the peripheral. 1444 */ 1445 count = err; 1446 } 1447 } 1448 } else { 1449 /* 1450 * For write commands, we have transmitted the 4-byte header 1451 * plus the variable-length payload. 1452 */ 1453 count = 4 + packet.payload_length; 1454 } 1455 1456 return count; 1457} 1458 1459static int tegra_dsi_ganged_setup(struct tegra_dsi *dsi) 1460{ 1461 struct clk *parent; 1462 int err; 1463 1464 /* make sure both DSI controllers share the same PLL */ 1465 parent = clk_get_parent(dsi->slave->clk); 1466 if (!parent) 1467 return -EINVAL; 1468 1469 err = clk_set_parent(parent, dsi->clk_parent); 1470 if (err < 0) 1471 return err; 1472 1473 return 0; 1474} 1475 1476static int tegra_dsi_host_attach(struct mipi_dsi_host *host, 1477 struct mipi_dsi_device *device) 1478{ 1479 struct tegra_dsi *dsi = host_to_tegra(host); 1480 1481 dsi->flags = device->mode_flags; 1482 dsi->format = device->format; 1483 dsi->lanes = device->lanes; 1484 1485 if (dsi->slave) { 1486 int err; 1487 1488 dev_dbg(dsi->dev, "attaching dual-channel device %s\n", 1489 dev_name(&device->dev)); 1490 1491 err = tegra_dsi_ganged_setup(dsi); 1492 if (err < 0) { 1493 dev_err(dsi->dev, "failed to set up ganged mode: %d\n", 1494 err); 1495 return err; 1496 } 1497 } 1498 1499 /* 1500 * Slaves don't have a panel associated with them, so they provide 1501 * merely the second channel. 1502 */ 1503 if (!dsi->master) { 1504 struct tegra_output *output = &dsi->output; 1505 1506 output->panel = of_drm_find_panel(device->dev.of_node); 1507 if (IS_ERR(output->panel)) 1508 output->panel = NULL; 1509 1510 if (output->panel && output->connector.dev) 1511 drm_helper_hpd_irq_event(output->connector.dev); 1512 } 1513 1514 return 0; 1515} 1516 1517static int tegra_dsi_host_detach(struct mipi_dsi_host *host, 1518 struct mipi_dsi_device *device) 1519{ 1520 struct tegra_dsi *dsi = host_to_tegra(host); 1521 struct tegra_output *output = &dsi->output; 1522 1523 if (output->panel && &device->dev == output->panel->dev) { 1524 output->panel = NULL; 1525 1526 if (output->connector.dev) 1527 drm_helper_hpd_irq_event(output->connector.dev); 1528 } 1529 1530 return 0; 1531} 1532 1533static const struct mipi_dsi_host_ops tegra_dsi_host_ops = { 1534 .attach = tegra_dsi_host_attach, 1535 .detach = tegra_dsi_host_detach, 1536 .transfer = tegra_dsi_host_transfer, 1537}; 1538 1539static int tegra_dsi_ganged_probe(struct tegra_dsi *dsi) 1540{ 1541 struct device_node *np; 1542 1543 np = of_parse_phandle(dsi->dev->of_node, "nvidia,ganged-mode", 0); 1544 if (np) { 1545 struct platform_device *gangster = of_find_device_by_node(np); 1546 of_node_put(np); 1547 if (!gangster) 1548 return -EPROBE_DEFER; 1549 1550 dsi->slave = platform_get_drvdata(gangster); 1551 1552 if (!dsi->slave) { 1553 put_device(&gangster->dev); 1554 return -EPROBE_DEFER; 1555 } 1556 1557 dsi->slave->master = dsi; 1558 } 1559 1560 return 0; 1561} 1562 1563static int tegra_dsi_probe(struct platform_device *pdev) 1564{ 1565 struct tegra_dsi *dsi; 1566 struct resource *regs; 1567 int err; 1568 1569 dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL); 1570 if (!dsi) 1571 return -ENOMEM; 1572 1573 dsi->output.dev = dsi->dev = &pdev->dev; 1574 dsi->video_fifo_depth = 1920; 1575 dsi->host_fifo_depth = 64; 1576 1577 err = tegra_dsi_ganged_probe(dsi); 1578 if (err < 0) 1579 return err; 1580 1581 err = tegra_output_probe(&dsi->output); 1582 if (err < 0) 1583 return err; 1584 1585 dsi->output.connector.polled = DRM_CONNECTOR_POLL_HPD; 1586 1587 /* 1588 * Assume these values by default. When a DSI peripheral driver 1589 * attaches to the DSI host, the parameters will be taken from 1590 * the attached device. 1591 */ 1592 dsi->flags = MIPI_DSI_MODE_VIDEO; 1593 dsi->format = MIPI_DSI_FMT_RGB888; 1594 dsi->lanes = 4; 1595 1596 if (!pdev->dev.pm_domain) { 1597 dsi->rst = devm_reset_control_get(&pdev->dev, "dsi"); 1598 if (IS_ERR(dsi->rst)) { 1599 err = PTR_ERR(dsi->rst); 1600 goto remove; 1601 } 1602 } 1603 1604 dsi->clk = devm_clk_get(&pdev->dev, NULL); 1605 if (IS_ERR(dsi->clk)) { 1606 err = dev_err_probe(&pdev->dev, PTR_ERR(dsi->clk), 1607 "cannot get DSI clock\n"); 1608 goto remove; 1609 } 1610 1611 dsi->clk_lp = devm_clk_get(&pdev->dev, "lp"); 1612 if (IS_ERR(dsi->clk_lp)) { 1613 err = dev_err_probe(&pdev->dev, PTR_ERR(dsi->clk_lp), 1614 "cannot get low-power clock\n"); 1615 goto remove; 1616 } 1617 1618 dsi->clk_parent = devm_clk_get(&pdev->dev, "parent"); 1619 if (IS_ERR(dsi->clk_parent)) { 1620 err = dev_err_probe(&pdev->dev, PTR_ERR(dsi->clk_parent), 1621 "cannot get parent clock\n"); 1622 goto remove; 1623 } 1624 1625 dsi->vdd = devm_regulator_get(&pdev->dev, "avdd-dsi-csi"); 1626 if (IS_ERR(dsi->vdd)) { 1627 err = dev_err_probe(&pdev->dev, PTR_ERR(dsi->vdd), 1628 "cannot get VDD supply\n"); 1629 goto remove; 1630 } 1631 1632 err = tegra_dsi_setup_clocks(dsi); 1633 if (err < 0) { 1634 dev_err(&pdev->dev, "cannot setup clocks\n"); 1635 goto remove; 1636 } 1637 1638 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1639 dsi->regs = devm_ioremap_resource(&pdev->dev, regs); 1640 if (IS_ERR(dsi->regs)) { 1641 err = PTR_ERR(dsi->regs); 1642 goto remove; 1643 } 1644 1645 dsi->mipi = tegra_mipi_request(&pdev->dev, pdev->dev.of_node); 1646 if (IS_ERR(dsi->mipi)) { 1647 err = PTR_ERR(dsi->mipi); 1648 goto remove; 1649 } 1650 1651 dsi->host.ops = &tegra_dsi_host_ops; 1652 dsi->host.dev = &pdev->dev; 1653 1654 err = mipi_dsi_host_register(&dsi->host); 1655 if (err < 0) { 1656 dev_err(&pdev->dev, "failed to register DSI host: %d\n", err); 1657 goto mipi_free; 1658 } 1659 1660 platform_set_drvdata(pdev, dsi); 1661 pm_runtime_enable(&pdev->dev); 1662 1663 INIT_LIST_HEAD(&dsi->client.list); 1664 dsi->client.ops = &dsi_client_ops; 1665 dsi->client.dev = &pdev->dev; 1666 1667 err = host1x_client_register(&dsi->client); 1668 if (err < 0) { 1669 dev_err(&pdev->dev, "failed to register host1x client: %d\n", 1670 err); 1671 goto unregister; 1672 } 1673 1674 return 0; 1675 1676unregister: 1677 pm_runtime_disable(&pdev->dev); 1678 mipi_dsi_host_unregister(&dsi->host); 1679mipi_free: 1680 tegra_mipi_free(dsi->mipi); 1681remove: 1682 tegra_output_remove(&dsi->output); 1683 return err; 1684} 1685 1686static void tegra_dsi_remove(struct platform_device *pdev) 1687{ 1688 struct tegra_dsi *dsi = platform_get_drvdata(pdev); 1689 1690 pm_runtime_disable(&pdev->dev); 1691 1692 host1x_client_unregister(&dsi->client); 1693 1694 tegra_output_remove(&dsi->output); 1695 1696 mipi_dsi_host_unregister(&dsi->host); 1697 tegra_mipi_free(dsi->mipi); 1698} 1699 1700static const struct of_device_id tegra_dsi_of_match[] = { 1701 { .compatible = "nvidia,tegra210-dsi", }, 1702 { .compatible = "nvidia,tegra132-dsi", }, 1703 { .compatible = "nvidia,tegra124-dsi", }, 1704 { .compatible = "nvidia,tegra114-dsi", }, 1705 { }, 1706}; 1707MODULE_DEVICE_TABLE(of, tegra_dsi_of_match); 1708 1709struct platform_driver tegra_dsi_driver = { 1710 .driver = { 1711 .name = "tegra-dsi", 1712 .of_match_table = tegra_dsi_of_match, 1713 }, 1714 .probe = tegra_dsi_probe, 1715 .remove_new = tegra_dsi_remove, 1716}; 1717