162306a36Sopenharmony_ci/* SPDX-License-Identifier: MIT */
262306a36Sopenharmony_ci/*
362306a36Sopenharmony_ci * Copyright (C) 2013-2019 NVIDIA Corporation.
462306a36Sopenharmony_ci * Copyright (C) 2015 Rob Clark
562306a36Sopenharmony_ci */
662306a36Sopenharmony_ci
762306a36Sopenharmony_ci#ifndef DRM_TEGRA_DP_H
862306a36Sopenharmony_ci#define DRM_TEGRA_DP_H 1
962306a36Sopenharmony_ci
1062306a36Sopenharmony_ci#include <linux/types.h>
1162306a36Sopenharmony_ci
1262306a36Sopenharmony_cistruct drm_display_info;
1362306a36Sopenharmony_cistruct drm_display_mode;
1462306a36Sopenharmony_cistruct drm_dp_aux;
1562306a36Sopenharmony_cistruct drm_dp_link;
1662306a36Sopenharmony_ci
1762306a36Sopenharmony_ci/**
1862306a36Sopenharmony_ci * struct drm_dp_link_caps - DP link capabilities
1962306a36Sopenharmony_ci */
2062306a36Sopenharmony_cistruct drm_dp_link_caps {
2162306a36Sopenharmony_ci	/**
2262306a36Sopenharmony_ci	 * @enhanced_framing:
2362306a36Sopenharmony_ci	 *
2462306a36Sopenharmony_ci	 * enhanced framing capability (mandatory as of DP 1.2)
2562306a36Sopenharmony_ci	 */
2662306a36Sopenharmony_ci	bool enhanced_framing;
2762306a36Sopenharmony_ci
2862306a36Sopenharmony_ci	/**
2962306a36Sopenharmony_ci	 * tps3_supported:
3062306a36Sopenharmony_ci	 *
3162306a36Sopenharmony_ci	 * training pattern sequence 3 supported for equalization
3262306a36Sopenharmony_ci	 */
3362306a36Sopenharmony_ci	bool tps3_supported;
3462306a36Sopenharmony_ci
3562306a36Sopenharmony_ci	/**
3662306a36Sopenharmony_ci	 * @fast_training:
3762306a36Sopenharmony_ci	 *
3862306a36Sopenharmony_ci	 * AUX CH handshake not required for link training
3962306a36Sopenharmony_ci	 */
4062306a36Sopenharmony_ci	bool fast_training;
4162306a36Sopenharmony_ci
4262306a36Sopenharmony_ci	/**
4362306a36Sopenharmony_ci	 * @channel_coding:
4462306a36Sopenharmony_ci	 *
4562306a36Sopenharmony_ci	 * ANSI 8B/10B channel coding capability
4662306a36Sopenharmony_ci	 */
4762306a36Sopenharmony_ci	bool channel_coding;
4862306a36Sopenharmony_ci
4962306a36Sopenharmony_ci	/**
5062306a36Sopenharmony_ci	 * @alternate_scrambler_reset:
5162306a36Sopenharmony_ci	 *
5262306a36Sopenharmony_ci	 * eDP alternate scrambler reset capability
5362306a36Sopenharmony_ci	 */
5462306a36Sopenharmony_ci	bool alternate_scrambler_reset;
5562306a36Sopenharmony_ci};
5662306a36Sopenharmony_ci
5762306a36Sopenharmony_civoid drm_dp_link_caps_copy(struct drm_dp_link_caps *dest,
5862306a36Sopenharmony_ci			   const struct drm_dp_link_caps *src);
5962306a36Sopenharmony_ci
6062306a36Sopenharmony_ci/**
6162306a36Sopenharmony_ci * struct drm_dp_link_ops - DP link operations
6262306a36Sopenharmony_ci */
6362306a36Sopenharmony_cistruct drm_dp_link_ops {
6462306a36Sopenharmony_ci	/**
6562306a36Sopenharmony_ci	 * @apply_training:
6662306a36Sopenharmony_ci	 */
6762306a36Sopenharmony_ci	int (*apply_training)(struct drm_dp_link *link);
6862306a36Sopenharmony_ci
6962306a36Sopenharmony_ci	/**
7062306a36Sopenharmony_ci	 * @configure:
7162306a36Sopenharmony_ci	 */
7262306a36Sopenharmony_ci	int (*configure)(struct drm_dp_link *link);
7362306a36Sopenharmony_ci};
7462306a36Sopenharmony_ci
7562306a36Sopenharmony_ci#define DP_TRAIN_VOLTAGE_SWING_LEVEL(x) ((x) << 0)
7662306a36Sopenharmony_ci#define DP_TRAIN_PRE_EMPHASIS_LEVEL(x) ((x) << 3)
7762306a36Sopenharmony_ci#define DP_LANE_POST_CURSOR(i, x) (((x) & 0x3) << (((i) & 1) << 2))
7862306a36Sopenharmony_ci
7962306a36Sopenharmony_ci/**
8062306a36Sopenharmony_ci * struct drm_dp_link_train_set - link training settings
8162306a36Sopenharmony_ci * @voltage_swing: per-lane voltage swing
8262306a36Sopenharmony_ci * @pre_emphasis: per-lane pre-emphasis
8362306a36Sopenharmony_ci * @post_cursor: per-lane post-cursor
8462306a36Sopenharmony_ci */
8562306a36Sopenharmony_cistruct drm_dp_link_train_set {
8662306a36Sopenharmony_ci	unsigned int voltage_swing[4];
8762306a36Sopenharmony_ci	unsigned int pre_emphasis[4];
8862306a36Sopenharmony_ci	unsigned int post_cursor[4];
8962306a36Sopenharmony_ci};
9062306a36Sopenharmony_ci
9162306a36Sopenharmony_ci/**
9262306a36Sopenharmony_ci * struct drm_dp_link_train - link training state information
9362306a36Sopenharmony_ci * @request: currently requested settings
9462306a36Sopenharmony_ci * @adjust: adjustments requested by sink
9562306a36Sopenharmony_ci * @pattern: currently requested training pattern
9662306a36Sopenharmony_ci * @clock_recovered: flag to track if clock recovery has completed
9762306a36Sopenharmony_ci * @channel_equalized: flag to track if channel equalization has completed
9862306a36Sopenharmony_ci */
9962306a36Sopenharmony_cistruct drm_dp_link_train {
10062306a36Sopenharmony_ci	struct drm_dp_link_train_set request;
10162306a36Sopenharmony_ci	struct drm_dp_link_train_set adjust;
10262306a36Sopenharmony_ci
10362306a36Sopenharmony_ci	unsigned int pattern;
10462306a36Sopenharmony_ci
10562306a36Sopenharmony_ci	bool clock_recovered;
10662306a36Sopenharmony_ci	bool channel_equalized;
10762306a36Sopenharmony_ci};
10862306a36Sopenharmony_ci
10962306a36Sopenharmony_ci/**
11062306a36Sopenharmony_ci * struct drm_dp_link - DP link capabilities and configuration
11162306a36Sopenharmony_ci * @revision: DP specification revision supported on the link
11262306a36Sopenharmony_ci * @max_rate: maximum clock rate supported on the link
11362306a36Sopenharmony_ci * @max_lanes: maximum number of lanes supported on the link
11462306a36Sopenharmony_ci * @caps: capabilities supported on the link (see &drm_dp_link_caps)
11562306a36Sopenharmony_ci * @aux_rd_interval: AUX read interval to use for training (in microseconds)
11662306a36Sopenharmony_ci * @edp: eDP revision (0x11: eDP 1.1, 0x12: eDP 1.2, ...)
11762306a36Sopenharmony_ci * @rate: currently configured link rate
11862306a36Sopenharmony_ci * @lanes: currently configured number of lanes
11962306a36Sopenharmony_ci * @rates: additional supported link rates in kHz (eDP 1.4)
12062306a36Sopenharmony_ci * @num_rates: number of additional supported link rates (eDP 1.4)
12162306a36Sopenharmony_ci */
12262306a36Sopenharmony_cistruct drm_dp_link {
12362306a36Sopenharmony_ci	unsigned char revision;
12462306a36Sopenharmony_ci	unsigned int max_rate;
12562306a36Sopenharmony_ci	unsigned int max_lanes;
12662306a36Sopenharmony_ci
12762306a36Sopenharmony_ci	struct drm_dp_link_caps caps;
12862306a36Sopenharmony_ci
12962306a36Sopenharmony_ci	/**
13062306a36Sopenharmony_ci	 * @cr: clock recovery read interval
13162306a36Sopenharmony_ci	 * @ce: channel equalization read interval
13262306a36Sopenharmony_ci	 */
13362306a36Sopenharmony_ci	struct {
13462306a36Sopenharmony_ci		unsigned int cr;
13562306a36Sopenharmony_ci		unsigned int ce;
13662306a36Sopenharmony_ci	} aux_rd_interval;
13762306a36Sopenharmony_ci
13862306a36Sopenharmony_ci	unsigned char edp;
13962306a36Sopenharmony_ci
14062306a36Sopenharmony_ci	unsigned int rate;
14162306a36Sopenharmony_ci	unsigned int lanes;
14262306a36Sopenharmony_ci
14362306a36Sopenharmony_ci	unsigned long rates[DP_MAX_SUPPORTED_RATES];
14462306a36Sopenharmony_ci	unsigned int num_rates;
14562306a36Sopenharmony_ci
14662306a36Sopenharmony_ci	/**
14762306a36Sopenharmony_ci	 * @ops: DP link operations
14862306a36Sopenharmony_ci	 */
14962306a36Sopenharmony_ci	const struct drm_dp_link_ops *ops;
15062306a36Sopenharmony_ci
15162306a36Sopenharmony_ci	/**
15262306a36Sopenharmony_ci	 * @aux: DP AUX channel
15362306a36Sopenharmony_ci	 */
15462306a36Sopenharmony_ci	struct drm_dp_aux *aux;
15562306a36Sopenharmony_ci
15662306a36Sopenharmony_ci	/**
15762306a36Sopenharmony_ci	 * @train: DP link training state
15862306a36Sopenharmony_ci	 */
15962306a36Sopenharmony_ci	struct drm_dp_link_train train;
16062306a36Sopenharmony_ci};
16162306a36Sopenharmony_ci
16262306a36Sopenharmony_ciint drm_dp_link_add_rate(struct drm_dp_link *link, unsigned long rate);
16362306a36Sopenharmony_ciint drm_dp_link_remove_rate(struct drm_dp_link *link, unsigned long rate);
16462306a36Sopenharmony_civoid drm_dp_link_update_rates(struct drm_dp_link *link);
16562306a36Sopenharmony_ci
16662306a36Sopenharmony_ciint drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link);
16762306a36Sopenharmony_ciint drm_dp_link_power_up(struct drm_dp_aux *aux, struct drm_dp_link *link);
16862306a36Sopenharmony_ciint drm_dp_link_power_down(struct drm_dp_aux *aux, struct drm_dp_link *link);
16962306a36Sopenharmony_ciint drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link);
17062306a36Sopenharmony_ciint drm_dp_link_choose(struct drm_dp_link *link,
17162306a36Sopenharmony_ci		       const struct drm_display_mode *mode,
17262306a36Sopenharmony_ci		       const struct drm_display_info *info);
17362306a36Sopenharmony_ci
17462306a36Sopenharmony_civoid drm_dp_link_train_init(struct drm_dp_link_train *train);
17562306a36Sopenharmony_ciint drm_dp_link_train(struct drm_dp_link *link);
17662306a36Sopenharmony_ci
17762306a36Sopenharmony_ci#endif
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