162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0 */ 262306a36Sopenharmony_ci/* 362306a36Sopenharmony_ci * Copyright (C) STMicroelectronics SA 2017 462306a36Sopenharmony_ci * 562306a36Sopenharmony_ci * Authors: Philippe Cornu <philippe.cornu@st.com> 662306a36Sopenharmony_ci * Yannick Fertre <yannick.fertre@st.com> 762306a36Sopenharmony_ci * Fabien Dessenne <fabien.dessenne@st.com> 862306a36Sopenharmony_ci * Mickael Reulier <mickael.reulier@st.com> 962306a36Sopenharmony_ci */ 1062306a36Sopenharmony_ci 1162306a36Sopenharmony_ci#ifndef _LTDC_H_ 1262306a36Sopenharmony_ci#define _LTDC_H_ 1362306a36Sopenharmony_ci 1462306a36Sopenharmony_cistruct ltdc_caps { 1562306a36Sopenharmony_ci u32 hw_version; /* hardware version */ 1662306a36Sopenharmony_ci u32 nb_layers; /* number of supported layers */ 1762306a36Sopenharmony_ci u32 layer_ofs; /* layer offset for applicable regs */ 1862306a36Sopenharmony_ci const u32 *layer_regs; /* layer register offset */ 1962306a36Sopenharmony_ci u32 bus_width; /* bus width (32 or 64 bits) */ 2062306a36Sopenharmony_ci const u32 *pix_fmt_hw; /* supported hw pixel formats */ 2162306a36Sopenharmony_ci const u32 *pix_fmt_drm; /* supported drm pixel formats */ 2262306a36Sopenharmony_ci int pix_fmt_nb; /* number of pixel format */ 2362306a36Sopenharmony_ci bool pix_fmt_flex; /* pixel format flexibility supported */ 2462306a36Sopenharmony_ci bool non_alpha_only_l1; /* non-native no-alpha formats on layer 1 */ 2562306a36Sopenharmony_ci int pad_max_freq_hz; /* max frequency supported by pad */ 2662306a36Sopenharmony_ci int nb_irq; /* number of hardware interrupts */ 2762306a36Sopenharmony_ci bool ycbcr_input; /* ycbcr input converter supported */ 2862306a36Sopenharmony_ci bool ycbcr_output; /* ycbcr output converter supported */ 2962306a36Sopenharmony_ci bool plane_reg_shadow; /* plane shadow registers ability */ 3062306a36Sopenharmony_ci bool crc; /* cyclic redundancy check supported */ 3162306a36Sopenharmony_ci bool dynamic_zorder; /* dynamic z-order */ 3262306a36Sopenharmony_ci bool plane_rotation; /* plane rotation */ 3362306a36Sopenharmony_ci bool fifo_threshold; /* fifo underrun threshold supported */ 3462306a36Sopenharmony_ci}; 3562306a36Sopenharmony_ci 3662306a36Sopenharmony_ci#define LTDC_MAX_LAYER 4 3762306a36Sopenharmony_ci 3862306a36Sopenharmony_cistruct fps_info { 3962306a36Sopenharmony_ci unsigned int counter; 4062306a36Sopenharmony_ci ktime_t last_timestamp; 4162306a36Sopenharmony_ci}; 4262306a36Sopenharmony_ci 4362306a36Sopenharmony_cistruct ltdc_device { 4462306a36Sopenharmony_ci void __iomem *regs; 4562306a36Sopenharmony_ci struct regmap *regmap; 4662306a36Sopenharmony_ci struct clk *pixel_clk; /* lcd pixel clock */ 4762306a36Sopenharmony_ci struct mutex err_lock; /* protecting error_status */ 4862306a36Sopenharmony_ci struct ltdc_caps caps; 4962306a36Sopenharmony_ci u32 irq_status; 5062306a36Sopenharmony_ci u32 fifo_err; /* fifo underrun error counter */ 5162306a36Sopenharmony_ci u32 fifo_warn; /* fifo underrun warning counter */ 5262306a36Sopenharmony_ci u32 fifo_threshold; /* fifo underrun threshold */ 5362306a36Sopenharmony_ci u32 transfer_err; /* transfer error counter */ 5462306a36Sopenharmony_ci struct fps_info plane_fpsi[LTDC_MAX_LAYER]; 5562306a36Sopenharmony_ci struct drm_atomic_state *suspend_state; 5662306a36Sopenharmony_ci int crc_skip_count; 5762306a36Sopenharmony_ci bool crc_active; 5862306a36Sopenharmony_ci}; 5962306a36Sopenharmony_ci 6062306a36Sopenharmony_ciint ltdc_load(struct drm_device *ddev); 6162306a36Sopenharmony_civoid ltdc_unload(struct drm_device *ddev); 6262306a36Sopenharmony_civoid ltdc_suspend(struct drm_device *ddev); 6362306a36Sopenharmony_ciint ltdc_resume(struct drm_device *ddev); 6462306a36Sopenharmony_ci 6562306a36Sopenharmony_ci#endif 66