162306a36Sopenharmony_ci1. stiH display hardware IP 262306a36Sopenharmony_ci--------------------------- 362306a36Sopenharmony_ciThe STMicroelectronics stiH SoCs use a common chain of HW display IP blocks: 462306a36Sopenharmony_ci- The High Quality Video Display Processor (HQVDP) gets video frames from a 562306a36Sopenharmony_ci video decoder and does high quality video processing, including scaling. 662306a36Sopenharmony_ci 762306a36Sopenharmony_ci- The Compositor is a multiplane, dual-mixer (Main & Aux) digital processor. It 862306a36Sopenharmony_ci has several inputs: 962306a36Sopenharmony_ci - The graphics planes are internally processed by the Generic Display 1062306a36Sopenharmony_ci Pipeline (GDP). 1162306a36Sopenharmony_ci - The video plug (VID) connects to the HQVDP output. 1262306a36Sopenharmony_ci - The cursor handles ... a cursor. 1362306a36Sopenharmony_ci- The TV OUT pre-formats (convert, clip, round) the compositor output data 1462306a36Sopenharmony_ci- The HDMI / DVO / HD Analog / SD analog IP builds the video signals 1562306a36Sopenharmony_ci - DVO (Digital Video Output) handles a 24bits parallel signal 1662306a36Sopenharmony_ci - The HD analog signal is typically driven by a YCbCr cable, supporting up to 1762306a36Sopenharmony_ci 1080i mode. 1862306a36Sopenharmony_ci - The SD analog signal is typically used for legacy TV 1962306a36Sopenharmony_ci- The VTG (Video Timing Generators) build Vsync signals used by the other HW IP 2062306a36Sopenharmony_ciNote that some stiH drivers support only a subset of thee HW IP. 2162306a36Sopenharmony_ci 2262306a36Sopenharmony_ci .-------------. .-----------. .-----------. 2362306a36Sopenharmony_ciGPU >-------------+GDP Main | | +---+ HDMI +--> HDMI 2462306a36Sopenharmony_ciGPU >-------------+GDP mixer+---+ | :===========: 2562306a36Sopenharmony_ciGPU >-------------+Cursor | | +---+ DVO +--> 24b// 2662306a36Sopenharmony_ci ------- | COMPOSITOR | | TV OUT | :===========: 2762306a36Sopenharmony_ci | | | | | +---+ HD analog +--> YCbCr 2862306a36Sopenharmony_ciVid >--+ HQVDP +--+VID Aux +---+ | :===========: 2962306a36Sopenharmony_cidec | | | mixer| | +---+ SD analog +--> CVBS 3062306a36Sopenharmony_ci '-------' '-------------' '-----------' '-----------' 3162306a36Sopenharmony_ci .-----------. 3262306a36Sopenharmony_ci | main+--> Vsync 3362306a36Sopenharmony_ci | VTG | 3462306a36Sopenharmony_ci | aux+--> Vsync 3562306a36Sopenharmony_ci '-----------' 3662306a36Sopenharmony_ci 3762306a36Sopenharmony_ci2. DRM / HW mapping 3862306a36Sopenharmony_ci------------------- 3962306a36Sopenharmony_ciThese IP are mapped to the DRM objects as following: 4062306a36Sopenharmony_ci- The CRTCs are mapped to the Compositor Main and Aux Mixers 4162306a36Sopenharmony_ci- The Framebuffers and planes are mapped to the Compositor GDP (non video 4262306a36Sopenharmony_ci buffers) and to HQVDP+VID (video buffers) 4362306a36Sopenharmony_ci- The Cursor is mapped to the Compositor Cursor 4462306a36Sopenharmony_ci- The Encoders are mapped to the TVOut 4562306a36Sopenharmony_ci- The Bridges/Connectors are mapped to the HDMI / DVO / HD Analog / SD analog 4662306a36Sopenharmony_ci 4762306a36Sopenharmony_ciFB & planes Cursor CRTC Encoders Bridges/Connectors 4862306a36Sopenharmony_ci | | | | | 4962306a36Sopenharmony_ci | | | | | 5062306a36Sopenharmony_ci | .-------------. | .-----------. .-----------. | 5162306a36Sopenharmony_ci +------------> |GDP | Main | | | +-> | | HDMI | <-+ 5262306a36Sopenharmony_ci +------------> |GDP v mixer|<+ | | | :===========: | 5362306a36Sopenharmony_ci | |Cursor | | | +-> | | DVO | <-+ 5462306a36Sopenharmony_ci | ------- | COMPOSITOR | | |TV OUT | | :===========: | 5562306a36Sopenharmony_ci | | | | | | | +-> | | HD analog | <-+ 5662306a36Sopenharmony_ci +-> | HQVDP | |VID Aux |<+ | | | :===========: | 5762306a36Sopenharmony_ci | | | mixer| | +-> | | SD analog | <-+ 5862306a36Sopenharmony_ci '-------' '-------------' '-----------' '-----------' 59