1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd 4 * Author:Mark Yao <mark.yao@rock-chips.com> 5 */ 6 7#include <linux/clk.h> 8#include <linux/component.h> 9#include <linux/delay.h> 10#include <linux/iopoll.h> 11#include <linux/kernel.h> 12#include <linux/log2.h> 13#include <linux/module.h> 14#include <linux/of.h> 15#include <linux/overflow.h> 16#include <linux/platform_device.h> 17#include <linux/pm_runtime.h> 18#include <linux/reset.h> 19 20#include <drm/drm.h> 21#include <drm/drm_atomic.h> 22#include <drm/drm_atomic_uapi.h> 23#include <drm/drm_blend.h> 24#include <drm/drm_crtc.h> 25#include <drm/drm_flip_work.h> 26#include <drm/drm_fourcc.h> 27#include <drm/drm_framebuffer.h> 28#include <drm/drm_gem_atomic_helper.h> 29#include <drm/drm_gem_framebuffer_helper.h> 30#include <drm/drm_probe_helper.h> 31#include <drm/drm_self_refresh_helper.h> 32#include <drm/drm_vblank.h> 33 34#ifdef CONFIG_DRM_ANALOGIX_DP 35#include <drm/bridge/analogix_dp.h> 36#endif 37 38#include "rockchip_drm_drv.h" 39#include "rockchip_drm_gem.h" 40#include "rockchip_drm_fb.h" 41#include "rockchip_drm_vop.h" 42#include "rockchip_rgb.h" 43 44#define VOP_WIN_SET(vop, win, name, v) \ 45 vop_reg_set(vop, &win->phy->name, win->base, ~0, v, #name) 46#define VOP_SCL_SET(vop, win, name, v) \ 47 vop_reg_set(vop, &win->phy->scl->name, win->base, ~0, v, #name) 48#define VOP_SCL_SET_EXT(vop, win, name, v) \ 49 vop_reg_set(vop, &win->phy->scl->ext->name, \ 50 win->base, ~0, v, #name) 51 52#define VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, name, v) \ 53 do { \ 54 if (win_yuv2yuv && win_yuv2yuv->name.mask) \ 55 vop_reg_set(vop, &win_yuv2yuv->name, 0, ~0, v, #name); \ 56 } while (0) 57 58#define VOP_WIN_YUV2YUV_COEFFICIENT_SET(vop, win_yuv2yuv, name, v) \ 59 do { \ 60 if (win_yuv2yuv && win_yuv2yuv->phy->name.mask) \ 61 vop_reg_set(vop, &win_yuv2yuv->phy->name, win_yuv2yuv->base, ~0, v, #name); \ 62 } while (0) 63 64#define VOP_INTR_SET_MASK(vop, name, mask, v) \ 65 vop_reg_set(vop, &vop->data->intr->name, 0, mask, v, #name) 66 67#define VOP_REG_SET(vop, group, name, v) \ 68 vop_reg_set(vop, &vop->data->group->name, 0, ~0, v, #name) 69 70#define VOP_HAS_REG(vop, group, name) \ 71 (!!(vop->data->group->name.mask)) 72 73#define VOP_INTR_SET_TYPE(vop, name, type, v) \ 74 do { \ 75 int i, reg = 0, mask = 0; \ 76 for (i = 0; i < vop->data->intr->nintrs; i++) { \ 77 if (vop->data->intr->intrs[i] & type) { \ 78 reg |= (v) << i; \ 79 mask |= 1 << i; \ 80 } \ 81 } \ 82 VOP_INTR_SET_MASK(vop, name, mask, reg); \ 83 } while (0) 84#define VOP_INTR_GET_TYPE(vop, name, type) \ 85 vop_get_intr_type(vop, &vop->data->intr->name, type) 86 87#define VOP_WIN_GET(vop, win, name) \ 88 vop_read_reg(vop, win->base, &win->phy->name) 89 90#define VOP_WIN_HAS_REG(win, name) \ 91 (!!(win->phy->name.mask)) 92 93#define VOP_WIN_GET_YRGBADDR(vop, win) \ 94 vop_readl(vop, win->base + win->phy->yrgb_mst.offset) 95 96#define VOP_WIN_TO_INDEX(vop_win) \ 97 ((vop_win) - (vop_win)->vop->win) 98 99#define VOP_AFBC_SET(vop, name, v) \ 100 do { \ 101 if ((vop)->data->afbc) \ 102 vop_reg_set((vop), &(vop)->data->afbc->name, \ 103 0, ~0, v, #name); \ 104 } while (0) 105 106#define to_vop(x) container_of(x, struct vop, crtc) 107#define to_vop_win(x) container_of(x, struct vop_win, base) 108 109#define AFBC_FMT_RGB565 0x0 110#define AFBC_FMT_U8U8U8U8 0x5 111#define AFBC_FMT_U8U8U8 0x4 112 113#define AFBC_TILE_16x16 BIT(4) 114 115/* 116 * The coefficients of the following matrix are all fixed points. 117 * The format is S2.10 for the 3x3 part of the matrix, and S9.12 for the offsets. 118 * They are all represented in two's complement. 119 */ 120static const uint32_t bt601_yuv2rgb[] = { 121 0x4A8, 0x0, 0x662, 122 0x4A8, 0x1E6F, 0x1CBF, 123 0x4A8, 0x812, 0x0, 124 0x321168, 0x0877CF, 0x2EB127 125}; 126 127enum vop_pending { 128 VOP_PENDING_FB_UNREF, 129}; 130 131struct vop_win { 132 struct drm_plane base; 133 const struct vop_win_data *data; 134 const struct vop_win_yuv2yuv_data *yuv2yuv_data; 135 struct vop *vop; 136}; 137 138struct rockchip_rgb; 139struct vop { 140 struct drm_crtc crtc; 141 struct device *dev; 142 struct drm_device *drm_dev; 143 bool is_enabled; 144 145 struct completion dsp_hold_completion; 146 unsigned int win_enabled; 147 148 /* protected by dev->event_lock */ 149 struct drm_pending_vblank_event *event; 150 151 struct drm_flip_work fb_unref_work; 152 unsigned long pending; 153 154 struct completion line_flag_completion; 155 156 const struct vop_data *data; 157 158 uint32_t *regsbak; 159 void __iomem *regs; 160 void __iomem *lut_regs; 161 162 /* physical map length of vop register */ 163 uint32_t len; 164 165 /* one time only one process allowed to config the register */ 166 spinlock_t reg_lock; 167 /* lock vop irq reg */ 168 spinlock_t irq_lock; 169 /* protects crtc enable/disable */ 170 struct mutex vop_lock; 171 172 unsigned int irq; 173 174 /* vop AHP clk */ 175 struct clk *hclk; 176 /* vop dclk */ 177 struct clk *dclk; 178 /* vop share memory frequency */ 179 struct clk *aclk; 180 181 /* vop dclk reset */ 182 struct reset_control *dclk_rst; 183 184 /* optional internal rgb encoder */ 185 struct rockchip_rgb *rgb; 186 187 struct vop_win win[]; 188}; 189 190static inline uint32_t vop_readl(struct vop *vop, uint32_t offset) 191{ 192 return readl(vop->regs + offset); 193} 194 195static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base, 196 const struct vop_reg *reg) 197{ 198 return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask; 199} 200 201static void vop_reg_set(struct vop *vop, const struct vop_reg *reg, 202 uint32_t _offset, uint32_t _mask, uint32_t v, 203 const char *reg_name) 204{ 205 int offset, mask, shift; 206 207 if (!reg || !reg->mask) { 208 DRM_DEV_DEBUG(vop->dev, "Warning: not support %s\n", reg_name); 209 return; 210 } 211 212 offset = reg->offset + _offset; 213 mask = reg->mask & _mask; 214 shift = reg->shift; 215 216 if (reg->write_mask) { 217 v = ((v << shift) & 0xffff) | (mask << (shift + 16)); 218 } else { 219 uint32_t cached_val = vop->regsbak[offset >> 2]; 220 221 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift); 222 vop->regsbak[offset >> 2] = v; 223 } 224 225 if (reg->relaxed) 226 writel_relaxed(v, vop->regs + offset); 227 else 228 writel(v, vop->regs + offset); 229} 230 231static inline uint32_t vop_get_intr_type(struct vop *vop, 232 const struct vop_reg *reg, int type) 233{ 234 uint32_t i, ret = 0; 235 uint32_t regs = vop_read_reg(vop, 0, reg); 236 237 for (i = 0; i < vop->data->intr->nintrs; i++) { 238 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i)) 239 ret |= vop->data->intr->intrs[i]; 240 } 241 242 return ret; 243} 244 245static inline void vop_cfg_done(struct vop *vop) 246{ 247 VOP_REG_SET(vop, common, cfg_done, 1); 248} 249 250static bool has_rb_swapped(uint32_t version, uint32_t format) 251{ 252 switch (format) { 253 case DRM_FORMAT_XBGR8888: 254 case DRM_FORMAT_ABGR8888: 255 case DRM_FORMAT_BGR565: 256 return true; 257 /* 258 * full framework (IP version 3.x) only need rb swapped for RGB888 and 259 * little framework (IP version 2.x) only need rb swapped for BGR888, 260 * check for 3.x to also only rb swap BGR888 for unknown vop version 261 */ 262 case DRM_FORMAT_RGB888: 263 return VOP_MAJOR(version) == 3; 264 case DRM_FORMAT_BGR888: 265 return VOP_MAJOR(version) != 3; 266 default: 267 return false; 268 } 269} 270 271static bool has_uv_swapped(uint32_t format) 272{ 273 switch (format) { 274 case DRM_FORMAT_NV21: 275 case DRM_FORMAT_NV61: 276 case DRM_FORMAT_NV42: 277 return true; 278 default: 279 return false; 280 } 281} 282 283static enum vop_data_format vop_convert_format(uint32_t format) 284{ 285 switch (format) { 286 case DRM_FORMAT_XRGB8888: 287 case DRM_FORMAT_ARGB8888: 288 case DRM_FORMAT_XBGR8888: 289 case DRM_FORMAT_ABGR8888: 290 return VOP_FMT_ARGB8888; 291 case DRM_FORMAT_RGB888: 292 case DRM_FORMAT_BGR888: 293 return VOP_FMT_RGB888; 294 case DRM_FORMAT_RGB565: 295 case DRM_FORMAT_BGR565: 296 return VOP_FMT_RGB565; 297 case DRM_FORMAT_NV12: 298 case DRM_FORMAT_NV21: 299 return VOP_FMT_YUV420SP; 300 case DRM_FORMAT_NV16: 301 case DRM_FORMAT_NV61: 302 return VOP_FMT_YUV422SP; 303 case DRM_FORMAT_NV24: 304 case DRM_FORMAT_NV42: 305 return VOP_FMT_YUV444SP; 306 default: 307 DRM_ERROR("unsupported format[%08x]\n", format); 308 return -EINVAL; 309 } 310} 311 312static int vop_convert_afbc_format(uint32_t format) 313{ 314 switch (format) { 315 case DRM_FORMAT_XRGB8888: 316 case DRM_FORMAT_ARGB8888: 317 case DRM_FORMAT_XBGR8888: 318 case DRM_FORMAT_ABGR8888: 319 return AFBC_FMT_U8U8U8U8; 320 case DRM_FORMAT_RGB888: 321 case DRM_FORMAT_BGR888: 322 return AFBC_FMT_U8U8U8; 323 case DRM_FORMAT_RGB565: 324 case DRM_FORMAT_BGR565: 325 return AFBC_FMT_RGB565; 326 default: 327 DRM_DEBUG_KMS("unsupported AFBC format[%08x]\n", format); 328 return -EINVAL; 329 } 330} 331 332static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src, 333 uint32_t dst, bool is_horizontal, 334 int vsu_mode, int *vskiplines) 335{ 336 uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT; 337 338 if (vskiplines) 339 *vskiplines = 0; 340 341 if (is_horizontal) { 342 if (mode == SCALE_UP) 343 val = GET_SCL_FT_BIC(src, dst); 344 else if (mode == SCALE_DOWN) 345 val = GET_SCL_FT_BILI_DN(src, dst); 346 } else { 347 if (mode == SCALE_UP) { 348 if (vsu_mode == SCALE_UP_BIL) 349 val = GET_SCL_FT_BILI_UP(src, dst); 350 else 351 val = GET_SCL_FT_BIC(src, dst); 352 } else if (mode == SCALE_DOWN) { 353 if (vskiplines) { 354 *vskiplines = scl_get_vskiplines(src, dst); 355 val = scl_get_bili_dn_vskip(src, dst, 356 *vskiplines); 357 } else { 358 val = GET_SCL_FT_BILI_DN(src, dst); 359 } 360 } 361 } 362 363 return val; 364} 365 366static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win, 367 uint32_t src_w, uint32_t src_h, uint32_t dst_w, 368 uint32_t dst_h, const struct drm_format_info *info) 369{ 370 uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode; 371 uint16_t cbcr_hor_scl_mode = SCALE_NONE; 372 uint16_t cbcr_ver_scl_mode = SCALE_NONE; 373 bool is_yuv = false; 374 uint16_t cbcr_src_w = src_w / info->hsub; 375 uint16_t cbcr_src_h = src_h / info->vsub; 376 uint16_t vsu_mode; 377 uint16_t lb_mode; 378 uint32_t val; 379 int vskiplines; 380 381 if (info->is_yuv) 382 is_yuv = true; 383 384 if (dst_w > 3840) { 385 DRM_DEV_ERROR(vop->dev, "Maximum dst width (3840) exceeded\n"); 386 return; 387 } 388 389 if (!win->phy->scl->ext) { 390 VOP_SCL_SET(vop, win, scale_yrgb_x, 391 scl_cal_scale2(src_w, dst_w)); 392 VOP_SCL_SET(vop, win, scale_yrgb_y, 393 scl_cal_scale2(src_h, dst_h)); 394 if (is_yuv) { 395 VOP_SCL_SET(vop, win, scale_cbcr_x, 396 scl_cal_scale2(cbcr_src_w, dst_w)); 397 VOP_SCL_SET(vop, win, scale_cbcr_y, 398 scl_cal_scale2(cbcr_src_h, dst_h)); 399 } 400 return; 401 } 402 403 yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w); 404 yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h); 405 406 if (is_yuv) { 407 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w); 408 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h); 409 if (cbcr_hor_scl_mode == SCALE_DOWN) 410 lb_mode = scl_vop_cal_lb_mode(dst_w, true); 411 else 412 lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true); 413 } else { 414 if (yrgb_hor_scl_mode == SCALE_DOWN) 415 lb_mode = scl_vop_cal_lb_mode(dst_w, false); 416 else 417 lb_mode = scl_vop_cal_lb_mode(src_w, false); 418 } 419 420 VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode); 421 if (lb_mode == LB_RGB_3840X2) { 422 if (yrgb_ver_scl_mode != SCALE_NONE) { 423 DRM_DEV_ERROR(vop->dev, "not allow yrgb ver scale\n"); 424 return; 425 } 426 if (cbcr_ver_scl_mode != SCALE_NONE) { 427 DRM_DEV_ERROR(vop->dev, "not allow cbcr ver scale\n"); 428 return; 429 } 430 vsu_mode = SCALE_UP_BIL; 431 } else if (lb_mode == LB_RGB_2560X4) { 432 vsu_mode = SCALE_UP_BIL; 433 } else { 434 vsu_mode = SCALE_UP_BIC; 435 } 436 437 val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w, 438 true, 0, NULL); 439 VOP_SCL_SET(vop, win, scale_yrgb_x, val); 440 val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h, 441 false, vsu_mode, &vskiplines); 442 VOP_SCL_SET(vop, win, scale_yrgb_y, val); 443 444 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4); 445 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2); 446 447 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode); 448 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode); 449 VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL); 450 VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL); 451 VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode); 452 if (is_yuv) { 453 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w, 454 dst_w, true, 0, NULL); 455 VOP_SCL_SET(vop, win, scale_cbcr_x, val); 456 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h, 457 dst_h, false, vsu_mode, &vskiplines); 458 VOP_SCL_SET(vop, win, scale_cbcr_y, val); 459 460 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4); 461 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2); 462 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode); 463 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode); 464 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL); 465 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL); 466 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode); 467 } 468} 469 470static void vop_dsp_hold_valid_irq_enable(struct vop *vop) 471{ 472 unsigned long flags; 473 474 if (WARN_ON(!vop->is_enabled)) 475 return; 476 477 spin_lock_irqsave(&vop->irq_lock, flags); 478 479 VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1); 480 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1); 481 482 spin_unlock_irqrestore(&vop->irq_lock, flags); 483} 484 485static void vop_dsp_hold_valid_irq_disable(struct vop *vop) 486{ 487 unsigned long flags; 488 489 if (WARN_ON(!vop->is_enabled)) 490 return; 491 492 spin_lock_irqsave(&vop->irq_lock, flags); 493 494 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0); 495 496 spin_unlock_irqrestore(&vop->irq_lock, flags); 497} 498 499/* 500 * (1) each frame starts at the start of the Vsync pulse which is signaled by 501 * the "FRAME_SYNC" interrupt. 502 * (2) the active data region of each frame ends at dsp_vact_end 503 * (3) we should program this same number (dsp_vact_end) into dsp_line_frag_num, 504 * to get "LINE_FLAG" interrupt at the end of the active on screen data. 505 * 506 * VOP_INTR_CTRL0.dsp_line_frag_num = VOP_DSP_VACT_ST_END.dsp_vact_end 507 * Interrupts 508 * LINE_FLAG -------------------------------+ 509 * FRAME_SYNC ----+ | 510 * | | 511 * v v 512 * | Vsync | Vbp | Vactive | Vfp | 513 * ^ ^ ^ ^ 514 * | | | | 515 * | | | | 516 * dsp_vs_end ------------+ | | | VOP_DSP_VTOTAL_VS_END 517 * dsp_vact_start --------------+ | | VOP_DSP_VACT_ST_END 518 * dsp_vact_end ----------------------------+ | VOP_DSP_VACT_ST_END 519 * dsp_total -------------------------------------+ VOP_DSP_VTOTAL_VS_END 520 */ 521static bool vop_line_flag_irq_is_enabled(struct vop *vop) 522{ 523 uint32_t line_flag_irq; 524 unsigned long flags; 525 526 spin_lock_irqsave(&vop->irq_lock, flags); 527 528 line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR); 529 530 spin_unlock_irqrestore(&vop->irq_lock, flags); 531 532 return !!line_flag_irq; 533} 534 535static void vop_line_flag_irq_enable(struct vop *vop) 536{ 537 unsigned long flags; 538 539 if (WARN_ON(!vop->is_enabled)) 540 return; 541 542 spin_lock_irqsave(&vop->irq_lock, flags); 543 544 VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1); 545 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1); 546 547 spin_unlock_irqrestore(&vop->irq_lock, flags); 548} 549 550static void vop_line_flag_irq_disable(struct vop *vop) 551{ 552 unsigned long flags; 553 554 if (WARN_ON(!vop->is_enabled)) 555 return; 556 557 spin_lock_irqsave(&vop->irq_lock, flags); 558 559 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0); 560 561 spin_unlock_irqrestore(&vop->irq_lock, flags); 562} 563 564static int vop_core_clks_enable(struct vop *vop) 565{ 566 int ret; 567 568 ret = clk_enable(vop->hclk); 569 if (ret < 0) 570 return ret; 571 572 ret = clk_enable(vop->aclk); 573 if (ret < 0) 574 goto err_disable_hclk; 575 576 return 0; 577 578err_disable_hclk: 579 clk_disable(vop->hclk); 580 return ret; 581} 582 583static void vop_core_clks_disable(struct vop *vop) 584{ 585 clk_disable(vop->aclk); 586 clk_disable(vop->hclk); 587} 588 589static void vop_win_disable(struct vop *vop, const struct vop_win *vop_win) 590{ 591 const struct vop_win_data *win = vop_win->data; 592 593 if (win->phy->scl && win->phy->scl->ext) { 594 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, SCALE_NONE); 595 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, SCALE_NONE); 596 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, SCALE_NONE); 597 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, SCALE_NONE); 598 } 599 600 VOP_WIN_SET(vop, win, enable, 0); 601 vop->win_enabled &= ~BIT(VOP_WIN_TO_INDEX(vop_win)); 602} 603 604static int vop_enable(struct drm_crtc *crtc, struct drm_crtc_state *old_state) 605{ 606 struct vop *vop = to_vop(crtc); 607 int ret, i; 608 609 ret = pm_runtime_resume_and_get(vop->dev); 610 if (ret < 0) { 611 DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret); 612 return ret; 613 } 614 615 ret = vop_core_clks_enable(vop); 616 if (WARN_ON(ret < 0)) 617 goto err_put_pm_runtime; 618 619 ret = clk_enable(vop->dclk); 620 if (WARN_ON(ret < 0)) 621 goto err_disable_core; 622 623 /* 624 * Slave iommu shares power, irq and clock with vop. It was associated 625 * automatically with this master device via common driver code. 626 * Now that we have enabled the clock we attach it to the shared drm 627 * mapping. 628 */ 629 ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev); 630 if (ret) { 631 DRM_DEV_ERROR(vop->dev, 632 "failed to attach dma mapping, %d\n", ret); 633 goto err_disable_dclk; 634 } 635 636 spin_lock(&vop->reg_lock); 637 for (i = 0; i < vop->len; i += 4) 638 writel_relaxed(vop->regsbak[i / 4], vop->regs + i); 639 640 /* 641 * We need to make sure that all windows are disabled before we 642 * enable the crtc. Otherwise we might try to scan from a destroyed 643 * buffer later. 644 * 645 * In the case of enable-after-PSR, we don't need to worry about this 646 * case since the buffer is guaranteed to be valid and disabling the 647 * window will result in screen glitches on PSR exit. 648 */ 649 if (!old_state || !old_state->self_refresh_active) { 650 for (i = 0; i < vop->data->win_size; i++) { 651 struct vop_win *vop_win = &vop->win[i]; 652 653 vop_win_disable(vop, vop_win); 654 } 655 } 656 657 if (vop->data->afbc) { 658 struct rockchip_crtc_state *s; 659 /* 660 * Disable AFBC and forget there was a vop window with AFBC 661 */ 662 VOP_AFBC_SET(vop, enable, 0); 663 s = to_rockchip_crtc_state(crtc->state); 664 s->enable_afbc = false; 665 } 666 667 vop_cfg_done(vop); 668 669 spin_unlock(&vop->reg_lock); 670 671 /* 672 * At here, vop clock & iommu is enable, R/W vop regs would be safe. 673 */ 674 vop->is_enabled = true; 675 676 spin_lock(&vop->reg_lock); 677 678 VOP_REG_SET(vop, common, standby, 1); 679 680 spin_unlock(&vop->reg_lock); 681 682 drm_crtc_vblank_on(crtc); 683 684 return 0; 685 686err_disable_dclk: 687 clk_disable(vop->dclk); 688err_disable_core: 689 vop_core_clks_disable(vop); 690err_put_pm_runtime: 691 pm_runtime_put_sync(vop->dev); 692 return ret; 693} 694 695static void rockchip_drm_set_win_enabled(struct drm_crtc *crtc, bool enabled) 696{ 697 struct vop *vop = to_vop(crtc); 698 int i; 699 700 spin_lock(&vop->reg_lock); 701 702 for (i = 0; i < vop->data->win_size; i++) { 703 struct vop_win *vop_win = &vop->win[i]; 704 const struct vop_win_data *win = vop_win->data; 705 706 VOP_WIN_SET(vop, win, enable, 707 enabled && (vop->win_enabled & BIT(i))); 708 } 709 vop_cfg_done(vop); 710 711 spin_unlock(&vop->reg_lock); 712} 713 714static void vop_crtc_atomic_disable(struct drm_crtc *crtc, 715 struct drm_atomic_state *state) 716{ 717 struct vop *vop = to_vop(crtc); 718 719 WARN_ON(vop->event); 720 721 if (crtc->state->self_refresh_active) 722 rockchip_drm_set_win_enabled(crtc, false); 723 724 if (crtc->state->self_refresh_active) 725 goto out; 726 727 mutex_lock(&vop->vop_lock); 728 729 drm_crtc_vblank_off(crtc); 730 731 /* 732 * Vop standby will take effect at end of current frame, 733 * if dsp hold valid irq happen, it means standby complete. 734 * 735 * we must wait standby complete when we want to disable aclk, 736 * if not, memory bus maybe dead. 737 */ 738 reinit_completion(&vop->dsp_hold_completion); 739 vop_dsp_hold_valid_irq_enable(vop); 740 741 spin_lock(&vop->reg_lock); 742 743 VOP_REG_SET(vop, common, standby, 1); 744 745 spin_unlock(&vop->reg_lock); 746 747 if (!wait_for_completion_timeout(&vop->dsp_hold_completion, 748 msecs_to_jiffies(200))) 749 WARN(1, "%s: timed out waiting for DSP hold", crtc->name); 750 751 vop_dsp_hold_valid_irq_disable(vop); 752 753 vop->is_enabled = false; 754 755 /* 756 * vop standby complete, so iommu detach is safe. 757 */ 758 rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev); 759 760 clk_disable(vop->dclk); 761 vop_core_clks_disable(vop); 762 pm_runtime_put(vop->dev); 763 764 mutex_unlock(&vop->vop_lock); 765 766out: 767 if (crtc->state->event && !crtc->state->active) { 768 spin_lock_irq(&crtc->dev->event_lock); 769 drm_crtc_send_vblank_event(crtc, crtc->state->event); 770 spin_unlock_irq(&crtc->dev->event_lock); 771 772 crtc->state->event = NULL; 773 } 774} 775 776static void vop_plane_destroy(struct drm_plane *plane) 777{ 778 drm_plane_cleanup(plane); 779} 780 781static inline bool rockchip_afbc(u64 modifier) 782{ 783 return modifier == ROCKCHIP_AFBC_MOD; 784} 785 786static bool rockchip_mod_supported(struct drm_plane *plane, 787 u32 format, u64 modifier) 788{ 789 if (modifier == DRM_FORMAT_MOD_LINEAR) 790 return true; 791 792 if (!rockchip_afbc(modifier)) { 793 DRM_DEBUG_KMS("Unsupported format modifier 0x%llx\n", modifier); 794 795 return false; 796 } 797 798 return vop_convert_afbc_format(format) >= 0; 799} 800 801static int vop_plane_atomic_check(struct drm_plane *plane, 802 struct drm_atomic_state *state) 803{ 804 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 805 plane); 806 struct drm_crtc *crtc = new_plane_state->crtc; 807 struct drm_crtc_state *crtc_state; 808 struct drm_framebuffer *fb = new_plane_state->fb; 809 struct vop_win *vop_win = to_vop_win(plane); 810 const struct vop_win_data *win = vop_win->data; 811 int ret; 812 int min_scale = win->phy->scl ? FRAC_16_16(1, 8) : 813 DRM_PLANE_NO_SCALING; 814 int max_scale = win->phy->scl ? FRAC_16_16(8, 1) : 815 DRM_PLANE_NO_SCALING; 816 817 if (!crtc || WARN_ON(!fb)) 818 return 0; 819 820 crtc_state = drm_atomic_get_existing_crtc_state(state, 821 crtc); 822 if (WARN_ON(!crtc_state)) 823 return -EINVAL; 824 825 ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state, 826 min_scale, max_scale, 827 true, true); 828 if (ret) 829 return ret; 830 831 if (!new_plane_state->visible) 832 return 0; 833 834 ret = vop_convert_format(fb->format->format); 835 if (ret < 0) 836 return ret; 837 838 /* 839 * Src.x1 can be odd when do clip, but yuv plane start point 840 * need align with 2 pixel. 841 */ 842 if (fb->format->is_yuv && ((new_plane_state->src.x1 >> 16) % 2)) { 843 DRM_DEBUG_KMS("Invalid Source: Yuv format not support odd xpos\n"); 844 return -EINVAL; 845 } 846 847 if (fb->format->is_yuv && new_plane_state->rotation & DRM_MODE_REFLECT_Y) { 848 DRM_DEBUG_KMS("Invalid Source: Yuv format does not support this rotation\n"); 849 return -EINVAL; 850 } 851 852 if (rockchip_afbc(fb->modifier)) { 853 struct vop *vop = to_vop(crtc); 854 855 if (!vop->data->afbc) { 856 DRM_DEBUG_KMS("vop does not support AFBC\n"); 857 return -EINVAL; 858 } 859 860 ret = vop_convert_afbc_format(fb->format->format); 861 if (ret < 0) 862 return ret; 863 864 if (new_plane_state->src.x1 || new_plane_state->src.y1) { 865 DRM_DEBUG_KMS("AFBC does not support offset display, " \ 866 "xpos=%d, ypos=%d, offset=%d\n", 867 new_plane_state->src.x1, new_plane_state->src.y1, 868 fb->offsets[0]); 869 return -EINVAL; 870 } 871 872 if (new_plane_state->rotation && new_plane_state->rotation != DRM_MODE_ROTATE_0) { 873 DRM_DEBUG_KMS("No rotation support in AFBC, rotation=%d\n", 874 new_plane_state->rotation); 875 return -EINVAL; 876 } 877 } 878 879 return 0; 880} 881 882static void vop_plane_atomic_disable(struct drm_plane *plane, 883 struct drm_atomic_state *state) 884{ 885 struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, 886 plane); 887 struct vop_win *vop_win = to_vop_win(plane); 888 struct vop *vop = to_vop(old_state->crtc); 889 890 if (!old_state->crtc) 891 return; 892 893 spin_lock(&vop->reg_lock); 894 895 vop_win_disable(vop, vop_win); 896 897 spin_unlock(&vop->reg_lock); 898} 899 900static void vop_plane_atomic_update(struct drm_plane *plane, 901 struct drm_atomic_state *state) 902{ 903 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, 904 plane); 905 struct drm_crtc *crtc = new_state->crtc; 906 struct vop_win *vop_win = to_vop_win(plane); 907 const struct vop_win_data *win = vop_win->data; 908 const struct vop_win_yuv2yuv_data *win_yuv2yuv = vop_win->yuv2yuv_data; 909 struct vop *vop = to_vop(new_state->crtc); 910 struct drm_framebuffer *fb = new_state->fb; 911 unsigned int actual_w, actual_h; 912 unsigned int dsp_stx, dsp_sty; 913 uint32_t act_info, dsp_info, dsp_st; 914 struct drm_rect *src = &new_state->src; 915 struct drm_rect *dest = &new_state->dst; 916 struct drm_gem_object *obj, *uv_obj; 917 struct rockchip_gem_object *rk_obj, *rk_uv_obj; 918 unsigned long offset; 919 dma_addr_t dma_addr; 920 uint32_t val; 921 bool rb_swap, uv_swap; 922 int win_index = VOP_WIN_TO_INDEX(vop_win); 923 int format; 924 int is_yuv = fb->format->is_yuv; 925 int i; 926 927 /* 928 * can't update plane when vop is disabled. 929 */ 930 if (WARN_ON(!crtc)) 931 return; 932 933 if (WARN_ON(!vop->is_enabled)) 934 return; 935 936 if (!new_state->visible) { 937 vop_plane_atomic_disable(plane, state); 938 return; 939 } 940 941 obj = fb->obj[0]; 942 rk_obj = to_rockchip_obj(obj); 943 944 actual_w = drm_rect_width(src) >> 16; 945 actual_h = drm_rect_height(src) >> 16; 946 act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff); 947 948 dsp_info = (drm_rect_height(dest) - 1) << 16; 949 dsp_info |= (drm_rect_width(dest) - 1) & 0xffff; 950 951 dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start; 952 dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start; 953 dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); 954 955 offset = (src->x1 >> 16) * fb->format->cpp[0]; 956 offset += (src->y1 >> 16) * fb->pitches[0]; 957 dma_addr = rk_obj->dma_addr + offset + fb->offsets[0]; 958 959 /* 960 * For y-mirroring we need to move address 961 * to the beginning of the last line. 962 */ 963 if (new_state->rotation & DRM_MODE_REFLECT_Y) 964 dma_addr += (actual_h - 1) * fb->pitches[0]; 965 966 format = vop_convert_format(fb->format->format); 967 968 spin_lock(&vop->reg_lock); 969 970 if (rockchip_afbc(fb->modifier)) { 971 int afbc_format = vop_convert_afbc_format(fb->format->format); 972 973 VOP_AFBC_SET(vop, format, afbc_format | AFBC_TILE_16x16); 974 VOP_AFBC_SET(vop, hreg_block_split, 0); 975 VOP_AFBC_SET(vop, win_sel, VOP_WIN_TO_INDEX(vop_win)); 976 VOP_AFBC_SET(vop, hdr_ptr, dma_addr); 977 VOP_AFBC_SET(vop, pic_size, act_info); 978 } 979 980 VOP_WIN_SET(vop, win, format, format); 981 VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4)); 982 VOP_WIN_SET(vop, win, yrgb_mst, dma_addr); 983 VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, y2r_en, is_yuv); 984 VOP_WIN_SET(vop, win, y_mir_en, 985 (new_state->rotation & DRM_MODE_REFLECT_Y) ? 1 : 0); 986 VOP_WIN_SET(vop, win, x_mir_en, 987 (new_state->rotation & DRM_MODE_REFLECT_X) ? 1 : 0); 988 989 if (is_yuv) { 990 int hsub = fb->format->hsub; 991 int vsub = fb->format->vsub; 992 int bpp = fb->format->cpp[1]; 993 994 uv_obj = fb->obj[1]; 995 rk_uv_obj = to_rockchip_obj(uv_obj); 996 997 offset = (src->x1 >> 16) * bpp / hsub; 998 offset += (src->y1 >> 16) * fb->pitches[1] / vsub; 999 1000 dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1]; 1001 VOP_WIN_SET(vop, win, uv_vir, DIV_ROUND_UP(fb->pitches[1], 4)); 1002 VOP_WIN_SET(vop, win, uv_mst, dma_addr); 1003 1004 for (i = 0; i < NUM_YUV2YUV_COEFFICIENTS; i++) { 1005 VOP_WIN_YUV2YUV_COEFFICIENT_SET(vop, 1006 win_yuv2yuv, 1007 y2r_coefficients[i], 1008 bt601_yuv2rgb[i]); 1009 } 1010 1011 uv_swap = has_uv_swapped(fb->format->format); 1012 VOP_WIN_SET(vop, win, uv_swap, uv_swap); 1013 } 1014 1015 if (win->phy->scl) 1016 scl_vop_cal_scl_fac(vop, win, actual_w, actual_h, 1017 drm_rect_width(dest), drm_rect_height(dest), 1018 fb->format); 1019 1020 VOP_WIN_SET(vop, win, act_info, act_info); 1021 VOP_WIN_SET(vop, win, dsp_info, dsp_info); 1022 VOP_WIN_SET(vop, win, dsp_st, dsp_st); 1023 1024 rb_swap = has_rb_swapped(vop->data->version, fb->format->format); 1025 VOP_WIN_SET(vop, win, rb_swap, rb_swap); 1026 1027 /* 1028 * Blending win0 with the background color doesn't seem to work 1029 * correctly. We only get the background color, no matter the contents 1030 * of the win0 framebuffer. However, blending pre-multiplied color 1031 * with the default opaque black default background color is a no-op, 1032 * so we can just disable blending to get the correct result. 1033 */ 1034 if (fb->format->has_alpha && win_index > 0) { 1035 VOP_WIN_SET(vop, win, dst_alpha_ctl, 1036 DST_FACTOR_M0(ALPHA_SRC_INVERSE)); 1037 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) | 1038 SRC_ALPHA_M0(ALPHA_STRAIGHT) | 1039 SRC_BLEND_M0(ALPHA_PER_PIX) | 1040 SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) | 1041 SRC_FACTOR_M0(ALPHA_ONE); 1042 VOP_WIN_SET(vop, win, src_alpha_ctl, val); 1043 1044 VOP_WIN_SET(vop, win, alpha_pre_mul, ALPHA_SRC_PRE_MUL); 1045 VOP_WIN_SET(vop, win, alpha_mode, ALPHA_PER_PIX); 1046 VOP_WIN_SET(vop, win, alpha_en, 1); 1047 } else { 1048 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0)); 1049 VOP_WIN_SET(vop, win, alpha_en, 0); 1050 } 1051 1052 VOP_WIN_SET(vop, win, enable, 1); 1053 vop->win_enabled |= BIT(win_index); 1054 spin_unlock(&vop->reg_lock); 1055} 1056 1057static int vop_plane_atomic_async_check(struct drm_plane *plane, 1058 struct drm_atomic_state *state) 1059{ 1060 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 1061 plane); 1062 struct vop_win *vop_win = to_vop_win(plane); 1063 const struct vop_win_data *win = vop_win->data; 1064 int min_scale = win->phy->scl ? FRAC_16_16(1, 8) : 1065 DRM_PLANE_NO_SCALING; 1066 int max_scale = win->phy->scl ? FRAC_16_16(8, 1) : 1067 DRM_PLANE_NO_SCALING; 1068 struct drm_crtc_state *crtc_state; 1069 1070 if (plane != new_plane_state->crtc->cursor) 1071 return -EINVAL; 1072 1073 if (!plane->state) 1074 return -EINVAL; 1075 1076 if (!plane->state->fb) 1077 return -EINVAL; 1078 1079 if (state) 1080 crtc_state = drm_atomic_get_existing_crtc_state(state, 1081 new_plane_state->crtc); 1082 else /* Special case for asynchronous cursor updates. */ 1083 crtc_state = plane->crtc->state; 1084 1085 return drm_atomic_helper_check_plane_state(plane->state, crtc_state, 1086 min_scale, max_scale, 1087 true, true); 1088} 1089 1090static void vop_plane_atomic_async_update(struct drm_plane *plane, 1091 struct drm_atomic_state *state) 1092{ 1093 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, 1094 plane); 1095 struct vop *vop = to_vop(plane->state->crtc); 1096 struct drm_framebuffer *old_fb = plane->state->fb; 1097 1098 plane->state->crtc_x = new_state->crtc_x; 1099 plane->state->crtc_y = new_state->crtc_y; 1100 plane->state->crtc_h = new_state->crtc_h; 1101 plane->state->crtc_w = new_state->crtc_w; 1102 plane->state->src_x = new_state->src_x; 1103 plane->state->src_y = new_state->src_y; 1104 plane->state->src_h = new_state->src_h; 1105 plane->state->src_w = new_state->src_w; 1106 swap(plane->state->fb, new_state->fb); 1107 1108 if (vop->is_enabled) { 1109 vop_plane_atomic_update(plane, state); 1110 spin_lock(&vop->reg_lock); 1111 vop_cfg_done(vop); 1112 spin_unlock(&vop->reg_lock); 1113 1114 /* 1115 * A scanout can still be occurring, so we can't drop the 1116 * reference to the old framebuffer. To solve this we get a 1117 * reference to old_fb and set a worker to release it later. 1118 * FIXME: if we perform 500 async_update calls before the 1119 * vblank, then we can have 500 different framebuffers waiting 1120 * to be released. 1121 */ 1122 if (old_fb && plane->state->fb != old_fb) { 1123 drm_framebuffer_get(old_fb); 1124 WARN_ON(drm_crtc_vblank_get(plane->state->crtc) != 0); 1125 drm_flip_work_queue(&vop->fb_unref_work, old_fb); 1126 set_bit(VOP_PENDING_FB_UNREF, &vop->pending); 1127 } 1128 } 1129} 1130 1131static const struct drm_plane_helper_funcs plane_helper_funcs = { 1132 .atomic_check = vop_plane_atomic_check, 1133 .atomic_update = vop_plane_atomic_update, 1134 .atomic_disable = vop_plane_atomic_disable, 1135 .atomic_async_check = vop_plane_atomic_async_check, 1136 .atomic_async_update = vop_plane_atomic_async_update, 1137}; 1138 1139static const struct drm_plane_funcs vop_plane_funcs = { 1140 .update_plane = drm_atomic_helper_update_plane, 1141 .disable_plane = drm_atomic_helper_disable_plane, 1142 .destroy = vop_plane_destroy, 1143 .reset = drm_atomic_helper_plane_reset, 1144 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 1145 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 1146 .format_mod_supported = rockchip_mod_supported, 1147}; 1148 1149static int vop_crtc_enable_vblank(struct drm_crtc *crtc) 1150{ 1151 struct vop *vop = to_vop(crtc); 1152 unsigned long flags; 1153 1154 if (WARN_ON(!vop->is_enabled)) 1155 return -EPERM; 1156 1157 spin_lock_irqsave(&vop->irq_lock, flags); 1158 1159 VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1); 1160 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1); 1161 1162 spin_unlock_irqrestore(&vop->irq_lock, flags); 1163 1164 return 0; 1165} 1166 1167static void vop_crtc_disable_vblank(struct drm_crtc *crtc) 1168{ 1169 struct vop *vop = to_vop(crtc); 1170 unsigned long flags; 1171 1172 if (WARN_ON(!vop->is_enabled)) 1173 return; 1174 1175 spin_lock_irqsave(&vop->irq_lock, flags); 1176 1177 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0); 1178 1179 spin_unlock_irqrestore(&vop->irq_lock, flags); 1180} 1181 1182static enum drm_mode_status vop_crtc_mode_valid(struct drm_crtc *crtc, 1183 const struct drm_display_mode *mode) 1184{ 1185 struct vop *vop = to_vop(crtc); 1186 1187 if (vop->data->max_output.width && mode->hdisplay > vop->data->max_output.width) 1188 return MODE_BAD_HVALUE; 1189 1190 return MODE_OK; 1191} 1192 1193static bool vop_crtc_mode_fixup(struct drm_crtc *crtc, 1194 const struct drm_display_mode *mode, 1195 struct drm_display_mode *adjusted_mode) 1196{ 1197 struct vop *vop = to_vop(crtc); 1198 unsigned long rate; 1199 1200 /* 1201 * Clock craziness. 1202 * 1203 * Key points: 1204 * 1205 * - DRM works in kHz. 1206 * - Clock framework works in Hz. 1207 * - Rockchip's clock driver picks the clock rate that is the 1208 * same _OR LOWER_ than the one requested. 1209 * 1210 * Action plan: 1211 * 1212 * 1. Try to set the exact rate first, and confirm the clock framework 1213 * can provide it. 1214 * 1215 * 2. If the clock framework cannot provide the exact rate, we should 1216 * add 999 Hz to the requested rate. That way if the clock we need 1217 * is 60000001 Hz (~60 MHz) and DRM tells us to make 60000 kHz then 1218 * the clock framework will actually give us the right clock. 1219 * 1220 * 3. Get the clock framework to round the rate for us to tell us 1221 * what it will actually make. 1222 * 1223 * 4. Store the rounded up rate so that we don't need to worry about 1224 * this in the actual clk_set_rate(). 1225 */ 1226 rate = clk_round_rate(vop->dclk, adjusted_mode->clock * 1000); 1227 if (rate / 1000 != adjusted_mode->clock) 1228 rate = clk_round_rate(vop->dclk, 1229 adjusted_mode->clock * 1000 + 999); 1230 adjusted_mode->clock = DIV_ROUND_UP(rate, 1000); 1231 1232 return true; 1233} 1234 1235static bool vop_dsp_lut_is_enabled(struct vop *vop) 1236{ 1237 return vop_read_reg(vop, 0, &vop->data->common->dsp_lut_en); 1238} 1239 1240static u32 vop_lut_buffer_index(struct vop *vop) 1241{ 1242 return vop_read_reg(vop, 0, &vop->data->common->lut_buffer_index); 1243} 1244 1245static void vop_crtc_write_gamma_lut(struct vop *vop, struct drm_crtc *crtc) 1246{ 1247 struct drm_color_lut *lut = crtc->state->gamma_lut->data; 1248 unsigned int i, bpc = ilog2(vop->data->lut_size); 1249 1250 for (i = 0; i < crtc->gamma_size; i++) { 1251 u32 word; 1252 1253 word = (drm_color_lut_extract(lut[i].red, bpc) << (2 * bpc)) | 1254 (drm_color_lut_extract(lut[i].green, bpc) << bpc) | 1255 drm_color_lut_extract(lut[i].blue, bpc); 1256 writel(word, vop->lut_regs + i * 4); 1257 } 1258} 1259 1260static void vop_crtc_gamma_set(struct vop *vop, struct drm_crtc *crtc, 1261 struct drm_crtc_state *old_state) 1262{ 1263 struct drm_crtc_state *state = crtc->state; 1264 unsigned int idle; 1265 u32 lut_idx, old_idx; 1266 int ret; 1267 1268 if (!vop->lut_regs) 1269 return; 1270 1271 if (!state->gamma_lut || !VOP_HAS_REG(vop, common, update_gamma_lut)) { 1272 /* 1273 * To disable gamma (gamma_lut is null) or to write 1274 * an update to the LUT, clear dsp_lut_en. 1275 */ 1276 spin_lock(&vop->reg_lock); 1277 VOP_REG_SET(vop, common, dsp_lut_en, 0); 1278 vop_cfg_done(vop); 1279 spin_unlock(&vop->reg_lock); 1280 1281 /* 1282 * In order to write the LUT to the internal memory, 1283 * we need to first make sure the dsp_lut_en bit is cleared. 1284 */ 1285 ret = readx_poll_timeout(vop_dsp_lut_is_enabled, vop, 1286 idle, !idle, 5, 30 * 1000); 1287 if (ret) { 1288 DRM_DEV_ERROR(vop->dev, "display LUT RAM enable timeout!\n"); 1289 return; 1290 } 1291 1292 if (!state->gamma_lut) 1293 return; 1294 } else { 1295 /* 1296 * On RK3399 the gamma LUT can updated without clearing dsp_lut_en, 1297 * by setting update_gamma_lut then waiting for lut_buffer_index change 1298 */ 1299 old_idx = vop_lut_buffer_index(vop); 1300 } 1301 1302 spin_lock(&vop->reg_lock); 1303 vop_crtc_write_gamma_lut(vop, crtc); 1304 VOP_REG_SET(vop, common, dsp_lut_en, 1); 1305 VOP_REG_SET(vop, common, update_gamma_lut, 1); 1306 vop_cfg_done(vop); 1307 spin_unlock(&vop->reg_lock); 1308 1309 if (VOP_HAS_REG(vop, common, update_gamma_lut)) { 1310 ret = readx_poll_timeout(vop_lut_buffer_index, vop, 1311 lut_idx, lut_idx != old_idx, 5, 30 * 1000); 1312 if (ret) { 1313 DRM_DEV_ERROR(vop->dev, "gamma LUT update timeout!\n"); 1314 return; 1315 } 1316 1317 /* 1318 * update_gamma_lut is auto cleared by HW, but write 0 to clear the bit 1319 * in our backup of the regs. 1320 */ 1321 spin_lock(&vop->reg_lock); 1322 VOP_REG_SET(vop, common, update_gamma_lut, 0); 1323 spin_unlock(&vop->reg_lock); 1324 } 1325} 1326 1327static void vop_crtc_atomic_begin(struct drm_crtc *crtc, 1328 struct drm_atomic_state *state) 1329{ 1330 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 1331 crtc); 1332 struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state, 1333 crtc); 1334 struct vop *vop = to_vop(crtc); 1335 1336 /* 1337 * Only update GAMMA if the 'active' flag is not changed, 1338 * otherwise it's updated by .atomic_enable. 1339 */ 1340 if (crtc_state->color_mgmt_changed && 1341 !crtc_state->active_changed) 1342 vop_crtc_gamma_set(vop, crtc, old_crtc_state); 1343} 1344 1345static void vop_crtc_atomic_enable(struct drm_crtc *crtc, 1346 struct drm_atomic_state *state) 1347{ 1348 struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state, 1349 crtc); 1350 struct vop *vop = to_vop(crtc); 1351 const struct vop_data *vop_data = vop->data; 1352 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state); 1353 struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode; 1354 u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start; 1355 u16 hdisplay = adjusted_mode->hdisplay; 1356 u16 htotal = adjusted_mode->htotal; 1357 u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start; 1358 u16 hact_end = hact_st + hdisplay; 1359 u16 vdisplay = adjusted_mode->vdisplay; 1360 u16 vtotal = adjusted_mode->vtotal; 1361 u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start; 1362 u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start; 1363 u16 vact_end = vact_st + vdisplay; 1364 uint32_t pin_pol, val; 1365 int dither_bpc = s->output_bpc ? s->output_bpc : 10; 1366 int ret; 1367 1368 if (old_state && old_state->self_refresh_active) { 1369 drm_crtc_vblank_on(crtc); 1370 rockchip_drm_set_win_enabled(crtc, true); 1371 return; 1372 } 1373 1374 mutex_lock(&vop->vop_lock); 1375 1376 WARN_ON(vop->event); 1377 1378 ret = vop_enable(crtc, old_state); 1379 if (ret) { 1380 mutex_unlock(&vop->vop_lock); 1381 DRM_DEV_ERROR(vop->dev, "Failed to enable vop (%d)\n", ret); 1382 return; 1383 } 1384 pin_pol = (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) ? 1385 BIT(HSYNC_POSITIVE) : 0; 1386 pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) ? 1387 BIT(VSYNC_POSITIVE) : 0; 1388 VOP_REG_SET(vop, output, pin_pol, pin_pol); 1389 VOP_REG_SET(vop, output, mipi_dual_channel_en, 0); 1390 1391 switch (s->output_type) { 1392 case DRM_MODE_CONNECTOR_LVDS: 1393 VOP_REG_SET(vop, output, rgb_dclk_pol, 1); 1394 VOP_REG_SET(vop, output, rgb_pin_pol, pin_pol); 1395 VOP_REG_SET(vop, output, rgb_en, 1); 1396 break; 1397 case DRM_MODE_CONNECTOR_eDP: 1398 VOP_REG_SET(vop, output, edp_dclk_pol, 1); 1399 VOP_REG_SET(vop, output, edp_pin_pol, pin_pol); 1400 VOP_REG_SET(vop, output, edp_en, 1); 1401 break; 1402 case DRM_MODE_CONNECTOR_HDMIA: 1403 VOP_REG_SET(vop, output, hdmi_dclk_pol, 1); 1404 VOP_REG_SET(vop, output, hdmi_pin_pol, pin_pol); 1405 VOP_REG_SET(vop, output, hdmi_en, 1); 1406 break; 1407 case DRM_MODE_CONNECTOR_DSI: 1408 VOP_REG_SET(vop, output, mipi_dclk_pol, 1); 1409 VOP_REG_SET(vop, output, mipi_pin_pol, pin_pol); 1410 VOP_REG_SET(vop, output, mipi_en, 1); 1411 VOP_REG_SET(vop, output, mipi_dual_channel_en, 1412 !!(s->output_flags & ROCKCHIP_OUTPUT_DSI_DUAL)); 1413 break; 1414 case DRM_MODE_CONNECTOR_DisplayPort: 1415 VOP_REG_SET(vop, output, dp_dclk_pol, 0); 1416 VOP_REG_SET(vop, output, dp_pin_pol, pin_pol); 1417 VOP_REG_SET(vop, output, dp_en, 1); 1418 break; 1419 default: 1420 DRM_DEV_ERROR(vop->dev, "unsupported connector_type [%d]\n", 1421 s->output_type); 1422 } 1423 1424 /* 1425 * if vop is not support RGB10 output, need force RGB10 to RGB888. 1426 */ 1427 if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && 1428 !(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10)) 1429 s->output_mode = ROCKCHIP_OUT_MODE_P888; 1430 1431 if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && dither_bpc <= 8) 1432 VOP_REG_SET(vop, common, pre_dither_down, 1); 1433 else 1434 VOP_REG_SET(vop, common, pre_dither_down, 0); 1435 1436 if (dither_bpc == 6) { 1437 VOP_REG_SET(vop, common, dither_down_sel, DITHER_DOWN_ALLEGRO); 1438 VOP_REG_SET(vop, common, dither_down_mode, RGB888_TO_RGB666); 1439 VOP_REG_SET(vop, common, dither_down_en, 1); 1440 } else { 1441 VOP_REG_SET(vop, common, dither_down_en, 0); 1442 } 1443 1444 VOP_REG_SET(vop, common, out_mode, s->output_mode); 1445 1446 VOP_REG_SET(vop, modeset, htotal_pw, (htotal << 16) | hsync_len); 1447 val = hact_st << 16; 1448 val |= hact_end; 1449 VOP_REG_SET(vop, modeset, hact_st_end, val); 1450 VOP_REG_SET(vop, modeset, hpost_st_end, val); 1451 1452 VOP_REG_SET(vop, modeset, vtotal_pw, (vtotal << 16) | vsync_len); 1453 val = vact_st << 16; 1454 val |= vact_end; 1455 VOP_REG_SET(vop, modeset, vact_st_end, val); 1456 VOP_REG_SET(vop, modeset, vpost_st_end, val); 1457 1458 VOP_REG_SET(vop, intr, line_flag_num[0], vact_end); 1459 1460 clk_set_rate(vop->dclk, adjusted_mode->clock * 1000); 1461 1462 VOP_REG_SET(vop, common, standby, 0); 1463 mutex_unlock(&vop->vop_lock); 1464 1465 /* 1466 * If we have a GAMMA LUT in the state, then let's make sure 1467 * it's updated. We might be coming out of suspend, 1468 * which means the LUT internal memory needs to be re-written. 1469 */ 1470 if (crtc->state->gamma_lut) 1471 vop_crtc_gamma_set(vop, crtc, old_state); 1472} 1473 1474static bool vop_fs_irq_is_pending(struct vop *vop) 1475{ 1476 return VOP_INTR_GET_TYPE(vop, status, FS_INTR); 1477} 1478 1479static void vop_wait_for_irq_handler(struct vop *vop) 1480{ 1481 bool pending; 1482 int ret; 1483 1484 /* 1485 * Spin until frame start interrupt status bit goes low, which means 1486 * that interrupt handler was invoked and cleared it. The timeout of 1487 * 10 msecs is really too long, but it is just a safety measure if 1488 * something goes really wrong. The wait will only happen in the very 1489 * unlikely case of a vblank happening exactly at the same time and 1490 * shouldn't exceed microseconds range. 1491 */ 1492 ret = readx_poll_timeout_atomic(vop_fs_irq_is_pending, vop, pending, 1493 !pending, 0, 10 * 1000); 1494 if (ret) 1495 DRM_DEV_ERROR(vop->dev, "VOP vblank IRQ stuck for 10 ms\n"); 1496 1497 synchronize_irq(vop->irq); 1498} 1499 1500static int vop_crtc_atomic_check(struct drm_crtc *crtc, 1501 struct drm_atomic_state *state) 1502{ 1503 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 1504 crtc); 1505 struct vop *vop = to_vop(crtc); 1506 struct drm_plane *plane; 1507 struct drm_plane_state *plane_state; 1508 struct rockchip_crtc_state *s; 1509 int afbc_planes = 0; 1510 1511 if (vop->lut_regs && crtc_state->color_mgmt_changed && 1512 crtc_state->gamma_lut) { 1513 unsigned int len; 1514 1515 len = drm_color_lut_size(crtc_state->gamma_lut); 1516 if (len != crtc->gamma_size) { 1517 DRM_DEBUG_KMS("Invalid LUT size; got %d, expected %d\n", 1518 len, crtc->gamma_size); 1519 return -EINVAL; 1520 } 1521 } 1522 1523 drm_atomic_crtc_state_for_each_plane(plane, crtc_state) { 1524 plane_state = 1525 drm_atomic_get_plane_state(crtc_state->state, plane); 1526 if (IS_ERR(plane_state)) { 1527 DRM_DEBUG_KMS("Cannot get plane state for plane %s\n", 1528 plane->name); 1529 return PTR_ERR(plane_state); 1530 } 1531 1532 if (drm_is_afbc(plane_state->fb->modifier)) 1533 ++afbc_planes; 1534 } 1535 1536 if (afbc_planes > 1) { 1537 DRM_DEBUG_KMS("Invalid number of AFBC planes; got %d, expected at most 1\n", afbc_planes); 1538 return -EINVAL; 1539 } 1540 1541 s = to_rockchip_crtc_state(crtc_state); 1542 s->enable_afbc = afbc_planes > 0; 1543 1544 return 0; 1545} 1546 1547static void vop_crtc_atomic_flush(struct drm_crtc *crtc, 1548 struct drm_atomic_state *state) 1549{ 1550 struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state, 1551 crtc); 1552 struct drm_atomic_state *old_state = old_crtc_state->state; 1553 struct drm_plane_state *old_plane_state, *new_plane_state; 1554 struct vop *vop = to_vop(crtc); 1555 struct drm_plane *plane; 1556 struct rockchip_crtc_state *s; 1557 int i; 1558 1559 if (WARN_ON(!vop->is_enabled)) 1560 return; 1561 1562 spin_lock(&vop->reg_lock); 1563 1564 /* Enable AFBC if there is some AFBC window, disable otherwise. */ 1565 s = to_rockchip_crtc_state(crtc->state); 1566 VOP_AFBC_SET(vop, enable, s->enable_afbc); 1567 vop_cfg_done(vop); 1568 1569 spin_unlock(&vop->reg_lock); 1570 1571 /* 1572 * There is a (rather unlikely) possiblity that a vblank interrupt 1573 * fired before we set the cfg_done bit. To avoid spuriously 1574 * signalling flip completion we need to wait for it to finish. 1575 */ 1576 vop_wait_for_irq_handler(vop); 1577 1578 spin_lock_irq(&crtc->dev->event_lock); 1579 if (crtc->state->event) { 1580 WARN_ON(drm_crtc_vblank_get(crtc) != 0); 1581 WARN_ON(vop->event); 1582 1583 vop->event = crtc->state->event; 1584 crtc->state->event = NULL; 1585 } 1586 spin_unlock_irq(&crtc->dev->event_lock); 1587 1588 for_each_oldnew_plane_in_state(old_state, plane, old_plane_state, 1589 new_plane_state, i) { 1590 if (!old_plane_state->fb) 1591 continue; 1592 1593 if (old_plane_state->fb == new_plane_state->fb) 1594 continue; 1595 1596 drm_framebuffer_get(old_plane_state->fb); 1597 WARN_ON(drm_crtc_vblank_get(crtc) != 0); 1598 drm_flip_work_queue(&vop->fb_unref_work, old_plane_state->fb); 1599 set_bit(VOP_PENDING_FB_UNREF, &vop->pending); 1600 } 1601} 1602 1603static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = { 1604 .mode_valid = vop_crtc_mode_valid, 1605 .mode_fixup = vop_crtc_mode_fixup, 1606 .atomic_check = vop_crtc_atomic_check, 1607 .atomic_begin = vop_crtc_atomic_begin, 1608 .atomic_flush = vop_crtc_atomic_flush, 1609 .atomic_enable = vop_crtc_atomic_enable, 1610 .atomic_disable = vop_crtc_atomic_disable, 1611}; 1612 1613static void vop_crtc_destroy(struct drm_crtc *crtc) 1614{ 1615 drm_crtc_cleanup(crtc); 1616} 1617 1618static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc) 1619{ 1620 struct rockchip_crtc_state *rockchip_state; 1621 1622 if (WARN_ON(!crtc->state)) 1623 return NULL; 1624 1625 rockchip_state = kmemdup(to_rockchip_crtc_state(crtc->state), 1626 sizeof(*rockchip_state), GFP_KERNEL); 1627 if (!rockchip_state) 1628 return NULL; 1629 1630 __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base); 1631 return &rockchip_state->base; 1632} 1633 1634static void vop_crtc_destroy_state(struct drm_crtc *crtc, 1635 struct drm_crtc_state *state) 1636{ 1637 struct rockchip_crtc_state *s = to_rockchip_crtc_state(state); 1638 1639 __drm_atomic_helper_crtc_destroy_state(&s->base); 1640 kfree(s); 1641} 1642 1643static void vop_crtc_reset(struct drm_crtc *crtc) 1644{ 1645 struct rockchip_crtc_state *crtc_state = 1646 kzalloc(sizeof(*crtc_state), GFP_KERNEL); 1647 1648 if (crtc->state) 1649 vop_crtc_destroy_state(crtc, crtc->state); 1650 1651 if (crtc_state) 1652 __drm_atomic_helper_crtc_reset(crtc, &crtc_state->base); 1653 else 1654 __drm_atomic_helper_crtc_reset(crtc, NULL); 1655} 1656 1657#ifdef CONFIG_DRM_ANALOGIX_DP 1658static struct drm_connector *vop_get_edp_connector(struct vop *vop) 1659{ 1660 struct drm_connector *connector; 1661 struct drm_connector_list_iter conn_iter; 1662 1663 drm_connector_list_iter_begin(vop->drm_dev, &conn_iter); 1664 drm_for_each_connector_iter(connector, &conn_iter) { 1665 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1666 drm_connector_list_iter_end(&conn_iter); 1667 return connector; 1668 } 1669 } 1670 drm_connector_list_iter_end(&conn_iter); 1671 1672 return NULL; 1673} 1674 1675static int vop_crtc_set_crc_source(struct drm_crtc *crtc, 1676 const char *source_name) 1677{ 1678 struct vop *vop = to_vop(crtc); 1679 struct drm_connector *connector; 1680 int ret; 1681 1682 connector = vop_get_edp_connector(vop); 1683 if (!connector) 1684 return -EINVAL; 1685 1686 if (source_name && strcmp(source_name, "auto") == 0) 1687 ret = analogix_dp_start_crc(connector); 1688 else if (!source_name) 1689 ret = analogix_dp_stop_crc(connector); 1690 else 1691 ret = -EINVAL; 1692 1693 return ret; 1694} 1695 1696static int 1697vop_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name, 1698 size_t *values_cnt) 1699{ 1700 if (source_name && strcmp(source_name, "auto") != 0) 1701 return -EINVAL; 1702 1703 *values_cnt = 3; 1704 return 0; 1705} 1706 1707#else 1708static int vop_crtc_set_crc_source(struct drm_crtc *crtc, 1709 const char *source_name) 1710{ 1711 return -ENODEV; 1712} 1713 1714static int 1715vop_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name, 1716 size_t *values_cnt) 1717{ 1718 return -ENODEV; 1719} 1720#endif 1721 1722static const struct drm_crtc_funcs vop_crtc_funcs = { 1723 .set_config = drm_atomic_helper_set_config, 1724 .page_flip = drm_atomic_helper_page_flip, 1725 .destroy = vop_crtc_destroy, 1726 .reset = vop_crtc_reset, 1727 .atomic_duplicate_state = vop_crtc_duplicate_state, 1728 .atomic_destroy_state = vop_crtc_destroy_state, 1729 .enable_vblank = vop_crtc_enable_vblank, 1730 .disable_vblank = vop_crtc_disable_vblank, 1731 .set_crc_source = vop_crtc_set_crc_source, 1732 .verify_crc_source = vop_crtc_verify_crc_source, 1733}; 1734 1735static void vop_fb_unref_worker(struct drm_flip_work *work, void *val) 1736{ 1737 struct vop *vop = container_of(work, struct vop, fb_unref_work); 1738 struct drm_framebuffer *fb = val; 1739 1740 drm_crtc_vblank_put(&vop->crtc); 1741 drm_framebuffer_put(fb); 1742} 1743 1744static void vop_handle_vblank(struct vop *vop) 1745{ 1746 struct drm_device *drm = vop->drm_dev; 1747 struct drm_crtc *crtc = &vop->crtc; 1748 1749 spin_lock(&drm->event_lock); 1750 if (vop->event) { 1751 drm_crtc_send_vblank_event(crtc, vop->event); 1752 drm_crtc_vblank_put(crtc); 1753 vop->event = NULL; 1754 } 1755 spin_unlock(&drm->event_lock); 1756 1757 if (test_and_clear_bit(VOP_PENDING_FB_UNREF, &vop->pending)) 1758 drm_flip_work_commit(&vop->fb_unref_work, system_unbound_wq); 1759} 1760 1761static irqreturn_t vop_isr(int irq, void *data) 1762{ 1763 struct vop *vop = data; 1764 struct drm_crtc *crtc = &vop->crtc; 1765 uint32_t active_irqs; 1766 int ret = IRQ_NONE; 1767 1768 /* 1769 * The irq is shared with the iommu. If the runtime-pm state of the 1770 * vop-device is disabled the irq has to be targeted at the iommu. 1771 */ 1772 if (!pm_runtime_get_if_in_use(vop->dev)) 1773 return IRQ_NONE; 1774 1775 if (vop_core_clks_enable(vop)) { 1776 DRM_DEV_ERROR_RATELIMITED(vop->dev, "couldn't enable clocks\n"); 1777 goto out; 1778 } 1779 1780 /* 1781 * interrupt register has interrupt status, enable and clear bits, we 1782 * must hold irq_lock to avoid a race with enable/disable_vblank(). 1783 */ 1784 spin_lock(&vop->irq_lock); 1785 1786 active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK); 1787 /* Clear all active interrupt sources */ 1788 if (active_irqs) 1789 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1); 1790 1791 spin_unlock(&vop->irq_lock); 1792 1793 /* This is expected for vop iommu irqs, since the irq is shared */ 1794 if (!active_irqs) 1795 goto out_disable; 1796 1797 if (active_irqs & DSP_HOLD_VALID_INTR) { 1798 complete(&vop->dsp_hold_completion); 1799 active_irqs &= ~DSP_HOLD_VALID_INTR; 1800 ret = IRQ_HANDLED; 1801 } 1802 1803 if (active_irqs & LINE_FLAG_INTR) { 1804 complete(&vop->line_flag_completion); 1805 active_irqs &= ~LINE_FLAG_INTR; 1806 ret = IRQ_HANDLED; 1807 } 1808 1809 if (active_irqs & FS_INTR) { 1810 drm_crtc_handle_vblank(crtc); 1811 vop_handle_vblank(vop); 1812 active_irqs &= ~FS_INTR; 1813 ret = IRQ_HANDLED; 1814 } 1815 1816 /* Unhandled irqs are spurious. */ 1817 if (active_irqs) 1818 DRM_DEV_ERROR(vop->dev, "Unknown VOP IRQs: %#02x\n", 1819 active_irqs); 1820 1821out_disable: 1822 vop_core_clks_disable(vop); 1823out: 1824 pm_runtime_put(vop->dev); 1825 return ret; 1826} 1827 1828static void vop_plane_add_properties(struct drm_plane *plane, 1829 const struct vop_win_data *win_data) 1830{ 1831 unsigned int flags = 0; 1832 1833 flags |= VOP_WIN_HAS_REG(win_data, x_mir_en) ? DRM_MODE_REFLECT_X : 0; 1834 flags |= VOP_WIN_HAS_REG(win_data, y_mir_en) ? DRM_MODE_REFLECT_Y : 0; 1835 if (flags) 1836 drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0, 1837 DRM_MODE_ROTATE_0 | flags); 1838} 1839 1840static int vop_create_crtc(struct vop *vop) 1841{ 1842 const struct vop_data *vop_data = vop->data; 1843 struct device *dev = vop->dev; 1844 struct drm_device *drm_dev = vop->drm_dev; 1845 struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp; 1846 struct drm_crtc *crtc = &vop->crtc; 1847 struct device_node *port; 1848 int ret; 1849 int i; 1850 1851 /* 1852 * Create drm_plane for primary and cursor planes first, since we need 1853 * to pass them to drm_crtc_init_with_planes, which sets the 1854 * "possible_crtcs" to the newly initialized crtc. 1855 */ 1856 for (i = 0; i < vop_data->win_size; i++) { 1857 struct vop_win *vop_win = &vop->win[i]; 1858 const struct vop_win_data *win_data = vop_win->data; 1859 1860 if (win_data->type != DRM_PLANE_TYPE_PRIMARY && 1861 win_data->type != DRM_PLANE_TYPE_CURSOR) 1862 continue; 1863 1864 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, 1865 0, &vop_plane_funcs, 1866 win_data->phy->data_formats, 1867 win_data->phy->nformats, 1868 win_data->phy->format_modifiers, 1869 win_data->type, NULL); 1870 if (ret) { 1871 DRM_DEV_ERROR(vop->dev, "failed to init plane %d\n", 1872 ret); 1873 goto err_cleanup_planes; 1874 } 1875 1876 plane = &vop_win->base; 1877 drm_plane_helper_add(plane, &plane_helper_funcs); 1878 vop_plane_add_properties(plane, win_data); 1879 if (plane->type == DRM_PLANE_TYPE_PRIMARY) 1880 primary = plane; 1881 else if (plane->type == DRM_PLANE_TYPE_CURSOR) 1882 cursor = plane; 1883 } 1884 1885 ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor, 1886 &vop_crtc_funcs, NULL); 1887 if (ret) 1888 goto err_cleanup_planes; 1889 1890 drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs); 1891 if (vop->lut_regs) { 1892 drm_mode_crtc_set_gamma_size(crtc, vop_data->lut_size); 1893 drm_crtc_enable_color_mgmt(crtc, 0, false, vop_data->lut_size); 1894 } 1895 1896 /* 1897 * Create drm_planes for overlay windows with possible_crtcs restricted 1898 * to the newly created crtc. 1899 */ 1900 for (i = 0; i < vop_data->win_size; i++) { 1901 struct vop_win *vop_win = &vop->win[i]; 1902 const struct vop_win_data *win_data = vop_win->data; 1903 unsigned long possible_crtcs = drm_crtc_mask(crtc); 1904 1905 if (win_data->type != DRM_PLANE_TYPE_OVERLAY) 1906 continue; 1907 1908 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, 1909 possible_crtcs, 1910 &vop_plane_funcs, 1911 win_data->phy->data_formats, 1912 win_data->phy->nformats, 1913 win_data->phy->format_modifiers, 1914 win_data->type, NULL); 1915 if (ret) { 1916 DRM_DEV_ERROR(vop->dev, "failed to init overlay %d\n", 1917 ret); 1918 goto err_cleanup_crtc; 1919 } 1920 drm_plane_helper_add(&vop_win->base, &plane_helper_funcs); 1921 vop_plane_add_properties(&vop_win->base, win_data); 1922 } 1923 1924 port = of_get_child_by_name(dev->of_node, "port"); 1925 if (!port) { 1926 DRM_DEV_ERROR(vop->dev, "no port node found in %pOF\n", 1927 dev->of_node); 1928 ret = -ENOENT; 1929 goto err_cleanup_crtc; 1930 } 1931 1932 drm_flip_work_init(&vop->fb_unref_work, "fb_unref", 1933 vop_fb_unref_worker); 1934 1935 init_completion(&vop->dsp_hold_completion); 1936 init_completion(&vop->line_flag_completion); 1937 crtc->port = port; 1938 1939 ret = drm_self_refresh_helper_init(crtc); 1940 if (ret) 1941 DRM_DEV_DEBUG_KMS(vop->dev, 1942 "Failed to init %s with SR helpers %d, ignoring\n", 1943 crtc->name, ret); 1944 1945 return 0; 1946 1947err_cleanup_crtc: 1948 drm_crtc_cleanup(crtc); 1949err_cleanup_planes: 1950 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list, 1951 head) 1952 drm_plane_cleanup(plane); 1953 return ret; 1954} 1955 1956static void vop_destroy_crtc(struct vop *vop) 1957{ 1958 struct drm_crtc *crtc = &vop->crtc; 1959 struct drm_device *drm_dev = vop->drm_dev; 1960 struct drm_plane *plane, *tmp; 1961 1962 drm_self_refresh_helper_cleanup(crtc); 1963 1964 of_node_put(crtc->port); 1965 1966 /* 1967 * We need to cleanup the planes now. Why? 1968 * 1969 * The planes are "&vop->win[i].base". That means the memory is 1970 * all part of the big "struct vop" chunk of memory. That memory 1971 * was devm allocated and associated with this component. We need to 1972 * free it ourselves before vop_unbind() finishes. 1973 */ 1974 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list, 1975 head) 1976 vop_plane_destroy(plane); 1977 1978 /* 1979 * Destroy CRTC after vop_plane_destroy() since vop_disable_plane() 1980 * references the CRTC. 1981 */ 1982 drm_crtc_cleanup(crtc); 1983 drm_flip_work_cleanup(&vop->fb_unref_work); 1984} 1985 1986static int vop_initial(struct vop *vop) 1987{ 1988 struct reset_control *ahb_rst; 1989 int i, ret; 1990 1991 vop->hclk = devm_clk_get(vop->dev, "hclk_vop"); 1992 if (IS_ERR(vop->hclk)) { 1993 DRM_DEV_ERROR(vop->dev, "failed to get hclk source\n"); 1994 return PTR_ERR(vop->hclk); 1995 } 1996 vop->aclk = devm_clk_get(vop->dev, "aclk_vop"); 1997 if (IS_ERR(vop->aclk)) { 1998 DRM_DEV_ERROR(vop->dev, "failed to get aclk source\n"); 1999 return PTR_ERR(vop->aclk); 2000 } 2001 vop->dclk = devm_clk_get(vop->dev, "dclk_vop"); 2002 if (IS_ERR(vop->dclk)) { 2003 DRM_DEV_ERROR(vop->dev, "failed to get dclk source\n"); 2004 return PTR_ERR(vop->dclk); 2005 } 2006 2007 ret = pm_runtime_resume_and_get(vop->dev); 2008 if (ret < 0) { 2009 DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret); 2010 return ret; 2011 } 2012 2013 ret = clk_prepare(vop->dclk); 2014 if (ret < 0) { 2015 DRM_DEV_ERROR(vop->dev, "failed to prepare dclk\n"); 2016 goto err_put_pm_runtime; 2017 } 2018 2019 /* Enable both the hclk and aclk to setup the vop */ 2020 ret = clk_prepare_enable(vop->hclk); 2021 if (ret < 0) { 2022 DRM_DEV_ERROR(vop->dev, "failed to prepare/enable hclk\n"); 2023 goto err_unprepare_dclk; 2024 } 2025 2026 ret = clk_prepare_enable(vop->aclk); 2027 if (ret < 0) { 2028 DRM_DEV_ERROR(vop->dev, "failed to prepare/enable aclk\n"); 2029 goto err_disable_hclk; 2030 } 2031 2032 /* 2033 * do hclk_reset, reset all vop registers. 2034 */ 2035 ahb_rst = devm_reset_control_get(vop->dev, "ahb"); 2036 if (IS_ERR(ahb_rst)) { 2037 DRM_DEV_ERROR(vop->dev, "failed to get ahb reset\n"); 2038 ret = PTR_ERR(ahb_rst); 2039 goto err_disable_aclk; 2040 } 2041 reset_control_assert(ahb_rst); 2042 usleep_range(10, 20); 2043 reset_control_deassert(ahb_rst); 2044 2045 VOP_INTR_SET_TYPE(vop, clear, INTR_MASK, 1); 2046 VOP_INTR_SET_TYPE(vop, enable, INTR_MASK, 0); 2047 2048 for (i = 0; i < vop->len; i += sizeof(u32)) 2049 vop->regsbak[i / 4] = readl_relaxed(vop->regs + i); 2050 2051 VOP_REG_SET(vop, misc, global_regdone_en, 1); 2052 VOP_REG_SET(vop, common, dsp_blank, 0); 2053 2054 for (i = 0; i < vop->data->win_size; i++) { 2055 struct vop_win *vop_win = &vop->win[i]; 2056 const struct vop_win_data *win = vop_win->data; 2057 int channel = i * 2 + 1; 2058 2059 VOP_WIN_SET(vop, win, channel, (channel + 1) << 4 | channel); 2060 vop_win_disable(vop, vop_win); 2061 VOP_WIN_SET(vop, win, gate, 1); 2062 } 2063 2064 vop_cfg_done(vop); 2065 2066 /* 2067 * do dclk_reset, let all config take affect. 2068 */ 2069 vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk"); 2070 if (IS_ERR(vop->dclk_rst)) { 2071 DRM_DEV_ERROR(vop->dev, "failed to get dclk reset\n"); 2072 ret = PTR_ERR(vop->dclk_rst); 2073 goto err_disable_aclk; 2074 } 2075 reset_control_assert(vop->dclk_rst); 2076 usleep_range(10, 20); 2077 reset_control_deassert(vop->dclk_rst); 2078 2079 clk_disable(vop->hclk); 2080 clk_disable(vop->aclk); 2081 2082 vop->is_enabled = false; 2083 2084 pm_runtime_put_sync(vop->dev); 2085 2086 return 0; 2087 2088err_disable_aclk: 2089 clk_disable_unprepare(vop->aclk); 2090err_disable_hclk: 2091 clk_disable_unprepare(vop->hclk); 2092err_unprepare_dclk: 2093 clk_unprepare(vop->dclk); 2094err_put_pm_runtime: 2095 pm_runtime_put_sync(vop->dev); 2096 return ret; 2097} 2098 2099/* 2100 * Initialize the vop->win array elements. 2101 */ 2102static void vop_win_init(struct vop *vop) 2103{ 2104 const struct vop_data *vop_data = vop->data; 2105 unsigned int i; 2106 2107 for (i = 0; i < vop_data->win_size; i++) { 2108 struct vop_win *vop_win = &vop->win[i]; 2109 const struct vop_win_data *win_data = &vop_data->win[i]; 2110 2111 vop_win->data = win_data; 2112 vop_win->vop = vop; 2113 2114 if (vop_data->win_yuv2yuv) 2115 vop_win->yuv2yuv_data = &vop_data->win_yuv2yuv[i]; 2116 } 2117} 2118 2119/** 2120 * rockchip_drm_wait_vact_end 2121 * @crtc: CRTC to enable line flag 2122 * @mstimeout: millisecond for timeout 2123 * 2124 * Wait for vact_end line flag irq or timeout. 2125 * 2126 * Returns: 2127 * Zero on success, negative errno on failure. 2128 */ 2129int rockchip_drm_wait_vact_end(struct drm_crtc *crtc, unsigned int mstimeout) 2130{ 2131 struct vop *vop = to_vop(crtc); 2132 unsigned long jiffies_left; 2133 int ret = 0; 2134 2135 if (!crtc || !vop->is_enabled) 2136 return -ENODEV; 2137 2138 mutex_lock(&vop->vop_lock); 2139 if (mstimeout <= 0) { 2140 ret = -EINVAL; 2141 goto out; 2142 } 2143 2144 if (vop_line_flag_irq_is_enabled(vop)) { 2145 ret = -EBUSY; 2146 goto out; 2147 } 2148 2149 reinit_completion(&vop->line_flag_completion); 2150 vop_line_flag_irq_enable(vop); 2151 2152 jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion, 2153 msecs_to_jiffies(mstimeout)); 2154 vop_line_flag_irq_disable(vop); 2155 2156 if (jiffies_left == 0) { 2157 DRM_DEV_ERROR(vop->dev, "Timeout waiting for IRQ\n"); 2158 ret = -ETIMEDOUT; 2159 goto out; 2160 } 2161 2162out: 2163 mutex_unlock(&vop->vop_lock); 2164 return ret; 2165} 2166EXPORT_SYMBOL(rockchip_drm_wait_vact_end); 2167 2168static int vop_bind(struct device *dev, struct device *master, void *data) 2169{ 2170 struct platform_device *pdev = to_platform_device(dev); 2171 const struct vop_data *vop_data; 2172 struct drm_device *drm_dev = data; 2173 struct vop *vop; 2174 struct resource *res; 2175 int ret, irq; 2176 2177 vop_data = of_device_get_match_data(dev); 2178 if (!vop_data) 2179 return -ENODEV; 2180 2181 /* Allocate vop struct and its vop_win array */ 2182 vop = devm_kzalloc(dev, struct_size(vop, win, vop_data->win_size), 2183 GFP_KERNEL); 2184 if (!vop) 2185 return -ENOMEM; 2186 2187 vop->dev = dev; 2188 vop->data = vop_data; 2189 vop->drm_dev = drm_dev; 2190 dev_set_drvdata(dev, vop); 2191 2192 vop_win_init(vop); 2193 2194 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2195 vop->regs = devm_ioremap_resource(dev, res); 2196 if (IS_ERR(vop->regs)) 2197 return PTR_ERR(vop->regs); 2198 vop->len = resource_size(res); 2199 2200 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 2201 if (res) { 2202 if (vop_data->lut_size != 1024 && vop_data->lut_size != 256) { 2203 DRM_DEV_ERROR(dev, "unsupported gamma LUT size %d\n", vop_data->lut_size); 2204 return -EINVAL; 2205 } 2206 vop->lut_regs = devm_ioremap_resource(dev, res); 2207 if (IS_ERR(vop->lut_regs)) 2208 return PTR_ERR(vop->lut_regs); 2209 } 2210 2211 vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL); 2212 if (!vop->regsbak) 2213 return -ENOMEM; 2214 2215 irq = platform_get_irq(pdev, 0); 2216 if (irq < 0) { 2217 DRM_DEV_ERROR(dev, "cannot find irq for vop\n"); 2218 return irq; 2219 } 2220 vop->irq = (unsigned int)irq; 2221 2222 spin_lock_init(&vop->reg_lock); 2223 spin_lock_init(&vop->irq_lock); 2224 mutex_init(&vop->vop_lock); 2225 2226 ret = vop_create_crtc(vop); 2227 if (ret) 2228 return ret; 2229 2230 pm_runtime_enable(&pdev->dev); 2231 2232 ret = vop_initial(vop); 2233 if (ret < 0) { 2234 DRM_DEV_ERROR(&pdev->dev, 2235 "cannot initial vop dev - err %d\n", ret); 2236 goto err_disable_pm_runtime; 2237 } 2238 2239 ret = devm_request_irq(dev, vop->irq, vop_isr, 2240 IRQF_SHARED, dev_name(dev), vop); 2241 if (ret) 2242 goto err_disable_pm_runtime; 2243 2244 if (vop->data->feature & VOP_FEATURE_INTERNAL_RGB) { 2245 vop->rgb = rockchip_rgb_init(dev, &vop->crtc, vop->drm_dev, 0); 2246 if (IS_ERR(vop->rgb)) { 2247 ret = PTR_ERR(vop->rgb); 2248 goto err_disable_pm_runtime; 2249 } 2250 } 2251 2252 rockchip_drm_dma_init_device(drm_dev, dev); 2253 2254 return 0; 2255 2256err_disable_pm_runtime: 2257 pm_runtime_disable(&pdev->dev); 2258 vop_destroy_crtc(vop); 2259 return ret; 2260} 2261 2262static void vop_unbind(struct device *dev, struct device *master, void *data) 2263{ 2264 struct vop *vop = dev_get_drvdata(dev); 2265 2266 if (vop->rgb) 2267 rockchip_rgb_fini(vop->rgb); 2268 2269 pm_runtime_disable(dev); 2270 vop_destroy_crtc(vop); 2271 2272 clk_unprepare(vop->aclk); 2273 clk_unprepare(vop->hclk); 2274 clk_unprepare(vop->dclk); 2275} 2276 2277const struct component_ops vop_component_ops = { 2278 .bind = vop_bind, 2279 .unbind = vop_unbind, 2280}; 2281EXPORT_SYMBOL_GPL(vop_component_ops); 2282