1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd 4 * Author: 5 * Chris Zhong <zyw@rock-chips.com> 6 * Nickey Yang <nickey.yang@rock-chips.com> 7 */ 8 9#include <linux/clk.h> 10#include <linux/iopoll.h> 11#include <linux/math64.h> 12#include <linux/mfd/syscon.h> 13#include <linux/module.h> 14#include <linux/of_device.h> 15#include <linux/of_platform.h> 16#include <linux/phy/phy.h> 17#include <linux/platform_device.h> 18#include <linux/pm_runtime.h> 19#include <linux/regmap.h> 20 21#include <video/mipi_display.h> 22 23#include <drm/bridge/dw_mipi_dsi.h> 24#include <drm/drm_mipi_dsi.h> 25#include <drm/drm_of.h> 26#include <drm/drm_simple_kms_helper.h> 27 28#include "rockchip_drm_drv.h" 29#include "rockchip_drm_vop.h" 30 31#define DSI_PHY_RSTZ 0xa0 32#define PHY_DISFORCEPLL 0 33#define PHY_ENFORCEPLL BIT(3) 34#define PHY_DISABLECLK 0 35#define PHY_ENABLECLK BIT(2) 36#define PHY_RSTZ 0 37#define PHY_UNRSTZ BIT(1) 38#define PHY_SHUTDOWNZ 0 39#define PHY_UNSHUTDOWNZ BIT(0) 40 41#define DSI_PHY_IF_CFG 0xa4 42#define N_LANES(n) ((((n) - 1) & 0x3) << 0) 43#define PHY_STOP_WAIT_TIME(cycle) (((cycle) & 0xff) << 8) 44 45#define DSI_PHY_STATUS 0xb0 46#define LOCK BIT(0) 47#define STOP_STATE_CLK_LANE BIT(2) 48 49#define DSI_PHY_TST_CTRL0 0xb4 50#define PHY_TESTCLK BIT(1) 51#define PHY_UNTESTCLK 0 52#define PHY_TESTCLR BIT(0) 53#define PHY_UNTESTCLR 0 54 55#define DSI_PHY_TST_CTRL1 0xb8 56#define PHY_TESTEN BIT(16) 57#define PHY_UNTESTEN 0 58#define PHY_TESTDOUT(n) (((n) & 0xff) << 8) 59#define PHY_TESTDIN(n) (((n) & 0xff) << 0) 60 61#define DSI_INT_ST0 0xbc 62#define DSI_INT_ST1 0xc0 63#define DSI_INT_MSK0 0xc4 64#define DSI_INT_MSK1 0xc8 65 66#define PHY_STATUS_TIMEOUT_US 10000 67#define CMD_PKT_STATUS_TIMEOUT_US 20000 68 69#define BYPASS_VCO_RANGE BIT(7) 70#define VCO_RANGE_CON_SEL(val) (((val) & 0x7) << 3) 71#define VCO_IN_CAP_CON_DEFAULT (0x0 << 1) 72#define VCO_IN_CAP_CON_LOW (0x1 << 1) 73#define VCO_IN_CAP_CON_HIGH (0x2 << 1) 74#define REF_BIAS_CUR_SEL BIT(0) 75 76#define CP_CURRENT_3UA 0x1 77#define CP_CURRENT_4_5UA 0x2 78#define CP_CURRENT_7_5UA 0x6 79#define CP_CURRENT_6UA 0x9 80#define CP_CURRENT_12UA 0xb 81#define CP_CURRENT_SEL(val) ((val) & 0xf) 82#define CP_PROGRAM_EN BIT(7) 83 84#define LPF_RESISTORS_15_5KOHM 0x1 85#define LPF_RESISTORS_13KOHM 0x2 86#define LPF_RESISTORS_11_5KOHM 0x4 87#define LPF_RESISTORS_10_5KOHM 0x8 88#define LPF_RESISTORS_8KOHM 0x10 89#define LPF_PROGRAM_EN BIT(6) 90#define LPF_RESISTORS_SEL(val) ((val) & 0x3f) 91 92#define HSFREQRANGE_SEL(val) (((val) & 0x3f) << 1) 93 94#define INPUT_DIVIDER(val) (((val) - 1) & 0x7f) 95#define LOW_PROGRAM_EN 0 96#define HIGH_PROGRAM_EN BIT(7) 97#define LOOP_DIV_LOW_SEL(val) (((val) - 1) & 0x1f) 98#define LOOP_DIV_HIGH_SEL(val) ((((val) - 1) >> 5) & 0xf) 99#define PLL_LOOP_DIV_EN BIT(5) 100#define PLL_INPUT_DIV_EN BIT(4) 101 102#define POWER_CONTROL BIT(6) 103#define INTERNAL_REG_CURRENT BIT(3) 104#define BIAS_BLOCK_ON BIT(2) 105#define BANDGAP_ON BIT(0) 106 107#define TER_RESISTOR_HIGH BIT(7) 108#define TER_RESISTOR_LOW 0 109#define LEVEL_SHIFTERS_ON BIT(6) 110#define TER_CAL_DONE BIT(5) 111#define SETRD_MAX (0x7 << 2) 112#define POWER_MANAGE BIT(1) 113#define TER_RESISTORS_ON BIT(0) 114 115#define BIASEXTR_SEL(val) ((val) & 0x7) 116#define BANDGAP_SEL(val) ((val) & 0x7) 117#define TLP_PROGRAM_EN BIT(7) 118#define THS_PRE_PROGRAM_EN BIT(7) 119#define THS_ZERO_PROGRAM_EN BIT(6) 120 121#define PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL 0x10 122#define PLL_CP_CONTROL_PLL_LOCK_BYPASS 0x11 123#define PLL_LPF_AND_CP_CONTROL 0x12 124#define PLL_INPUT_DIVIDER_RATIO 0x17 125#define PLL_LOOP_DIVIDER_RATIO 0x18 126#define PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL 0x19 127#define BANDGAP_AND_BIAS_CONTROL 0x20 128#define TERMINATION_RESISTER_CONTROL 0x21 129#define AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY 0x22 130#define HS_RX_CONTROL_OF_LANE_CLK 0x34 131#define HS_RX_CONTROL_OF_LANE_0 0x44 132#define HS_RX_CONTROL_OF_LANE_1 0x54 133#define HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROL 0x60 134#define HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROL 0x61 135#define HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROL 0x62 136#define HS_TX_CLOCK_LANE_TRAIL_STATE_TIME_CONTROL 0x63 137#define HS_TX_CLOCK_LANE_EXIT_STATE_TIME_CONTROL 0x64 138#define HS_TX_CLOCK_LANE_POST_TIME_CONTROL 0x65 139#define HS_TX_DATA_LANE_REQUEST_STATE_TIME_CONTROL 0x70 140#define HS_TX_DATA_LANE_PREPARE_STATE_TIME_CONTROL 0x71 141#define HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROL 0x72 142#define HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROL 0x73 143#define HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL 0x74 144#define HS_RX_DATA_LANE_THS_SETTLE_CONTROL 0x75 145#define HS_RX_CONTROL_OF_LANE_2 0x84 146#define HS_RX_CONTROL_OF_LANE_3 0x94 147 148#define DW_MIPI_NEEDS_PHY_CFG_CLK BIT(0) 149#define DW_MIPI_NEEDS_GRF_CLK BIT(1) 150 151#define PX30_GRF_PD_VO_CON1 0x0438 152#define PX30_DSI_FORCETXSTOPMODE (0xf << 7) 153#define PX30_DSI_FORCERXMODE BIT(6) 154#define PX30_DSI_TURNDISABLE BIT(5) 155#define PX30_DSI_LCDC_SEL BIT(0) 156 157#define RK3288_GRF_SOC_CON6 0x025c 158#define RK3288_DSI0_LCDC_SEL BIT(6) 159#define RK3288_DSI1_LCDC_SEL BIT(9) 160 161#define RK3399_GRF_SOC_CON20 0x6250 162#define RK3399_DSI0_LCDC_SEL BIT(0) 163#define RK3399_DSI1_LCDC_SEL BIT(4) 164 165#define RK3399_GRF_SOC_CON22 0x6258 166#define RK3399_DSI0_TURNREQUEST (0xf << 12) 167#define RK3399_DSI0_TURNDISABLE (0xf << 8) 168#define RK3399_DSI0_FORCETXSTOPMODE (0xf << 4) 169#define RK3399_DSI0_FORCERXMODE (0xf << 0) 170 171#define RK3399_GRF_SOC_CON23 0x625c 172#define RK3399_DSI1_TURNDISABLE (0xf << 12) 173#define RK3399_DSI1_FORCETXSTOPMODE (0xf << 8) 174#define RK3399_DSI1_FORCERXMODE (0xf << 4) 175#define RK3399_DSI1_ENABLE (0xf << 0) 176 177#define RK3399_GRF_SOC_CON24 0x6260 178#define RK3399_TXRX_MASTERSLAVEZ BIT(7) 179#define RK3399_TXRX_ENABLECLK BIT(6) 180#define RK3399_TXRX_BASEDIR BIT(5) 181#define RK3399_TXRX_SRC_SEL_ISP0 BIT(4) 182#define RK3399_TXRX_TURNREQUEST GENMASK(3, 0) 183 184#define RK3568_GRF_VO_CON2 0x0368 185#define RK3568_DSI0_SKEWCALHS (0x1f << 11) 186#define RK3568_DSI0_FORCETXSTOPMODE (0xf << 4) 187#define RK3568_DSI0_TURNDISABLE BIT(2) 188#define RK3568_DSI0_FORCERXMODE BIT(0) 189 190/* 191 * Note these registers do not appear in the datasheet, they are 192 * however present in the BSP driver which is where these values 193 * come from. Name GRF_VO_CON3 is assumed. 194 */ 195#define RK3568_GRF_VO_CON3 0x36c 196#define RK3568_DSI1_SKEWCALHS (0x1f << 11) 197#define RK3568_DSI1_FORCETXSTOPMODE (0xf << 4) 198#define RK3568_DSI1_TURNDISABLE BIT(2) 199#define RK3568_DSI1_FORCERXMODE BIT(0) 200 201#define HIWORD_UPDATE(val, mask) (val | (mask) << 16) 202 203enum { 204 DW_DSI_USAGE_IDLE, 205 DW_DSI_USAGE_DSI, 206 DW_DSI_USAGE_PHY, 207}; 208 209enum { 210 BANDGAP_97_07, 211 BANDGAP_98_05, 212 BANDGAP_99_02, 213 BANDGAP_100_00, 214 BANDGAP_93_17, 215 BANDGAP_94_15, 216 BANDGAP_95_12, 217 BANDGAP_96_10, 218}; 219 220enum { 221 BIASEXTR_87_1, 222 BIASEXTR_91_5, 223 BIASEXTR_95_9, 224 BIASEXTR_100, 225 BIASEXTR_105_94, 226 BIASEXTR_111_88, 227 BIASEXTR_118_8, 228 BIASEXTR_127_7, 229}; 230 231struct rockchip_dw_dsi_chip_data { 232 u32 reg; 233 234 u32 lcdsel_grf_reg; 235 u32 lcdsel_big; 236 u32 lcdsel_lit; 237 238 u32 enable_grf_reg; 239 u32 enable; 240 241 u32 lanecfg1_grf_reg; 242 u32 lanecfg1; 243 u32 lanecfg2_grf_reg; 244 u32 lanecfg2; 245 246 int (*dphy_rx_init)(struct phy *phy); 247 int (*dphy_rx_power_on)(struct phy *phy); 248 int (*dphy_rx_power_off)(struct phy *phy); 249 250 unsigned int flags; 251 unsigned int max_data_lanes; 252}; 253 254struct dw_mipi_dsi_rockchip { 255 struct device *dev; 256 struct rockchip_encoder encoder; 257 void __iomem *base; 258 259 struct regmap *grf_regmap; 260 struct clk *pclk; 261 struct clk *pllref_clk; 262 struct clk *grf_clk; 263 struct clk *phy_cfg_clk; 264 265 /* dual-channel */ 266 bool is_slave; 267 struct dw_mipi_dsi_rockchip *slave; 268 269 /* optional external dphy */ 270 struct phy *phy; 271 union phy_configure_opts phy_opts; 272 273 /* being a phy for other mipi hosts */ 274 unsigned int usage_mode; 275 struct mutex usage_mutex; 276 struct phy *dphy; 277 struct phy_configure_opts_mipi_dphy dphy_config; 278 279 unsigned int lane_mbps; /* per lane */ 280 u16 input_div; 281 u16 feedback_div; 282 u32 format; 283 284 struct dw_mipi_dsi *dmd; 285 const struct rockchip_dw_dsi_chip_data *cdata; 286 struct dw_mipi_dsi_plat_data pdata; 287 288 bool dsi_bound; 289}; 290 291static struct dw_mipi_dsi_rockchip *to_dsi(struct drm_encoder *encoder) 292{ 293 struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder); 294 295 return container_of(rkencoder, struct dw_mipi_dsi_rockchip, encoder); 296} 297 298struct dphy_pll_parameter_map { 299 unsigned int max_mbps; 300 u8 hsfreqrange; 301 u8 icpctrl; 302 u8 lpfctrl; 303}; 304 305/* The table is based on 27MHz DPHY pll reference clock. */ 306static const struct dphy_pll_parameter_map dppa_map[] = { 307 { 89, 0x00, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM }, 308 { 99, 0x10, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM }, 309 { 109, 0x20, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM }, 310 { 129, 0x01, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM }, 311 { 139, 0x11, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM }, 312 { 149, 0x21, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM }, 313 { 169, 0x02, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM }, 314 { 179, 0x12, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM }, 315 { 199, 0x22, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM }, 316 { 219, 0x03, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM }, 317 { 239, 0x13, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM }, 318 { 249, 0x23, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM }, 319 { 269, 0x04, CP_CURRENT_6UA, LPF_RESISTORS_11_5KOHM }, 320 { 299, 0x14, CP_CURRENT_6UA, LPF_RESISTORS_11_5KOHM }, 321 { 329, 0x05, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM }, 322 { 359, 0x15, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM }, 323 { 399, 0x25, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM }, 324 { 449, 0x06, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 325 { 499, 0x16, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 326 { 549, 0x07, CP_CURRENT_7_5UA, LPF_RESISTORS_10_5KOHM }, 327 { 599, 0x17, CP_CURRENT_7_5UA, LPF_RESISTORS_10_5KOHM }, 328 { 649, 0x08, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 329 { 699, 0x18, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 330 { 749, 0x09, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 331 { 799, 0x19, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 332 { 849, 0x29, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 333 { 899, 0x39, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 334 { 949, 0x0a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM }, 335 { 999, 0x1a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM }, 336 {1049, 0x2a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM }, 337 {1099, 0x3a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM }, 338 {1149, 0x0b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }, 339 {1199, 0x1b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }, 340 {1249, 0x2b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }, 341 {1299, 0x3b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }, 342 {1349, 0x0c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }, 343 {1399, 0x1c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }, 344 {1449, 0x2c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }, 345 {1500, 0x3c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM } 346}; 347 348static int max_mbps_to_parameter(unsigned int max_mbps) 349{ 350 int i; 351 352 for (i = 0; i < ARRAY_SIZE(dppa_map); i++) 353 if (dppa_map[i].max_mbps >= max_mbps) 354 return i; 355 356 return -EINVAL; 357} 358 359static inline void dsi_write(struct dw_mipi_dsi_rockchip *dsi, u32 reg, u32 val) 360{ 361 writel(val, dsi->base + reg); 362} 363 364static void dw_mipi_dsi_phy_write(struct dw_mipi_dsi_rockchip *dsi, 365 u8 test_code, 366 u8 test_data) 367{ 368 /* 369 * With the falling edge on TESTCLK, the TESTDIN[7:0] signal content 370 * is latched internally as the current test code. Test data is 371 * programmed internally by rising edge on TESTCLK. 372 */ 373 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR); 374 375 dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN | PHY_TESTDOUT(0) | 376 PHY_TESTDIN(test_code)); 377 378 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR); 379 380 dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_UNTESTEN | PHY_TESTDOUT(0) | 381 PHY_TESTDIN(test_data)); 382 383 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR); 384} 385 386/* 387 * ns2bc - Nanoseconds to byte clock cycles 388 */ 389static inline unsigned int ns2bc(struct dw_mipi_dsi_rockchip *dsi, int ns) 390{ 391 return DIV_ROUND_UP(ns * dsi->lane_mbps / 8, 1000); 392} 393 394/* 395 * ns2ui - Nanoseconds to UI time periods 396 */ 397static inline unsigned int ns2ui(struct dw_mipi_dsi_rockchip *dsi, int ns) 398{ 399 return DIV_ROUND_UP(ns * dsi->lane_mbps, 1000); 400} 401 402static int dw_mipi_dsi_phy_init(void *priv_data) 403{ 404 struct dw_mipi_dsi_rockchip *dsi = priv_data; 405 int ret, i, vco; 406 407 if (dsi->phy) 408 return 0; 409 410 /* 411 * Get vco from frequency(lane_mbps) 412 * vco frequency table 413 * 000 - between 80 and 200 MHz 414 * 001 - between 200 and 300 MHz 415 * 010 - between 300 and 500 MHz 416 * 011 - between 500 and 700 MHz 417 * 100 - between 700 and 900 MHz 418 * 101 - between 900 and 1100 MHz 419 * 110 - between 1100 and 1300 MHz 420 * 111 - between 1300 and 1500 MHz 421 */ 422 vco = (dsi->lane_mbps < 200) ? 0 : (dsi->lane_mbps + 100) / 200; 423 424 i = max_mbps_to_parameter(dsi->lane_mbps); 425 if (i < 0) { 426 DRM_DEV_ERROR(dsi->dev, 427 "failed to get parameter for %dmbps clock\n", 428 dsi->lane_mbps); 429 return i; 430 } 431 432 ret = clk_prepare_enable(dsi->phy_cfg_clk); 433 if (ret) { 434 DRM_DEV_ERROR(dsi->dev, "Failed to enable phy_cfg_clk\n"); 435 return ret; 436 } 437 438 dw_mipi_dsi_phy_write(dsi, PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL, 439 BYPASS_VCO_RANGE | 440 VCO_RANGE_CON_SEL(vco) | 441 VCO_IN_CAP_CON_LOW | 442 REF_BIAS_CUR_SEL); 443 444 dw_mipi_dsi_phy_write(dsi, PLL_CP_CONTROL_PLL_LOCK_BYPASS, 445 CP_CURRENT_SEL(dppa_map[i].icpctrl)); 446 dw_mipi_dsi_phy_write(dsi, PLL_LPF_AND_CP_CONTROL, 447 CP_PROGRAM_EN | LPF_PROGRAM_EN | 448 LPF_RESISTORS_SEL(dppa_map[i].lpfctrl)); 449 450 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_0, 451 HSFREQRANGE_SEL(dppa_map[i].hsfreqrange)); 452 453 dw_mipi_dsi_phy_write(dsi, PLL_INPUT_DIVIDER_RATIO, 454 INPUT_DIVIDER(dsi->input_div)); 455 dw_mipi_dsi_phy_write(dsi, PLL_LOOP_DIVIDER_RATIO, 456 LOOP_DIV_LOW_SEL(dsi->feedback_div) | 457 LOW_PROGRAM_EN); 458 /* 459 * We need set PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL immediately 460 * to make the configured LSB effective according to IP simulation 461 * and lab test results. 462 * Only in this way can we get correct mipi phy pll frequency. 463 */ 464 dw_mipi_dsi_phy_write(dsi, PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL, 465 PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN); 466 dw_mipi_dsi_phy_write(dsi, PLL_LOOP_DIVIDER_RATIO, 467 LOOP_DIV_HIGH_SEL(dsi->feedback_div) | 468 HIGH_PROGRAM_EN); 469 dw_mipi_dsi_phy_write(dsi, PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL, 470 PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN); 471 472 dw_mipi_dsi_phy_write(dsi, AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY, 473 LOW_PROGRAM_EN | BIASEXTR_SEL(BIASEXTR_127_7)); 474 dw_mipi_dsi_phy_write(dsi, AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY, 475 HIGH_PROGRAM_EN | BANDGAP_SEL(BANDGAP_96_10)); 476 477 dw_mipi_dsi_phy_write(dsi, BANDGAP_AND_BIAS_CONTROL, 478 POWER_CONTROL | INTERNAL_REG_CURRENT | 479 BIAS_BLOCK_ON | BANDGAP_ON); 480 481 dw_mipi_dsi_phy_write(dsi, TERMINATION_RESISTER_CONTROL, 482 TER_RESISTOR_LOW | TER_CAL_DONE | 483 SETRD_MAX | TER_RESISTORS_ON); 484 dw_mipi_dsi_phy_write(dsi, TERMINATION_RESISTER_CONTROL, 485 TER_RESISTOR_HIGH | LEVEL_SHIFTERS_ON | 486 SETRD_MAX | POWER_MANAGE | 487 TER_RESISTORS_ON); 488 489 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROL, 490 TLP_PROGRAM_EN | ns2bc(dsi, 500)); 491 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROL, 492 THS_PRE_PROGRAM_EN | ns2ui(dsi, 40)); 493 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROL, 494 THS_ZERO_PROGRAM_EN | ns2bc(dsi, 300)); 495 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_TRAIL_STATE_TIME_CONTROL, 496 THS_PRE_PROGRAM_EN | ns2ui(dsi, 100)); 497 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_EXIT_STATE_TIME_CONTROL, 498 BIT(5) | ns2bc(dsi, 100)); 499 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_POST_TIME_CONTROL, 500 BIT(5) | (ns2bc(dsi, 60) + 7)); 501 502 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_REQUEST_STATE_TIME_CONTROL, 503 TLP_PROGRAM_EN | ns2bc(dsi, 500)); 504 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_PREPARE_STATE_TIME_CONTROL, 505 THS_PRE_PROGRAM_EN | (ns2ui(dsi, 50) + 20)); 506 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROL, 507 THS_ZERO_PROGRAM_EN | (ns2bc(dsi, 140) + 2)); 508 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROL, 509 THS_PRE_PROGRAM_EN | (ns2ui(dsi, 60) + 8)); 510 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL, 511 BIT(5) | ns2bc(dsi, 100)); 512 513 clk_disable_unprepare(dsi->phy_cfg_clk); 514 515 return ret; 516} 517 518static void dw_mipi_dsi_phy_power_on(void *priv_data) 519{ 520 struct dw_mipi_dsi_rockchip *dsi = priv_data; 521 int ret; 522 523 ret = phy_set_mode(dsi->phy, PHY_MODE_MIPI_DPHY); 524 if (ret) { 525 DRM_DEV_ERROR(dsi->dev, "failed to set phy mode: %d\n", ret); 526 return; 527 } 528 529 phy_configure(dsi->phy, &dsi->phy_opts); 530 phy_power_on(dsi->phy); 531} 532 533static void dw_mipi_dsi_phy_power_off(void *priv_data) 534{ 535 struct dw_mipi_dsi_rockchip *dsi = priv_data; 536 537 phy_power_off(dsi->phy); 538} 539 540static int 541dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode, 542 unsigned long mode_flags, u32 lanes, u32 format, 543 unsigned int *lane_mbps) 544{ 545 struct dw_mipi_dsi_rockchip *dsi = priv_data; 546 int bpp; 547 unsigned long mpclk, tmp; 548 unsigned int target_mbps = 1000; 549 unsigned int max_mbps = dppa_map[ARRAY_SIZE(dppa_map) - 1].max_mbps; 550 unsigned long best_freq = 0; 551 unsigned long fvco_min, fvco_max, fin, fout; 552 unsigned int min_prediv, max_prediv; 553 unsigned int _prediv, best_prediv; 554 unsigned long _fbdiv, best_fbdiv; 555 unsigned long min_delta = ULONG_MAX; 556 557 dsi->format = format; 558 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); 559 if (bpp < 0) { 560 DRM_DEV_ERROR(dsi->dev, 561 "failed to get bpp for pixel format %d\n", 562 dsi->format); 563 return bpp; 564 } 565 566 mpclk = DIV_ROUND_UP(mode->clock, MSEC_PER_SEC); 567 if (mpclk) { 568 /* take 1 / 0.8, since mbps must big than bandwidth of RGB */ 569 tmp = mpclk * (bpp / lanes) * 10 / 8; 570 if (tmp < max_mbps) 571 target_mbps = tmp; 572 else 573 DRM_DEV_ERROR(dsi->dev, 574 "DPHY clock frequency is out of range\n"); 575 } 576 577 /* for external phy only a the mipi_dphy_config is necessary */ 578 if (dsi->phy) { 579 phy_mipi_dphy_get_default_config(mode->clock * 1000 * 10 / 8, 580 bpp, lanes, 581 &dsi->phy_opts.mipi_dphy); 582 dsi->lane_mbps = target_mbps; 583 *lane_mbps = dsi->lane_mbps; 584 585 return 0; 586 } 587 588 fin = clk_get_rate(dsi->pllref_clk); 589 fout = target_mbps * USEC_PER_SEC; 590 591 /* constraint: 5Mhz <= Fref / N <= 40MHz */ 592 min_prediv = DIV_ROUND_UP(fin, 40 * USEC_PER_SEC); 593 max_prediv = fin / (5 * USEC_PER_SEC); 594 595 /* constraint: 80MHz <= Fvco <= 1500Mhz */ 596 fvco_min = 80 * USEC_PER_SEC; 597 fvco_max = 1500 * USEC_PER_SEC; 598 599 for (_prediv = min_prediv; _prediv <= max_prediv; _prediv++) { 600 u64 tmp; 601 u32 delta; 602 /* Fvco = Fref * M / N */ 603 tmp = (u64)fout * _prediv; 604 do_div(tmp, fin); 605 _fbdiv = tmp; 606 /* 607 * Due to the use of a "by 2 pre-scaler," the range of the 608 * feedback multiplication value M is limited to even division 609 * numbers, and m must be greater than 6, not bigger than 512. 610 */ 611 if (_fbdiv < 6 || _fbdiv > 512) 612 continue; 613 614 _fbdiv += _fbdiv % 2; 615 616 tmp = (u64)_fbdiv * fin; 617 do_div(tmp, _prediv); 618 if (tmp < fvco_min || tmp > fvco_max) 619 continue; 620 621 delta = abs(fout - tmp); 622 if (delta < min_delta) { 623 best_prediv = _prediv; 624 best_fbdiv = _fbdiv; 625 min_delta = delta; 626 best_freq = tmp; 627 } 628 } 629 630 if (best_freq) { 631 dsi->lane_mbps = DIV_ROUND_UP(best_freq, USEC_PER_SEC); 632 *lane_mbps = dsi->lane_mbps; 633 dsi->input_div = best_prediv; 634 dsi->feedback_div = best_fbdiv; 635 } else { 636 DRM_DEV_ERROR(dsi->dev, "Can not find best_freq for DPHY\n"); 637 return -EINVAL; 638 } 639 640 return 0; 641} 642 643struct hstt { 644 unsigned int maxfreq; 645 struct dw_mipi_dsi_dphy_timing timing; 646}; 647 648#define HSTT(_maxfreq, _c_lp2hs, _c_hs2lp, _d_lp2hs, _d_hs2lp) \ 649{ \ 650 .maxfreq = _maxfreq, \ 651 .timing = { \ 652 .clk_lp2hs = _c_lp2hs, \ 653 .clk_hs2lp = _c_hs2lp, \ 654 .data_lp2hs = _d_lp2hs, \ 655 .data_hs2lp = _d_hs2lp, \ 656 } \ 657} 658 659/* Table A-3 High-Speed Transition Times */ 660static struct hstt hstt_table[] = { 661 HSTT( 90, 32, 20, 26, 13), 662 HSTT( 100, 35, 23, 28, 14), 663 HSTT( 110, 32, 22, 26, 13), 664 HSTT( 130, 31, 20, 27, 13), 665 HSTT( 140, 33, 22, 26, 14), 666 HSTT( 150, 33, 21, 26, 14), 667 HSTT( 170, 32, 20, 27, 13), 668 HSTT( 180, 36, 23, 30, 15), 669 HSTT( 200, 40, 22, 33, 15), 670 HSTT( 220, 40, 22, 33, 15), 671 HSTT( 240, 44, 24, 36, 16), 672 HSTT( 250, 48, 24, 38, 17), 673 HSTT( 270, 48, 24, 38, 17), 674 HSTT( 300, 50, 27, 41, 18), 675 HSTT( 330, 56, 28, 45, 18), 676 HSTT( 360, 59, 28, 48, 19), 677 HSTT( 400, 61, 30, 50, 20), 678 HSTT( 450, 67, 31, 55, 21), 679 HSTT( 500, 73, 31, 59, 22), 680 HSTT( 550, 79, 36, 63, 24), 681 HSTT( 600, 83, 37, 68, 25), 682 HSTT( 650, 90, 38, 73, 27), 683 HSTT( 700, 95, 40, 77, 28), 684 HSTT( 750, 102, 40, 84, 28), 685 HSTT( 800, 106, 42, 87, 30), 686 HSTT( 850, 113, 44, 93, 31), 687 HSTT( 900, 118, 47, 98, 32), 688 HSTT( 950, 124, 47, 102, 34), 689 HSTT(1000, 130, 49, 107, 35), 690 HSTT(1050, 135, 51, 111, 37), 691 HSTT(1100, 139, 51, 114, 38), 692 HSTT(1150, 146, 54, 120, 40), 693 HSTT(1200, 153, 57, 125, 41), 694 HSTT(1250, 158, 58, 130, 42), 695 HSTT(1300, 163, 58, 135, 44), 696 HSTT(1350, 168, 60, 140, 45), 697 HSTT(1400, 172, 64, 144, 47), 698 HSTT(1450, 176, 65, 148, 48), 699 HSTT(1500, 181, 66, 153, 50) 700}; 701 702static int 703dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps, 704 struct dw_mipi_dsi_dphy_timing *timing) 705{ 706 int i; 707 708 for (i = 0; i < ARRAY_SIZE(hstt_table); i++) 709 if (lane_mbps < hstt_table[i].maxfreq) 710 break; 711 712 if (i == ARRAY_SIZE(hstt_table)) 713 i--; 714 715 *timing = hstt_table[i].timing; 716 717 return 0; 718} 719 720static const struct dw_mipi_dsi_phy_ops dw_mipi_dsi_rockchip_phy_ops = { 721 .init = dw_mipi_dsi_phy_init, 722 .power_on = dw_mipi_dsi_phy_power_on, 723 .power_off = dw_mipi_dsi_phy_power_off, 724 .get_lane_mbps = dw_mipi_dsi_get_lane_mbps, 725 .get_timing = dw_mipi_dsi_phy_get_timing, 726}; 727 728static void dw_mipi_dsi_rockchip_config(struct dw_mipi_dsi_rockchip *dsi) 729{ 730 if (dsi->cdata->lanecfg1_grf_reg) 731 regmap_write(dsi->grf_regmap, dsi->cdata->lanecfg1_grf_reg, 732 dsi->cdata->lanecfg1); 733 734 if (dsi->cdata->lanecfg2_grf_reg) 735 regmap_write(dsi->grf_regmap, dsi->cdata->lanecfg2_grf_reg, 736 dsi->cdata->lanecfg2); 737 738 if (dsi->cdata->enable_grf_reg) 739 regmap_write(dsi->grf_regmap, dsi->cdata->enable_grf_reg, 740 dsi->cdata->enable); 741} 742 743static void dw_mipi_dsi_rockchip_set_lcdsel(struct dw_mipi_dsi_rockchip *dsi, 744 int mux) 745{ 746 if (dsi->cdata->lcdsel_grf_reg) 747 regmap_write(dsi->grf_regmap, dsi->cdata->lcdsel_grf_reg, 748 mux ? dsi->cdata->lcdsel_lit : dsi->cdata->lcdsel_big); 749} 750 751static int 752dw_mipi_dsi_encoder_atomic_check(struct drm_encoder *encoder, 753 struct drm_crtc_state *crtc_state, 754 struct drm_connector_state *conn_state) 755{ 756 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state); 757 struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder); 758 759 switch (dsi->format) { 760 case MIPI_DSI_FMT_RGB888: 761 s->output_mode = ROCKCHIP_OUT_MODE_P888; 762 break; 763 case MIPI_DSI_FMT_RGB666: 764 s->output_mode = ROCKCHIP_OUT_MODE_P666; 765 break; 766 case MIPI_DSI_FMT_RGB565: 767 s->output_mode = ROCKCHIP_OUT_MODE_P565; 768 break; 769 default: 770 WARN_ON(1); 771 return -EINVAL; 772 } 773 774 s->output_type = DRM_MODE_CONNECTOR_DSI; 775 if (dsi->slave) 776 s->output_flags = ROCKCHIP_OUTPUT_DSI_DUAL; 777 778 return 0; 779} 780 781static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder) 782{ 783 struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder); 784 int ret, mux; 785 786 mux = drm_of_encoder_active_endpoint_id(dsi->dev->of_node, 787 &dsi->encoder.encoder); 788 if (mux < 0) 789 return; 790 791 /* 792 * For the RK3399, the clk of grf must be enabled before writing grf 793 * register. And for RK3288 or other soc, this grf_clk must be NULL, 794 * the clk_prepare_enable return true directly. 795 */ 796 ret = clk_prepare_enable(dsi->grf_clk); 797 if (ret) { 798 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); 799 return; 800 } 801 802 dw_mipi_dsi_rockchip_set_lcdsel(dsi, mux); 803 if (dsi->slave) 804 dw_mipi_dsi_rockchip_set_lcdsel(dsi->slave, mux); 805 806 clk_disable_unprepare(dsi->grf_clk); 807} 808 809static const struct drm_encoder_helper_funcs 810dw_mipi_dsi_encoder_helper_funcs = { 811 .atomic_check = dw_mipi_dsi_encoder_atomic_check, 812 .enable = dw_mipi_dsi_encoder_enable, 813}; 814 815static int rockchip_dsi_drm_create_encoder(struct dw_mipi_dsi_rockchip *dsi, 816 struct drm_device *drm_dev) 817{ 818 struct drm_encoder *encoder = &dsi->encoder.encoder; 819 int ret; 820 821 encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev, 822 dsi->dev->of_node); 823 824 ret = drm_simple_encoder_init(drm_dev, encoder, DRM_MODE_ENCODER_DSI); 825 if (ret) { 826 DRM_ERROR("Failed to initialize encoder with drm\n"); 827 return ret; 828 } 829 830 drm_encoder_helper_add(encoder, &dw_mipi_dsi_encoder_helper_funcs); 831 832 return 0; 833} 834 835static struct device 836*dw_mipi_dsi_rockchip_find_second(struct dw_mipi_dsi_rockchip *dsi) 837{ 838 const struct of_device_id *match; 839 struct device_node *node = NULL, *local; 840 841 match = of_match_device(dsi->dev->driver->of_match_table, dsi->dev); 842 843 local = of_graph_get_remote_node(dsi->dev->of_node, 1, 0); 844 if (!local) 845 return NULL; 846 847 while ((node = of_find_compatible_node(node, NULL, 848 match->compatible))) { 849 struct device_node *remote; 850 851 /* found ourself */ 852 if (node == dsi->dev->of_node) 853 continue; 854 855 remote = of_graph_get_remote_node(node, 1, 0); 856 if (!remote) 857 continue; 858 859 /* same display device in port1-ep0 for both */ 860 if (remote == local) { 861 struct dw_mipi_dsi_rockchip *dsi2; 862 struct platform_device *pdev; 863 864 pdev = of_find_device_by_node(node); 865 866 /* 867 * we have found the second, so will either return it 868 * or return with an error. In any case won't need the 869 * nodes anymore nor continue the loop. 870 */ 871 of_node_put(remote); 872 of_node_put(node); 873 of_node_put(local); 874 875 if (!pdev) 876 return ERR_PTR(-EPROBE_DEFER); 877 878 dsi2 = platform_get_drvdata(pdev); 879 if (!dsi2) { 880 platform_device_put(pdev); 881 return ERR_PTR(-EPROBE_DEFER); 882 } 883 884 return &pdev->dev; 885 } 886 887 of_node_put(remote); 888 } 889 890 of_node_put(local); 891 892 return NULL; 893} 894 895static int dw_mipi_dsi_rockchip_bind(struct device *dev, 896 struct device *master, 897 void *data) 898{ 899 struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev); 900 struct drm_device *drm_dev = data; 901 struct device *second; 902 bool master1, master2; 903 int ret; 904 905 second = dw_mipi_dsi_rockchip_find_second(dsi); 906 if (IS_ERR(second)) 907 return PTR_ERR(second); 908 909 if (second) { 910 master1 = of_property_read_bool(dsi->dev->of_node, 911 "clock-master"); 912 master2 = of_property_read_bool(second->of_node, 913 "clock-master"); 914 915 if (master1 && master2) { 916 DRM_DEV_ERROR(dsi->dev, "only one clock-master allowed\n"); 917 return -EINVAL; 918 } 919 920 if (!master1 && !master2) { 921 DRM_DEV_ERROR(dsi->dev, "no clock-master defined\n"); 922 return -EINVAL; 923 } 924 925 /* we are the slave in dual-DSI */ 926 if (!master1) { 927 dsi->is_slave = true; 928 return 0; 929 } 930 931 dsi->slave = dev_get_drvdata(second); 932 if (!dsi->slave) { 933 DRM_DEV_ERROR(dev, "could not get slaves data\n"); 934 return -ENODEV; 935 } 936 937 dsi->slave->is_slave = true; 938 dw_mipi_dsi_set_slave(dsi->dmd, dsi->slave->dmd); 939 put_device(second); 940 } 941 942 pm_runtime_get_sync(dsi->dev); 943 if (dsi->slave) 944 pm_runtime_get_sync(dsi->slave->dev); 945 946 ret = clk_prepare_enable(dsi->pllref_clk); 947 if (ret) { 948 DRM_DEV_ERROR(dev, "Failed to enable pllref_clk: %d\n", ret); 949 goto out_pm_runtime; 950 } 951 952 /* 953 * With the GRF clock running, write lane and dual-mode configurations 954 * that won't change immediately. If we waited until enable() to do 955 * this, things like panel preparation would not be able to send 956 * commands over DSI. 957 */ 958 ret = clk_prepare_enable(dsi->grf_clk); 959 if (ret) { 960 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); 961 goto out_pll_clk; 962 } 963 964 dw_mipi_dsi_rockchip_config(dsi); 965 if (dsi->slave) 966 dw_mipi_dsi_rockchip_config(dsi->slave); 967 968 clk_disable_unprepare(dsi->grf_clk); 969 970 ret = rockchip_dsi_drm_create_encoder(dsi, drm_dev); 971 if (ret) { 972 DRM_DEV_ERROR(dev, "Failed to create drm encoder\n"); 973 goto out_pll_clk; 974 } 975 rockchip_drm_encoder_set_crtc_endpoint_id(&dsi->encoder, 976 dev->of_node, 0, 0); 977 978 ret = dw_mipi_dsi_bind(dsi->dmd, &dsi->encoder.encoder); 979 if (ret) { 980 DRM_DEV_ERROR(dev, "Failed to bind: %d\n", ret); 981 goto out_pll_clk; 982 } 983 984 dsi->dsi_bound = true; 985 986 return 0; 987 988out_pll_clk: 989 clk_disable_unprepare(dsi->pllref_clk); 990out_pm_runtime: 991 pm_runtime_put(dsi->dev); 992 if (dsi->slave) 993 pm_runtime_put(dsi->slave->dev); 994 995 return ret; 996} 997 998static void dw_mipi_dsi_rockchip_unbind(struct device *dev, 999 struct device *master, 1000 void *data) 1001{ 1002 struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev); 1003 1004 if (dsi->is_slave) 1005 return; 1006 1007 dsi->dsi_bound = false; 1008 1009 dw_mipi_dsi_unbind(dsi->dmd); 1010 1011 clk_disable_unprepare(dsi->pllref_clk); 1012 1013 pm_runtime_put(dsi->dev); 1014 if (dsi->slave) 1015 pm_runtime_put(dsi->slave->dev); 1016} 1017 1018static const struct component_ops dw_mipi_dsi_rockchip_ops = { 1019 .bind = dw_mipi_dsi_rockchip_bind, 1020 .unbind = dw_mipi_dsi_rockchip_unbind, 1021}; 1022 1023static int dw_mipi_dsi_rockchip_host_attach(void *priv_data, 1024 struct mipi_dsi_device *device) 1025{ 1026 struct dw_mipi_dsi_rockchip *dsi = priv_data; 1027 struct device *second; 1028 int ret; 1029 1030 mutex_lock(&dsi->usage_mutex); 1031 1032 if (dsi->usage_mode != DW_DSI_USAGE_IDLE) { 1033 DRM_DEV_ERROR(dsi->dev, "dsi controller already in use\n"); 1034 mutex_unlock(&dsi->usage_mutex); 1035 return -EBUSY; 1036 } 1037 1038 dsi->usage_mode = DW_DSI_USAGE_DSI; 1039 mutex_unlock(&dsi->usage_mutex); 1040 1041 ret = component_add(dsi->dev, &dw_mipi_dsi_rockchip_ops); 1042 if (ret) { 1043 DRM_DEV_ERROR(dsi->dev, "Failed to register component: %d\n", 1044 ret); 1045 goto out; 1046 } 1047 1048 second = dw_mipi_dsi_rockchip_find_second(dsi); 1049 if (IS_ERR(second)) { 1050 ret = PTR_ERR(second); 1051 goto out; 1052 } 1053 if (second) { 1054 ret = component_add(second, &dw_mipi_dsi_rockchip_ops); 1055 if (ret) { 1056 DRM_DEV_ERROR(second, 1057 "Failed to register component: %d\n", 1058 ret); 1059 goto out; 1060 } 1061 } 1062 1063 return 0; 1064 1065out: 1066 mutex_lock(&dsi->usage_mutex); 1067 dsi->usage_mode = DW_DSI_USAGE_IDLE; 1068 mutex_unlock(&dsi->usage_mutex); 1069 return ret; 1070} 1071 1072static int dw_mipi_dsi_rockchip_host_detach(void *priv_data, 1073 struct mipi_dsi_device *device) 1074{ 1075 struct dw_mipi_dsi_rockchip *dsi = priv_data; 1076 struct device *second; 1077 1078 second = dw_mipi_dsi_rockchip_find_second(dsi); 1079 if (second && !IS_ERR(second)) 1080 component_del(second, &dw_mipi_dsi_rockchip_ops); 1081 1082 component_del(dsi->dev, &dw_mipi_dsi_rockchip_ops); 1083 1084 mutex_lock(&dsi->usage_mutex); 1085 dsi->usage_mode = DW_DSI_USAGE_IDLE; 1086 mutex_unlock(&dsi->usage_mutex); 1087 1088 return 0; 1089} 1090 1091static const struct dw_mipi_dsi_host_ops dw_mipi_dsi_rockchip_host_ops = { 1092 .attach = dw_mipi_dsi_rockchip_host_attach, 1093 .detach = dw_mipi_dsi_rockchip_host_detach, 1094}; 1095 1096static int dw_mipi_dsi_rockchip_dphy_bind(struct device *dev, 1097 struct device *master, 1098 void *data) 1099{ 1100 /* 1101 * Nothing to do when used as a dphy. 1102 * Just make the rest of Rockchip-DRM happy 1103 * by being here. 1104 */ 1105 1106 return 0; 1107} 1108 1109static void dw_mipi_dsi_rockchip_dphy_unbind(struct device *dev, 1110 struct device *master, 1111 void *data) 1112{ 1113 /* Nothing to do when used as a dphy. */ 1114} 1115 1116static const struct component_ops dw_mipi_dsi_rockchip_dphy_ops = { 1117 .bind = dw_mipi_dsi_rockchip_dphy_bind, 1118 .unbind = dw_mipi_dsi_rockchip_dphy_unbind, 1119}; 1120 1121static int dw_mipi_dsi_dphy_init(struct phy *phy) 1122{ 1123 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); 1124 int ret; 1125 1126 mutex_lock(&dsi->usage_mutex); 1127 1128 if (dsi->usage_mode != DW_DSI_USAGE_IDLE) { 1129 DRM_DEV_ERROR(dsi->dev, "dsi controller already in use\n"); 1130 mutex_unlock(&dsi->usage_mutex); 1131 return -EBUSY; 1132 } 1133 1134 dsi->usage_mode = DW_DSI_USAGE_PHY; 1135 mutex_unlock(&dsi->usage_mutex); 1136 1137 ret = component_add(dsi->dev, &dw_mipi_dsi_rockchip_dphy_ops); 1138 if (ret < 0) 1139 goto err_graph; 1140 1141 if (dsi->cdata->dphy_rx_init) { 1142 ret = clk_prepare_enable(dsi->pclk); 1143 if (ret < 0) 1144 goto err_init; 1145 1146 ret = clk_prepare_enable(dsi->grf_clk); 1147 if (ret) { 1148 clk_disable_unprepare(dsi->pclk); 1149 goto err_init; 1150 } 1151 1152 ret = dsi->cdata->dphy_rx_init(phy); 1153 clk_disable_unprepare(dsi->grf_clk); 1154 clk_disable_unprepare(dsi->pclk); 1155 if (ret < 0) 1156 goto err_init; 1157 } 1158 1159 return 0; 1160 1161err_init: 1162 component_del(dsi->dev, &dw_mipi_dsi_rockchip_dphy_ops); 1163err_graph: 1164 mutex_lock(&dsi->usage_mutex); 1165 dsi->usage_mode = DW_DSI_USAGE_IDLE; 1166 mutex_unlock(&dsi->usage_mutex); 1167 1168 return ret; 1169} 1170 1171static int dw_mipi_dsi_dphy_exit(struct phy *phy) 1172{ 1173 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); 1174 1175 component_del(dsi->dev, &dw_mipi_dsi_rockchip_dphy_ops); 1176 1177 mutex_lock(&dsi->usage_mutex); 1178 dsi->usage_mode = DW_DSI_USAGE_IDLE; 1179 mutex_unlock(&dsi->usage_mutex); 1180 1181 return 0; 1182} 1183 1184static int dw_mipi_dsi_dphy_configure(struct phy *phy, union phy_configure_opts *opts) 1185{ 1186 struct phy_configure_opts_mipi_dphy *config = &opts->mipi_dphy; 1187 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); 1188 int ret; 1189 1190 ret = phy_mipi_dphy_config_validate(&opts->mipi_dphy); 1191 if (ret) 1192 return ret; 1193 1194 dsi->dphy_config = *config; 1195 dsi->lane_mbps = div_u64(config->hs_clk_rate, 1000 * 1000 * 1); 1196 1197 return 0; 1198} 1199 1200static int dw_mipi_dsi_dphy_power_on(struct phy *phy) 1201{ 1202 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); 1203 int i, ret; 1204 1205 DRM_DEV_DEBUG(dsi->dev, "lanes %d - data_rate_mbps %u\n", 1206 dsi->dphy_config.lanes, dsi->lane_mbps); 1207 1208 i = max_mbps_to_parameter(dsi->lane_mbps); 1209 if (i < 0) { 1210 DRM_DEV_ERROR(dsi->dev, "failed to get parameter for %dmbps clock\n", 1211 dsi->lane_mbps); 1212 return i; 1213 } 1214 1215 ret = pm_runtime_resume_and_get(dsi->dev); 1216 if (ret < 0) { 1217 DRM_DEV_ERROR(dsi->dev, "failed to enable device: %d\n", ret); 1218 return ret; 1219 } 1220 1221 ret = clk_prepare_enable(dsi->pclk); 1222 if (ret) { 1223 DRM_DEV_ERROR(dsi->dev, "Failed to enable pclk: %d\n", ret); 1224 goto err_pclk; 1225 } 1226 1227 ret = clk_prepare_enable(dsi->grf_clk); 1228 if (ret) { 1229 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); 1230 goto err_grf_clk; 1231 } 1232 1233 ret = clk_prepare_enable(dsi->phy_cfg_clk); 1234 if (ret) { 1235 DRM_DEV_ERROR(dsi->dev, "Failed to enable phy_cfg_clk: %d\n", ret); 1236 goto err_phy_cfg_clk; 1237 } 1238 1239 /* do soc-variant specific init */ 1240 if (dsi->cdata->dphy_rx_power_on) { 1241 ret = dsi->cdata->dphy_rx_power_on(phy); 1242 if (ret < 0) { 1243 DRM_DEV_ERROR(dsi->dev, "hardware-specific phy bringup failed: %d\n", ret); 1244 goto err_pwr_on; 1245 } 1246 } 1247 1248 /* 1249 * Configure hsfreqrange according to frequency values 1250 * Set clock lane and hsfreqrange by lane0(test code 0x44) 1251 */ 1252 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_CLK, 0); 1253 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_0, 1254 HSFREQRANGE_SEL(dppa_map[i].hsfreqrange)); 1255 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_1, 0); 1256 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_2, 0); 1257 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_3, 0); 1258 1259 /* Normal operation */ 1260 dw_mipi_dsi_phy_write(dsi, 0x0, 0); 1261 1262 clk_disable_unprepare(dsi->phy_cfg_clk); 1263 clk_disable_unprepare(dsi->grf_clk); 1264 1265 return ret; 1266 1267err_pwr_on: 1268 clk_disable_unprepare(dsi->phy_cfg_clk); 1269err_phy_cfg_clk: 1270 clk_disable_unprepare(dsi->grf_clk); 1271err_grf_clk: 1272 clk_disable_unprepare(dsi->pclk); 1273err_pclk: 1274 pm_runtime_put(dsi->dev); 1275 return ret; 1276} 1277 1278static int dw_mipi_dsi_dphy_power_off(struct phy *phy) 1279{ 1280 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); 1281 int ret; 1282 1283 ret = clk_prepare_enable(dsi->grf_clk); 1284 if (ret) { 1285 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); 1286 return ret; 1287 } 1288 1289 if (dsi->cdata->dphy_rx_power_off) { 1290 ret = dsi->cdata->dphy_rx_power_off(phy); 1291 if (ret < 0) 1292 DRM_DEV_ERROR(dsi->dev, "hardware-specific phy shutdown failed: %d\n", ret); 1293 } 1294 1295 clk_disable_unprepare(dsi->grf_clk); 1296 clk_disable_unprepare(dsi->pclk); 1297 1298 pm_runtime_put(dsi->dev); 1299 1300 return ret; 1301} 1302 1303static const struct phy_ops dw_mipi_dsi_dphy_ops = { 1304 .configure = dw_mipi_dsi_dphy_configure, 1305 .power_on = dw_mipi_dsi_dphy_power_on, 1306 .power_off = dw_mipi_dsi_dphy_power_off, 1307 .init = dw_mipi_dsi_dphy_init, 1308 .exit = dw_mipi_dsi_dphy_exit, 1309}; 1310 1311static int __maybe_unused dw_mipi_dsi_rockchip_resume(struct device *dev) 1312{ 1313 struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev); 1314 int ret; 1315 1316 /* 1317 * Re-configure DSI state, if we were previously initialized. We need 1318 * to do this before rockchip_drm_drv tries to re-enable() any panels. 1319 */ 1320 if (dsi->dsi_bound) { 1321 ret = clk_prepare_enable(dsi->grf_clk); 1322 if (ret) { 1323 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); 1324 return ret; 1325 } 1326 1327 dw_mipi_dsi_rockchip_config(dsi); 1328 if (dsi->slave) 1329 dw_mipi_dsi_rockchip_config(dsi->slave); 1330 1331 clk_disable_unprepare(dsi->grf_clk); 1332 } 1333 1334 return 0; 1335} 1336 1337static const struct dev_pm_ops dw_mipi_dsi_rockchip_pm_ops = { 1338 SET_LATE_SYSTEM_SLEEP_PM_OPS(NULL, dw_mipi_dsi_rockchip_resume) 1339}; 1340 1341static int dw_mipi_dsi_rockchip_probe(struct platform_device *pdev) 1342{ 1343 struct device *dev = &pdev->dev; 1344 struct device_node *np = dev->of_node; 1345 struct dw_mipi_dsi_rockchip *dsi; 1346 struct phy_provider *phy_provider; 1347 struct resource *res; 1348 const struct rockchip_dw_dsi_chip_data *cdata = 1349 of_device_get_match_data(dev); 1350 int ret, i; 1351 1352 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL); 1353 if (!dsi) 1354 return -ENOMEM; 1355 1356 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1357 dsi->base = devm_ioremap_resource(dev, res); 1358 if (IS_ERR(dsi->base)) { 1359 DRM_DEV_ERROR(dev, "Unable to get dsi registers\n"); 1360 return PTR_ERR(dsi->base); 1361 } 1362 1363 i = 0; 1364 while (cdata[i].reg) { 1365 if (cdata[i].reg == res->start) { 1366 dsi->cdata = &cdata[i]; 1367 break; 1368 } 1369 1370 i++; 1371 } 1372 1373 if (!dsi->cdata) { 1374 DRM_DEV_ERROR(dev, "no dsi-config for %s node\n", np->name); 1375 return -EINVAL; 1376 } 1377 1378 /* try to get a possible external dphy */ 1379 dsi->phy = devm_phy_optional_get(dev, "dphy"); 1380 if (IS_ERR(dsi->phy)) { 1381 ret = PTR_ERR(dsi->phy); 1382 DRM_DEV_ERROR(dev, "failed to get mipi dphy: %d\n", ret); 1383 return ret; 1384 } 1385 1386 dsi->pclk = devm_clk_get(dev, "pclk"); 1387 if (IS_ERR(dsi->pclk)) { 1388 ret = PTR_ERR(dsi->pclk); 1389 DRM_DEV_ERROR(dev, "Unable to get pclk: %d\n", ret); 1390 return ret; 1391 } 1392 1393 dsi->pllref_clk = devm_clk_get(dev, "ref"); 1394 if (IS_ERR(dsi->pllref_clk)) { 1395 if (dsi->phy) { 1396 /* 1397 * if external phy is present, pll will be 1398 * generated there. 1399 */ 1400 dsi->pllref_clk = NULL; 1401 } else { 1402 ret = PTR_ERR(dsi->pllref_clk); 1403 DRM_DEV_ERROR(dev, 1404 "Unable to get pll reference clock: %d\n", 1405 ret); 1406 return ret; 1407 } 1408 } 1409 1410 if (dsi->cdata->flags & DW_MIPI_NEEDS_PHY_CFG_CLK) { 1411 dsi->phy_cfg_clk = devm_clk_get(dev, "phy_cfg"); 1412 if (IS_ERR(dsi->phy_cfg_clk)) { 1413 ret = PTR_ERR(dsi->phy_cfg_clk); 1414 DRM_DEV_ERROR(dev, 1415 "Unable to get phy_cfg_clk: %d\n", ret); 1416 return ret; 1417 } 1418 } 1419 1420 if (dsi->cdata->flags & DW_MIPI_NEEDS_GRF_CLK) { 1421 dsi->grf_clk = devm_clk_get(dev, "grf"); 1422 if (IS_ERR(dsi->grf_clk)) { 1423 ret = PTR_ERR(dsi->grf_clk); 1424 DRM_DEV_ERROR(dev, "Unable to get grf_clk: %d\n", ret); 1425 return ret; 1426 } 1427 } 1428 1429 dsi->grf_regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); 1430 if (IS_ERR(dsi->grf_regmap)) { 1431 DRM_DEV_ERROR(dev, "Unable to get rockchip,grf\n"); 1432 return PTR_ERR(dsi->grf_regmap); 1433 } 1434 1435 dsi->dev = dev; 1436 dsi->pdata.base = dsi->base; 1437 dsi->pdata.max_data_lanes = dsi->cdata->max_data_lanes; 1438 dsi->pdata.phy_ops = &dw_mipi_dsi_rockchip_phy_ops; 1439 dsi->pdata.host_ops = &dw_mipi_dsi_rockchip_host_ops; 1440 dsi->pdata.priv_data = dsi; 1441 platform_set_drvdata(pdev, dsi); 1442 1443 mutex_init(&dsi->usage_mutex); 1444 1445 dsi->dphy = devm_phy_create(dev, NULL, &dw_mipi_dsi_dphy_ops); 1446 if (IS_ERR(dsi->dphy)) { 1447 DRM_DEV_ERROR(&pdev->dev, "failed to create PHY\n"); 1448 return PTR_ERR(dsi->dphy); 1449 } 1450 1451 phy_set_drvdata(dsi->dphy, dsi); 1452 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 1453 if (IS_ERR(phy_provider)) 1454 return PTR_ERR(phy_provider); 1455 1456 dsi->dmd = dw_mipi_dsi_probe(pdev, &dsi->pdata); 1457 if (IS_ERR(dsi->dmd)) { 1458 ret = PTR_ERR(dsi->dmd); 1459 if (ret != -EPROBE_DEFER) 1460 DRM_DEV_ERROR(dev, 1461 "Failed to probe dw_mipi_dsi: %d\n", ret); 1462 return ret; 1463 } 1464 1465 return 0; 1466} 1467 1468static void dw_mipi_dsi_rockchip_remove(struct platform_device *pdev) 1469{ 1470 struct dw_mipi_dsi_rockchip *dsi = platform_get_drvdata(pdev); 1471 1472 dw_mipi_dsi_remove(dsi->dmd); 1473} 1474 1475static const struct rockchip_dw_dsi_chip_data px30_chip_data[] = { 1476 { 1477 .reg = 0xff450000, 1478 .lcdsel_grf_reg = PX30_GRF_PD_VO_CON1, 1479 .lcdsel_big = HIWORD_UPDATE(0, PX30_DSI_LCDC_SEL), 1480 .lcdsel_lit = HIWORD_UPDATE(PX30_DSI_LCDC_SEL, 1481 PX30_DSI_LCDC_SEL), 1482 1483 .lanecfg1_grf_reg = PX30_GRF_PD_VO_CON1, 1484 .lanecfg1 = HIWORD_UPDATE(0, PX30_DSI_TURNDISABLE | 1485 PX30_DSI_FORCERXMODE | 1486 PX30_DSI_FORCETXSTOPMODE), 1487 1488 .max_data_lanes = 4, 1489 }, 1490 { /* sentinel */ } 1491}; 1492 1493static const struct rockchip_dw_dsi_chip_data rk3288_chip_data[] = { 1494 { 1495 .reg = 0xff960000, 1496 .lcdsel_grf_reg = RK3288_GRF_SOC_CON6, 1497 .lcdsel_big = HIWORD_UPDATE(0, RK3288_DSI0_LCDC_SEL), 1498 .lcdsel_lit = HIWORD_UPDATE(RK3288_DSI0_LCDC_SEL, RK3288_DSI0_LCDC_SEL), 1499 1500 .max_data_lanes = 4, 1501 }, 1502 { 1503 .reg = 0xff964000, 1504 .lcdsel_grf_reg = RK3288_GRF_SOC_CON6, 1505 .lcdsel_big = HIWORD_UPDATE(0, RK3288_DSI1_LCDC_SEL), 1506 .lcdsel_lit = HIWORD_UPDATE(RK3288_DSI1_LCDC_SEL, RK3288_DSI1_LCDC_SEL), 1507 1508 .max_data_lanes = 4, 1509 }, 1510 { /* sentinel */ } 1511}; 1512 1513static int rk3399_dphy_tx1rx1_init(struct phy *phy) 1514{ 1515 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); 1516 1517 /* 1518 * Set TX1RX1 source to isp1. 1519 * Assume ISP0 is supplied by the RX0 dphy. 1520 */ 1521 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, 1522 HIWORD_UPDATE(0, RK3399_TXRX_SRC_SEL_ISP0)); 1523 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, 1524 HIWORD_UPDATE(0, RK3399_TXRX_MASTERSLAVEZ)); 1525 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, 1526 HIWORD_UPDATE(0, RK3399_TXRX_BASEDIR)); 1527 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, 1528 HIWORD_UPDATE(0, RK3399_DSI1_ENABLE)); 1529 1530 return 0; 1531} 1532 1533static int rk3399_dphy_tx1rx1_power_on(struct phy *phy) 1534{ 1535 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); 1536 1537 /* tester reset pulse */ 1538 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_TESTCLR); 1539 usleep_range(100, 150); 1540 1541 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, 1542 HIWORD_UPDATE(0, RK3399_TXRX_MASTERSLAVEZ)); 1543 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, 1544 HIWORD_UPDATE(RK3399_TXRX_BASEDIR, RK3399_TXRX_BASEDIR)); 1545 1546 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, 1547 HIWORD_UPDATE(0, RK3399_DSI1_FORCERXMODE)); 1548 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, 1549 HIWORD_UPDATE(0, RK3399_DSI1_FORCETXSTOPMODE)); 1550 1551 /* Disable lane turn around, which is ignored in receive mode */ 1552 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, 1553 HIWORD_UPDATE(0, RK3399_TXRX_TURNREQUEST)); 1554 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, 1555 HIWORD_UPDATE(RK3399_DSI1_TURNDISABLE, 1556 RK3399_DSI1_TURNDISABLE)); 1557 usleep_range(100, 150); 1558 1559 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR); 1560 usleep_range(100, 150); 1561 1562 /* Enable dphy lanes */ 1563 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, 1564 HIWORD_UPDATE(GENMASK(dsi->dphy_config.lanes - 1, 0), 1565 RK3399_DSI1_ENABLE)); 1566 1567 usleep_range(100, 150); 1568 1569 return 0; 1570} 1571 1572static int rk3399_dphy_tx1rx1_power_off(struct phy *phy) 1573{ 1574 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); 1575 1576 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, 1577 HIWORD_UPDATE(0, RK3399_DSI1_ENABLE)); 1578 1579 return 0; 1580} 1581 1582static const struct rockchip_dw_dsi_chip_data rk3399_chip_data[] = { 1583 { 1584 .reg = 0xff960000, 1585 .lcdsel_grf_reg = RK3399_GRF_SOC_CON20, 1586 .lcdsel_big = HIWORD_UPDATE(0, RK3399_DSI0_LCDC_SEL), 1587 .lcdsel_lit = HIWORD_UPDATE(RK3399_DSI0_LCDC_SEL, 1588 RK3399_DSI0_LCDC_SEL), 1589 1590 .lanecfg1_grf_reg = RK3399_GRF_SOC_CON22, 1591 .lanecfg1 = HIWORD_UPDATE(0, RK3399_DSI0_TURNREQUEST | 1592 RK3399_DSI0_TURNDISABLE | 1593 RK3399_DSI0_FORCETXSTOPMODE | 1594 RK3399_DSI0_FORCERXMODE), 1595 1596 .flags = DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK, 1597 .max_data_lanes = 4, 1598 }, 1599 { 1600 .reg = 0xff968000, 1601 .lcdsel_grf_reg = RK3399_GRF_SOC_CON20, 1602 .lcdsel_big = HIWORD_UPDATE(0, RK3399_DSI1_LCDC_SEL), 1603 .lcdsel_lit = HIWORD_UPDATE(RK3399_DSI1_LCDC_SEL, 1604 RK3399_DSI1_LCDC_SEL), 1605 1606 .lanecfg1_grf_reg = RK3399_GRF_SOC_CON23, 1607 .lanecfg1 = HIWORD_UPDATE(0, RK3399_DSI1_TURNDISABLE | 1608 RK3399_DSI1_FORCETXSTOPMODE | 1609 RK3399_DSI1_FORCERXMODE | 1610 RK3399_DSI1_ENABLE), 1611 1612 .lanecfg2_grf_reg = RK3399_GRF_SOC_CON24, 1613 .lanecfg2 = HIWORD_UPDATE(RK3399_TXRX_MASTERSLAVEZ | 1614 RK3399_TXRX_ENABLECLK, 1615 RK3399_TXRX_MASTERSLAVEZ | 1616 RK3399_TXRX_ENABLECLK | 1617 RK3399_TXRX_BASEDIR), 1618 1619 .enable_grf_reg = RK3399_GRF_SOC_CON23, 1620 .enable = HIWORD_UPDATE(RK3399_DSI1_ENABLE, RK3399_DSI1_ENABLE), 1621 1622 .flags = DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK, 1623 .max_data_lanes = 4, 1624 1625 .dphy_rx_init = rk3399_dphy_tx1rx1_init, 1626 .dphy_rx_power_on = rk3399_dphy_tx1rx1_power_on, 1627 .dphy_rx_power_off = rk3399_dphy_tx1rx1_power_off, 1628 }, 1629 { /* sentinel */ } 1630}; 1631 1632static const struct rockchip_dw_dsi_chip_data rk3568_chip_data[] = { 1633 { 1634 .reg = 0xfe060000, 1635 .lanecfg1_grf_reg = RK3568_GRF_VO_CON2, 1636 .lanecfg1 = HIWORD_UPDATE(0, RK3568_DSI0_SKEWCALHS | 1637 RK3568_DSI0_FORCETXSTOPMODE | 1638 RK3568_DSI0_TURNDISABLE | 1639 RK3568_DSI0_FORCERXMODE), 1640 .max_data_lanes = 4, 1641 }, 1642 { 1643 .reg = 0xfe070000, 1644 .lanecfg1_grf_reg = RK3568_GRF_VO_CON3, 1645 .lanecfg1 = HIWORD_UPDATE(0, RK3568_DSI1_SKEWCALHS | 1646 RK3568_DSI1_FORCETXSTOPMODE | 1647 RK3568_DSI1_TURNDISABLE | 1648 RK3568_DSI1_FORCERXMODE), 1649 .max_data_lanes = 4, 1650 }, 1651 { /* sentinel */ } 1652}; 1653 1654static const struct of_device_id dw_mipi_dsi_rockchip_dt_ids[] = { 1655 { 1656 .compatible = "rockchip,px30-mipi-dsi", 1657 .data = &px30_chip_data, 1658 }, { 1659 .compatible = "rockchip,rk3288-mipi-dsi", 1660 .data = &rk3288_chip_data, 1661 }, { 1662 .compatible = "rockchip,rk3399-mipi-dsi", 1663 .data = &rk3399_chip_data, 1664 }, { 1665 .compatible = "rockchip,rk3568-mipi-dsi", 1666 .data = &rk3568_chip_data, 1667 }, 1668 { /* sentinel */ } 1669}; 1670MODULE_DEVICE_TABLE(of, dw_mipi_dsi_rockchip_dt_ids); 1671 1672struct platform_driver dw_mipi_dsi_rockchip_driver = { 1673 .probe = dw_mipi_dsi_rockchip_probe, 1674 .remove_new = dw_mipi_dsi_rockchip_remove, 1675 .driver = { 1676 .of_match_table = dw_mipi_dsi_rockchip_dt_ids, 1677 .pm = &dw_mipi_dsi_rockchip_pm_ops, 1678 .name = "dw-mipi-dsi-rockchip", 1679 /* 1680 * For dual-DSI display, one DSI pokes at the other DSI's 1681 * drvdata in dw_mipi_dsi_rockchip_find_second(). This is not 1682 * safe for asynchronous probe. 1683 */ 1684 .probe_type = PROBE_FORCE_SYNCHRONOUS, 1685 }, 1686}; 1687