1/* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29#include <linux/pci.h> 30#include <linux/seq_file.h> 31#include <linux/slab.h> 32 33#include <drm/drm.h> 34#include <drm/drm_device.h> 35#include <drm/drm_file.h> 36#include <drm/radeon_drm.h> 37 38#include "r100_track.h" 39#include "r300_reg_safe.h" 40#include "r300d.h" 41#include "radeon.h" 42#include "radeon_asic.h" 43#include "radeon_reg.h" 44#include "rv350d.h" 45 46/* This files gather functions specifics to: r300,r350,rv350,rv370,rv380 47 * 48 * GPU Errata: 49 * - HOST_PATH_CNTL: r300 family seems to dislike write to HOST_PATH_CNTL 50 * using MMIO to flush host path read cache, this lead to HARDLOCKUP. 51 * However, scheduling such write to the ring seems harmless, i suspect 52 * the CP read collide with the flush somehow, or maybe the MC, hard to 53 * tell. (Jerome Glisse) 54 */ 55 56/* 57 * Indirect registers accessor 58 */ 59uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) 60{ 61 unsigned long flags; 62 uint32_t r; 63 64 spin_lock_irqsave(&rdev->pcie_idx_lock, flags); 65 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); 66 r = RREG32(RADEON_PCIE_DATA); 67 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags); 68 return r; 69} 70 71void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 72{ 73 unsigned long flags; 74 75 spin_lock_irqsave(&rdev->pcie_idx_lock, flags); 76 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); 77 WREG32(RADEON_PCIE_DATA, (v)); 78 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags); 79} 80 81/* 82 * rv370,rv380 PCIE GART 83 */ 84static void rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev); 85 86void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev) 87{ 88 uint32_t tmp; 89 int i; 90 91 /* Workaround HW bug do flush 2 times */ 92 for (i = 0; i < 2; i++) { 93 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); 94 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB); 95 (void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); 96 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); 97 } 98 mb(); 99} 100 101#define R300_PTE_UNSNOOPED (1 << 0) 102#define R300_PTE_WRITEABLE (1 << 2) 103#define R300_PTE_READABLE (1 << 3) 104 105uint64_t rv370_pcie_gart_get_page_entry(uint64_t addr, uint32_t flags) 106{ 107 addr = (lower_32_bits(addr) >> 8) | 108 ((upper_32_bits(addr) & 0xff) << 24); 109 if (flags & RADEON_GART_PAGE_READ) 110 addr |= R300_PTE_READABLE; 111 if (flags & RADEON_GART_PAGE_WRITE) 112 addr |= R300_PTE_WRITEABLE; 113 if (!(flags & RADEON_GART_PAGE_SNOOP)) 114 addr |= R300_PTE_UNSNOOPED; 115 return addr; 116} 117 118void rv370_pcie_gart_set_page(struct radeon_device *rdev, unsigned i, 119 uint64_t entry) 120{ 121 void __iomem *ptr = rdev->gart.ptr; 122 123 /* on x86 we want this to be CPU endian, on powerpc 124 * on powerpc without HW swappers, it'll get swapped on way 125 * into VRAM - so no need for cpu_to_le32 on VRAM tables */ 126 writel(entry, ((void __iomem *)ptr) + (i * 4)); 127} 128 129int rv370_pcie_gart_init(struct radeon_device *rdev) 130{ 131 int r; 132 133 if (rdev->gart.robj) { 134 WARN(1, "RV370 PCIE GART already initialized\n"); 135 return 0; 136 } 137 /* Initialize common gart structure */ 138 r = radeon_gart_init(rdev); 139 if (r) 140 return r; 141 rv370_debugfs_pcie_gart_info_init(rdev); 142 143 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; 144 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush; 145 rdev->asic->gart.get_page_entry = &rv370_pcie_gart_get_page_entry; 146 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page; 147 return radeon_gart_table_vram_alloc(rdev); 148} 149 150int rv370_pcie_gart_enable(struct radeon_device *rdev) 151{ 152 uint32_t table_addr; 153 uint32_t tmp; 154 int r; 155 156 if (rdev->gart.robj == NULL) { 157 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); 158 return -EINVAL; 159 } 160 r = radeon_gart_table_vram_pin(rdev); 161 if (r) 162 return r; 163 /* discard memory request outside of configured range */ 164 tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; 165 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); 166 WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_start); 167 tmp = rdev->mc.gtt_end & ~RADEON_GPU_PAGE_MASK; 168 WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp); 169 WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0); 170 WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0); 171 table_addr = rdev->gart.table_addr; 172 WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr); 173 /* FIXME: setup default page */ 174 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_start); 175 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0); 176 /* Clear error */ 177 WREG32_PCIE(RADEON_PCIE_TX_GART_ERROR, 0); 178 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); 179 tmp |= RADEON_PCIE_TX_GART_EN; 180 tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; 181 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); 182 rv370_pcie_gart_tlb_flush(rdev); 183 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 184 (unsigned)(rdev->mc.gtt_size >> 20), 185 (unsigned long long)table_addr); 186 rdev->gart.ready = true; 187 return 0; 188} 189 190void rv370_pcie_gart_disable(struct radeon_device *rdev) 191{ 192 u32 tmp; 193 194 WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, 0); 195 WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, 0); 196 WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0); 197 WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0); 198 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); 199 tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; 200 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN); 201 radeon_gart_table_vram_unpin(rdev); 202} 203 204void rv370_pcie_gart_fini(struct radeon_device *rdev) 205{ 206 radeon_gart_fini(rdev); 207 rv370_pcie_gart_disable(rdev); 208 radeon_gart_table_vram_free(rdev); 209} 210 211void r300_fence_ring_emit(struct radeon_device *rdev, 212 struct radeon_fence *fence) 213{ 214 struct radeon_ring *ring = &rdev->ring[fence->ring]; 215 216 /* Who ever call radeon_fence_emit should call ring_lock and ask 217 * for enough space (today caller are ib schedule and buffer move) */ 218 /* Write SC register so SC & US assert idle */ 219 radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_TL, 0)); 220 radeon_ring_write(ring, 0); 221 radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_BR, 0)); 222 radeon_ring_write(ring, 0); 223 /* Flush 3D cache */ 224 radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); 225 radeon_ring_write(ring, R300_RB3D_DC_FLUSH); 226 radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); 227 radeon_ring_write(ring, R300_ZC_FLUSH); 228 /* Wait until IDLE & CLEAN */ 229 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); 230 radeon_ring_write(ring, (RADEON_WAIT_3D_IDLECLEAN | 231 RADEON_WAIT_2D_IDLECLEAN | 232 RADEON_WAIT_DMA_GUI_IDLE)); 233 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); 234 radeon_ring_write(ring, rdev->config.r300.hdp_cntl | 235 RADEON_HDP_READ_BUFFER_INVALIDATE); 236 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); 237 radeon_ring_write(ring, rdev->config.r300.hdp_cntl); 238 /* Emit fence sequence & fire IRQ */ 239 radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0)); 240 radeon_ring_write(ring, fence->seq); 241 radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0)); 242 radeon_ring_write(ring, RADEON_SW_INT_FIRE); 243} 244 245void r300_ring_start(struct radeon_device *rdev, struct radeon_ring *ring) 246{ 247 unsigned gb_tile_config; 248 int r; 249 250 /* Sub pixel 1/12 so we can have 4K rendering according to doc */ 251 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16); 252 switch (rdev->num_gb_pipes) { 253 case 2: 254 gb_tile_config |= R300_PIPE_COUNT_R300; 255 break; 256 case 3: 257 gb_tile_config |= R300_PIPE_COUNT_R420_3P; 258 break; 259 case 4: 260 gb_tile_config |= R300_PIPE_COUNT_R420; 261 break; 262 case 1: 263 default: 264 gb_tile_config |= R300_PIPE_COUNT_RV350; 265 break; 266 } 267 268 r = radeon_ring_lock(rdev, ring, 64); 269 if (r) { 270 return; 271 } 272 radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0)); 273 radeon_ring_write(ring, 274 RADEON_ISYNC_ANY2D_IDLE3D | 275 RADEON_ISYNC_ANY3D_IDLE2D | 276 RADEON_ISYNC_WAIT_IDLEGUI | 277 RADEON_ISYNC_CPSCRATCH_IDLEGUI); 278 radeon_ring_write(ring, PACKET0(R300_GB_TILE_CONFIG, 0)); 279 radeon_ring_write(ring, gb_tile_config); 280 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); 281 radeon_ring_write(ring, 282 RADEON_WAIT_2D_IDLECLEAN | 283 RADEON_WAIT_3D_IDLECLEAN); 284 radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0)); 285 radeon_ring_write(ring, R300_PIPE_AUTO_CONFIG); 286 radeon_ring_write(ring, PACKET0(R300_GB_SELECT, 0)); 287 radeon_ring_write(ring, 0); 288 radeon_ring_write(ring, PACKET0(R300_GB_ENABLE, 0)); 289 radeon_ring_write(ring, 0); 290 radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); 291 radeon_ring_write(ring, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); 292 radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); 293 radeon_ring_write(ring, R300_ZC_FLUSH | R300_ZC_FREE); 294 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); 295 radeon_ring_write(ring, 296 RADEON_WAIT_2D_IDLECLEAN | 297 RADEON_WAIT_3D_IDLECLEAN); 298 radeon_ring_write(ring, PACKET0(R300_GB_AA_CONFIG, 0)); 299 radeon_ring_write(ring, 0); 300 radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); 301 radeon_ring_write(ring, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); 302 radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); 303 radeon_ring_write(ring, R300_ZC_FLUSH | R300_ZC_FREE); 304 radeon_ring_write(ring, PACKET0(R300_GB_MSPOS0, 0)); 305 radeon_ring_write(ring, 306 ((6 << R300_MS_X0_SHIFT) | 307 (6 << R300_MS_Y0_SHIFT) | 308 (6 << R300_MS_X1_SHIFT) | 309 (6 << R300_MS_Y1_SHIFT) | 310 (6 << R300_MS_X2_SHIFT) | 311 (6 << R300_MS_Y2_SHIFT) | 312 (6 << R300_MSBD0_Y_SHIFT) | 313 (6 << R300_MSBD0_X_SHIFT))); 314 radeon_ring_write(ring, PACKET0(R300_GB_MSPOS1, 0)); 315 radeon_ring_write(ring, 316 ((6 << R300_MS_X3_SHIFT) | 317 (6 << R300_MS_Y3_SHIFT) | 318 (6 << R300_MS_X4_SHIFT) | 319 (6 << R300_MS_Y4_SHIFT) | 320 (6 << R300_MS_X5_SHIFT) | 321 (6 << R300_MS_Y5_SHIFT) | 322 (6 << R300_MSBD1_SHIFT))); 323 radeon_ring_write(ring, PACKET0(R300_GA_ENHANCE, 0)); 324 radeon_ring_write(ring, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL); 325 radeon_ring_write(ring, PACKET0(R300_GA_POLY_MODE, 0)); 326 radeon_ring_write(ring, 327 R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE); 328 radeon_ring_write(ring, PACKET0(R300_GA_ROUND_MODE, 0)); 329 radeon_ring_write(ring, 330 R300_GEOMETRY_ROUND_NEAREST | 331 R300_COLOR_ROUND_NEAREST); 332 radeon_ring_unlock_commit(rdev, ring, false); 333} 334 335static void r300_errata(struct radeon_device *rdev) 336{ 337 rdev->pll_errata = 0; 338 339 if (rdev->family == CHIP_R300 && 340 (RREG32(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) == RADEON_CFG_ATI_REV_A11) { 341 rdev->pll_errata |= CHIP_ERRATA_R300_CG; 342 } 343} 344 345int r300_mc_wait_for_idle(struct radeon_device *rdev) 346{ 347 unsigned i; 348 uint32_t tmp; 349 350 for (i = 0; i < rdev->usec_timeout; i++) { 351 /* read MC_STATUS */ 352 tmp = RREG32(RADEON_MC_STATUS); 353 if (tmp & R300_MC_IDLE) { 354 return 0; 355 } 356 udelay(1); 357 } 358 return -1; 359} 360 361static void r300_gpu_init(struct radeon_device *rdev) 362{ 363 uint32_t gb_tile_config, tmp; 364 365 if ((rdev->family == CHIP_R300 && rdev->pdev->device != 0x4144) || 366 (rdev->family == CHIP_R350 && rdev->pdev->device != 0x4148)) { 367 /* r300,r350 */ 368 rdev->num_gb_pipes = 2; 369 } else { 370 /* rv350,rv370,rv380,r300 AD, r350 AH */ 371 rdev->num_gb_pipes = 1; 372 } 373 rdev->num_z_pipes = 1; 374 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16); 375 switch (rdev->num_gb_pipes) { 376 case 2: 377 gb_tile_config |= R300_PIPE_COUNT_R300; 378 break; 379 case 3: 380 gb_tile_config |= R300_PIPE_COUNT_R420_3P; 381 break; 382 case 4: 383 gb_tile_config |= R300_PIPE_COUNT_R420; 384 break; 385 default: 386 case 1: 387 gb_tile_config |= R300_PIPE_COUNT_RV350; 388 break; 389 } 390 WREG32(R300_GB_TILE_CONFIG, gb_tile_config); 391 392 if (r100_gui_wait_for_idle(rdev)) { 393 pr_warn("Failed to wait GUI idle while programming pipes. Bad things might happen.\n"); 394 } 395 396 tmp = RREG32(R300_DST_PIPE_CONFIG); 397 WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG); 398 399 WREG32(R300_RB2D_DSTCACHE_MODE, 400 R300_DC_AUTOFLUSH_ENABLE | 401 R300_DC_DC_DISABLE_IGNORE_PE); 402 403 if (r100_gui_wait_for_idle(rdev)) { 404 pr_warn("Failed to wait GUI idle while programming pipes. Bad things might happen.\n"); 405 } 406 if (r300_mc_wait_for_idle(rdev)) { 407 pr_warn("Failed to wait MC idle while programming pipes. Bad things might happen.\n"); 408 } 409 DRM_INFO("radeon: %d quad pipes, %d Z pipes initialized\n", 410 rdev->num_gb_pipes, rdev->num_z_pipes); 411} 412 413int r300_asic_reset(struct radeon_device *rdev, bool hard) 414{ 415 struct r100_mc_save save; 416 u32 status, tmp; 417 int ret = 0; 418 419 status = RREG32(R_000E40_RBBM_STATUS); 420 if (!G_000E40_GUI_ACTIVE(status)) { 421 return 0; 422 } 423 r100_mc_stop(rdev, &save); 424 status = RREG32(R_000E40_RBBM_STATUS); 425 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 426 /* stop CP */ 427 WREG32(RADEON_CP_CSQ_CNTL, 0); 428 tmp = RREG32(RADEON_CP_RB_CNTL); 429 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); 430 WREG32(RADEON_CP_RB_RPTR_WR, 0); 431 WREG32(RADEON_CP_RB_WPTR, 0); 432 WREG32(RADEON_CP_RB_CNTL, tmp); 433 /* save PCI state */ 434 pci_save_state(rdev->pdev); 435 /* disable bus mastering */ 436 r100_bm_disable(rdev); 437 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) | 438 S_0000F0_SOFT_RESET_GA(1)); 439 RREG32(R_0000F0_RBBM_SOFT_RESET); 440 mdelay(500); 441 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 442 mdelay(1); 443 status = RREG32(R_000E40_RBBM_STATUS); 444 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 445 /* resetting the CP seems to be problematic sometimes it end up 446 * hard locking the computer, but it's necessary for successful 447 * reset more test & playing is needed on R3XX/R4XX to find a 448 * reliable (if any solution) 449 */ 450 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1)); 451 RREG32(R_0000F0_RBBM_SOFT_RESET); 452 mdelay(500); 453 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 454 mdelay(1); 455 status = RREG32(R_000E40_RBBM_STATUS); 456 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 457 /* restore PCI & busmastering */ 458 pci_restore_state(rdev->pdev); 459 r100_enable_bm(rdev); 460 /* Check if GPU is idle */ 461 if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) { 462 dev_err(rdev->dev, "failed to reset GPU\n"); 463 ret = -1; 464 } else 465 dev_info(rdev->dev, "GPU reset succeed\n"); 466 r100_mc_resume(rdev, &save); 467 return ret; 468} 469 470/* 471 * r300,r350,rv350,rv380 VRAM info 472 */ 473void r300_mc_init(struct radeon_device *rdev) 474{ 475 u64 base; 476 u32 tmp; 477 478 /* DDR for all card after R300 & IGP */ 479 rdev->mc.vram_is_ddr = true; 480 tmp = RREG32(RADEON_MEM_CNTL); 481 tmp &= R300_MEM_NUM_CHANNELS_MASK; 482 switch (tmp) { 483 case 0: rdev->mc.vram_width = 64; break; 484 case 1: rdev->mc.vram_width = 128; break; 485 case 2: rdev->mc.vram_width = 256; break; 486 default: rdev->mc.vram_width = 128; break; 487 } 488 r100_vram_init_sizes(rdev); 489 base = rdev->mc.aper_base; 490 if (rdev->flags & RADEON_IS_IGP) 491 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; 492 radeon_vram_location(rdev, &rdev->mc, base); 493 rdev->mc.gtt_base_align = 0; 494 if (!(rdev->flags & RADEON_IS_AGP)) 495 radeon_gtt_location(rdev, &rdev->mc); 496 radeon_update_bandwidth_info(rdev); 497} 498 499void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes) 500{ 501 uint32_t link_width_cntl, mask; 502 503 if (rdev->flags & RADEON_IS_IGP) 504 return; 505 506 if (!(rdev->flags & RADEON_IS_PCIE)) 507 return; 508 509 /* FIXME wait for idle */ 510 511 switch (lanes) { 512 case 0: 513 mask = RADEON_PCIE_LC_LINK_WIDTH_X0; 514 break; 515 case 1: 516 mask = RADEON_PCIE_LC_LINK_WIDTH_X1; 517 break; 518 case 2: 519 mask = RADEON_PCIE_LC_LINK_WIDTH_X2; 520 break; 521 case 4: 522 mask = RADEON_PCIE_LC_LINK_WIDTH_X4; 523 break; 524 case 8: 525 mask = RADEON_PCIE_LC_LINK_WIDTH_X8; 526 break; 527 case 12: 528 mask = RADEON_PCIE_LC_LINK_WIDTH_X12; 529 break; 530 case 16: 531 default: 532 mask = RADEON_PCIE_LC_LINK_WIDTH_X16; 533 break; 534 } 535 536 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 537 538 if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) == 539 (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT)) 540 return; 541 542 link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK | 543 RADEON_PCIE_LC_RECONFIG_NOW | 544 RADEON_PCIE_LC_RECONFIG_LATER | 545 RADEON_PCIE_LC_SHORT_RECONFIG_EN); 546 link_width_cntl |= mask; 547 WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 548 WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl | 549 RADEON_PCIE_LC_RECONFIG_NOW)); 550 551 /* wait for lane set to complete */ 552 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 553 while (link_width_cntl == 0xffffffff) 554 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 555 556} 557 558int rv370_get_pcie_lanes(struct radeon_device *rdev) 559{ 560 u32 link_width_cntl; 561 562 if (rdev->flags & RADEON_IS_IGP) 563 return 0; 564 565 if (!(rdev->flags & RADEON_IS_PCIE)) 566 return 0; 567 568 /* FIXME wait for idle */ 569 570 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 571 572 switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) { 573 case RADEON_PCIE_LC_LINK_WIDTH_X0: 574 return 0; 575 case RADEON_PCIE_LC_LINK_WIDTH_X1: 576 return 1; 577 case RADEON_PCIE_LC_LINK_WIDTH_X2: 578 return 2; 579 case RADEON_PCIE_LC_LINK_WIDTH_X4: 580 return 4; 581 case RADEON_PCIE_LC_LINK_WIDTH_X8: 582 return 8; 583 case RADEON_PCIE_LC_LINK_WIDTH_X16: 584 default: 585 return 16; 586 } 587} 588 589#if defined(CONFIG_DEBUG_FS) 590static int rv370_debugfs_pcie_gart_info_show(struct seq_file *m, void *unused) 591{ 592 struct radeon_device *rdev = m->private; 593 uint32_t tmp; 594 595 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); 596 seq_printf(m, "PCIE_TX_GART_CNTL 0x%08x\n", tmp); 597 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE); 598 seq_printf(m, "PCIE_TX_GART_BASE 0x%08x\n", tmp); 599 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO); 600 seq_printf(m, "PCIE_TX_GART_START_LO 0x%08x\n", tmp); 601 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI); 602 seq_printf(m, "PCIE_TX_GART_START_HI 0x%08x\n", tmp); 603 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO); 604 seq_printf(m, "PCIE_TX_GART_END_LO 0x%08x\n", tmp); 605 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI); 606 seq_printf(m, "PCIE_TX_GART_END_HI 0x%08x\n", tmp); 607 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_ERROR); 608 seq_printf(m, "PCIE_TX_GART_ERROR 0x%08x\n", tmp); 609 return 0; 610} 611 612DEFINE_SHOW_ATTRIBUTE(rv370_debugfs_pcie_gart_info); 613#endif 614 615static void rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev) 616{ 617#if defined(CONFIG_DEBUG_FS) 618 struct dentry *root = rdev->ddev->primary->debugfs_root; 619 620 debugfs_create_file("rv370_pcie_gart_info", 0444, root, rdev, 621 &rv370_debugfs_pcie_gart_info_fops); 622#endif 623} 624 625static int r300_packet0_check(struct radeon_cs_parser *p, 626 struct radeon_cs_packet *pkt, 627 unsigned idx, unsigned reg) 628{ 629 struct radeon_bo_list *reloc; 630 struct r100_cs_track *track; 631 volatile uint32_t *ib; 632 uint32_t tmp, tile_flags = 0; 633 unsigned i; 634 int r; 635 u32 idx_value; 636 637 ib = p->ib.ptr; 638 track = (struct r100_cs_track *)p->track; 639 idx_value = radeon_get_ib_value(p, idx); 640 641 switch (reg) { 642 case AVIVO_D1MODE_VLINE_START_END: 643 case RADEON_CRTC_GUI_TRIG_VLINE: 644 r = r100_cs_packet_parse_vline(p); 645 if (r) { 646 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 647 idx, reg); 648 radeon_cs_dump_packet(p, pkt); 649 return r; 650 } 651 break; 652 case RADEON_DST_PITCH_OFFSET: 653 case RADEON_SRC_PITCH_OFFSET: 654 r = r100_reloc_pitch_offset(p, pkt, idx, reg); 655 if (r) 656 return r; 657 break; 658 case R300_RB3D_COLOROFFSET0: 659 case R300_RB3D_COLOROFFSET1: 660 case R300_RB3D_COLOROFFSET2: 661 case R300_RB3D_COLOROFFSET3: 662 i = (reg - R300_RB3D_COLOROFFSET0) >> 2; 663 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 664 if (r) { 665 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 666 idx, reg); 667 radeon_cs_dump_packet(p, pkt); 668 return r; 669 } 670 track->cb[i].robj = reloc->robj; 671 track->cb[i].offset = idx_value; 672 track->cb_dirty = true; 673 ib[idx] = idx_value + ((u32)reloc->gpu_offset); 674 break; 675 case R300_ZB_DEPTHOFFSET: 676 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 677 if (r) { 678 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 679 idx, reg); 680 radeon_cs_dump_packet(p, pkt); 681 return r; 682 } 683 track->zb.robj = reloc->robj; 684 track->zb.offset = idx_value; 685 track->zb_dirty = true; 686 ib[idx] = idx_value + ((u32)reloc->gpu_offset); 687 break; 688 case R300_TX_OFFSET_0: 689 case R300_TX_OFFSET_0+4: 690 case R300_TX_OFFSET_0+8: 691 case R300_TX_OFFSET_0+12: 692 case R300_TX_OFFSET_0+16: 693 case R300_TX_OFFSET_0+20: 694 case R300_TX_OFFSET_0+24: 695 case R300_TX_OFFSET_0+28: 696 case R300_TX_OFFSET_0+32: 697 case R300_TX_OFFSET_0+36: 698 case R300_TX_OFFSET_0+40: 699 case R300_TX_OFFSET_0+44: 700 case R300_TX_OFFSET_0+48: 701 case R300_TX_OFFSET_0+52: 702 case R300_TX_OFFSET_0+56: 703 case R300_TX_OFFSET_0+60: 704 i = (reg - R300_TX_OFFSET_0) >> 2; 705 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 706 if (r) { 707 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 708 idx, reg); 709 radeon_cs_dump_packet(p, pkt); 710 return r; 711 } 712 713 if (p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) { 714 ib[idx] = (idx_value & 31) | /* keep the 1st 5 bits */ 715 ((idx_value & ~31) + (u32)reloc->gpu_offset); 716 } else { 717 if (reloc->tiling_flags & RADEON_TILING_MACRO) 718 tile_flags |= R300_TXO_MACRO_TILE; 719 if (reloc->tiling_flags & RADEON_TILING_MICRO) 720 tile_flags |= R300_TXO_MICRO_TILE; 721 else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE) 722 tile_flags |= R300_TXO_MICRO_TILE_SQUARE; 723 724 tmp = idx_value + ((u32)reloc->gpu_offset); 725 tmp |= tile_flags; 726 ib[idx] = tmp; 727 } 728 track->textures[i].robj = reloc->robj; 729 track->tex_dirty = true; 730 break; 731 /* Tracked registers */ 732 case 0x2084: 733 /* VAP_VF_CNTL */ 734 track->vap_vf_cntl = idx_value; 735 break; 736 case 0x20B4: 737 /* VAP_VTX_SIZE */ 738 track->vtx_size = idx_value & 0x7F; 739 break; 740 case 0x2134: 741 /* VAP_VF_MAX_VTX_INDX */ 742 track->max_indx = idx_value & 0x00FFFFFFUL; 743 break; 744 case 0x2088: 745 /* VAP_ALT_NUM_VERTICES - only valid on r500 */ 746 if (p->rdev->family < CHIP_RV515) 747 goto fail; 748 track->vap_alt_nverts = idx_value & 0xFFFFFF; 749 break; 750 case 0x43E4: 751 /* SC_SCISSOR1 */ 752 track->maxy = ((idx_value >> 13) & 0x1FFF) + 1; 753 if (p->rdev->family < CHIP_RV515) { 754 track->maxy -= 1440; 755 } 756 track->cb_dirty = true; 757 track->zb_dirty = true; 758 break; 759 case 0x4E00: 760 /* RB3D_CCTL */ 761 if ((idx_value & (1 << 10)) && /* CMASK_ENABLE */ 762 p->rdev->cmask_filp != p->filp) { 763 DRM_ERROR("Invalid RB3D_CCTL: Cannot enable CMASK.\n"); 764 return -EINVAL; 765 } 766 track->num_cb = ((idx_value >> 5) & 0x3) + 1; 767 track->cb_dirty = true; 768 break; 769 case 0x4E38: 770 case 0x4E3C: 771 case 0x4E40: 772 case 0x4E44: 773 /* RB3D_COLORPITCH0 */ 774 /* RB3D_COLORPITCH1 */ 775 /* RB3D_COLORPITCH2 */ 776 /* RB3D_COLORPITCH3 */ 777 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 778 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 779 if (r) { 780 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 781 idx, reg); 782 radeon_cs_dump_packet(p, pkt); 783 return r; 784 } 785 786 if (reloc->tiling_flags & RADEON_TILING_MACRO) 787 tile_flags |= R300_COLOR_TILE_ENABLE; 788 if (reloc->tiling_flags & RADEON_TILING_MICRO) 789 tile_flags |= R300_COLOR_MICROTILE_ENABLE; 790 else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE) 791 tile_flags |= R300_COLOR_MICROTILE_SQUARE_ENABLE; 792 793 tmp = idx_value & ~(0x7 << 16); 794 tmp |= tile_flags; 795 ib[idx] = tmp; 796 } 797 i = (reg - 0x4E38) >> 2; 798 track->cb[i].pitch = idx_value & 0x3FFE; 799 switch (((idx_value >> 21) & 0xF)) { 800 case 9: 801 case 11: 802 case 12: 803 track->cb[i].cpp = 1; 804 break; 805 case 3: 806 case 4: 807 case 13: 808 case 15: 809 track->cb[i].cpp = 2; 810 break; 811 case 5: 812 if (p->rdev->family < CHIP_RV515) { 813 DRM_ERROR("Invalid color buffer format (%d)!\n", 814 ((idx_value >> 21) & 0xF)); 815 return -EINVAL; 816 } 817 fallthrough; 818 case 6: 819 track->cb[i].cpp = 4; 820 break; 821 case 10: 822 track->cb[i].cpp = 8; 823 break; 824 case 7: 825 track->cb[i].cpp = 16; 826 break; 827 default: 828 DRM_ERROR("Invalid color buffer format (%d) !\n", 829 ((idx_value >> 21) & 0xF)); 830 return -EINVAL; 831 } 832 track->cb_dirty = true; 833 break; 834 case 0x4F00: 835 /* ZB_CNTL */ 836 if (idx_value & 2) { 837 track->z_enabled = true; 838 } else { 839 track->z_enabled = false; 840 } 841 track->zb_dirty = true; 842 break; 843 case 0x4F10: 844 /* ZB_FORMAT */ 845 switch ((idx_value & 0xF)) { 846 case 0: 847 case 1: 848 track->zb.cpp = 2; 849 break; 850 case 2: 851 track->zb.cpp = 4; 852 break; 853 default: 854 DRM_ERROR("Invalid z buffer format (%d) !\n", 855 (idx_value & 0xF)); 856 return -EINVAL; 857 } 858 track->zb_dirty = true; 859 break; 860 case 0x4F24: 861 /* ZB_DEPTHPITCH */ 862 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 863 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 864 if (r) { 865 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 866 idx, reg); 867 radeon_cs_dump_packet(p, pkt); 868 return r; 869 } 870 871 if (reloc->tiling_flags & RADEON_TILING_MACRO) 872 tile_flags |= R300_DEPTHMACROTILE_ENABLE; 873 if (reloc->tiling_flags & RADEON_TILING_MICRO) 874 tile_flags |= R300_DEPTHMICROTILE_TILED; 875 else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE) 876 tile_flags |= R300_DEPTHMICROTILE_TILED_SQUARE; 877 878 tmp = idx_value & ~(0x7 << 16); 879 tmp |= tile_flags; 880 ib[idx] = tmp; 881 } 882 track->zb.pitch = idx_value & 0x3FFC; 883 track->zb_dirty = true; 884 break; 885 case 0x4104: 886 /* TX_ENABLE */ 887 for (i = 0; i < 16; i++) { 888 bool enabled; 889 890 enabled = !!(idx_value & (1 << i)); 891 track->textures[i].enabled = enabled; 892 } 893 track->tex_dirty = true; 894 break; 895 case 0x44C0: 896 case 0x44C4: 897 case 0x44C8: 898 case 0x44CC: 899 case 0x44D0: 900 case 0x44D4: 901 case 0x44D8: 902 case 0x44DC: 903 case 0x44E0: 904 case 0x44E4: 905 case 0x44E8: 906 case 0x44EC: 907 case 0x44F0: 908 case 0x44F4: 909 case 0x44F8: 910 case 0x44FC: 911 /* TX_FORMAT1_[0-15] */ 912 i = (reg - 0x44C0) >> 2; 913 tmp = (idx_value >> 25) & 0x3; 914 track->textures[i].tex_coord_type = tmp; 915 switch ((idx_value & 0x1F)) { 916 case R300_TX_FORMAT_X8: 917 case R300_TX_FORMAT_Y4X4: 918 case R300_TX_FORMAT_Z3Y3X2: 919 track->textures[i].cpp = 1; 920 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 921 break; 922 case R300_TX_FORMAT_X16: 923 case R300_TX_FORMAT_FL_I16: 924 case R300_TX_FORMAT_Y8X8: 925 case R300_TX_FORMAT_Z5Y6X5: 926 case R300_TX_FORMAT_Z6Y5X5: 927 case R300_TX_FORMAT_W4Z4Y4X4: 928 case R300_TX_FORMAT_W1Z5Y5X5: 929 case R300_TX_FORMAT_D3DMFT_CxV8U8: 930 case R300_TX_FORMAT_B8G8_B8G8: 931 case R300_TX_FORMAT_G8R8_G8B8: 932 track->textures[i].cpp = 2; 933 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 934 break; 935 case R300_TX_FORMAT_Y16X16: 936 case R300_TX_FORMAT_FL_I16A16: 937 case R300_TX_FORMAT_Z11Y11X10: 938 case R300_TX_FORMAT_Z10Y11X11: 939 case R300_TX_FORMAT_W8Z8Y8X8: 940 case R300_TX_FORMAT_W2Z10Y10X10: 941 case 0x17: 942 case R300_TX_FORMAT_FL_I32: 943 case 0x1e: 944 track->textures[i].cpp = 4; 945 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 946 break; 947 case R300_TX_FORMAT_W16Z16Y16X16: 948 case R300_TX_FORMAT_FL_R16G16B16A16: 949 case R300_TX_FORMAT_FL_I32A32: 950 track->textures[i].cpp = 8; 951 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 952 break; 953 case R300_TX_FORMAT_FL_R32G32B32A32: 954 track->textures[i].cpp = 16; 955 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 956 break; 957 case R300_TX_FORMAT_DXT1: 958 track->textures[i].cpp = 1; 959 track->textures[i].compress_format = R100_TRACK_COMP_DXT1; 960 break; 961 case R300_TX_FORMAT_ATI2N: 962 if (p->rdev->family < CHIP_R420) { 963 DRM_ERROR("Invalid texture format %u\n", 964 (idx_value & 0x1F)); 965 return -EINVAL; 966 } 967 /* The same rules apply as for DXT3/5. */ 968 fallthrough; 969 case R300_TX_FORMAT_DXT3: 970 case R300_TX_FORMAT_DXT5: 971 track->textures[i].cpp = 1; 972 track->textures[i].compress_format = R100_TRACK_COMP_DXT35; 973 break; 974 default: 975 DRM_ERROR("Invalid texture format %u\n", 976 (idx_value & 0x1F)); 977 return -EINVAL; 978 } 979 track->tex_dirty = true; 980 break; 981 case 0x4400: 982 case 0x4404: 983 case 0x4408: 984 case 0x440C: 985 case 0x4410: 986 case 0x4414: 987 case 0x4418: 988 case 0x441C: 989 case 0x4420: 990 case 0x4424: 991 case 0x4428: 992 case 0x442C: 993 case 0x4430: 994 case 0x4434: 995 case 0x4438: 996 case 0x443C: 997 /* TX_FILTER0_[0-15] */ 998 i = (reg - 0x4400) >> 2; 999 tmp = idx_value & 0x7; 1000 if (tmp == 2 || tmp == 4 || tmp == 6) { 1001 track->textures[i].roundup_w = false; 1002 } 1003 tmp = (idx_value >> 3) & 0x7; 1004 if (tmp == 2 || tmp == 4 || tmp == 6) { 1005 track->textures[i].roundup_h = false; 1006 } 1007 track->tex_dirty = true; 1008 break; 1009 case 0x4500: 1010 case 0x4504: 1011 case 0x4508: 1012 case 0x450C: 1013 case 0x4510: 1014 case 0x4514: 1015 case 0x4518: 1016 case 0x451C: 1017 case 0x4520: 1018 case 0x4524: 1019 case 0x4528: 1020 case 0x452C: 1021 case 0x4530: 1022 case 0x4534: 1023 case 0x4538: 1024 case 0x453C: 1025 /* TX_FORMAT2_[0-15] */ 1026 i = (reg - 0x4500) >> 2; 1027 tmp = idx_value & 0x3FFF; 1028 track->textures[i].pitch = tmp + 1; 1029 if (p->rdev->family >= CHIP_RV515) { 1030 tmp = ((idx_value >> 15) & 1) << 11; 1031 track->textures[i].width_11 = tmp; 1032 tmp = ((idx_value >> 16) & 1) << 11; 1033 track->textures[i].height_11 = tmp; 1034 1035 /* ATI1N */ 1036 if (idx_value & (1 << 14)) { 1037 /* The same rules apply as for DXT1. */ 1038 track->textures[i].compress_format = 1039 R100_TRACK_COMP_DXT1; 1040 } 1041 } else if (idx_value & (1 << 14)) { 1042 DRM_ERROR("Forbidden bit TXFORMAT_MSB\n"); 1043 return -EINVAL; 1044 } 1045 track->tex_dirty = true; 1046 break; 1047 case 0x4480: 1048 case 0x4484: 1049 case 0x4488: 1050 case 0x448C: 1051 case 0x4490: 1052 case 0x4494: 1053 case 0x4498: 1054 case 0x449C: 1055 case 0x44A0: 1056 case 0x44A4: 1057 case 0x44A8: 1058 case 0x44AC: 1059 case 0x44B0: 1060 case 0x44B4: 1061 case 0x44B8: 1062 case 0x44BC: 1063 /* TX_FORMAT0_[0-15] */ 1064 i = (reg - 0x4480) >> 2; 1065 tmp = idx_value & 0x7FF; 1066 track->textures[i].width = tmp + 1; 1067 tmp = (idx_value >> 11) & 0x7FF; 1068 track->textures[i].height = tmp + 1; 1069 tmp = (idx_value >> 26) & 0xF; 1070 track->textures[i].num_levels = tmp; 1071 tmp = idx_value & (1 << 31); 1072 track->textures[i].use_pitch = !!tmp; 1073 tmp = (idx_value >> 22) & 0xF; 1074 track->textures[i].txdepth = tmp; 1075 track->tex_dirty = true; 1076 break; 1077 case R300_ZB_ZPASS_ADDR: 1078 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1079 if (r) { 1080 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1081 idx, reg); 1082 radeon_cs_dump_packet(p, pkt); 1083 return r; 1084 } 1085 ib[idx] = idx_value + ((u32)reloc->gpu_offset); 1086 break; 1087 case 0x4e0c: 1088 /* RB3D_COLOR_CHANNEL_MASK */ 1089 track->color_channel_mask = idx_value; 1090 track->cb_dirty = true; 1091 break; 1092 case 0x43a4: 1093 /* SC_HYPERZ_EN */ 1094 /* r300c emits this register - we need to disable hyperz for it 1095 * without complaining */ 1096 if (p->rdev->hyperz_filp != p->filp) { 1097 if (idx_value & 0x1) 1098 ib[idx] = idx_value & ~1; 1099 } 1100 break; 1101 case 0x4f1c: 1102 /* ZB_BW_CNTL */ 1103 track->zb_cb_clear = !!(idx_value & (1 << 5)); 1104 track->cb_dirty = true; 1105 track->zb_dirty = true; 1106 if (p->rdev->hyperz_filp != p->filp) { 1107 if (idx_value & (R300_HIZ_ENABLE | 1108 R300_RD_COMP_ENABLE | 1109 R300_WR_COMP_ENABLE | 1110 R300_FAST_FILL_ENABLE)) 1111 goto fail; 1112 } 1113 break; 1114 case 0x4e04: 1115 /* RB3D_BLENDCNTL */ 1116 track->blend_read_enable = !!(idx_value & (1 << 2)); 1117 track->cb_dirty = true; 1118 break; 1119 case R300_RB3D_AARESOLVE_OFFSET: 1120 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1121 if (r) { 1122 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1123 idx, reg); 1124 radeon_cs_dump_packet(p, pkt); 1125 return r; 1126 } 1127 track->aa.robj = reloc->robj; 1128 track->aa.offset = idx_value; 1129 track->aa_dirty = true; 1130 ib[idx] = idx_value + ((u32)reloc->gpu_offset); 1131 break; 1132 case R300_RB3D_AARESOLVE_PITCH: 1133 track->aa.pitch = idx_value & 0x3FFE; 1134 track->aa_dirty = true; 1135 break; 1136 case R300_RB3D_AARESOLVE_CTL: 1137 track->aaresolve = idx_value & 0x1; 1138 track->aa_dirty = true; 1139 break; 1140 case 0x4f30: /* ZB_MASK_OFFSET */ 1141 case 0x4f34: /* ZB_ZMASK_PITCH */ 1142 case 0x4f44: /* ZB_HIZ_OFFSET */ 1143 case 0x4f54: /* ZB_HIZ_PITCH */ 1144 if (idx_value && (p->rdev->hyperz_filp != p->filp)) 1145 goto fail; 1146 break; 1147 case 0x4028: 1148 if (idx_value && (p->rdev->hyperz_filp != p->filp)) 1149 goto fail; 1150 /* GB_Z_PEQ_CONFIG */ 1151 if (p->rdev->family >= CHIP_RV350) 1152 break; 1153 goto fail; 1154 break; 1155 case 0x4be8: 1156 /* valid register only on RV530 */ 1157 if (p->rdev->family == CHIP_RV530) 1158 break; 1159 fallthrough; 1160 /* fallthrough do not move */ 1161 default: 1162 goto fail; 1163 } 1164 return 0; 1165fail: 1166 pr_err("Forbidden register 0x%04X in cs at %d (val=%08x)\n", 1167 reg, idx, idx_value); 1168 return -EINVAL; 1169} 1170 1171static int r300_packet3_check(struct radeon_cs_parser *p, 1172 struct radeon_cs_packet *pkt) 1173{ 1174 struct radeon_bo_list *reloc; 1175 struct r100_cs_track *track; 1176 volatile uint32_t *ib; 1177 unsigned idx; 1178 int r; 1179 1180 ib = p->ib.ptr; 1181 idx = pkt->idx + 1; 1182 track = (struct r100_cs_track *)p->track; 1183 switch (pkt->opcode) { 1184 case PACKET3_3D_LOAD_VBPNTR: 1185 r = r100_packet3_load_vbpntr(p, pkt, idx); 1186 if (r) 1187 return r; 1188 break; 1189 case PACKET3_INDX_BUFFER: 1190 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1191 if (r) { 1192 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); 1193 radeon_cs_dump_packet(p, pkt); 1194 return r; 1195 } 1196 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset); 1197 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj); 1198 if (r) { 1199 return r; 1200 } 1201 break; 1202 /* Draw packet */ 1203 case PACKET3_3D_DRAW_IMMD: 1204 /* Number of dwords is vtx_size * (num_vertices - 1) 1205 * PRIM_WALK must be equal to 3 vertex data in embedded 1206 * in cmd stream */ 1207 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) { 1208 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); 1209 return -EINVAL; 1210 } 1211 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 1212 track->immd_dwords = pkt->count - 1; 1213 r = r100_cs_track_check(p->rdev, track); 1214 if (r) { 1215 return r; 1216 } 1217 break; 1218 case PACKET3_3D_DRAW_IMMD_2: 1219 /* Number of dwords is vtx_size * (num_vertices - 1) 1220 * PRIM_WALK must be equal to 3 vertex data in embedded 1221 * in cmd stream */ 1222 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) { 1223 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); 1224 return -EINVAL; 1225 } 1226 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 1227 track->immd_dwords = pkt->count; 1228 r = r100_cs_track_check(p->rdev, track); 1229 if (r) { 1230 return r; 1231 } 1232 break; 1233 case PACKET3_3D_DRAW_VBUF: 1234 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 1235 r = r100_cs_track_check(p->rdev, track); 1236 if (r) { 1237 return r; 1238 } 1239 break; 1240 case PACKET3_3D_DRAW_VBUF_2: 1241 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 1242 r = r100_cs_track_check(p->rdev, track); 1243 if (r) { 1244 return r; 1245 } 1246 break; 1247 case PACKET3_3D_DRAW_INDX: 1248 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 1249 r = r100_cs_track_check(p->rdev, track); 1250 if (r) { 1251 return r; 1252 } 1253 break; 1254 case PACKET3_3D_DRAW_INDX_2: 1255 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 1256 r = r100_cs_track_check(p->rdev, track); 1257 if (r) { 1258 return r; 1259 } 1260 break; 1261 case PACKET3_3D_CLEAR_HIZ: 1262 case PACKET3_3D_CLEAR_ZMASK: 1263 if (p->rdev->hyperz_filp != p->filp) 1264 return -EINVAL; 1265 break; 1266 case PACKET3_3D_CLEAR_CMASK: 1267 if (p->rdev->cmask_filp != p->filp) 1268 return -EINVAL; 1269 break; 1270 case PACKET3_NOP: 1271 break; 1272 default: 1273 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode); 1274 return -EINVAL; 1275 } 1276 return 0; 1277} 1278 1279int r300_cs_parse(struct radeon_cs_parser *p) 1280{ 1281 struct radeon_cs_packet pkt; 1282 struct r100_cs_track *track; 1283 int r; 1284 1285 track = kzalloc(sizeof(*track), GFP_KERNEL); 1286 if (track == NULL) 1287 return -ENOMEM; 1288 r100_cs_track_clear(p->rdev, track); 1289 p->track = track; 1290 do { 1291 r = radeon_cs_packet_parse(p, &pkt, p->idx); 1292 if (r) { 1293 return r; 1294 } 1295 p->idx += pkt.count + 2; 1296 switch (pkt.type) { 1297 case RADEON_PACKET_TYPE0: 1298 r = r100_cs_parse_packet0(p, &pkt, 1299 p->rdev->config.r300.reg_safe_bm, 1300 p->rdev->config.r300.reg_safe_bm_size, 1301 &r300_packet0_check); 1302 break; 1303 case RADEON_PACKET_TYPE2: 1304 break; 1305 case RADEON_PACKET_TYPE3: 1306 r = r300_packet3_check(p, &pkt); 1307 break; 1308 default: 1309 DRM_ERROR("Unknown packet type %d !\n", pkt.type); 1310 return -EINVAL; 1311 } 1312 if (r) { 1313 return r; 1314 } 1315 } while (p->idx < p->chunk_ib->length_dw); 1316 return 0; 1317} 1318 1319void r300_set_reg_safe(struct radeon_device *rdev) 1320{ 1321 rdev->config.r300.reg_safe_bm = r300_reg_safe_bm; 1322 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm); 1323} 1324 1325void r300_mc_program(struct radeon_device *rdev) 1326{ 1327 struct r100_mc_save save; 1328 1329 r100_debugfs_mc_info_init(rdev); 1330 1331 /* Stops all mc clients */ 1332 r100_mc_stop(rdev, &save); 1333 if (rdev->flags & RADEON_IS_AGP) { 1334 WREG32(R_00014C_MC_AGP_LOCATION, 1335 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) | 1336 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); 1337 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); 1338 WREG32(R_00015C_AGP_BASE_2, 1339 upper_32_bits(rdev->mc.agp_base) & 0xff); 1340 } else { 1341 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF); 1342 WREG32(R_000170_AGP_BASE, 0); 1343 WREG32(R_00015C_AGP_BASE_2, 0); 1344 } 1345 /* Wait for mc idle */ 1346 if (r300_mc_wait_for_idle(rdev)) 1347 DRM_INFO("Failed to wait MC idle before programming MC.\n"); 1348 /* Program MC, should be a 32bits limited address space */ 1349 WREG32(R_000148_MC_FB_LOCATION, 1350 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | 1351 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); 1352 r100_mc_resume(rdev, &save); 1353} 1354 1355void r300_clock_startup(struct radeon_device *rdev) 1356{ 1357 u32 tmp; 1358 1359 if (radeon_dynclks != -1 && radeon_dynclks) 1360 radeon_legacy_set_clock_gating(rdev, 1); 1361 /* We need to force on some of the block */ 1362 tmp = RREG32_PLL(R_00000D_SCLK_CNTL); 1363 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1); 1364 if ((rdev->family == CHIP_RV350) || (rdev->family == CHIP_RV380)) 1365 tmp |= S_00000D_FORCE_VAP(1); 1366 WREG32_PLL(R_00000D_SCLK_CNTL, tmp); 1367} 1368 1369static int r300_startup(struct radeon_device *rdev) 1370{ 1371 int r; 1372 1373 /* set common regs */ 1374 r100_set_common_regs(rdev); 1375 /* program mc */ 1376 r300_mc_program(rdev); 1377 /* Resume clock */ 1378 r300_clock_startup(rdev); 1379 /* Initialize GPU configuration (# pipes, ...) */ 1380 r300_gpu_init(rdev); 1381 /* Initialize GART (initialize after TTM so we can allocate 1382 * memory through TTM but finalize after TTM) */ 1383 if (rdev->flags & RADEON_IS_PCIE) { 1384 r = rv370_pcie_gart_enable(rdev); 1385 if (r) 1386 return r; 1387 } 1388 1389 if (rdev->family == CHIP_R300 || 1390 rdev->family == CHIP_R350 || 1391 rdev->family == CHIP_RV350) 1392 r100_enable_bm(rdev); 1393 1394 if (rdev->flags & RADEON_IS_PCI) { 1395 r = r100_pci_gart_enable(rdev); 1396 if (r) 1397 return r; 1398 } 1399 1400 /* allocate wb buffer */ 1401 r = radeon_wb_init(rdev); 1402 if (r) 1403 return r; 1404 1405 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 1406 if (r) { 1407 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 1408 return r; 1409 } 1410 1411 /* Enable IRQ */ 1412 if (!rdev->irq.installed) { 1413 r = radeon_irq_kms_init(rdev); 1414 if (r) 1415 return r; 1416 } 1417 1418 r100_irq_set(rdev); 1419 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 1420 /* 1M ring buffer */ 1421 r = r100_cp_init(rdev, 1024 * 1024); 1422 if (r) { 1423 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); 1424 return r; 1425 } 1426 1427 r = radeon_ib_pool_init(rdev); 1428 if (r) { 1429 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 1430 return r; 1431 } 1432 1433 return 0; 1434} 1435 1436int r300_resume(struct radeon_device *rdev) 1437{ 1438 int r; 1439 1440 /* Make sur GART are not working */ 1441 if (rdev->flags & RADEON_IS_PCIE) 1442 rv370_pcie_gart_disable(rdev); 1443 if (rdev->flags & RADEON_IS_PCI) 1444 r100_pci_gart_disable(rdev); 1445 /* Resume clock before doing reset */ 1446 r300_clock_startup(rdev); 1447 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 1448 if (radeon_asic_reset(rdev)) { 1449 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 1450 RREG32(R_000E40_RBBM_STATUS), 1451 RREG32(R_0007C0_CP_STAT)); 1452 } 1453 /* post */ 1454 radeon_combios_asic_init(rdev->ddev); 1455 /* Resume clock after posting */ 1456 r300_clock_startup(rdev); 1457 /* Initialize surface registers */ 1458 radeon_surface_init(rdev); 1459 1460 rdev->accel_working = true; 1461 r = r300_startup(rdev); 1462 if (r) { 1463 rdev->accel_working = false; 1464 } 1465 return r; 1466} 1467 1468int r300_suspend(struct radeon_device *rdev) 1469{ 1470 radeon_pm_suspend(rdev); 1471 r100_cp_disable(rdev); 1472 radeon_wb_disable(rdev); 1473 r100_irq_disable(rdev); 1474 if (rdev->flags & RADEON_IS_PCIE) 1475 rv370_pcie_gart_disable(rdev); 1476 if (rdev->flags & RADEON_IS_PCI) 1477 r100_pci_gart_disable(rdev); 1478 return 0; 1479} 1480 1481void r300_fini(struct radeon_device *rdev) 1482{ 1483 radeon_pm_fini(rdev); 1484 r100_cp_fini(rdev); 1485 radeon_wb_fini(rdev); 1486 radeon_ib_pool_fini(rdev); 1487 radeon_gem_fini(rdev); 1488 if (rdev->flags & RADEON_IS_PCIE) 1489 rv370_pcie_gart_fini(rdev); 1490 if (rdev->flags & RADEON_IS_PCI) 1491 r100_pci_gart_fini(rdev); 1492 radeon_agp_fini(rdev); 1493 radeon_irq_kms_fini(rdev); 1494 radeon_fence_driver_fini(rdev); 1495 radeon_bo_fini(rdev); 1496 radeon_atombios_fini(rdev); 1497 kfree(rdev->bios); 1498 rdev->bios = NULL; 1499} 1500 1501int r300_init(struct radeon_device *rdev) 1502{ 1503 int r; 1504 1505 /* Disable VGA */ 1506 r100_vga_render_disable(rdev); 1507 /* Initialize scratch registers */ 1508 radeon_scratch_init(rdev); 1509 /* Initialize surface registers */ 1510 radeon_surface_init(rdev); 1511 /* TODO: disable VGA need to use VGA request */ 1512 /* restore some register to sane defaults */ 1513 r100_restore_sanity(rdev); 1514 /* BIOS*/ 1515 if (!radeon_get_bios(rdev)) { 1516 if (ASIC_IS_AVIVO(rdev)) 1517 return -EINVAL; 1518 } 1519 if (rdev->is_atom_bios) { 1520 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n"); 1521 return -EINVAL; 1522 } else { 1523 r = radeon_combios_init(rdev); 1524 if (r) 1525 return r; 1526 } 1527 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 1528 if (radeon_asic_reset(rdev)) { 1529 dev_warn(rdev->dev, 1530 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 1531 RREG32(R_000E40_RBBM_STATUS), 1532 RREG32(R_0007C0_CP_STAT)); 1533 } 1534 /* check if cards are posted or not */ 1535 if (radeon_boot_test_post_card(rdev) == false) 1536 return -EINVAL; 1537 /* Set asic errata */ 1538 r300_errata(rdev); 1539 /* Initialize clocks */ 1540 radeon_get_clock_info(rdev->ddev); 1541 /* initialize AGP */ 1542 if (rdev->flags & RADEON_IS_AGP) { 1543 r = radeon_agp_init(rdev); 1544 if (r) { 1545 radeon_agp_disable(rdev); 1546 } 1547 } 1548 /* initialize memory controller */ 1549 r300_mc_init(rdev); 1550 /* Fence driver */ 1551 radeon_fence_driver_init(rdev); 1552 /* Memory manager */ 1553 r = radeon_bo_init(rdev); 1554 if (r) 1555 return r; 1556 if (rdev->flags & RADEON_IS_PCIE) { 1557 r = rv370_pcie_gart_init(rdev); 1558 if (r) 1559 return r; 1560 } 1561 if (rdev->flags & RADEON_IS_PCI) { 1562 r = r100_pci_gart_init(rdev); 1563 if (r) 1564 return r; 1565 } 1566 r300_set_reg_safe(rdev); 1567 1568 /* Initialize power management */ 1569 radeon_pm_init(rdev); 1570 1571 rdev->accel_working = true; 1572 r = r300_startup(rdev); 1573 if (r) { 1574 /* Something went wrong with the accel init, so stop accel */ 1575 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 1576 r100_cp_fini(rdev); 1577 radeon_wb_fini(rdev); 1578 radeon_ib_pool_fini(rdev); 1579 radeon_irq_kms_fini(rdev); 1580 if (rdev->flags & RADEON_IS_PCIE) 1581 rv370_pcie_gart_fini(rdev); 1582 if (rdev->flags & RADEON_IS_PCI) 1583 r100_pci_gart_fini(rdev); 1584 radeon_agp_fini(rdev); 1585 rdev->accel_working = false; 1586 } 1587 return 0; 1588} 1589