162306a36Sopenharmony_ci/* SPDX-License-Identifier: MIT */ 262306a36Sopenharmony_ci 362306a36Sopenharmony_ci#include "radeon.h" 462306a36Sopenharmony_ci 562306a36Sopenharmony_ci#define R100_TRACK_MAX_TEXTURE 3 662306a36Sopenharmony_ci#define R200_TRACK_MAX_TEXTURE 6 762306a36Sopenharmony_ci#define R300_TRACK_MAX_TEXTURE 16 862306a36Sopenharmony_ci 962306a36Sopenharmony_ci#define R100_MAX_CB 1 1062306a36Sopenharmony_ci#define R300_MAX_CB 4 1162306a36Sopenharmony_ci 1262306a36Sopenharmony_ci/* 1362306a36Sopenharmony_ci * CS functions 1462306a36Sopenharmony_ci */ 1562306a36Sopenharmony_cistruct r100_cs_track_cb { 1662306a36Sopenharmony_ci struct radeon_bo *robj; 1762306a36Sopenharmony_ci unsigned pitch; 1862306a36Sopenharmony_ci unsigned cpp; 1962306a36Sopenharmony_ci unsigned offset; 2062306a36Sopenharmony_ci}; 2162306a36Sopenharmony_ci 2262306a36Sopenharmony_cistruct r100_cs_track_array { 2362306a36Sopenharmony_ci struct radeon_bo *robj; 2462306a36Sopenharmony_ci unsigned esize; 2562306a36Sopenharmony_ci}; 2662306a36Sopenharmony_ci 2762306a36Sopenharmony_cistruct r100_cs_cube_info { 2862306a36Sopenharmony_ci struct radeon_bo *robj; 2962306a36Sopenharmony_ci unsigned offset; 3062306a36Sopenharmony_ci unsigned width; 3162306a36Sopenharmony_ci unsigned height; 3262306a36Sopenharmony_ci}; 3362306a36Sopenharmony_ci 3462306a36Sopenharmony_ci#define R100_TRACK_COMP_NONE 0 3562306a36Sopenharmony_ci#define R100_TRACK_COMP_DXT1 1 3662306a36Sopenharmony_ci#define R100_TRACK_COMP_DXT35 2 3762306a36Sopenharmony_ci 3862306a36Sopenharmony_cistruct r100_cs_track_texture { 3962306a36Sopenharmony_ci struct radeon_bo *robj; 4062306a36Sopenharmony_ci struct r100_cs_cube_info cube_info[5]; /* info for 5 non-primary faces */ 4162306a36Sopenharmony_ci unsigned pitch; 4262306a36Sopenharmony_ci unsigned width; 4362306a36Sopenharmony_ci unsigned height; 4462306a36Sopenharmony_ci unsigned num_levels; 4562306a36Sopenharmony_ci unsigned cpp; 4662306a36Sopenharmony_ci unsigned tex_coord_type; 4762306a36Sopenharmony_ci unsigned txdepth; 4862306a36Sopenharmony_ci unsigned width_11; 4962306a36Sopenharmony_ci unsigned height_11; 5062306a36Sopenharmony_ci bool use_pitch; 5162306a36Sopenharmony_ci bool enabled; 5262306a36Sopenharmony_ci bool lookup_disable; 5362306a36Sopenharmony_ci bool roundup_w; 5462306a36Sopenharmony_ci bool roundup_h; 5562306a36Sopenharmony_ci unsigned compress_format; 5662306a36Sopenharmony_ci}; 5762306a36Sopenharmony_ci 5862306a36Sopenharmony_cistruct r100_cs_track { 5962306a36Sopenharmony_ci unsigned num_cb; 6062306a36Sopenharmony_ci unsigned num_texture; 6162306a36Sopenharmony_ci unsigned maxy; 6262306a36Sopenharmony_ci unsigned vtx_size; 6362306a36Sopenharmony_ci unsigned vap_vf_cntl; 6462306a36Sopenharmony_ci unsigned vap_alt_nverts; 6562306a36Sopenharmony_ci unsigned immd_dwords; 6662306a36Sopenharmony_ci unsigned num_arrays; 6762306a36Sopenharmony_ci unsigned max_indx; 6862306a36Sopenharmony_ci unsigned color_channel_mask; 6962306a36Sopenharmony_ci struct r100_cs_track_array arrays[16]; 7062306a36Sopenharmony_ci struct r100_cs_track_cb cb[R300_MAX_CB]; 7162306a36Sopenharmony_ci struct r100_cs_track_cb zb; 7262306a36Sopenharmony_ci struct r100_cs_track_cb aa; 7362306a36Sopenharmony_ci struct r100_cs_track_texture textures[R300_TRACK_MAX_TEXTURE]; 7462306a36Sopenharmony_ci bool z_enabled; 7562306a36Sopenharmony_ci bool separate_cube; 7662306a36Sopenharmony_ci bool zb_cb_clear; 7762306a36Sopenharmony_ci bool blend_read_enable; 7862306a36Sopenharmony_ci bool cb_dirty; 7962306a36Sopenharmony_ci bool zb_dirty; 8062306a36Sopenharmony_ci bool tex_dirty; 8162306a36Sopenharmony_ci bool aa_dirty; 8262306a36Sopenharmony_ci bool aaresolve; 8362306a36Sopenharmony_ci}; 8462306a36Sopenharmony_ci 8562306a36Sopenharmony_ciint r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track); 8662306a36Sopenharmony_civoid r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track); 8762306a36Sopenharmony_ci 8862306a36Sopenharmony_ciint r100_cs_packet_parse_vline(struct radeon_cs_parser *p); 8962306a36Sopenharmony_ci 9062306a36Sopenharmony_ciint r200_packet0_check(struct radeon_cs_parser *p, 9162306a36Sopenharmony_ci struct radeon_cs_packet *pkt, 9262306a36Sopenharmony_ci unsigned idx, unsigned reg); 9362306a36Sopenharmony_ci 9462306a36Sopenharmony_ciint r100_reloc_pitch_offset(struct radeon_cs_parser *p, 9562306a36Sopenharmony_ci struct radeon_cs_packet *pkt, 9662306a36Sopenharmony_ci unsigned idx, 9762306a36Sopenharmony_ci unsigned reg); 9862306a36Sopenharmony_ciint r100_packet3_load_vbpntr(struct radeon_cs_parser *p, 9962306a36Sopenharmony_ci struct radeon_cs_packet *pkt, 10062306a36Sopenharmony_ci int idx); 101