1// SPDX-License-Identifier: GPL-2.0 2/* Copyright 2019 Linaro, Ltd, Rob Herring <robh@kernel.org> */ 3 4#include <drm/panfrost_drm.h> 5 6#include <linux/atomic.h> 7#include <linux/bitfield.h> 8#include <linux/delay.h> 9#include <linux/dma-mapping.h> 10#include <linux/interrupt.h> 11#include <linux/io.h> 12#include <linux/iopoll.h> 13#include <linux/io-pgtable.h> 14#include <linux/iommu.h> 15#include <linux/platform_device.h> 16#include <linux/pm_runtime.h> 17#include <linux/shmem_fs.h> 18#include <linux/sizes.h> 19 20#include "panfrost_device.h" 21#include "panfrost_mmu.h" 22#include "panfrost_gem.h" 23#include "panfrost_features.h" 24#include "panfrost_regs.h" 25 26#define mmu_write(dev, reg, data) writel(data, dev->iomem + reg) 27#define mmu_read(dev, reg) readl(dev->iomem + reg) 28 29static int wait_ready(struct panfrost_device *pfdev, u32 as_nr) 30{ 31 int ret; 32 u32 val; 33 34 /* Wait for the MMU status to indicate there is no active command, in 35 * case one is pending. */ 36 ret = readl_relaxed_poll_timeout_atomic(pfdev->iomem + AS_STATUS(as_nr), 37 val, !(val & AS_STATUS_AS_ACTIVE), 10, 100000); 38 39 if (ret) { 40 /* The GPU hung, let's trigger a reset */ 41 panfrost_device_schedule_reset(pfdev); 42 dev_err(pfdev->dev, "AS_ACTIVE bit stuck\n"); 43 } 44 45 return ret; 46} 47 48static int write_cmd(struct panfrost_device *pfdev, u32 as_nr, u32 cmd) 49{ 50 int status; 51 52 /* write AS_COMMAND when MMU is ready to accept another command */ 53 status = wait_ready(pfdev, as_nr); 54 if (!status) 55 mmu_write(pfdev, AS_COMMAND(as_nr), cmd); 56 57 return status; 58} 59 60static void lock_region(struct panfrost_device *pfdev, u32 as_nr, 61 u64 region_start, u64 size) 62{ 63 u8 region_width; 64 u64 region; 65 u64 region_end = region_start + size; 66 67 if (!size) 68 return; 69 70 /* 71 * The locked region is a naturally aligned power of 2 block encoded as 72 * log2 minus(1). 73 * Calculate the desired start/end and look for the highest bit which 74 * differs. The smallest naturally aligned block must include this bit 75 * change, the desired region starts with this bit (and subsequent bits) 76 * zeroed and ends with the bit (and subsequent bits) set to one. 77 */ 78 region_width = max(fls64(region_start ^ (region_end - 1)), 79 const_ilog2(AS_LOCK_REGION_MIN_SIZE)) - 1; 80 81 /* 82 * Mask off the low bits of region_start (which would be ignored by 83 * the hardware anyway) 84 */ 85 region_start &= GENMASK_ULL(63, region_width); 86 87 region = region_width | region_start; 88 89 /* Lock the region that needs to be updated */ 90 mmu_write(pfdev, AS_LOCKADDR_LO(as_nr), lower_32_bits(region)); 91 mmu_write(pfdev, AS_LOCKADDR_HI(as_nr), upper_32_bits(region)); 92 write_cmd(pfdev, as_nr, AS_COMMAND_LOCK); 93} 94 95 96static int mmu_hw_do_operation_locked(struct panfrost_device *pfdev, int as_nr, 97 u64 iova, u64 size, u32 op) 98{ 99 if (as_nr < 0) 100 return 0; 101 102 if (op != AS_COMMAND_UNLOCK) 103 lock_region(pfdev, as_nr, iova, size); 104 105 /* Run the MMU operation */ 106 write_cmd(pfdev, as_nr, op); 107 108 /* Wait for the flush to complete */ 109 return wait_ready(pfdev, as_nr); 110} 111 112static int mmu_hw_do_operation(struct panfrost_device *pfdev, 113 struct panfrost_mmu *mmu, 114 u64 iova, u64 size, u32 op) 115{ 116 int ret; 117 118 spin_lock(&pfdev->as_lock); 119 ret = mmu_hw_do_operation_locked(pfdev, mmu->as, iova, size, op); 120 spin_unlock(&pfdev->as_lock); 121 return ret; 122} 123 124static void panfrost_mmu_enable(struct panfrost_device *pfdev, struct panfrost_mmu *mmu) 125{ 126 int as_nr = mmu->as; 127 struct io_pgtable_cfg *cfg = &mmu->pgtbl_cfg; 128 u64 transtab = cfg->arm_mali_lpae_cfg.transtab; 129 u64 memattr = cfg->arm_mali_lpae_cfg.memattr; 130 131 mmu_hw_do_operation_locked(pfdev, as_nr, 0, ~0ULL, AS_COMMAND_FLUSH_MEM); 132 133 mmu_write(pfdev, AS_TRANSTAB_LO(as_nr), lower_32_bits(transtab)); 134 mmu_write(pfdev, AS_TRANSTAB_HI(as_nr), upper_32_bits(transtab)); 135 136 /* Need to revisit mem attrs. 137 * NC is the default, Mali driver is inner WT. 138 */ 139 mmu_write(pfdev, AS_MEMATTR_LO(as_nr), lower_32_bits(memattr)); 140 mmu_write(pfdev, AS_MEMATTR_HI(as_nr), upper_32_bits(memattr)); 141 142 write_cmd(pfdev, as_nr, AS_COMMAND_UPDATE); 143} 144 145static void panfrost_mmu_disable(struct panfrost_device *pfdev, u32 as_nr) 146{ 147 mmu_hw_do_operation_locked(pfdev, as_nr, 0, ~0ULL, AS_COMMAND_FLUSH_MEM); 148 149 mmu_write(pfdev, AS_TRANSTAB_LO(as_nr), 0); 150 mmu_write(pfdev, AS_TRANSTAB_HI(as_nr), 0); 151 152 mmu_write(pfdev, AS_MEMATTR_LO(as_nr), 0); 153 mmu_write(pfdev, AS_MEMATTR_HI(as_nr), 0); 154 155 write_cmd(pfdev, as_nr, AS_COMMAND_UPDATE); 156} 157 158u32 panfrost_mmu_as_get(struct panfrost_device *pfdev, struct panfrost_mmu *mmu) 159{ 160 int as; 161 162 spin_lock(&pfdev->as_lock); 163 164 as = mmu->as; 165 if (as >= 0) { 166 int en = atomic_inc_return(&mmu->as_count); 167 u32 mask = BIT(as) | BIT(16 + as); 168 169 /* 170 * AS can be retained by active jobs or a perfcnt context, 171 * hence the '+ 1' here. 172 */ 173 WARN_ON(en >= (NUM_JOB_SLOTS + 1)); 174 175 list_move(&mmu->list, &pfdev->as_lru_list); 176 177 if (pfdev->as_faulty_mask & mask) { 178 /* Unhandled pagefault on this AS, the MMU was 179 * disabled. We need to re-enable the MMU after 180 * clearing+unmasking the AS interrupts. 181 */ 182 mmu_write(pfdev, MMU_INT_CLEAR, mask); 183 mmu_write(pfdev, MMU_INT_MASK, ~pfdev->as_faulty_mask); 184 pfdev->as_faulty_mask &= ~mask; 185 panfrost_mmu_enable(pfdev, mmu); 186 } 187 188 goto out; 189 } 190 191 /* Check for a free AS */ 192 as = ffz(pfdev->as_alloc_mask); 193 if (!(BIT(as) & pfdev->features.as_present)) { 194 struct panfrost_mmu *lru_mmu; 195 196 list_for_each_entry_reverse(lru_mmu, &pfdev->as_lru_list, list) { 197 if (!atomic_read(&lru_mmu->as_count)) 198 break; 199 } 200 WARN_ON(&lru_mmu->list == &pfdev->as_lru_list); 201 202 list_del_init(&lru_mmu->list); 203 as = lru_mmu->as; 204 205 WARN_ON(as < 0); 206 lru_mmu->as = -1; 207 } 208 209 /* Assign the free or reclaimed AS to the FD */ 210 mmu->as = as; 211 set_bit(as, &pfdev->as_alloc_mask); 212 atomic_set(&mmu->as_count, 1); 213 list_add(&mmu->list, &pfdev->as_lru_list); 214 215 dev_dbg(pfdev->dev, "Assigned AS%d to mmu %p, alloc_mask=%lx", as, mmu, pfdev->as_alloc_mask); 216 217 panfrost_mmu_enable(pfdev, mmu); 218 219out: 220 spin_unlock(&pfdev->as_lock); 221 return as; 222} 223 224void panfrost_mmu_as_put(struct panfrost_device *pfdev, struct panfrost_mmu *mmu) 225{ 226 atomic_dec(&mmu->as_count); 227 WARN_ON(atomic_read(&mmu->as_count) < 0); 228} 229 230void panfrost_mmu_reset(struct panfrost_device *pfdev) 231{ 232 struct panfrost_mmu *mmu, *mmu_tmp; 233 234 spin_lock(&pfdev->as_lock); 235 236 pfdev->as_alloc_mask = 0; 237 pfdev->as_faulty_mask = 0; 238 239 list_for_each_entry_safe(mmu, mmu_tmp, &pfdev->as_lru_list, list) { 240 mmu->as = -1; 241 atomic_set(&mmu->as_count, 0); 242 list_del_init(&mmu->list); 243 } 244 245 spin_unlock(&pfdev->as_lock); 246 247 mmu_write(pfdev, MMU_INT_CLEAR, ~0); 248 mmu_write(pfdev, MMU_INT_MASK, ~0); 249} 250 251static size_t get_pgsize(u64 addr, size_t size, size_t *count) 252{ 253 /* 254 * io-pgtable only operates on multiple pages within a single table 255 * entry, so we need to split at boundaries of the table size, i.e. 256 * the next block size up. The distance from address A to the next 257 * boundary of block size B is logically B - A % B, but in unsigned 258 * two's complement where B is a power of two we get the equivalence 259 * B - A % B == (B - A) % B == (n * B - A) % B, and choose n = 0 :) 260 */ 261 size_t blk_offset = -addr % SZ_2M; 262 263 if (blk_offset || size < SZ_2M) { 264 *count = min_not_zero(blk_offset, size) / SZ_4K; 265 return SZ_4K; 266 } 267 blk_offset = -addr % SZ_1G ?: SZ_1G; 268 *count = min(blk_offset, size) / SZ_2M; 269 return SZ_2M; 270} 271 272static void panfrost_mmu_flush_range(struct panfrost_device *pfdev, 273 struct panfrost_mmu *mmu, 274 u64 iova, u64 size) 275{ 276 if (mmu->as < 0) 277 return; 278 279 pm_runtime_get_noresume(pfdev->dev); 280 281 /* Flush the PTs only if we're already awake */ 282 if (pm_runtime_active(pfdev->dev)) 283 mmu_hw_do_operation(pfdev, mmu, iova, size, AS_COMMAND_FLUSH_PT); 284 285 pm_runtime_put_autosuspend(pfdev->dev); 286} 287 288static int mmu_map_sg(struct panfrost_device *pfdev, struct panfrost_mmu *mmu, 289 u64 iova, int prot, struct sg_table *sgt) 290{ 291 unsigned int count; 292 struct scatterlist *sgl; 293 struct io_pgtable_ops *ops = mmu->pgtbl_ops; 294 u64 start_iova = iova; 295 296 for_each_sgtable_dma_sg(sgt, sgl, count) { 297 unsigned long paddr = sg_dma_address(sgl); 298 size_t len = sg_dma_len(sgl); 299 300 dev_dbg(pfdev->dev, "map: as=%d, iova=%llx, paddr=%lx, len=%zx", mmu->as, iova, paddr, len); 301 302 while (len) { 303 size_t pgcount, mapped = 0; 304 size_t pgsize = get_pgsize(iova | paddr, len, &pgcount); 305 306 ops->map_pages(ops, iova, paddr, pgsize, pgcount, prot, 307 GFP_KERNEL, &mapped); 308 /* Don't get stuck if things have gone wrong */ 309 mapped = max(mapped, pgsize); 310 iova += mapped; 311 paddr += mapped; 312 len -= mapped; 313 } 314 } 315 316 panfrost_mmu_flush_range(pfdev, mmu, start_iova, iova - start_iova); 317 318 return 0; 319} 320 321int panfrost_mmu_map(struct panfrost_gem_mapping *mapping) 322{ 323 struct panfrost_gem_object *bo = mapping->obj; 324 struct drm_gem_shmem_object *shmem = &bo->base; 325 struct drm_gem_object *obj = &shmem->base; 326 struct panfrost_device *pfdev = to_panfrost_device(obj->dev); 327 struct sg_table *sgt; 328 int prot = IOMMU_READ | IOMMU_WRITE; 329 330 if (WARN_ON(mapping->active)) 331 return 0; 332 333 if (bo->noexec) 334 prot |= IOMMU_NOEXEC; 335 336 sgt = drm_gem_shmem_get_pages_sgt(shmem); 337 if (WARN_ON(IS_ERR(sgt))) 338 return PTR_ERR(sgt); 339 340 mmu_map_sg(pfdev, mapping->mmu, mapping->mmnode.start << PAGE_SHIFT, 341 prot, sgt); 342 mapping->active = true; 343 344 return 0; 345} 346 347void panfrost_mmu_unmap(struct panfrost_gem_mapping *mapping) 348{ 349 struct panfrost_gem_object *bo = mapping->obj; 350 struct drm_gem_object *obj = &bo->base.base; 351 struct panfrost_device *pfdev = to_panfrost_device(obj->dev); 352 struct io_pgtable_ops *ops = mapping->mmu->pgtbl_ops; 353 u64 iova = mapping->mmnode.start << PAGE_SHIFT; 354 size_t len = mapping->mmnode.size << PAGE_SHIFT; 355 size_t unmapped_len = 0; 356 357 if (WARN_ON(!mapping->active)) 358 return; 359 360 dev_dbg(pfdev->dev, "unmap: as=%d, iova=%llx, len=%zx", 361 mapping->mmu->as, iova, len); 362 363 while (unmapped_len < len) { 364 size_t unmapped_page, pgcount; 365 size_t pgsize = get_pgsize(iova, len - unmapped_len, &pgcount); 366 367 if (bo->is_heap) 368 pgcount = 1; 369 if (!bo->is_heap || ops->iova_to_phys(ops, iova)) { 370 unmapped_page = ops->unmap_pages(ops, iova, pgsize, pgcount, NULL); 371 WARN_ON(unmapped_page != pgsize * pgcount); 372 } 373 iova += pgsize * pgcount; 374 unmapped_len += pgsize * pgcount; 375 } 376 377 panfrost_mmu_flush_range(pfdev, mapping->mmu, 378 mapping->mmnode.start << PAGE_SHIFT, len); 379 mapping->active = false; 380} 381 382static void mmu_tlb_inv_context_s1(void *cookie) 383{} 384 385static void mmu_tlb_sync_context(void *cookie) 386{ 387 //struct panfrost_mmu *mmu = cookie; 388 // TODO: Wait 1000 GPU cycles for HW_ISSUE_6367/T60X 389} 390 391static void mmu_tlb_flush_walk(unsigned long iova, size_t size, size_t granule, 392 void *cookie) 393{ 394 mmu_tlb_sync_context(cookie); 395} 396 397static const struct iommu_flush_ops mmu_tlb_ops = { 398 .tlb_flush_all = mmu_tlb_inv_context_s1, 399 .tlb_flush_walk = mmu_tlb_flush_walk, 400}; 401 402static struct panfrost_gem_mapping * 403addr_to_mapping(struct panfrost_device *pfdev, int as, u64 addr) 404{ 405 struct panfrost_gem_mapping *mapping = NULL; 406 struct drm_mm_node *node; 407 u64 offset = addr >> PAGE_SHIFT; 408 struct panfrost_mmu *mmu; 409 410 spin_lock(&pfdev->as_lock); 411 list_for_each_entry(mmu, &pfdev->as_lru_list, list) { 412 if (as == mmu->as) 413 goto found_mmu; 414 } 415 goto out; 416 417found_mmu: 418 419 spin_lock(&mmu->mm_lock); 420 421 drm_mm_for_each_node(node, &mmu->mm) { 422 if (offset >= node->start && 423 offset < (node->start + node->size)) { 424 mapping = drm_mm_node_to_panfrost_mapping(node); 425 426 kref_get(&mapping->refcount); 427 break; 428 } 429 } 430 431 spin_unlock(&mmu->mm_lock); 432out: 433 spin_unlock(&pfdev->as_lock); 434 return mapping; 435} 436 437#define NUM_FAULT_PAGES (SZ_2M / PAGE_SIZE) 438 439static int panfrost_mmu_map_fault_addr(struct panfrost_device *pfdev, int as, 440 u64 addr) 441{ 442 int ret, i; 443 struct panfrost_gem_mapping *bomapping; 444 struct panfrost_gem_object *bo; 445 struct address_space *mapping; 446 struct drm_gem_object *obj; 447 pgoff_t page_offset; 448 struct sg_table *sgt; 449 struct page **pages; 450 451 bomapping = addr_to_mapping(pfdev, as, addr); 452 if (!bomapping) 453 return -ENOENT; 454 455 bo = bomapping->obj; 456 if (!bo->is_heap) { 457 dev_WARN(pfdev->dev, "matching BO is not heap type (GPU VA = %llx)", 458 bomapping->mmnode.start << PAGE_SHIFT); 459 ret = -EINVAL; 460 goto err_bo; 461 } 462 WARN_ON(bomapping->mmu->as != as); 463 464 /* Assume 2MB alignment and size multiple */ 465 addr &= ~((u64)SZ_2M - 1); 466 page_offset = addr >> PAGE_SHIFT; 467 page_offset -= bomapping->mmnode.start; 468 469 obj = &bo->base.base; 470 471 dma_resv_lock(obj->resv, NULL); 472 473 if (!bo->base.pages) { 474 bo->sgts = kvmalloc_array(bo->base.base.size / SZ_2M, 475 sizeof(struct sg_table), GFP_KERNEL | __GFP_ZERO); 476 if (!bo->sgts) { 477 ret = -ENOMEM; 478 goto err_unlock; 479 } 480 481 pages = kvmalloc_array(bo->base.base.size >> PAGE_SHIFT, 482 sizeof(struct page *), GFP_KERNEL | __GFP_ZERO); 483 if (!pages) { 484 kvfree(bo->sgts); 485 bo->sgts = NULL; 486 ret = -ENOMEM; 487 goto err_unlock; 488 } 489 bo->base.pages = pages; 490 bo->base.pages_use_count = 1; 491 } else { 492 pages = bo->base.pages; 493 if (pages[page_offset]) { 494 /* Pages are already mapped, bail out. */ 495 goto out; 496 } 497 } 498 499 mapping = bo->base.base.filp->f_mapping; 500 mapping_set_unevictable(mapping); 501 502 for (i = page_offset; i < page_offset + NUM_FAULT_PAGES; i++) { 503 pages[i] = shmem_read_mapping_page(mapping, i); 504 if (IS_ERR(pages[i])) { 505 ret = PTR_ERR(pages[i]); 506 pages[i] = NULL; 507 goto err_pages; 508 } 509 } 510 511 sgt = &bo->sgts[page_offset / (SZ_2M / PAGE_SIZE)]; 512 ret = sg_alloc_table_from_pages(sgt, pages + page_offset, 513 NUM_FAULT_PAGES, 0, SZ_2M, GFP_KERNEL); 514 if (ret) 515 goto err_pages; 516 517 ret = dma_map_sgtable(pfdev->dev, sgt, DMA_BIDIRECTIONAL, 0); 518 if (ret) 519 goto err_map; 520 521 mmu_map_sg(pfdev, bomapping->mmu, addr, 522 IOMMU_WRITE | IOMMU_READ | IOMMU_NOEXEC, sgt); 523 524 bomapping->active = true; 525 526 dev_dbg(pfdev->dev, "mapped page fault @ AS%d %llx", as, addr); 527 528out: 529 dma_resv_unlock(obj->resv); 530 531 panfrost_gem_mapping_put(bomapping); 532 533 return 0; 534 535err_map: 536 sg_free_table(sgt); 537err_pages: 538 drm_gem_shmem_put_pages(&bo->base); 539err_unlock: 540 dma_resv_unlock(obj->resv); 541err_bo: 542 panfrost_gem_mapping_put(bomapping); 543 return ret; 544} 545 546static void panfrost_mmu_release_ctx(struct kref *kref) 547{ 548 struct panfrost_mmu *mmu = container_of(kref, struct panfrost_mmu, 549 refcount); 550 struct panfrost_device *pfdev = mmu->pfdev; 551 552 spin_lock(&pfdev->as_lock); 553 if (mmu->as >= 0) { 554 pm_runtime_get_noresume(pfdev->dev); 555 if (pm_runtime_active(pfdev->dev)) 556 panfrost_mmu_disable(pfdev, mmu->as); 557 pm_runtime_put_autosuspend(pfdev->dev); 558 559 clear_bit(mmu->as, &pfdev->as_alloc_mask); 560 clear_bit(mmu->as, &pfdev->as_in_use_mask); 561 list_del(&mmu->list); 562 } 563 spin_unlock(&pfdev->as_lock); 564 565 free_io_pgtable_ops(mmu->pgtbl_ops); 566 drm_mm_takedown(&mmu->mm); 567 kfree(mmu); 568} 569 570void panfrost_mmu_ctx_put(struct panfrost_mmu *mmu) 571{ 572 kref_put(&mmu->refcount, panfrost_mmu_release_ctx); 573} 574 575struct panfrost_mmu *panfrost_mmu_ctx_get(struct panfrost_mmu *mmu) 576{ 577 kref_get(&mmu->refcount); 578 579 return mmu; 580} 581 582#define PFN_4G (SZ_4G >> PAGE_SHIFT) 583#define PFN_4G_MASK (PFN_4G - 1) 584#define PFN_16M (SZ_16M >> PAGE_SHIFT) 585 586static void panfrost_drm_mm_color_adjust(const struct drm_mm_node *node, 587 unsigned long color, 588 u64 *start, u64 *end) 589{ 590 /* Executable buffers can't start or end on a 4GB boundary */ 591 if (!(color & PANFROST_BO_NOEXEC)) { 592 u64 next_seg; 593 594 if ((*start & PFN_4G_MASK) == 0) 595 (*start)++; 596 597 if ((*end & PFN_4G_MASK) == 0) 598 (*end)--; 599 600 next_seg = ALIGN(*start, PFN_4G); 601 if (next_seg - *start <= PFN_16M) 602 *start = next_seg + 1; 603 604 *end = min(*end, ALIGN(*start, PFN_4G) - 1); 605 } 606} 607 608struct panfrost_mmu *panfrost_mmu_ctx_create(struct panfrost_device *pfdev) 609{ 610 struct panfrost_mmu *mmu; 611 612 mmu = kzalloc(sizeof(*mmu), GFP_KERNEL); 613 if (!mmu) 614 return ERR_PTR(-ENOMEM); 615 616 mmu->pfdev = pfdev; 617 spin_lock_init(&mmu->mm_lock); 618 619 /* 4G enough for now. can be 48-bit */ 620 drm_mm_init(&mmu->mm, SZ_32M >> PAGE_SHIFT, (SZ_4G - SZ_32M) >> PAGE_SHIFT); 621 mmu->mm.color_adjust = panfrost_drm_mm_color_adjust; 622 623 INIT_LIST_HEAD(&mmu->list); 624 mmu->as = -1; 625 626 mmu->pgtbl_cfg = (struct io_pgtable_cfg) { 627 .pgsize_bitmap = SZ_4K | SZ_2M, 628 .ias = FIELD_GET(0xff, pfdev->features.mmu_features), 629 .oas = FIELD_GET(0xff00, pfdev->features.mmu_features), 630 .coherent_walk = pfdev->coherent, 631 .tlb = &mmu_tlb_ops, 632 .iommu_dev = pfdev->dev, 633 }; 634 635 mmu->pgtbl_ops = alloc_io_pgtable_ops(ARM_MALI_LPAE, &mmu->pgtbl_cfg, 636 mmu); 637 if (!mmu->pgtbl_ops) { 638 kfree(mmu); 639 return ERR_PTR(-EINVAL); 640 } 641 642 kref_init(&mmu->refcount); 643 644 return mmu; 645} 646 647static const char *access_type_name(struct panfrost_device *pfdev, 648 u32 fault_status) 649{ 650 switch (fault_status & AS_FAULTSTATUS_ACCESS_TYPE_MASK) { 651 case AS_FAULTSTATUS_ACCESS_TYPE_ATOMIC: 652 if (panfrost_has_hw_feature(pfdev, HW_FEATURE_AARCH64_MMU)) 653 return "ATOMIC"; 654 else 655 return "UNKNOWN"; 656 case AS_FAULTSTATUS_ACCESS_TYPE_READ: 657 return "READ"; 658 case AS_FAULTSTATUS_ACCESS_TYPE_WRITE: 659 return "WRITE"; 660 case AS_FAULTSTATUS_ACCESS_TYPE_EX: 661 return "EXECUTE"; 662 default: 663 WARN_ON(1); 664 return NULL; 665 } 666} 667 668static irqreturn_t panfrost_mmu_irq_handler(int irq, void *data) 669{ 670 struct panfrost_device *pfdev = data; 671 672 if (!mmu_read(pfdev, MMU_INT_STAT)) 673 return IRQ_NONE; 674 675 mmu_write(pfdev, MMU_INT_MASK, 0); 676 return IRQ_WAKE_THREAD; 677} 678 679static irqreturn_t panfrost_mmu_irq_handler_thread(int irq, void *data) 680{ 681 struct panfrost_device *pfdev = data; 682 u32 status = mmu_read(pfdev, MMU_INT_RAWSTAT); 683 int ret; 684 685 while (status) { 686 u32 as = ffs(status | (status >> 16)) - 1; 687 u32 mask = BIT(as) | BIT(as + 16); 688 u64 addr; 689 u32 fault_status; 690 u32 exception_type; 691 u32 access_type; 692 u32 source_id; 693 694 fault_status = mmu_read(pfdev, AS_FAULTSTATUS(as)); 695 addr = mmu_read(pfdev, AS_FAULTADDRESS_LO(as)); 696 addr |= (u64)mmu_read(pfdev, AS_FAULTADDRESS_HI(as)) << 32; 697 698 /* decode the fault status */ 699 exception_type = fault_status & 0xFF; 700 access_type = (fault_status >> 8) & 0x3; 701 source_id = (fault_status >> 16); 702 703 mmu_write(pfdev, MMU_INT_CLEAR, mask); 704 705 /* Page fault only */ 706 ret = -1; 707 if ((status & mask) == BIT(as) && (exception_type & 0xF8) == 0xC0) 708 ret = panfrost_mmu_map_fault_addr(pfdev, as, addr); 709 710 if (ret) { 711 /* terminal fault, print info about the fault */ 712 dev_err(pfdev->dev, 713 "Unhandled Page fault in AS%d at VA 0x%016llX\n" 714 "Reason: %s\n" 715 "raw fault status: 0x%X\n" 716 "decoded fault status: %s\n" 717 "exception type 0x%X: %s\n" 718 "access type 0x%X: %s\n" 719 "source id 0x%X\n", 720 as, addr, 721 "TODO", 722 fault_status, 723 (fault_status & (1 << 10) ? "DECODER FAULT" : "SLAVE FAULT"), 724 exception_type, panfrost_exception_name(exception_type), 725 access_type, access_type_name(pfdev, fault_status), 726 source_id); 727 728 spin_lock(&pfdev->as_lock); 729 /* Ignore MMU interrupts on this AS until it's been 730 * re-enabled. 731 */ 732 pfdev->as_faulty_mask |= mask; 733 734 /* Disable the MMU to kill jobs on this AS. */ 735 panfrost_mmu_disable(pfdev, as); 736 spin_unlock(&pfdev->as_lock); 737 } 738 739 status &= ~mask; 740 741 /* If we received new MMU interrupts, process them before returning. */ 742 if (!status) 743 status = mmu_read(pfdev, MMU_INT_RAWSTAT) & ~pfdev->as_faulty_mask; 744 } 745 746 spin_lock(&pfdev->as_lock); 747 mmu_write(pfdev, MMU_INT_MASK, ~pfdev->as_faulty_mask); 748 spin_unlock(&pfdev->as_lock); 749 750 return IRQ_HANDLED; 751}; 752 753int panfrost_mmu_init(struct panfrost_device *pfdev) 754{ 755 int err, irq; 756 757 irq = platform_get_irq_byname(to_platform_device(pfdev->dev), "mmu"); 758 if (irq <= 0) 759 return -ENODEV; 760 761 err = devm_request_threaded_irq(pfdev->dev, irq, 762 panfrost_mmu_irq_handler, 763 panfrost_mmu_irq_handler_thread, 764 IRQF_SHARED, KBUILD_MODNAME "-mmu", 765 pfdev); 766 767 if (err) { 768 dev_err(pfdev->dev, "failed to request mmu irq"); 769 return err; 770 } 771 772 return 0; 773} 774 775void panfrost_mmu_fini(struct panfrost_device *pfdev) 776{ 777 mmu_write(pfdev, MMU_INT_MASK, 0); 778} 779