1// SPDX-License-Identifier: GPL-2.0
2/* Copyright 2018 Marty E. Plummer <hanetzer@startmail.com> */
3/* Copyright 2019 Linaro, Ltd., Rob Herring <robh@kernel.org> */
4/* Copyright 2019 Collabora ltd. */
5#include <linux/bitfield.h>
6#include <linux/bitmap.h>
7#include <linux/delay.h>
8#include <linux/dma-mapping.h>
9#include <linux/interrupt.h>
10#include <linux/io.h>
11#include <linux/iopoll.h>
12#include <linux/platform_device.h>
13#include <linux/pm_runtime.h>
14
15#include "panfrost_device.h"
16#include "panfrost_features.h"
17#include "panfrost_issues.h"
18#include "panfrost_gpu.h"
19#include "panfrost_perfcnt.h"
20#include "panfrost_regs.h"
21
22static irqreturn_t panfrost_gpu_irq_handler(int irq, void *data)
23{
24	struct panfrost_device *pfdev = data;
25	u32 state = gpu_read(pfdev, GPU_INT_STAT);
26	u32 fault_status = gpu_read(pfdev, GPU_FAULT_STATUS);
27
28	if (!state)
29		return IRQ_NONE;
30
31	if (state & GPU_IRQ_MASK_ERROR) {
32		u64 address = (u64) gpu_read(pfdev, GPU_FAULT_ADDRESS_HI) << 32;
33		address |= gpu_read(pfdev, GPU_FAULT_ADDRESS_LO);
34
35		dev_warn(pfdev->dev, "GPU Fault 0x%08x (%s) at 0x%016llx\n",
36			 fault_status, panfrost_exception_name(fault_status & 0xFF),
37			 address);
38
39		if (state & GPU_IRQ_MULTIPLE_FAULT)
40			dev_warn(pfdev->dev, "There were multiple GPU faults - some have not been reported\n");
41
42		gpu_write(pfdev, GPU_INT_MASK, 0);
43	}
44
45	if (state & GPU_IRQ_PERFCNT_SAMPLE_COMPLETED)
46		panfrost_perfcnt_sample_done(pfdev);
47
48	if (state & GPU_IRQ_CLEAN_CACHES_COMPLETED)
49		panfrost_perfcnt_clean_cache_done(pfdev);
50
51	gpu_write(pfdev, GPU_INT_CLEAR, state);
52
53	return IRQ_HANDLED;
54}
55
56int panfrost_gpu_soft_reset(struct panfrost_device *pfdev)
57{
58	int ret;
59	u32 val;
60
61	gpu_write(pfdev, GPU_INT_MASK, 0);
62	gpu_write(pfdev, GPU_INT_CLEAR, GPU_IRQ_RESET_COMPLETED);
63	gpu_write(pfdev, GPU_CMD, GPU_CMD_SOFT_RESET);
64
65	ret = readl_relaxed_poll_timeout(pfdev->iomem + GPU_INT_RAWSTAT,
66		val, val & GPU_IRQ_RESET_COMPLETED, 100, 10000);
67
68	if (ret) {
69		dev_err(pfdev->dev, "gpu soft reset timed out\n");
70		return ret;
71	}
72
73	gpu_write(pfdev, GPU_INT_CLEAR, GPU_IRQ_MASK_ALL);
74
75	/* Only enable the interrupts we care about */
76	gpu_write(pfdev, GPU_INT_MASK,
77		  GPU_IRQ_MASK_ERROR |
78		  GPU_IRQ_PERFCNT_SAMPLE_COMPLETED |
79		  GPU_IRQ_CLEAN_CACHES_COMPLETED);
80
81	return 0;
82}
83
84void panfrost_gpu_amlogic_quirk(struct panfrost_device *pfdev)
85{
86	/*
87	 * The Amlogic integrated Mali-T820, Mali-G31 & Mali-G52 needs
88	 * these undocumented bits in GPU_PWR_OVERRIDE1 to be set in order
89	 * to operate correctly.
90	 */
91	gpu_write(pfdev, GPU_PWR_KEY, GPU_PWR_KEY_UNLOCK);
92	gpu_write(pfdev, GPU_PWR_OVERRIDE1, 0xfff | (0x20 << 16));
93}
94
95static void panfrost_gpu_init_quirks(struct panfrost_device *pfdev)
96{
97	u32 quirks = 0;
98
99	if (panfrost_has_hw_issue(pfdev, HW_ISSUE_8443) ||
100	    panfrost_has_hw_issue(pfdev, HW_ISSUE_11035))
101		quirks |= SC_LS_PAUSEBUFFER_DISABLE;
102
103	if (panfrost_has_hw_issue(pfdev, HW_ISSUE_10327))
104		quirks |= SC_SDC_DISABLE_OQ_DISCARD;
105
106	if (panfrost_has_hw_issue(pfdev, HW_ISSUE_10797))
107		quirks |= SC_ENABLE_TEXGRD_FLAGS;
108
109	if (!panfrost_has_hw_issue(pfdev, GPUCORE_1619)) {
110		if (panfrost_model_cmp(pfdev, 0x750) < 0) /* T60x, T62x, T72x */
111			quirks |= SC_LS_ATTR_CHECK_DISABLE;
112		else if (panfrost_model_cmp(pfdev, 0x880) <= 0) /* T76x, T8xx */
113			quirks |= SC_LS_ALLOW_ATTR_TYPES;
114	}
115
116	if (panfrost_has_hw_issue(pfdev, HW_ISSUE_TTRX_2968_TTRX_3162))
117		quirks |= SC_VAR_ALGORITHM;
118
119	if (panfrost_has_hw_feature(pfdev, HW_FEATURE_TLS_HASHING))
120		quirks |= SC_TLS_HASH_ENABLE;
121
122	if (quirks)
123		gpu_write(pfdev, GPU_SHADER_CONFIG, quirks);
124
125
126	quirks = gpu_read(pfdev, GPU_TILER_CONFIG);
127
128	/* Set tiler clock gate override if required */
129	if (panfrost_has_hw_issue(pfdev, HW_ISSUE_T76X_3953))
130		quirks |= TC_CLOCK_GATE_OVERRIDE;
131
132	gpu_write(pfdev, GPU_TILER_CONFIG, quirks);
133
134
135	quirks = 0;
136	if ((panfrost_model_eq(pfdev, 0x860) || panfrost_model_eq(pfdev, 0x880)) &&
137	    pfdev->features.revision >= 0x2000)
138		quirks |= JM_MAX_JOB_THROTTLE_LIMIT << JM_JOB_THROTTLE_LIMIT_SHIFT;
139	else if (panfrost_model_eq(pfdev, 0x6000) &&
140		 pfdev->features.coherency_features == COHERENCY_ACE)
141		quirks |= (COHERENCY_ACE_LITE | COHERENCY_ACE) <<
142			   JM_FORCE_COHERENCY_FEATURES_SHIFT;
143
144	if (panfrost_has_hw_feature(pfdev, HW_FEATURE_IDVS_GROUP_SIZE))
145		quirks |= JM_DEFAULT_IDVS_GROUP_SIZE << JM_IDVS_GROUP_SIZE_SHIFT;
146
147	if (quirks)
148		gpu_write(pfdev, GPU_JM_CONFIG, quirks);
149
150	/* Here goes platform specific quirks */
151	if (pfdev->comp->vendor_quirk)
152		pfdev->comp->vendor_quirk(pfdev);
153}
154
155#define MAX_HW_REVS 6
156
157struct panfrost_model {
158	const char *name;
159	u32 id;
160	u32 id_mask;
161	u64 features;
162	u64 issues;
163	struct {
164		u32 revision;
165		u64 issues;
166	} revs[MAX_HW_REVS];
167};
168
169#define GPU_MODEL(_name, _id, ...) \
170{\
171	.name = __stringify(_name),				\
172	.id = _id,						\
173	.features = hw_features_##_name,			\
174	.issues = hw_issues_##_name,				\
175	.revs = { __VA_ARGS__ },				\
176}
177
178#define GPU_REV_EXT(name, _rev, _p, _s, stat) \
179{\
180	.revision = (_rev) << 12 | (_p) << 4 | (_s),		\
181	.issues = hw_issues_##name##_r##_rev##p##_p##stat,	\
182}
183#define GPU_REV(name, r, p) GPU_REV_EXT(name, r, p, 0, )
184
185static const struct panfrost_model gpu_models[] = {
186	/* T60x has an oddball version */
187	GPU_MODEL(t600, 0x600,
188		GPU_REV_EXT(t600, 0, 0, 1, _15dev0)),
189	GPU_MODEL(t620, 0x620,
190		GPU_REV(t620, 0, 1), GPU_REV(t620, 1, 0)),
191	GPU_MODEL(t720, 0x720),
192	GPU_MODEL(t760, 0x750,
193		GPU_REV(t760, 0, 0), GPU_REV(t760, 0, 1),
194		GPU_REV_EXT(t760, 0, 1, 0, _50rel0),
195		GPU_REV(t760, 0, 2), GPU_REV(t760, 0, 3)),
196	GPU_MODEL(t820, 0x820),
197	GPU_MODEL(t830, 0x830),
198	GPU_MODEL(t860, 0x860),
199	GPU_MODEL(t880, 0x880),
200
201	GPU_MODEL(g71, 0x6000,
202		GPU_REV_EXT(g71, 0, 0, 1, _05dev0)),
203	GPU_MODEL(g72, 0x6001),
204	GPU_MODEL(g51, 0x7000),
205	GPU_MODEL(g76, 0x7001),
206	GPU_MODEL(g52, 0x7002),
207	GPU_MODEL(g31, 0x7003,
208		GPU_REV(g31, 1, 0)),
209
210	GPU_MODEL(g57, 0x9001,
211		GPU_REV(g57, 0, 0)),
212
213	/* MediaTek MT8192 has a Mali-G57 with a different GPU ID from the
214	 * standard. Arm's driver does not appear to handle this model.
215	 * ChromeOS has a hack downstream for it. Treat it as equivalent to
216	 * standard Mali-G57 for now.
217	 */
218	GPU_MODEL(g57, 0x9003,
219		GPU_REV(g57, 0, 0)),
220};
221
222static void panfrost_gpu_init_features(struct panfrost_device *pfdev)
223{
224	u32 gpu_id, num_js, major, minor, status, rev;
225	const char *name = "unknown";
226	u64 hw_feat = 0;
227	u64 hw_issues = hw_issues_all;
228	const struct panfrost_model *model;
229	int i;
230
231	pfdev->features.l2_features = gpu_read(pfdev, GPU_L2_FEATURES);
232	pfdev->features.core_features = gpu_read(pfdev, GPU_CORE_FEATURES);
233	pfdev->features.tiler_features = gpu_read(pfdev, GPU_TILER_FEATURES);
234	pfdev->features.mem_features = gpu_read(pfdev, GPU_MEM_FEATURES);
235	pfdev->features.mmu_features = gpu_read(pfdev, GPU_MMU_FEATURES);
236	pfdev->features.thread_features = gpu_read(pfdev, GPU_THREAD_FEATURES);
237	pfdev->features.max_threads = gpu_read(pfdev, GPU_THREAD_MAX_THREADS);
238	pfdev->features.thread_max_workgroup_sz = gpu_read(pfdev, GPU_THREAD_MAX_WORKGROUP_SIZE);
239	pfdev->features.thread_max_barrier_sz = gpu_read(pfdev, GPU_THREAD_MAX_BARRIER_SIZE);
240	pfdev->features.coherency_features = gpu_read(pfdev, GPU_COHERENCY_FEATURES);
241	pfdev->features.afbc_features = gpu_read(pfdev, GPU_AFBC_FEATURES);
242	for (i = 0; i < 4; i++)
243		pfdev->features.texture_features[i] = gpu_read(pfdev, GPU_TEXTURE_FEATURES(i));
244
245	pfdev->features.as_present = gpu_read(pfdev, GPU_AS_PRESENT);
246
247	pfdev->features.js_present = gpu_read(pfdev, GPU_JS_PRESENT);
248	num_js = hweight32(pfdev->features.js_present);
249	for (i = 0; i < num_js; i++)
250		pfdev->features.js_features[i] = gpu_read(pfdev, GPU_JS_FEATURES(i));
251
252	pfdev->features.shader_present = gpu_read(pfdev, GPU_SHADER_PRESENT_LO);
253	pfdev->features.shader_present |= (u64)gpu_read(pfdev, GPU_SHADER_PRESENT_HI) << 32;
254
255	pfdev->features.tiler_present = gpu_read(pfdev, GPU_TILER_PRESENT_LO);
256	pfdev->features.tiler_present |= (u64)gpu_read(pfdev, GPU_TILER_PRESENT_HI) << 32;
257
258	pfdev->features.l2_present = gpu_read(pfdev, GPU_L2_PRESENT_LO);
259	pfdev->features.l2_present |= (u64)gpu_read(pfdev, GPU_L2_PRESENT_HI) << 32;
260	pfdev->features.nr_core_groups = hweight64(pfdev->features.l2_present);
261
262	pfdev->features.stack_present = gpu_read(pfdev, GPU_STACK_PRESENT_LO);
263	pfdev->features.stack_present |= (u64)gpu_read(pfdev, GPU_STACK_PRESENT_HI) << 32;
264
265	pfdev->features.thread_tls_alloc = gpu_read(pfdev, GPU_THREAD_TLS_ALLOC);
266
267	gpu_id = gpu_read(pfdev, GPU_ID);
268	pfdev->features.revision = gpu_id & 0xffff;
269	pfdev->features.id = gpu_id >> 16;
270
271	/* The T60x has an oddball ID value. Fix it up to the standard Midgard
272	 * format so we (and userspace) don't have to special case it.
273	 */
274	if (pfdev->features.id == 0x6956)
275		pfdev->features.id = 0x0600;
276
277	major = (pfdev->features.revision >> 12) & 0xf;
278	minor = (pfdev->features.revision >> 4) & 0xff;
279	status = pfdev->features.revision & 0xf;
280	rev = pfdev->features.revision;
281
282	gpu_id = pfdev->features.id;
283
284	for (model = gpu_models; model->name; model++) {
285		int best = -1;
286
287		if (!panfrost_model_eq(pfdev, model->id))
288			continue;
289
290		name = model->name;
291		hw_feat = model->features;
292		hw_issues |= model->issues;
293		for (i = 0; i < MAX_HW_REVS; i++) {
294			if (model->revs[i].revision == rev) {
295				best = i;
296				break;
297			} else if (model->revs[i].revision == (rev & ~0xf))
298				best = i;
299		}
300
301		if (best >= 0)
302			hw_issues |= model->revs[best].issues;
303
304		break;
305	}
306
307	bitmap_from_u64(pfdev->features.hw_features, hw_feat);
308	bitmap_from_u64(pfdev->features.hw_issues, hw_issues);
309
310	dev_info(pfdev->dev, "mali-%s id 0x%x major 0x%x minor 0x%x status 0x%x",
311		 name, gpu_id, major, minor, status);
312	dev_info(pfdev->dev, "features: %64pb, issues: %64pb",
313		 pfdev->features.hw_features,
314		 pfdev->features.hw_issues);
315
316	dev_info(pfdev->dev, "Features: L2:0x%08x Shader:0x%08x Tiler:0x%08x Mem:0x%0x MMU:0x%08x AS:0x%x JS:0x%x",
317		 pfdev->features.l2_features,
318		 pfdev->features.core_features,
319		 pfdev->features.tiler_features,
320		 pfdev->features.mem_features,
321		 pfdev->features.mmu_features,
322		 pfdev->features.as_present,
323		 pfdev->features.js_present);
324
325	dev_info(pfdev->dev, "shader_present=0x%0llx l2_present=0x%0llx",
326		 pfdev->features.shader_present, pfdev->features.l2_present);
327}
328
329static u64 panfrost_get_core_mask(struct panfrost_device *pfdev)
330{
331	u64 core_mask;
332
333	if (pfdev->features.l2_present == 1)
334		return U64_MAX;
335
336	/*
337	 * Only support one core group now.
338	 * ~(l2_present - 1) unsets all bits in l2_present except
339	 * the bottom bit. (l2_present - 2) has all the bits in
340	 * the first core group set. AND them together to generate
341	 * a mask of cores in the first core group.
342	 */
343	core_mask = ~(pfdev->features.l2_present - 1) &
344		     (pfdev->features.l2_present - 2);
345	dev_info_once(pfdev->dev, "using only 1st core group (%lu cores from %lu)\n",
346		      hweight64(core_mask),
347		      hweight64(pfdev->features.shader_present));
348
349	return core_mask;
350}
351
352void panfrost_gpu_power_on(struct panfrost_device *pfdev)
353{
354	int ret;
355	u32 val;
356	u64 core_mask;
357
358	panfrost_gpu_init_quirks(pfdev);
359	core_mask = panfrost_get_core_mask(pfdev);
360
361	gpu_write(pfdev, L2_PWRON_LO, pfdev->features.l2_present & core_mask);
362	ret = readl_relaxed_poll_timeout(pfdev->iomem + L2_READY_LO,
363		val, val == (pfdev->features.l2_present & core_mask),
364		100, 20000);
365	if (ret)
366		dev_err(pfdev->dev, "error powering up gpu L2");
367
368	gpu_write(pfdev, SHADER_PWRON_LO,
369		  pfdev->features.shader_present & core_mask);
370	ret = readl_relaxed_poll_timeout(pfdev->iomem + SHADER_READY_LO,
371		val, val == (pfdev->features.shader_present & core_mask),
372		100, 20000);
373	if (ret)
374		dev_err(pfdev->dev, "error powering up gpu shader");
375
376	gpu_write(pfdev, TILER_PWRON_LO, pfdev->features.tiler_present);
377	ret = readl_relaxed_poll_timeout(pfdev->iomem + TILER_READY_LO,
378		val, val == pfdev->features.tiler_present, 100, 1000);
379	if (ret)
380		dev_err(pfdev->dev, "error powering up gpu tiler");
381}
382
383void panfrost_gpu_power_off(struct panfrost_device *pfdev)
384{
385	int ret;
386	u32 val;
387
388	gpu_write(pfdev, SHADER_PWROFF_LO, pfdev->features.shader_present);
389	ret = readl_relaxed_poll_timeout(pfdev->iomem + SHADER_PWRTRANS_LO,
390					 val, !val, 1, 1000);
391	if (ret)
392		dev_err(pfdev->dev, "shader power transition timeout");
393
394	gpu_write(pfdev, TILER_PWROFF_LO, pfdev->features.tiler_present);
395	ret = readl_relaxed_poll_timeout(pfdev->iomem + TILER_PWRTRANS_LO,
396					 val, !val, 1, 1000);
397	if (ret)
398		dev_err(pfdev->dev, "tiler power transition timeout");
399
400	gpu_write(pfdev, L2_PWROFF_LO, pfdev->features.l2_present);
401	ret = readl_poll_timeout(pfdev->iomem + L2_PWRTRANS_LO,
402				 val, !val, 0, 1000);
403	if (ret)
404		dev_err(pfdev->dev, "l2 power transition timeout");
405}
406
407int panfrost_gpu_init(struct panfrost_device *pfdev)
408{
409	int err, irq;
410
411	err = panfrost_gpu_soft_reset(pfdev);
412	if (err)
413		return err;
414
415	panfrost_gpu_init_features(pfdev);
416
417	err = dma_set_mask_and_coherent(pfdev->dev,
418		DMA_BIT_MASK(FIELD_GET(0xff00, pfdev->features.mmu_features)));
419	if (err)
420		return err;
421
422	dma_set_max_seg_size(pfdev->dev, UINT_MAX);
423
424	irq = platform_get_irq_byname(to_platform_device(pfdev->dev), "gpu");
425	if (irq <= 0)
426		return -ENODEV;
427
428	err = devm_request_irq(pfdev->dev, irq, panfrost_gpu_irq_handler,
429			       IRQF_SHARED, KBUILD_MODNAME "-gpu", pfdev);
430	if (err) {
431		dev_err(pfdev->dev, "failed to request gpu irq");
432		return err;
433	}
434
435	panfrost_gpu_power_on(pfdev);
436
437	return 0;
438}
439
440void panfrost_gpu_fini(struct panfrost_device *pfdev)
441{
442	panfrost_gpu_power_off(pfdev);
443}
444
445u32 panfrost_gpu_get_latest_flush_id(struct panfrost_device *pfdev)
446{
447	u32 flush_id;
448
449	if (panfrost_has_hw_feature(pfdev, HW_FEATURE_FLUSH_REDUCTION)) {
450		/* Flush reduction only makes sense when the GPU is kept powered on between jobs */
451		if (pm_runtime_get_if_in_use(pfdev->dev)) {
452			flush_id = gpu_read(pfdev, GPU_LATEST_FLUSH_ID);
453			pm_runtime_put(pfdev->dev);
454			return flush_id;
455		}
456	}
457
458	return 0;
459}
460