1/* 2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sub license, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the 12 * next paragraph) shall be included in all copies or substantial portions 13 * of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24#include <linux/delay.h> 25#include <linux/gpio/consumer.h> 26#include <linux/i2c.h> 27#include <linux/media-bus-format.h> 28#include <linux/module.h> 29#include <linux/of_platform.h> 30#include <linux/platform_device.h> 31#include <linux/pm_runtime.h> 32#include <linux/regulator/consumer.h> 33 34#include <video/display_timing.h> 35#include <video/of_display_timing.h> 36#include <video/videomode.h> 37 38#include <drm/drm_crtc.h> 39#include <drm/drm_device.h> 40#include <drm/drm_edid.h> 41#include <drm/drm_mipi_dsi.h> 42#include <drm/drm_panel.h> 43 44/** 45 * struct panel_desc - Describes a simple panel. 46 */ 47struct panel_desc { 48 /** 49 * @modes: Pointer to array of fixed modes appropriate for this panel. 50 * 51 * If only one mode then this can just be the address of the mode. 52 * NOTE: cannot be used with "timings" and also if this is specified 53 * then you cannot override the mode in the device tree. 54 */ 55 const struct drm_display_mode *modes; 56 57 /** @num_modes: Number of elements in modes array. */ 58 unsigned int num_modes; 59 60 /** 61 * @timings: Pointer to array of display timings 62 * 63 * NOTE: cannot be used with "modes" and also these will be used to 64 * validate a device tree override if one is present. 65 */ 66 const struct display_timing *timings; 67 68 /** @num_timings: Number of elements in timings array. */ 69 unsigned int num_timings; 70 71 /** @bpc: Bits per color. */ 72 unsigned int bpc; 73 74 /** @size: Structure containing the physical size of this panel. */ 75 struct { 76 /** 77 * @size.width: Width (in mm) of the active display area. 78 */ 79 unsigned int width; 80 81 /** 82 * @size.height: Height (in mm) of the active display area. 83 */ 84 unsigned int height; 85 } size; 86 87 /** @delay: Structure containing various delay values for this panel. */ 88 struct { 89 /** 90 * @delay.prepare: Time for the panel to become ready. 91 * 92 * The time (in milliseconds) that it takes for the panel to 93 * become ready and start receiving video data 94 */ 95 unsigned int prepare; 96 97 /** 98 * @delay.enable: Time for the panel to display a valid frame. 99 * 100 * The time (in milliseconds) that it takes for the panel to 101 * display the first valid frame after starting to receive 102 * video data. 103 */ 104 unsigned int enable; 105 106 /** 107 * @delay.disable: Time for the panel to turn the display off. 108 * 109 * The time (in milliseconds) that it takes for the panel to 110 * turn the display off (no content is visible). 111 */ 112 unsigned int disable; 113 114 /** 115 * @delay.unprepare: Time to power down completely. 116 * 117 * The time (in milliseconds) that it takes for the panel 118 * to power itself down completely. 119 * 120 * This time is used to prevent a future "prepare" from 121 * starting until at least this many milliseconds has passed. 122 * If at prepare time less time has passed since unprepare 123 * finished, the driver waits for the remaining time. 124 */ 125 unsigned int unprepare; 126 } delay; 127 128 /** @bus_format: See MEDIA_BUS_FMT_... defines. */ 129 u32 bus_format; 130 131 /** @bus_flags: See DRM_BUS_FLAG_... defines. */ 132 u32 bus_flags; 133 134 /** @connector_type: LVDS, eDP, DSI, DPI, etc. */ 135 int connector_type; 136}; 137 138struct panel_simple { 139 struct drm_panel base; 140 bool enabled; 141 142 bool prepared; 143 144 ktime_t unprepared_time; 145 146 const struct panel_desc *desc; 147 148 struct regulator *supply; 149 struct i2c_adapter *ddc; 150 151 struct gpio_desc *enable_gpio; 152 153 struct edid *edid; 154 155 struct drm_display_mode override_mode; 156 157 enum drm_panel_orientation orientation; 158}; 159 160static inline struct panel_simple *to_panel_simple(struct drm_panel *panel) 161{ 162 return container_of(panel, struct panel_simple, base); 163} 164 165static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel, 166 struct drm_connector *connector) 167{ 168 struct drm_display_mode *mode; 169 unsigned int i, num = 0; 170 171 for (i = 0; i < panel->desc->num_timings; i++) { 172 const struct display_timing *dt = &panel->desc->timings[i]; 173 struct videomode vm; 174 175 videomode_from_timing(dt, &vm); 176 mode = drm_mode_create(connector->dev); 177 if (!mode) { 178 dev_err(panel->base.dev, "failed to add mode %ux%u\n", 179 dt->hactive.typ, dt->vactive.typ); 180 continue; 181 } 182 183 drm_display_mode_from_videomode(&vm, mode); 184 185 mode->type |= DRM_MODE_TYPE_DRIVER; 186 187 if (panel->desc->num_timings == 1) 188 mode->type |= DRM_MODE_TYPE_PREFERRED; 189 190 drm_mode_probed_add(connector, mode); 191 num++; 192 } 193 194 return num; 195} 196 197static unsigned int panel_simple_get_display_modes(struct panel_simple *panel, 198 struct drm_connector *connector) 199{ 200 struct drm_display_mode *mode; 201 unsigned int i, num = 0; 202 203 for (i = 0; i < panel->desc->num_modes; i++) { 204 const struct drm_display_mode *m = &panel->desc->modes[i]; 205 206 mode = drm_mode_duplicate(connector->dev, m); 207 if (!mode) { 208 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n", 209 m->hdisplay, m->vdisplay, 210 drm_mode_vrefresh(m)); 211 continue; 212 } 213 214 mode->type |= DRM_MODE_TYPE_DRIVER; 215 216 if (panel->desc->num_modes == 1) 217 mode->type |= DRM_MODE_TYPE_PREFERRED; 218 219 drm_mode_set_name(mode); 220 221 drm_mode_probed_add(connector, mode); 222 num++; 223 } 224 225 return num; 226} 227 228static int panel_simple_get_non_edid_modes(struct panel_simple *panel, 229 struct drm_connector *connector) 230{ 231 struct drm_display_mode *mode; 232 bool has_override = panel->override_mode.type; 233 unsigned int num = 0; 234 235 if (!panel->desc) 236 return 0; 237 238 if (has_override) { 239 mode = drm_mode_duplicate(connector->dev, 240 &panel->override_mode); 241 if (mode) { 242 drm_mode_probed_add(connector, mode); 243 num = 1; 244 } else { 245 dev_err(panel->base.dev, "failed to add override mode\n"); 246 } 247 } 248 249 /* Only add timings if override was not there or failed to validate */ 250 if (num == 0 && panel->desc->num_timings) 251 num = panel_simple_get_timings_modes(panel, connector); 252 253 /* 254 * Only add fixed modes if timings/override added no mode. 255 * 256 * We should only ever have either the display timings specified 257 * or a fixed mode. Anything else is rather bogus. 258 */ 259 WARN_ON(panel->desc->num_timings && panel->desc->num_modes); 260 if (num == 0) 261 num = panel_simple_get_display_modes(panel, connector); 262 263 connector->display_info.bpc = panel->desc->bpc; 264 connector->display_info.width_mm = panel->desc->size.width; 265 connector->display_info.height_mm = panel->desc->size.height; 266 if (panel->desc->bus_format) 267 drm_display_info_set_bus_formats(&connector->display_info, 268 &panel->desc->bus_format, 1); 269 connector->display_info.bus_flags = panel->desc->bus_flags; 270 271 return num; 272} 273 274static void panel_simple_wait(ktime_t start_ktime, unsigned int min_ms) 275{ 276 ktime_t now_ktime, min_ktime; 277 278 if (!min_ms) 279 return; 280 281 min_ktime = ktime_add(start_ktime, ms_to_ktime(min_ms)); 282 now_ktime = ktime_get_boottime(); 283 284 if (ktime_before(now_ktime, min_ktime)) 285 msleep(ktime_to_ms(ktime_sub(min_ktime, now_ktime)) + 1); 286} 287 288static int panel_simple_disable(struct drm_panel *panel) 289{ 290 struct panel_simple *p = to_panel_simple(panel); 291 292 if (!p->enabled) 293 return 0; 294 295 if (p->desc->delay.disable) 296 msleep(p->desc->delay.disable); 297 298 p->enabled = false; 299 300 return 0; 301} 302 303static int panel_simple_suspend(struct device *dev) 304{ 305 struct panel_simple *p = dev_get_drvdata(dev); 306 307 gpiod_set_value_cansleep(p->enable_gpio, 0); 308 regulator_disable(p->supply); 309 p->unprepared_time = ktime_get_boottime(); 310 311 kfree(p->edid); 312 p->edid = NULL; 313 314 return 0; 315} 316 317static int panel_simple_unprepare(struct drm_panel *panel) 318{ 319 struct panel_simple *p = to_panel_simple(panel); 320 int ret; 321 322 /* Unpreparing when already unprepared is a no-op */ 323 if (!p->prepared) 324 return 0; 325 326 pm_runtime_mark_last_busy(panel->dev); 327 ret = pm_runtime_put_autosuspend(panel->dev); 328 if (ret < 0) 329 return ret; 330 p->prepared = false; 331 332 return 0; 333} 334 335static int panel_simple_resume(struct device *dev) 336{ 337 struct panel_simple *p = dev_get_drvdata(dev); 338 int err; 339 340 panel_simple_wait(p->unprepared_time, p->desc->delay.unprepare); 341 342 err = regulator_enable(p->supply); 343 if (err < 0) { 344 dev_err(dev, "failed to enable supply: %d\n", err); 345 return err; 346 } 347 348 gpiod_set_value_cansleep(p->enable_gpio, 1); 349 350 if (p->desc->delay.prepare) 351 msleep(p->desc->delay.prepare); 352 353 return 0; 354} 355 356static int panel_simple_prepare(struct drm_panel *panel) 357{ 358 struct panel_simple *p = to_panel_simple(panel); 359 int ret; 360 361 /* Preparing when already prepared is a no-op */ 362 if (p->prepared) 363 return 0; 364 365 ret = pm_runtime_get_sync(panel->dev); 366 if (ret < 0) { 367 pm_runtime_put_autosuspend(panel->dev); 368 return ret; 369 } 370 371 p->prepared = true; 372 373 return 0; 374} 375 376static int panel_simple_enable(struct drm_panel *panel) 377{ 378 struct panel_simple *p = to_panel_simple(panel); 379 380 if (p->enabled) 381 return 0; 382 383 if (p->desc->delay.enable) 384 msleep(p->desc->delay.enable); 385 386 p->enabled = true; 387 388 return 0; 389} 390 391static int panel_simple_get_modes(struct drm_panel *panel, 392 struct drm_connector *connector) 393{ 394 struct panel_simple *p = to_panel_simple(panel); 395 int num = 0; 396 397 /* probe EDID if a DDC bus is available */ 398 if (p->ddc) { 399 pm_runtime_get_sync(panel->dev); 400 401 if (!p->edid) 402 p->edid = drm_get_edid(connector, p->ddc); 403 404 if (p->edid) 405 num += drm_add_edid_modes(connector, p->edid); 406 407 pm_runtime_mark_last_busy(panel->dev); 408 pm_runtime_put_autosuspend(panel->dev); 409 } 410 411 /* add hard-coded panel modes */ 412 num += panel_simple_get_non_edid_modes(p, connector); 413 414 /* 415 * TODO: Remove once all drm drivers call 416 * drm_connector_set_orientation_from_panel() 417 */ 418 drm_connector_set_panel_orientation(connector, p->orientation); 419 420 return num; 421} 422 423static int panel_simple_get_timings(struct drm_panel *panel, 424 unsigned int num_timings, 425 struct display_timing *timings) 426{ 427 struct panel_simple *p = to_panel_simple(panel); 428 unsigned int i; 429 430 if (p->desc->num_timings < num_timings) 431 num_timings = p->desc->num_timings; 432 433 if (timings) 434 for (i = 0; i < num_timings; i++) 435 timings[i] = p->desc->timings[i]; 436 437 return p->desc->num_timings; 438} 439 440static enum drm_panel_orientation panel_simple_get_orientation(struct drm_panel *panel) 441{ 442 struct panel_simple *p = to_panel_simple(panel); 443 444 return p->orientation; 445} 446 447static const struct drm_panel_funcs panel_simple_funcs = { 448 .disable = panel_simple_disable, 449 .unprepare = panel_simple_unprepare, 450 .prepare = panel_simple_prepare, 451 .enable = panel_simple_enable, 452 .get_modes = panel_simple_get_modes, 453 .get_orientation = panel_simple_get_orientation, 454 .get_timings = panel_simple_get_timings, 455}; 456 457static struct panel_desc panel_dpi; 458 459static int panel_dpi_probe(struct device *dev, 460 struct panel_simple *panel) 461{ 462 struct display_timing *timing; 463 const struct device_node *np; 464 struct panel_desc *desc; 465 unsigned int bus_flags; 466 struct videomode vm; 467 int ret; 468 469 np = dev->of_node; 470 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL); 471 if (!desc) 472 return -ENOMEM; 473 474 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL); 475 if (!timing) 476 return -ENOMEM; 477 478 ret = of_get_display_timing(np, "panel-timing", timing); 479 if (ret < 0) { 480 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n", 481 np); 482 return ret; 483 } 484 485 desc->timings = timing; 486 desc->num_timings = 1; 487 488 of_property_read_u32(np, "width-mm", &desc->size.width); 489 of_property_read_u32(np, "height-mm", &desc->size.height); 490 491 /* Extract bus_flags from display_timing */ 492 bus_flags = 0; 493 vm.flags = timing->flags; 494 drm_bus_flags_from_videomode(&vm, &bus_flags); 495 desc->bus_flags = bus_flags; 496 497 /* We do not know the connector for the DT node, so guess it */ 498 desc->connector_type = DRM_MODE_CONNECTOR_DPI; 499 500 panel->desc = desc; 501 502 return 0; 503} 504 505#define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \ 506 (to_check->field.typ >= bounds->field.min && \ 507 to_check->field.typ <= bounds->field.max) 508static void panel_simple_parse_panel_timing_node(struct device *dev, 509 struct panel_simple *panel, 510 const struct display_timing *ot) 511{ 512 const struct panel_desc *desc = panel->desc; 513 struct videomode vm; 514 unsigned int i; 515 516 if (WARN_ON(desc->num_modes)) { 517 dev_err(dev, "Reject override mode: panel has a fixed mode\n"); 518 return; 519 } 520 if (WARN_ON(!desc->num_timings)) { 521 dev_err(dev, "Reject override mode: no timings specified\n"); 522 return; 523 } 524 525 for (i = 0; i < panel->desc->num_timings; i++) { 526 const struct display_timing *dt = &panel->desc->timings[i]; 527 528 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) || 529 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) || 530 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) || 531 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) || 532 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) || 533 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) || 534 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) || 535 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len)) 536 continue; 537 538 if (ot->flags != dt->flags) 539 continue; 540 541 videomode_from_timing(ot, &vm); 542 drm_display_mode_from_videomode(&vm, &panel->override_mode); 543 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER | 544 DRM_MODE_TYPE_PREFERRED; 545 break; 546 } 547 548 if (WARN_ON(!panel->override_mode.type)) 549 dev_err(dev, "Reject override mode: No display_timing found\n"); 550} 551 552static int panel_simple_probe(struct device *dev, const struct panel_desc *desc) 553{ 554 struct panel_simple *panel; 555 struct display_timing dt; 556 struct device_node *ddc; 557 int connector_type; 558 u32 bus_flags; 559 int err; 560 561 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL); 562 if (!panel) 563 return -ENOMEM; 564 565 panel->enabled = false; 566 panel->desc = desc; 567 568 panel->supply = devm_regulator_get(dev, "power"); 569 if (IS_ERR(panel->supply)) 570 return PTR_ERR(panel->supply); 571 572 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", 573 GPIOD_OUT_LOW); 574 if (IS_ERR(panel->enable_gpio)) 575 return dev_err_probe(dev, PTR_ERR(panel->enable_gpio), 576 "failed to request GPIO\n"); 577 578 err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation); 579 if (err) { 580 dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err); 581 return err; 582 } 583 584 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0); 585 if (ddc) { 586 panel->ddc = of_find_i2c_adapter_by_node(ddc); 587 of_node_put(ddc); 588 589 if (!panel->ddc) 590 return -EPROBE_DEFER; 591 } 592 593 if (desc == &panel_dpi) { 594 /* Handle the generic panel-dpi binding */ 595 err = panel_dpi_probe(dev, panel); 596 if (err) 597 goto free_ddc; 598 desc = panel->desc; 599 } else { 600 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt)) 601 panel_simple_parse_panel_timing_node(dev, panel, &dt); 602 } 603 604 connector_type = desc->connector_type; 605 /* Catch common mistakes for panels. */ 606 switch (connector_type) { 607 case 0: 608 dev_warn(dev, "Specify missing connector_type\n"); 609 connector_type = DRM_MODE_CONNECTOR_DPI; 610 break; 611 case DRM_MODE_CONNECTOR_LVDS: 612 WARN_ON(desc->bus_flags & 613 ~(DRM_BUS_FLAG_DE_LOW | 614 DRM_BUS_FLAG_DE_HIGH | 615 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 616 DRM_BUS_FLAG_DATA_LSB_TO_MSB)); 617 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 618 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG && 619 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA); 620 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 621 desc->bpc != 6); 622 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG || 623 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) && 624 desc->bpc != 8); 625 break; 626 case DRM_MODE_CONNECTOR_eDP: 627 dev_warn(dev, "eDP panels moved to panel-edp\n"); 628 err = -EINVAL; 629 goto free_ddc; 630 case DRM_MODE_CONNECTOR_DSI: 631 if (desc->bpc != 6 && desc->bpc != 8) 632 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 633 break; 634 case DRM_MODE_CONNECTOR_DPI: 635 bus_flags = DRM_BUS_FLAG_DE_LOW | 636 DRM_BUS_FLAG_DE_HIGH | 637 DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE | 638 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 639 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 640 DRM_BUS_FLAG_DATA_LSB_TO_MSB | 641 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE | 642 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE; 643 if (desc->bus_flags & ~bus_flags) 644 dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags); 645 if (!(desc->bus_flags & bus_flags)) 646 dev_warn(dev, "Specify missing bus_flags\n"); 647 if (desc->bus_format == 0) 648 dev_warn(dev, "Specify missing bus_format\n"); 649 if (desc->bpc != 6 && desc->bpc != 8) 650 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 651 break; 652 default: 653 dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type); 654 connector_type = DRM_MODE_CONNECTOR_DPI; 655 break; 656 } 657 658 dev_set_drvdata(dev, panel); 659 660 /* 661 * We use runtime PM for prepare / unprepare since those power the panel 662 * on and off and those can be very slow operations. This is important 663 * to optimize powering the panel on briefly to read the EDID before 664 * fully enabling the panel. 665 */ 666 pm_runtime_enable(dev); 667 pm_runtime_set_autosuspend_delay(dev, 1000); 668 pm_runtime_use_autosuspend(dev); 669 670 drm_panel_init(&panel->base, dev, &panel_simple_funcs, connector_type); 671 672 err = drm_panel_of_backlight(&panel->base); 673 if (err) { 674 dev_err_probe(dev, err, "Could not find backlight\n"); 675 goto disable_pm_runtime; 676 } 677 678 drm_panel_add(&panel->base); 679 680 return 0; 681 682disable_pm_runtime: 683 pm_runtime_dont_use_autosuspend(dev); 684 pm_runtime_disable(dev); 685free_ddc: 686 if (panel->ddc) 687 put_device(&panel->ddc->dev); 688 689 return err; 690} 691 692static void panel_simple_remove(struct device *dev) 693{ 694 struct panel_simple *panel = dev_get_drvdata(dev); 695 696 drm_panel_remove(&panel->base); 697 drm_panel_disable(&panel->base); 698 drm_panel_unprepare(&panel->base); 699 700 pm_runtime_dont_use_autosuspend(dev); 701 pm_runtime_disable(dev); 702 if (panel->ddc) 703 put_device(&panel->ddc->dev); 704} 705 706static void panel_simple_shutdown(struct device *dev) 707{ 708 struct panel_simple *panel = dev_get_drvdata(dev); 709 710 drm_panel_disable(&panel->base); 711 drm_panel_unprepare(&panel->base); 712} 713 714static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = { 715 .clock = 71100, 716 .hdisplay = 1280, 717 .hsync_start = 1280 + 40, 718 .hsync_end = 1280 + 40 + 80, 719 .htotal = 1280 + 40 + 80 + 40, 720 .vdisplay = 800, 721 .vsync_start = 800 + 3, 722 .vsync_end = 800 + 3 + 10, 723 .vtotal = 800 + 3 + 10 + 10, 724 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 725}; 726 727static const struct panel_desc ampire_am_1280800n3tzqw_t00h = { 728 .modes = &ire_am_1280800n3tzqw_t00h_mode, 729 .num_modes = 1, 730 .bpc = 8, 731 .size = { 732 .width = 217, 733 .height = 136, 734 }, 735 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 736 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 737 .connector_type = DRM_MODE_CONNECTOR_LVDS, 738}; 739 740static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = { 741 .clock = 9000, 742 .hdisplay = 480, 743 .hsync_start = 480 + 2, 744 .hsync_end = 480 + 2 + 41, 745 .htotal = 480 + 2 + 41 + 2, 746 .vdisplay = 272, 747 .vsync_start = 272 + 2, 748 .vsync_end = 272 + 2 + 10, 749 .vtotal = 272 + 2 + 10 + 2, 750 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 751}; 752 753static const struct panel_desc ampire_am_480272h3tmqw_t01h = { 754 .modes = &ire_am_480272h3tmqw_t01h_mode, 755 .num_modes = 1, 756 .bpc = 8, 757 .size = { 758 .width = 99, 759 .height = 58, 760 }, 761 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 762}; 763 764static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = { 765 .clock = 33333, 766 .hdisplay = 800, 767 .hsync_start = 800 + 0, 768 .hsync_end = 800 + 0 + 255, 769 .htotal = 800 + 0 + 255 + 0, 770 .vdisplay = 480, 771 .vsync_start = 480 + 2, 772 .vsync_end = 480 + 2 + 45, 773 .vtotal = 480 + 2 + 45 + 0, 774 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 775}; 776 777static const struct display_timing ampire_am_800480l1tmqw_t00h_timing = { 778 .pixelclock = { 29930000, 33260000, 36590000 }, 779 .hactive = { 800, 800, 800 }, 780 .hfront_porch = { 1, 40, 168 }, 781 .hback_porch = { 88, 88, 88 }, 782 .hsync_len = { 1, 128, 128 }, 783 .vactive = { 480, 480, 480 }, 784 .vfront_porch = { 1, 35, 37 }, 785 .vback_porch = { 8, 8, 8 }, 786 .vsync_len = { 1, 2, 2 }, 787 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 788 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 789 DISPLAY_FLAGS_SYNC_POSEDGE, 790}; 791 792static const struct panel_desc ampire_am_800480l1tmqw_t00h = { 793 .timings = &ire_am_800480l1tmqw_t00h_timing, 794 .num_timings = 1, 795 .bpc = 8, 796 .size = { 797 .width = 111, 798 .height = 67, 799 }, 800 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 801 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 802 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 803 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 804 .connector_type = DRM_MODE_CONNECTOR_DPI, 805}; 806 807static const struct panel_desc ampire_am800480r3tmqwa1h = { 808 .modes = &ire_am800480r3tmqwa1h_mode, 809 .num_modes = 1, 810 .bpc = 6, 811 .size = { 812 .width = 152, 813 .height = 91, 814 }, 815 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 816}; 817 818static const struct display_timing ampire_am800600p5tmqw_tb8h_timing = { 819 .pixelclock = { 34500000, 39600000, 50400000 }, 820 .hactive = { 800, 800, 800 }, 821 .hfront_porch = { 12, 112, 312 }, 822 .hback_porch = { 87, 87, 48 }, 823 .hsync_len = { 1, 1, 40 }, 824 .vactive = { 600, 600, 600 }, 825 .vfront_porch = { 1, 21, 61 }, 826 .vback_porch = { 38, 38, 19 }, 827 .vsync_len = { 1, 1, 20 }, 828 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 829 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 830 DISPLAY_FLAGS_SYNC_POSEDGE, 831}; 832 833static const struct panel_desc ampire_am800600p5tmqwtb8h = { 834 .timings = &ire_am800600p5tmqw_tb8h_timing, 835 .num_timings = 1, 836 .bpc = 6, 837 .size = { 838 .width = 162, 839 .height = 122, 840 }, 841 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 842 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 843 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 844 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 845 .connector_type = DRM_MODE_CONNECTOR_DPI, 846}; 847 848static const struct display_timing santek_st0700i5y_rbslw_f_timing = { 849 .pixelclock = { 26400000, 33300000, 46800000 }, 850 .hactive = { 800, 800, 800 }, 851 .hfront_porch = { 16, 210, 354 }, 852 .hback_porch = { 45, 36, 6 }, 853 .hsync_len = { 1, 10, 40 }, 854 .vactive = { 480, 480, 480 }, 855 .vfront_porch = { 7, 22, 147 }, 856 .vback_porch = { 22, 13, 3 }, 857 .vsync_len = { 1, 10, 20 }, 858 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 859 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE 860}; 861 862static const struct panel_desc armadeus_st0700_adapt = { 863 .timings = &santek_st0700i5y_rbslw_f_timing, 864 .num_timings = 1, 865 .bpc = 6, 866 .size = { 867 .width = 154, 868 .height = 86, 869 }, 870 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 871 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 872}; 873 874static const struct drm_display_mode auo_b101aw03_mode = { 875 .clock = 51450, 876 .hdisplay = 1024, 877 .hsync_start = 1024 + 156, 878 .hsync_end = 1024 + 156 + 8, 879 .htotal = 1024 + 156 + 8 + 156, 880 .vdisplay = 600, 881 .vsync_start = 600 + 16, 882 .vsync_end = 600 + 16 + 6, 883 .vtotal = 600 + 16 + 6 + 16, 884}; 885 886static const struct panel_desc auo_b101aw03 = { 887 .modes = &auo_b101aw03_mode, 888 .num_modes = 1, 889 .bpc = 6, 890 .size = { 891 .width = 223, 892 .height = 125, 893 }, 894 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 895 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 896 .connector_type = DRM_MODE_CONNECTOR_LVDS, 897}; 898 899static const struct drm_display_mode auo_b101xtn01_mode = { 900 .clock = 72000, 901 .hdisplay = 1366, 902 .hsync_start = 1366 + 20, 903 .hsync_end = 1366 + 20 + 70, 904 .htotal = 1366 + 20 + 70, 905 .vdisplay = 768, 906 .vsync_start = 768 + 14, 907 .vsync_end = 768 + 14 + 42, 908 .vtotal = 768 + 14 + 42, 909 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 910}; 911 912static const struct panel_desc auo_b101xtn01 = { 913 .modes = &auo_b101xtn01_mode, 914 .num_modes = 1, 915 .bpc = 6, 916 .size = { 917 .width = 223, 918 .height = 125, 919 }, 920}; 921 922static const struct drm_display_mode auo_b116xw03_mode = { 923 .clock = 70589, 924 .hdisplay = 1366, 925 .hsync_start = 1366 + 40, 926 .hsync_end = 1366 + 40 + 40, 927 .htotal = 1366 + 40 + 40 + 32, 928 .vdisplay = 768, 929 .vsync_start = 768 + 10, 930 .vsync_end = 768 + 10 + 12, 931 .vtotal = 768 + 10 + 12 + 6, 932 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 933}; 934 935static const struct panel_desc auo_b116xw03 = { 936 .modes = &auo_b116xw03_mode, 937 .num_modes = 1, 938 .bpc = 6, 939 .size = { 940 .width = 256, 941 .height = 144, 942 }, 943 .delay = { 944 .prepare = 1, 945 .enable = 200, 946 .disable = 200, 947 .unprepare = 500, 948 }, 949 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 950 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 951 .connector_type = DRM_MODE_CONNECTOR_LVDS, 952}; 953 954static const struct display_timing auo_g070vvn01_timings = { 955 .pixelclock = { 33300000, 34209000, 45000000 }, 956 .hactive = { 800, 800, 800 }, 957 .hfront_porch = { 20, 40, 200 }, 958 .hback_porch = { 87, 40, 1 }, 959 .hsync_len = { 1, 48, 87 }, 960 .vactive = { 480, 480, 480 }, 961 .vfront_porch = { 5, 13, 200 }, 962 .vback_porch = { 31, 31, 29 }, 963 .vsync_len = { 1, 1, 3 }, 964}; 965 966static const struct panel_desc auo_g070vvn01 = { 967 .timings = &auo_g070vvn01_timings, 968 .num_timings = 1, 969 .bpc = 8, 970 .size = { 971 .width = 152, 972 .height = 91, 973 }, 974 .delay = { 975 .prepare = 200, 976 .enable = 50, 977 .disable = 50, 978 .unprepare = 1000, 979 }, 980}; 981 982static const struct drm_display_mode auo_g101evn010_mode = { 983 .clock = 68930, 984 .hdisplay = 1280, 985 .hsync_start = 1280 + 82, 986 .hsync_end = 1280 + 82 + 2, 987 .htotal = 1280 + 82 + 2 + 84, 988 .vdisplay = 800, 989 .vsync_start = 800 + 8, 990 .vsync_end = 800 + 8 + 2, 991 .vtotal = 800 + 8 + 2 + 6, 992}; 993 994static const struct panel_desc auo_g101evn010 = { 995 .modes = &auo_g101evn010_mode, 996 .num_modes = 1, 997 .bpc = 6, 998 .size = { 999 .width = 216, 1000 .height = 135, 1001 }, 1002 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1003 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1004}; 1005 1006static const struct drm_display_mode auo_g104sn02_mode = { 1007 .clock = 40000, 1008 .hdisplay = 800, 1009 .hsync_start = 800 + 40, 1010 .hsync_end = 800 + 40 + 216, 1011 .htotal = 800 + 40 + 216 + 128, 1012 .vdisplay = 600, 1013 .vsync_start = 600 + 10, 1014 .vsync_end = 600 + 10 + 35, 1015 .vtotal = 600 + 10 + 35 + 2, 1016}; 1017 1018static const struct panel_desc auo_g104sn02 = { 1019 .modes = &auo_g104sn02_mode, 1020 .num_modes = 1, 1021 .bpc = 8, 1022 .size = { 1023 .width = 211, 1024 .height = 158, 1025 }, 1026 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1027 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1028}; 1029 1030static const struct display_timing auo_g121ean01_timing = { 1031 .pixelclock = { 60000000, 74400000, 90000000 }, 1032 .hactive = { 1280, 1280, 1280 }, 1033 .hfront_porch = { 20, 50, 100 }, 1034 .hback_porch = { 20, 50, 100 }, 1035 .hsync_len = { 30, 100, 200 }, 1036 .vactive = { 800, 800, 800 }, 1037 .vfront_porch = { 2, 10, 25 }, 1038 .vback_porch = { 2, 10, 25 }, 1039 .vsync_len = { 4, 18, 50 }, 1040}; 1041 1042static const struct panel_desc auo_g121ean01 = { 1043 .timings = &auo_g121ean01_timing, 1044 .num_timings = 1, 1045 .bpc = 8, 1046 .size = { 1047 .width = 261, 1048 .height = 163, 1049 }, 1050 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1051 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1052}; 1053 1054static const struct display_timing auo_g133han01_timings = { 1055 .pixelclock = { 134000000, 141200000, 149000000 }, 1056 .hactive = { 1920, 1920, 1920 }, 1057 .hfront_porch = { 39, 58, 77 }, 1058 .hback_porch = { 59, 88, 117 }, 1059 .hsync_len = { 28, 42, 56 }, 1060 .vactive = { 1080, 1080, 1080 }, 1061 .vfront_porch = { 3, 8, 11 }, 1062 .vback_porch = { 5, 14, 19 }, 1063 .vsync_len = { 4, 14, 19 }, 1064}; 1065 1066static const struct panel_desc auo_g133han01 = { 1067 .timings = &auo_g133han01_timings, 1068 .num_timings = 1, 1069 .bpc = 8, 1070 .size = { 1071 .width = 293, 1072 .height = 165, 1073 }, 1074 .delay = { 1075 .prepare = 200, 1076 .enable = 50, 1077 .disable = 50, 1078 .unprepare = 1000, 1079 }, 1080 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1081 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1082}; 1083 1084static const struct drm_display_mode auo_g156xtn01_mode = { 1085 .clock = 76000, 1086 .hdisplay = 1366, 1087 .hsync_start = 1366 + 33, 1088 .hsync_end = 1366 + 33 + 67, 1089 .htotal = 1560, 1090 .vdisplay = 768, 1091 .vsync_start = 768 + 4, 1092 .vsync_end = 768 + 4 + 4, 1093 .vtotal = 806, 1094}; 1095 1096static const struct panel_desc auo_g156xtn01 = { 1097 .modes = &auo_g156xtn01_mode, 1098 .num_modes = 1, 1099 .bpc = 8, 1100 .size = { 1101 .width = 344, 1102 .height = 194, 1103 }, 1104 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1105 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1106}; 1107 1108static const struct display_timing auo_g185han01_timings = { 1109 .pixelclock = { 120000000, 144000000, 175000000 }, 1110 .hactive = { 1920, 1920, 1920 }, 1111 .hfront_porch = { 36, 120, 148 }, 1112 .hback_porch = { 24, 88, 108 }, 1113 .hsync_len = { 20, 48, 64 }, 1114 .vactive = { 1080, 1080, 1080 }, 1115 .vfront_porch = { 6, 10, 40 }, 1116 .vback_porch = { 2, 5, 20 }, 1117 .vsync_len = { 2, 5, 20 }, 1118}; 1119 1120static const struct panel_desc auo_g185han01 = { 1121 .timings = &auo_g185han01_timings, 1122 .num_timings = 1, 1123 .bpc = 8, 1124 .size = { 1125 .width = 409, 1126 .height = 230, 1127 }, 1128 .delay = { 1129 .prepare = 50, 1130 .enable = 200, 1131 .disable = 110, 1132 .unprepare = 1000, 1133 }, 1134 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1135 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1136}; 1137 1138static const struct display_timing auo_g190ean01_timings = { 1139 .pixelclock = { 90000000, 108000000, 135000000 }, 1140 .hactive = { 1280, 1280, 1280 }, 1141 .hfront_porch = { 126, 184, 1266 }, 1142 .hback_porch = { 84, 122, 844 }, 1143 .hsync_len = { 70, 102, 704 }, 1144 .vactive = { 1024, 1024, 1024 }, 1145 .vfront_porch = { 4, 26, 76 }, 1146 .vback_porch = { 2, 8, 25 }, 1147 .vsync_len = { 2, 8, 25 }, 1148}; 1149 1150static const struct panel_desc auo_g190ean01 = { 1151 .timings = &auo_g190ean01_timings, 1152 .num_timings = 1, 1153 .bpc = 8, 1154 .size = { 1155 .width = 376, 1156 .height = 301, 1157 }, 1158 .delay = { 1159 .prepare = 50, 1160 .enable = 200, 1161 .disable = 110, 1162 .unprepare = 1000, 1163 }, 1164 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1165 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1166}; 1167 1168static const struct display_timing auo_p320hvn03_timings = { 1169 .pixelclock = { 106000000, 148500000, 164000000 }, 1170 .hactive = { 1920, 1920, 1920 }, 1171 .hfront_porch = { 25, 50, 130 }, 1172 .hback_porch = { 25, 50, 130 }, 1173 .hsync_len = { 20, 40, 105 }, 1174 .vactive = { 1080, 1080, 1080 }, 1175 .vfront_porch = { 8, 17, 150 }, 1176 .vback_porch = { 8, 17, 150 }, 1177 .vsync_len = { 4, 11, 100 }, 1178}; 1179 1180static const struct panel_desc auo_p320hvn03 = { 1181 .timings = &auo_p320hvn03_timings, 1182 .num_timings = 1, 1183 .bpc = 8, 1184 .size = { 1185 .width = 698, 1186 .height = 393, 1187 }, 1188 .delay = { 1189 .prepare = 1, 1190 .enable = 450, 1191 .unprepare = 500, 1192 }, 1193 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1194 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1195}; 1196 1197static const struct drm_display_mode auo_t215hvn01_mode = { 1198 .clock = 148800, 1199 .hdisplay = 1920, 1200 .hsync_start = 1920 + 88, 1201 .hsync_end = 1920 + 88 + 44, 1202 .htotal = 1920 + 88 + 44 + 148, 1203 .vdisplay = 1080, 1204 .vsync_start = 1080 + 4, 1205 .vsync_end = 1080 + 4 + 5, 1206 .vtotal = 1080 + 4 + 5 + 36, 1207}; 1208 1209static const struct panel_desc auo_t215hvn01 = { 1210 .modes = &auo_t215hvn01_mode, 1211 .num_modes = 1, 1212 .bpc = 8, 1213 .size = { 1214 .width = 430, 1215 .height = 270, 1216 }, 1217 .delay = { 1218 .disable = 5, 1219 .unprepare = 1000, 1220 }, 1221 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1222 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1223}; 1224 1225static const struct drm_display_mode avic_tm070ddh03_mode = { 1226 .clock = 51200, 1227 .hdisplay = 1024, 1228 .hsync_start = 1024 + 160, 1229 .hsync_end = 1024 + 160 + 4, 1230 .htotal = 1024 + 160 + 4 + 156, 1231 .vdisplay = 600, 1232 .vsync_start = 600 + 17, 1233 .vsync_end = 600 + 17 + 1, 1234 .vtotal = 600 + 17 + 1 + 17, 1235}; 1236 1237static const struct panel_desc avic_tm070ddh03 = { 1238 .modes = &avic_tm070ddh03_mode, 1239 .num_modes = 1, 1240 .bpc = 8, 1241 .size = { 1242 .width = 154, 1243 .height = 90, 1244 }, 1245 .delay = { 1246 .prepare = 20, 1247 .enable = 200, 1248 .disable = 200, 1249 }, 1250}; 1251 1252static const struct drm_display_mode bananapi_s070wv20_ct16_mode = { 1253 .clock = 30000, 1254 .hdisplay = 800, 1255 .hsync_start = 800 + 40, 1256 .hsync_end = 800 + 40 + 48, 1257 .htotal = 800 + 40 + 48 + 40, 1258 .vdisplay = 480, 1259 .vsync_start = 480 + 13, 1260 .vsync_end = 480 + 13 + 3, 1261 .vtotal = 480 + 13 + 3 + 29, 1262}; 1263 1264static const struct panel_desc bananapi_s070wv20_ct16 = { 1265 .modes = &bananapi_s070wv20_ct16_mode, 1266 .num_modes = 1, 1267 .bpc = 6, 1268 .size = { 1269 .width = 154, 1270 .height = 86, 1271 }, 1272}; 1273 1274static const struct display_timing boe_ev121wxm_n10_1850_timing = { 1275 .pixelclock = { 69922000, 71000000, 72293000 }, 1276 .hactive = { 1280, 1280, 1280 }, 1277 .hfront_porch = { 48, 48, 48 }, 1278 .hback_porch = { 80, 80, 80 }, 1279 .hsync_len = { 32, 32, 32 }, 1280 .vactive = { 800, 800, 800 }, 1281 .vfront_porch = { 3, 3, 3 }, 1282 .vback_porch = { 14, 14, 14 }, 1283 .vsync_len = { 6, 6, 6 }, 1284}; 1285 1286static const struct panel_desc boe_ev121wxm_n10_1850 = { 1287 .timings = &boe_ev121wxm_n10_1850_timing, 1288 .num_timings = 1, 1289 .bpc = 8, 1290 .size = { 1291 .width = 261, 1292 .height = 163, 1293 }, 1294 .delay = { 1295 .prepare = 9, 1296 .enable = 300, 1297 .unprepare = 300, 1298 .disable = 560, 1299 }, 1300 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1301 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1302 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1303}; 1304 1305static const struct drm_display_mode boe_hv070wsa_mode = { 1306 .clock = 42105, 1307 .hdisplay = 1024, 1308 .hsync_start = 1024 + 30, 1309 .hsync_end = 1024 + 30 + 30, 1310 .htotal = 1024 + 30 + 30 + 30, 1311 .vdisplay = 600, 1312 .vsync_start = 600 + 10, 1313 .vsync_end = 600 + 10 + 10, 1314 .vtotal = 600 + 10 + 10 + 10, 1315}; 1316 1317static const struct panel_desc boe_hv070wsa = { 1318 .modes = &boe_hv070wsa_mode, 1319 .num_modes = 1, 1320 .bpc = 8, 1321 .size = { 1322 .width = 154, 1323 .height = 90, 1324 }, 1325 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1326 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1327 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1328}; 1329 1330static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = { 1331 .clock = 9000, 1332 .hdisplay = 480, 1333 .hsync_start = 480 + 5, 1334 .hsync_end = 480 + 5 + 5, 1335 .htotal = 480 + 5 + 5 + 40, 1336 .vdisplay = 272, 1337 .vsync_start = 272 + 8, 1338 .vsync_end = 272 + 8 + 8, 1339 .vtotal = 272 + 8 + 8 + 8, 1340 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1341}; 1342 1343static const struct panel_desc cdtech_s043wq26h_ct7 = { 1344 .modes = &cdtech_s043wq26h_ct7_mode, 1345 .num_modes = 1, 1346 .bpc = 8, 1347 .size = { 1348 .width = 95, 1349 .height = 54, 1350 }, 1351 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1352}; 1353 1354/* S070PWS19HP-FC21 2017/04/22 */ 1355static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = { 1356 .clock = 51200, 1357 .hdisplay = 1024, 1358 .hsync_start = 1024 + 160, 1359 .hsync_end = 1024 + 160 + 20, 1360 .htotal = 1024 + 160 + 20 + 140, 1361 .vdisplay = 600, 1362 .vsync_start = 600 + 12, 1363 .vsync_end = 600 + 12 + 3, 1364 .vtotal = 600 + 12 + 3 + 20, 1365 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1366}; 1367 1368static const struct panel_desc cdtech_s070pws19hp_fc21 = { 1369 .modes = &cdtech_s070pws19hp_fc21_mode, 1370 .num_modes = 1, 1371 .bpc = 6, 1372 .size = { 1373 .width = 154, 1374 .height = 86, 1375 }, 1376 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1377 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1378 .connector_type = DRM_MODE_CONNECTOR_DPI, 1379}; 1380 1381/* S070SWV29HG-DC44 2017/09/21 */ 1382static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = { 1383 .clock = 33300, 1384 .hdisplay = 800, 1385 .hsync_start = 800 + 210, 1386 .hsync_end = 800 + 210 + 2, 1387 .htotal = 800 + 210 + 2 + 44, 1388 .vdisplay = 480, 1389 .vsync_start = 480 + 22, 1390 .vsync_end = 480 + 22 + 2, 1391 .vtotal = 480 + 22 + 2 + 21, 1392 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1393}; 1394 1395static const struct panel_desc cdtech_s070swv29hg_dc44 = { 1396 .modes = &cdtech_s070swv29hg_dc44_mode, 1397 .num_modes = 1, 1398 .bpc = 6, 1399 .size = { 1400 .width = 154, 1401 .height = 86, 1402 }, 1403 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1404 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1405 .connector_type = DRM_MODE_CONNECTOR_DPI, 1406}; 1407 1408static const struct drm_display_mode cdtech_s070wv95_ct16_mode = { 1409 .clock = 35000, 1410 .hdisplay = 800, 1411 .hsync_start = 800 + 40, 1412 .hsync_end = 800 + 40 + 40, 1413 .htotal = 800 + 40 + 40 + 48, 1414 .vdisplay = 480, 1415 .vsync_start = 480 + 29, 1416 .vsync_end = 480 + 29 + 13, 1417 .vtotal = 480 + 29 + 13 + 3, 1418 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1419}; 1420 1421static const struct panel_desc cdtech_s070wv95_ct16 = { 1422 .modes = &cdtech_s070wv95_ct16_mode, 1423 .num_modes = 1, 1424 .bpc = 8, 1425 .size = { 1426 .width = 154, 1427 .height = 85, 1428 }, 1429}; 1430 1431static const struct display_timing chefree_ch101olhlwh_002_timing = { 1432 .pixelclock = { 68900000, 71100000, 73400000 }, 1433 .hactive = { 1280, 1280, 1280 }, 1434 .hfront_porch = { 65, 80, 95 }, 1435 .hback_porch = { 64, 79, 94 }, 1436 .hsync_len = { 1, 1, 1 }, 1437 .vactive = { 800, 800, 800 }, 1438 .vfront_porch = { 7, 11, 14 }, 1439 .vback_porch = { 7, 11, 14 }, 1440 .vsync_len = { 1, 1, 1 }, 1441 .flags = DISPLAY_FLAGS_DE_HIGH, 1442}; 1443 1444static const struct panel_desc chefree_ch101olhlwh_002 = { 1445 .timings = &chefree_ch101olhlwh_002_timing, 1446 .num_timings = 1, 1447 .bpc = 8, 1448 .size = { 1449 .width = 217, 1450 .height = 135, 1451 }, 1452 .delay = { 1453 .enable = 200, 1454 .disable = 200, 1455 }, 1456 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1457 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1458 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1459}; 1460 1461static const struct drm_display_mode chunghwa_claa070wp03xg_mode = { 1462 .clock = 66770, 1463 .hdisplay = 800, 1464 .hsync_start = 800 + 49, 1465 .hsync_end = 800 + 49 + 33, 1466 .htotal = 800 + 49 + 33 + 17, 1467 .vdisplay = 1280, 1468 .vsync_start = 1280 + 1, 1469 .vsync_end = 1280 + 1 + 7, 1470 .vtotal = 1280 + 1 + 7 + 15, 1471 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1472}; 1473 1474static const struct panel_desc chunghwa_claa070wp03xg = { 1475 .modes = &chunghwa_claa070wp03xg_mode, 1476 .num_modes = 1, 1477 .bpc = 6, 1478 .size = { 1479 .width = 94, 1480 .height = 150, 1481 }, 1482 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1483 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1484 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1485}; 1486 1487static const struct drm_display_mode chunghwa_claa101wa01a_mode = { 1488 .clock = 72070, 1489 .hdisplay = 1366, 1490 .hsync_start = 1366 + 58, 1491 .hsync_end = 1366 + 58 + 58, 1492 .htotal = 1366 + 58 + 58 + 58, 1493 .vdisplay = 768, 1494 .vsync_start = 768 + 4, 1495 .vsync_end = 768 + 4 + 4, 1496 .vtotal = 768 + 4 + 4 + 4, 1497}; 1498 1499static const struct panel_desc chunghwa_claa101wa01a = { 1500 .modes = &chunghwa_claa101wa01a_mode, 1501 .num_modes = 1, 1502 .bpc = 6, 1503 .size = { 1504 .width = 220, 1505 .height = 120, 1506 }, 1507 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1508 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1509 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1510}; 1511 1512static const struct drm_display_mode chunghwa_claa101wb01_mode = { 1513 .clock = 69300, 1514 .hdisplay = 1366, 1515 .hsync_start = 1366 + 48, 1516 .hsync_end = 1366 + 48 + 32, 1517 .htotal = 1366 + 48 + 32 + 20, 1518 .vdisplay = 768, 1519 .vsync_start = 768 + 16, 1520 .vsync_end = 768 + 16 + 8, 1521 .vtotal = 768 + 16 + 8 + 16, 1522}; 1523 1524static const struct panel_desc chunghwa_claa101wb01 = { 1525 .modes = &chunghwa_claa101wb01_mode, 1526 .num_modes = 1, 1527 .bpc = 6, 1528 .size = { 1529 .width = 223, 1530 .height = 125, 1531 }, 1532 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1533 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1534 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1535}; 1536 1537static const struct display_timing dataimage_fg040346dsswbg04_timing = { 1538 .pixelclock = { 5000000, 9000000, 12000000 }, 1539 .hactive = { 480, 480, 480 }, 1540 .hfront_porch = { 12, 12, 12 }, 1541 .hback_porch = { 12, 12, 12 }, 1542 .hsync_len = { 21, 21, 21 }, 1543 .vactive = { 272, 272, 272 }, 1544 .vfront_porch = { 4, 4, 4 }, 1545 .vback_porch = { 4, 4, 4 }, 1546 .vsync_len = { 8, 8, 8 }, 1547}; 1548 1549static const struct panel_desc dataimage_fg040346dsswbg04 = { 1550 .timings = &dataimage_fg040346dsswbg04_timing, 1551 .num_timings = 1, 1552 .bpc = 8, 1553 .size = { 1554 .width = 95, 1555 .height = 54, 1556 }, 1557 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1558 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1559 .connector_type = DRM_MODE_CONNECTOR_DPI, 1560}; 1561 1562static const struct display_timing dataimage_fg1001l0dsswmg01_timing = { 1563 .pixelclock = { 68900000, 71110000, 73400000 }, 1564 .hactive = { 1280, 1280, 1280 }, 1565 .vactive = { 800, 800, 800 }, 1566 .hback_porch = { 100, 100, 100 }, 1567 .hfront_porch = { 100, 100, 100 }, 1568 .vback_porch = { 5, 5, 5 }, 1569 .vfront_porch = { 5, 5, 5 }, 1570 .hsync_len = { 24, 24, 24 }, 1571 .vsync_len = { 3, 3, 3 }, 1572 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 1573 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1574}; 1575 1576static const struct panel_desc dataimage_fg1001l0dsswmg01 = { 1577 .timings = &dataimage_fg1001l0dsswmg01_timing, 1578 .num_timings = 1, 1579 .bpc = 8, 1580 .size = { 1581 .width = 217, 1582 .height = 136, 1583 }, 1584}; 1585 1586static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = { 1587 .clock = 33260, 1588 .hdisplay = 800, 1589 .hsync_start = 800 + 40, 1590 .hsync_end = 800 + 40 + 128, 1591 .htotal = 800 + 40 + 128 + 88, 1592 .vdisplay = 480, 1593 .vsync_start = 480 + 10, 1594 .vsync_end = 480 + 10 + 2, 1595 .vtotal = 480 + 10 + 2 + 33, 1596 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1597}; 1598 1599static const struct panel_desc dataimage_scf0700c48ggu18 = { 1600 .modes = &dataimage_scf0700c48ggu18_mode, 1601 .num_modes = 1, 1602 .bpc = 8, 1603 .size = { 1604 .width = 152, 1605 .height = 91, 1606 }, 1607 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1608 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1609}; 1610 1611static const struct display_timing dlc_dlc0700yzg_1_timing = { 1612 .pixelclock = { 45000000, 51200000, 57000000 }, 1613 .hactive = { 1024, 1024, 1024 }, 1614 .hfront_porch = { 100, 106, 113 }, 1615 .hback_porch = { 100, 106, 113 }, 1616 .hsync_len = { 100, 108, 114 }, 1617 .vactive = { 600, 600, 600 }, 1618 .vfront_porch = { 8, 11, 15 }, 1619 .vback_porch = { 8, 11, 15 }, 1620 .vsync_len = { 9, 13, 15 }, 1621 .flags = DISPLAY_FLAGS_DE_HIGH, 1622}; 1623 1624static const struct panel_desc dlc_dlc0700yzg_1 = { 1625 .timings = &dlc_dlc0700yzg_1_timing, 1626 .num_timings = 1, 1627 .bpc = 6, 1628 .size = { 1629 .width = 154, 1630 .height = 86, 1631 }, 1632 .delay = { 1633 .prepare = 30, 1634 .enable = 200, 1635 .disable = 200, 1636 }, 1637 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1638 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1639}; 1640 1641static const struct display_timing dlc_dlc1010gig_timing = { 1642 .pixelclock = { 68900000, 71100000, 73400000 }, 1643 .hactive = { 1280, 1280, 1280 }, 1644 .hfront_porch = { 43, 53, 63 }, 1645 .hback_porch = { 43, 53, 63 }, 1646 .hsync_len = { 44, 54, 64 }, 1647 .vactive = { 800, 800, 800 }, 1648 .vfront_porch = { 5, 8, 11 }, 1649 .vback_porch = { 5, 8, 11 }, 1650 .vsync_len = { 5, 7, 11 }, 1651 .flags = DISPLAY_FLAGS_DE_HIGH, 1652}; 1653 1654static const struct panel_desc dlc_dlc1010gig = { 1655 .timings = &dlc_dlc1010gig_timing, 1656 .num_timings = 1, 1657 .bpc = 8, 1658 .size = { 1659 .width = 216, 1660 .height = 135, 1661 }, 1662 .delay = { 1663 .prepare = 60, 1664 .enable = 150, 1665 .disable = 100, 1666 .unprepare = 60, 1667 }, 1668 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1669 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1670}; 1671 1672static const struct drm_display_mode edt_et035012dm6_mode = { 1673 .clock = 6500, 1674 .hdisplay = 320, 1675 .hsync_start = 320 + 20, 1676 .hsync_end = 320 + 20 + 30, 1677 .htotal = 320 + 20 + 68, 1678 .vdisplay = 240, 1679 .vsync_start = 240 + 4, 1680 .vsync_end = 240 + 4 + 4, 1681 .vtotal = 240 + 4 + 4 + 14, 1682 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1683}; 1684 1685static const struct panel_desc edt_et035012dm6 = { 1686 .modes = &edt_et035012dm6_mode, 1687 .num_modes = 1, 1688 .bpc = 8, 1689 .size = { 1690 .width = 70, 1691 .height = 52, 1692 }, 1693 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1694 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1695}; 1696 1697static const struct drm_display_mode edt_etm0350g0dh6_mode = { 1698 .clock = 6520, 1699 .hdisplay = 320, 1700 .hsync_start = 320 + 20, 1701 .hsync_end = 320 + 20 + 68, 1702 .htotal = 320 + 20 + 68, 1703 .vdisplay = 240, 1704 .vsync_start = 240 + 4, 1705 .vsync_end = 240 + 4 + 18, 1706 .vtotal = 240 + 4 + 18, 1707 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1708}; 1709 1710static const struct panel_desc edt_etm0350g0dh6 = { 1711 .modes = &edt_etm0350g0dh6_mode, 1712 .num_modes = 1, 1713 .bpc = 6, 1714 .size = { 1715 .width = 70, 1716 .height = 53, 1717 }, 1718 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1719 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1720 .connector_type = DRM_MODE_CONNECTOR_DPI, 1721}; 1722 1723static const struct drm_display_mode edt_etm043080dh6gp_mode = { 1724 .clock = 10870, 1725 .hdisplay = 480, 1726 .hsync_start = 480 + 8, 1727 .hsync_end = 480 + 8 + 4, 1728 .htotal = 480 + 8 + 4 + 41, 1729 1730 /* 1731 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while 1732 * fb_align 1733 */ 1734 1735 .vdisplay = 288, 1736 .vsync_start = 288 + 2, 1737 .vsync_end = 288 + 2 + 4, 1738 .vtotal = 288 + 2 + 4 + 10, 1739}; 1740 1741static const struct panel_desc edt_etm043080dh6gp = { 1742 .modes = &edt_etm043080dh6gp_mode, 1743 .num_modes = 1, 1744 .bpc = 8, 1745 .size = { 1746 .width = 100, 1747 .height = 65, 1748 }, 1749 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1750 .connector_type = DRM_MODE_CONNECTOR_DPI, 1751}; 1752 1753static const struct drm_display_mode edt_etm0430g0dh6_mode = { 1754 .clock = 9000, 1755 .hdisplay = 480, 1756 .hsync_start = 480 + 2, 1757 .hsync_end = 480 + 2 + 41, 1758 .htotal = 480 + 2 + 41 + 2, 1759 .vdisplay = 272, 1760 .vsync_start = 272 + 2, 1761 .vsync_end = 272 + 2 + 10, 1762 .vtotal = 272 + 2 + 10 + 2, 1763 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1764}; 1765 1766static const struct panel_desc edt_etm0430g0dh6 = { 1767 .modes = &edt_etm0430g0dh6_mode, 1768 .num_modes = 1, 1769 .bpc = 6, 1770 .size = { 1771 .width = 95, 1772 .height = 54, 1773 }, 1774 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1775 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1776 .connector_type = DRM_MODE_CONNECTOR_DPI, 1777}; 1778 1779static const struct drm_display_mode edt_et057090dhu_mode = { 1780 .clock = 25175, 1781 .hdisplay = 640, 1782 .hsync_start = 640 + 16, 1783 .hsync_end = 640 + 16 + 30, 1784 .htotal = 640 + 16 + 30 + 114, 1785 .vdisplay = 480, 1786 .vsync_start = 480 + 10, 1787 .vsync_end = 480 + 10 + 3, 1788 .vtotal = 480 + 10 + 3 + 32, 1789 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1790}; 1791 1792static const struct panel_desc edt_et057090dhu = { 1793 .modes = &edt_et057090dhu_mode, 1794 .num_modes = 1, 1795 .bpc = 6, 1796 .size = { 1797 .width = 115, 1798 .height = 86, 1799 }, 1800 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1801 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1802 .connector_type = DRM_MODE_CONNECTOR_DPI, 1803}; 1804 1805static const struct drm_display_mode edt_etm0700g0dh6_mode = { 1806 .clock = 33260, 1807 .hdisplay = 800, 1808 .hsync_start = 800 + 40, 1809 .hsync_end = 800 + 40 + 128, 1810 .htotal = 800 + 40 + 128 + 88, 1811 .vdisplay = 480, 1812 .vsync_start = 480 + 10, 1813 .vsync_end = 480 + 10 + 2, 1814 .vtotal = 480 + 10 + 2 + 33, 1815 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1816}; 1817 1818static const struct panel_desc edt_etm0700g0dh6 = { 1819 .modes = &edt_etm0700g0dh6_mode, 1820 .num_modes = 1, 1821 .bpc = 6, 1822 .size = { 1823 .width = 152, 1824 .height = 91, 1825 }, 1826 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1827 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1828 .connector_type = DRM_MODE_CONNECTOR_DPI, 1829}; 1830 1831static const struct panel_desc edt_etm0700g0bdh6 = { 1832 .modes = &edt_etm0700g0dh6_mode, 1833 .num_modes = 1, 1834 .bpc = 6, 1835 .size = { 1836 .width = 152, 1837 .height = 91, 1838 }, 1839 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1840 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1841 .connector_type = DRM_MODE_CONNECTOR_DPI, 1842}; 1843 1844static const struct display_timing edt_etml0700y5dha_timing = { 1845 .pixelclock = { 40800000, 51200000, 67200000 }, 1846 .hactive = { 1024, 1024, 1024 }, 1847 .hfront_porch = { 30, 106, 125 }, 1848 .hback_porch = { 30, 106, 125 }, 1849 .hsync_len = { 30, 108, 126 }, 1850 .vactive = { 600, 600, 600 }, 1851 .vfront_porch = { 3, 12, 67}, 1852 .vback_porch = { 3, 12, 67 }, 1853 .vsync_len = { 4, 11, 66 }, 1854 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 1855 DISPLAY_FLAGS_DE_HIGH, 1856}; 1857 1858static const struct panel_desc edt_etml0700y5dha = { 1859 .timings = &edt_etml0700y5dha_timing, 1860 .num_timings = 1, 1861 .bpc = 8, 1862 .size = { 1863 .width = 155, 1864 .height = 86, 1865 }, 1866 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1867 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1868}; 1869 1870static const struct drm_display_mode edt_etmv570g2dhu_mode = { 1871 .clock = 25175, 1872 .hdisplay = 640, 1873 .hsync_start = 640, 1874 .hsync_end = 640 + 16, 1875 .htotal = 640 + 16 + 30 + 114, 1876 .vdisplay = 480, 1877 .vsync_start = 480 + 10, 1878 .vsync_end = 480 + 10 + 3, 1879 .vtotal = 480 + 10 + 3 + 35, 1880 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC, 1881}; 1882 1883static const struct panel_desc edt_etmv570g2dhu = { 1884 .modes = &edt_etmv570g2dhu_mode, 1885 .num_modes = 1, 1886 .bpc = 6, 1887 .size = { 1888 .width = 115, 1889 .height = 86, 1890 }, 1891 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1892 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1893 .connector_type = DRM_MODE_CONNECTOR_DPI, 1894}; 1895 1896static const struct display_timing eink_vb3300_kca_timing = { 1897 .pixelclock = { 40000000, 40000000, 40000000 }, 1898 .hactive = { 334, 334, 334 }, 1899 .hfront_porch = { 1, 1, 1 }, 1900 .hback_porch = { 1, 1, 1 }, 1901 .hsync_len = { 1, 1, 1 }, 1902 .vactive = { 1405, 1405, 1405 }, 1903 .vfront_porch = { 1, 1, 1 }, 1904 .vback_porch = { 1, 1, 1 }, 1905 .vsync_len = { 1, 1, 1 }, 1906 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 1907 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 1908}; 1909 1910static const struct panel_desc eink_vb3300_kca = { 1911 .timings = &eink_vb3300_kca_timing, 1912 .num_timings = 1, 1913 .bpc = 6, 1914 .size = { 1915 .width = 157, 1916 .height = 209, 1917 }, 1918 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1919 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1920 .connector_type = DRM_MODE_CONNECTOR_DPI, 1921}; 1922 1923static const struct display_timing evervision_vgg804821_timing = { 1924 .pixelclock = { 27600000, 33300000, 50000000 }, 1925 .hactive = { 800, 800, 800 }, 1926 .hfront_porch = { 40, 66, 70 }, 1927 .hback_porch = { 40, 67, 70 }, 1928 .hsync_len = { 40, 67, 70 }, 1929 .vactive = { 480, 480, 480 }, 1930 .vfront_porch = { 6, 10, 10 }, 1931 .vback_porch = { 7, 11, 11 }, 1932 .vsync_len = { 7, 11, 11 }, 1933 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH | 1934 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 1935 DISPLAY_FLAGS_SYNC_NEGEDGE, 1936}; 1937 1938static const struct panel_desc evervision_vgg804821 = { 1939 .timings = &evervision_vgg804821_timing, 1940 .num_timings = 1, 1941 .bpc = 8, 1942 .size = { 1943 .width = 108, 1944 .height = 64, 1945 }, 1946 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1947 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1948}; 1949 1950static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = { 1951 .clock = 32260, 1952 .hdisplay = 800, 1953 .hsync_start = 800 + 168, 1954 .hsync_end = 800 + 168 + 64, 1955 .htotal = 800 + 168 + 64 + 88, 1956 .vdisplay = 480, 1957 .vsync_start = 480 + 37, 1958 .vsync_end = 480 + 37 + 2, 1959 .vtotal = 480 + 37 + 2 + 8, 1960}; 1961 1962static const struct panel_desc foxlink_fl500wvr00_a0t = { 1963 .modes = &foxlink_fl500wvr00_a0t_mode, 1964 .num_modes = 1, 1965 .bpc = 8, 1966 .size = { 1967 .width = 108, 1968 .height = 65, 1969 }, 1970 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1971}; 1972 1973static const struct drm_display_mode frida_frd350h54004_modes[] = { 1974 { /* 60 Hz */ 1975 .clock = 6000, 1976 .hdisplay = 320, 1977 .hsync_start = 320 + 44, 1978 .hsync_end = 320 + 44 + 16, 1979 .htotal = 320 + 44 + 16 + 20, 1980 .vdisplay = 240, 1981 .vsync_start = 240 + 2, 1982 .vsync_end = 240 + 2 + 6, 1983 .vtotal = 240 + 2 + 6 + 2, 1984 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1985 }, 1986 { /* 50 Hz */ 1987 .clock = 5400, 1988 .hdisplay = 320, 1989 .hsync_start = 320 + 56, 1990 .hsync_end = 320 + 56 + 16, 1991 .htotal = 320 + 56 + 16 + 40, 1992 .vdisplay = 240, 1993 .vsync_start = 240 + 2, 1994 .vsync_end = 240 + 2 + 6, 1995 .vtotal = 240 + 2 + 6 + 2, 1996 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1997 }, 1998}; 1999 2000static const struct panel_desc frida_frd350h54004 = { 2001 .modes = frida_frd350h54004_modes, 2002 .num_modes = ARRAY_SIZE(frida_frd350h54004_modes), 2003 .bpc = 8, 2004 .size = { 2005 .width = 77, 2006 .height = 64, 2007 }, 2008 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2009 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2010 .connector_type = DRM_MODE_CONNECTOR_DPI, 2011}; 2012 2013static const struct drm_display_mode friendlyarm_hd702e_mode = { 2014 .clock = 67185, 2015 .hdisplay = 800, 2016 .hsync_start = 800 + 20, 2017 .hsync_end = 800 + 20 + 24, 2018 .htotal = 800 + 20 + 24 + 20, 2019 .vdisplay = 1280, 2020 .vsync_start = 1280 + 4, 2021 .vsync_end = 1280 + 4 + 8, 2022 .vtotal = 1280 + 4 + 8 + 4, 2023 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2024}; 2025 2026static const struct panel_desc friendlyarm_hd702e = { 2027 .modes = &friendlyarm_hd702e_mode, 2028 .num_modes = 1, 2029 .size = { 2030 .width = 94, 2031 .height = 151, 2032 }, 2033}; 2034 2035static const struct drm_display_mode giantplus_gpg482739qs5_mode = { 2036 .clock = 9000, 2037 .hdisplay = 480, 2038 .hsync_start = 480 + 5, 2039 .hsync_end = 480 + 5 + 1, 2040 .htotal = 480 + 5 + 1 + 40, 2041 .vdisplay = 272, 2042 .vsync_start = 272 + 8, 2043 .vsync_end = 272 + 8 + 1, 2044 .vtotal = 272 + 8 + 1 + 8, 2045}; 2046 2047static const struct panel_desc giantplus_gpg482739qs5 = { 2048 .modes = &giantplus_gpg482739qs5_mode, 2049 .num_modes = 1, 2050 .bpc = 8, 2051 .size = { 2052 .width = 95, 2053 .height = 54, 2054 }, 2055 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2056}; 2057 2058static const struct display_timing giantplus_gpm940b0_timing = { 2059 .pixelclock = { 13500000, 27000000, 27500000 }, 2060 .hactive = { 320, 320, 320 }, 2061 .hfront_porch = { 14, 686, 718 }, 2062 .hback_porch = { 50, 70, 255 }, 2063 .hsync_len = { 1, 1, 1 }, 2064 .vactive = { 240, 240, 240 }, 2065 .vfront_porch = { 1, 1, 179 }, 2066 .vback_porch = { 1, 21, 31 }, 2067 .vsync_len = { 1, 1, 6 }, 2068 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 2069}; 2070 2071static const struct panel_desc giantplus_gpm940b0 = { 2072 .timings = &giantplus_gpm940b0_timing, 2073 .num_timings = 1, 2074 .bpc = 8, 2075 .size = { 2076 .width = 60, 2077 .height = 45, 2078 }, 2079 .bus_format = MEDIA_BUS_FMT_RGB888_3X8, 2080 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2081}; 2082 2083static const struct display_timing hannstar_hsd070pww1_timing = { 2084 .pixelclock = { 64300000, 71100000, 82000000 }, 2085 .hactive = { 1280, 1280, 1280 }, 2086 .hfront_porch = { 1, 1, 10 }, 2087 .hback_porch = { 1, 1, 10 }, 2088 /* 2089 * According to the data sheet, the minimum horizontal blanking interval 2090 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the 2091 * minimum working horizontal blanking interval to be 60 clocks. 2092 */ 2093 .hsync_len = { 58, 158, 661 }, 2094 .vactive = { 800, 800, 800 }, 2095 .vfront_porch = { 1, 1, 10 }, 2096 .vback_porch = { 1, 1, 10 }, 2097 .vsync_len = { 1, 21, 203 }, 2098 .flags = DISPLAY_FLAGS_DE_HIGH, 2099}; 2100 2101static const struct panel_desc hannstar_hsd070pww1 = { 2102 .timings = &hannstar_hsd070pww1_timing, 2103 .num_timings = 1, 2104 .bpc = 6, 2105 .size = { 2106 .width = 151, 2107 .height = 94, 2108 }, 2109 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2110 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2111}; 2112 2113static const struct display_timing hannstar_hsd100pxn1_timing = { 2114 .pixelclock = { 55000000, 65000000, 75000000 }, 2115 .hactive = { 1024, 1024, 1024 }, 2116 .hfront_porch = { 40, 40, 40 }, 2117 .hback_porch = { 220, 220, 220 }, 2118 .hsync_len = { 20, 60, 100 }, 2119 .vactive = { 768, 768, 768 }, 2120 .vfront_porch = { 7, 7, 7 }, 2121 .vback_porch = { 21, 21, 21 }, 2122 .vsync_len = { 10, 10, 10 }, 2123 .flags = DISPLAY_FLAGS_DE_HIGH, 2124}; 2125 2126static const struct panel_desc hannstar_hsd100pxn1 = { 2127 .timings = &hannstar_hsd100pxn1_timing, 2128 .num_timings = 1, 2129 .bpc = 6, 2130 .size = { 2131 .width = 203, 2132 .height = 152, 2133 }, 2134 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2135 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2136}; 2137 2138static const struct display_timing hannstar_hsd101pww2_timing = { 2139 .pixelclock = { 64300000, 71100000, 82000000 }, 2140 .hactive = { 1280, 1280, 1280 }, 2141 .hfront_porch = { 1, 1, 10 }, 2142 .hback_porch = { 1, 1, 10 }, 2143 .hsync_len = { 58, 158, 661 }, 2144 .vactive = { 800, 800, 800 }, 2145 .vfront_porch = { 1, 1, 10 }, 2146 .vback_porch = { 1, 1, 10 }, 2147 .vsync_len = { 1, 21, 203 }, 2148 .flags = DISPLAY_FLAGS_DE_HIGH, 2149}; 2150 2151static const struct panel_desc hannstar_hsd101pww2 = { 2152 .timings = &hannstar_hsd101pww2_timing, 2153 .num_timings = 1, 2154 .bpc = 8, 2155 .size = { 2156 .width = 217, 2157 .height = 136, 2158 }, 2159 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2160 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2161}; 2162 2163static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = { 2164 .clock = 33333, 2165 .hdisplay = 800, 2166 .hsync_start = 800 + 85, 2167 .hsync_end = 800 + 85 + 86, 2168 .htotal = 800 + 85 + 86 + 85, 2169 .vdisplay = 480, 2170 .vsync_start = 480 + 16, 2171 .vsync_end = 480 + 16 + 13, 2172 .vtotal = 480 + 16 + 13 + 16, 2173}; 2174 2175static const struct panel_desc hitachi_tx23d38vm0caa = { 2176 .modes = &hitachi_tx23d38vm0caa_mode, 2177 .num_modes = 1, 2178 .bpc = 6, 2179 .size = { 2180 .width = 195, 2181 .height = 117, 2182 }, 2183 .delay = { 2184 .enable = 160, 2185 .disable = 160, 2186 }, 2187}; 2188 2189static const struct drm_display_mode innolux_at043tn24_mode = { 2190 .clock = 9000, 2191 .hdisplay = 480, 2192 .hsync_start = 480 + 2, 2193 .hsync_end = 480 + 2 + 41, 2194 .htotal = 480 + 2 + 41 + 2, 2195 .vdisplay = 272, 2196 .vsync_start = 272 + 2, 2197 .vsync_end = 272 + 2 + 10, 2198 .vtotal = 272 + 2 + 10 + 2, 2199 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2200}; 2201 2202static const struct panel_desc innolux_at043tn24 = { 2203 .modes = &innolux_at043tn24_mode, 2204 .num_modes = 1, 2205 .bpc = 8, 2206 .size = { 2207 .width = 95, 2208 .height = 54, 2209 }, 2210 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2211 .connector_type = DRM_MODE_CONNECTOR_DPI, 2212 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2213}; 2214 2215static const struct drm_display_mode innolux_at070tn92_mode = { 2216 .clock = 33333, 2217 .hdisplay = 800, 2218 .hsync_start = 800 + 210, 2219 .hsync_end = 800 + 210 + 20, 2220 .htotal = 800 + 210 + 20 + 46, 2221 .vdisplay = 480, 2222 .vsync_start = 480 + 22, 2223 .vsync_end = 480 + 22 + 10, 2224 .vtotal = 480 + 22 + 23 + 10, 2225}; 2226 2227static const struct panel_desc innolux_at070tn92 = { 2228 .modes = &innolux_at070tn92_mode, 2229 .num_modes = 1, 2230 .size = { 2231 .width = 154, 2232 .height = 86, 2233 }, 2234 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2235}; 2236 2237static const struct display_timing innolux_g070ace_l01_timing = { 2238 .pixelclock = { 25200000, 35000000, 35700000 }, 2239 .hactive = { 800, 800, 800 }, 2240 .hfront_porch = { 30, 32, 87 }, 2241 .hback_porch = { 30, 32, 87 }, 2242 .hsync_len = { 1, 1, 1 }, 2243 .vactive = { 480, 480, 480 }, 2244 .vfront_porch = { 3, 3, 3 }, 2245 .vback_porch = { 13, 13, 13 }, 2246 .vsync_len = { 1, 1, 4 }, 2247 .flags = DISPLAY_FLAGS_DE_HIGH, 2248}; 2249 2250static const struct panel_desc innolux_g070ace_l01 = { 2251 .timings = &innolux_g070ace_l01_timing, 2252 .num_timings = 1, 2253 .bpc = 8, 2254 .size = { 2255 .width = 152, 2256 .height = 91, 2257 }, 2258 .delay = { 2259 .prepare = 10, 2260 .enable = 50, 2261 .disable = 50, 2262 .unprepare = 500, 2263 }, 2264 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2265 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2266 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2267}; 2268 2269static const struct display_timing innolux_g070y2_l01_timing = { 2270 .pixelclock = { 28000000, 29500000, 32000000 }, 2271 .hactive = { 800, 800, 800 }, 2272 .hfront_porch = { 61, 91, 141 }, 2273 .hback_porch = { 60, 90, 140 }, 2274 .hsync_len = { 12, 12, 12 }, 2275 .vactive = { 480, 480, 480 }, 2276 .vfront_porch = { 4, 9, 30 }, 2277 .vback_porch = { 4, 8, 28 }, 2278 .vsync_len = { 2, 2, 2 }, 2279 .flags = DISPLAY_FLAGS_DE_HIGH, 2280}; 2281 2282static const struct panel_desc innolux_g070y2_l01 = { 2283 .timings = &innolux_g070y2_l01_timing, 2284 .num_timings = 1, 2285 .bpc = 8, 2286 .size = { 2287 .width = 152, 2288 .height = 91, 2289 }, 2290 .delay = { 2291 .prepare = 10, 2292 .enable = 100, 2293 .disable = 100, 2294 .unprepare = 800, 2295 }, 2296 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2297 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2298 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2299}; 2300 2301static const struct drm_display_mode innolux_g070y2_t02_mode = { 2302 .clock = 33333, 2303 .hdisplay = 800, 2304 .hsync_start = 800 + 210, 2305 .hsync_end = 800 + 210 + 20, 2306 .htotal = 800 + 210 + 20 + 46, 2307 .vdisplay = 480, 2308 .vsync_start = 480 + 22, 2309 .vsync_end = 480 + 22 + 10, 2310 .vtotal = 480 + 22 + 23 + 10, 2311}; 2312 2313static const struct panel_desc innolux_g070y2_t02 = { 2314 .modes = &innolux_g070y2_t02_mode, 2315 .num_modes = 1, 2316 .bpc = 8, 2317 .size = { 2318 .width = 152, 2319 .height = 92, 2320 }, 2321 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2322 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2323 .connector_type = DRM_MODE_CONNECTOR_DPI, 2324}; 2325 2326static const struct display_timing innolux_g101ice_l01_timing = { 2327 .pixelclock = { 60400000, 71100000, 74700000 }, 2328 .hactive = { 1280, 1280, 1280 }, 2329 .hfront_porch = { 30, 60, 70 }, 2330 .hback_porch = { 30, 60, 70 }, 2331 .hsync_len = { 22, 40, 60 }, 2332 .vactive = { 800, 800, 800 }, 2333 .vfront_porch = { 3, 8, 14 }, 2334 .vback_porch = { 3, 8, 14 }, 2335 .vsync_len = { 4, 7, 12 }, 2336 .flags = DISPLAY_FLAGS_DE_HIGH, 2337}; 2338 2339static const struct panel_desc innolux_g101ice_l01 = { 2340 .timings = &innolux_g101ice_l01_timing, 2341 .num_timings = 1, 2342 .bpc = 8, 2343 .size = { 2344 .width = 217, 2345 .height = 135, 2346 }, 2347 .delay = { 2348 .enable = 200, 2349 .disable = 200, 2350 }, 2351 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2352 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2353 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2354}; 2355 2356static const struct display_timing innolux_g121i1_l01_timing = { 2357 .pixelclock = { 67450000, 71000000, 74550000 }, 2358 .hactive = { 1280, 1280, 1280 }, 2359 .hfront_porch = { 40, 80, 160 }, 2360 .hback_porch = { 39, 79, 159 }, 2361 .hsync_len = { 1, 1, 1 }, 2362 .vactive = { 800, 800, 800 }, 2363 .vfront_porch = { 5, 11, 100 }, 2364 .vback_porch = { 4, 11, 99 }, 2365 .vsync_len = { 1, 1, 1 }, 2366}; 2367 2368static const struct panel_desc innolux_g121i1_l01 = { 2369 .timings = &innolux_g121i1_l01_timing, 2370 .num_timings = 1, 2371 .bpc = 6, 2372 .size = { 2373 .width = 261, 2374 .height = 163, 2375 }, 2376 .delay = { 2377 .enable = 200, 2378 .disable = 20, 2379 }, 2380 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2381 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2382}; 2383 2384static const struct drm_display_mode innolux_g121x1_l03_mode = { 2385 .clock = 65000, 2386 .hdisplay = 1024, 2387 .hsync_start = 1024 + 0, 2388 .hsync_end = 1024 + 1, 2389 .htotal = 1024 + 0 + 1 + 320, 2390 .vdisplay = 768, 2391 .vsync_start = 768 + 38, 2392 .vsync_end = 768 + 38 + 1, 2393 .vtotal = 768 + 38 + 1 + 0, 2394 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2395}; 2396 2397static const struct panel_desc innolux_g121x1_l03 = { 2398 .modes = &innolux_g121x1_l03_mode, 2399 .num_modes = 1, 2400 .bpc = 6, 2401 .size = { 2402 .width = 246, 2403 .height = 185, 2404 }, 2405 .delay = { 2406 .enable = 200, 2407 .unprepare = 200, 2408 .disable = 400, 2409 }, 2410}; 2411 2412static const struct display_timing innolux_g156hce_l01_timings = { 2413 .pixelclock = { 120000000, 141860000, 150000000 }, 2414 .hactive = { 1920, 1920, 1920 }, 2415 .hfront_porch = { 80, 90, 100 }, 2416 .hback_porch = { 80, 90, 100 }, 2417 .hsync_len = { 20, 30, 30 }, 2418 .vactive = { 1080, 1080, 1080 }, 2419 .vfront_porch = { 3, 10, 20 }, 2420 .vback_porch = { 3, 10, 20 }, 2421 .vsync_len = { 4, 10, 10 }, 2422}; 2423 2424static const struct panel_desc innolux_g156hce_l01 = { 2425 .timings = &innolux_g156hce_l01_timings, 2426 .num_timings = 1, 2427 .bpc = 8, 2428 .size = { 2429 .width = 344, 2430 .height = 194, 2431 }, 2432 .delay = { 2433 .prepare = 1, /* T1+T2 */ 2434 .enable = 450, /* T5 */ 2435 .disable = 200, /* T6 */ 2436 .unprepare = 10, /* T3+T7 */ 2437 }, 2438 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2439 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2440 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2441}; 2442 2443static const struct drm_display_mode innolux_n156bge_l21_mode = { 2444 .clock = 69300, 2445 .hdisplay = 1366, 2446 .hsync_start = 1366 + 16, 2447 .hsync_end = 1366 + 16 + 34, 2448 .htotal = 1366 + 16 + 34 + 50, 2449 .vdisplay = 768, 2450 .vsync_start = 768 + 2, 2451 .vsync_end = 768 + 2 + 6, 2452 .vtotal = 768 + 2 + 6 + 12, 2453}; 2454 2455static const struct panel_desc innolux_n156bge_l21 = { 2456 .modes = &innolux_n156bge_l21_mode, 2457 .num_modes = 1, 2458 .bpc = 6, 2459 .size = { 2460 .width = 344, 2461 .height = 193, 2462 }, 2463 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2464 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2465 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2466}; 2467 2468static const struct drm_display_mode innolux_zj070na_01p_mode = { 2469 .clock = 51501, 2470 .hdisplay = 1024, 2471 .hsync_start = 1024 + 128, 2472 .hsync_end = 1024 + 128 + 64, 2473 .htotal = 1024 + 128 + 64 + 128, 2474 .vdisplay = 600, 2475 .vsync_start = 600 + 16, 2476 .vsync_end = 600 + 16 + 4, 2477 .vtotal = 600 + 16 + 4 + 16, 2478}; 2479 2480static const struct panel_desc innolux_zj070na_01p = { 2481 .modes = &innolux_zj070na_01p_mode, 2482 .num_modes = 1, 2483 .bpc = 6, 2484 .size = { 2485 .width = 154, 2486 .height = 90, 2487 }, 2488}; 2489 2490static const struct display_timing koe_tx14d24vm1bpa_timing = { 2491 .pixelclock = { 5580000, 5850000, 6200000 }, 2492 .hactive = { 320, 320, 320 }, 2493 .hfront_porch = { 30, 30, 30 }, 2494 .hback_porch = { 30, 30, 30 }, 2495 .hsync_len = { 1, 5, 17 }, 2496 .vactive = { 240, 240, 240 }, 2497 .vfront_porch = { 6, 6, 6 }, 2498 .vback_porch = { 5, 5, 5 }, 2499 .vsync_len = { 1, 2, 11 }, 2500 .flags = DISPLAY_FLAGS_DE_HIGH, 2501}; 2502 2503static const struct panel_desc koe_tx14d24vm1bpa = { 2504 .timings = &koe_tx14d24vm1bpa_timing, 2505 .num_timings = 1, 2506 .bpc = 6, 2507 .size = { 2508 .width = 115, 2509 .height = 86, 2510 }, 2511}; 2512 2513static const struct display_timing koe_tx26d202vm0bwa_timing = { 2514 .pixelclock = { 151820000, 156720000, 159780000 }, 2515 .hactive = { 1920, 1920, 1920 }, 2516 .hfront_porch = { 105, 130, 142 }, 2517 .hback_porch = { 45, 70, 82 }, 2518 .hsync_len = { 30, 30, 30 }, 2519 .vactive = { 1200, 1200, 1200}, 2520 .vfront_porch = { 3, 5, 10 }, 2521 .vback_porch = { 2, 5, 10 }, 2522 .vsync_len = { 5, 5, 5 }, 2523}; 2524 2525static const struct panel_desc koe_tx26d202vm0bwa = { 2526 .timings = &koe_tx26d202vm0bwa_timing, 2527 .num_timings = 1, 2528 .bpc = 8, 2529 .size = { 2530 .width = 217, 2531 .height = 136, 2532 }, 2533 .delay = { 2534 .prepare = 1000, 2535 .enable = 1000, 2536 .unprepare = 1000, 2537 .disable = 1000, 2538 }, 2539 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2540 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2541 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2542}; 2543 2544static const struct display_timing koe_tx31d200vm0baa_timing = { 2545 .pixelclock = { 39600000, 43200000, 48000000 }, 2546 .hactive = { 1280, 1280, 1280 }, 2547 .hfront_porch = { 16, 36, 56 }, 2548 .hback_porch = { 16, 36, 56 }, 2549 .hsync_len = { 8, 8, 8 }, 2550 .vactive = { 480, 480, 480 }, 2551 .vfront_porch = { 6, 21, 33 }, 2552 .vback_porch = { 6, 21, 33 }, 2553 .vsync_len = { 8, 8, 8 }, 2554 .flags = DISPLAY_FLAGS_DE_HIGH, 2555}; 2556 2557static const struct panel_desc koe_tx31d200vm0baa = { 2558 .timings = &koe_tx31d200vm0baa_timing, 2559 .num_timings = 1, 2560 .bpc = 6, 2561 .size = { 2562 .width = 292, 2563 .height = 109, 2564 }, 2565 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2566 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2567}; 2568 2569static const struct display_timing kyo_tcg121xglp_timing = { 2570 .pixelclock = { 52000000, 65000000, 71000000 }, 2571 .hactive = { 1024, 1024, 1024 }, 2572 .hfront_porch = { 2, 2, 2 }, 2573 .hback_porch = { 2, 2, 2 }, 2574 .hsync_len = { 86, 124, 244 }, 2575 .vactive = { 768, 768, 768 }, 2576 .vfront_porch = { 2, 2, 2 }, 2577 .vback_porch = { 2, 2, 2 }, 2578 .vsync_len = { 6, 34, 73 }, 2579 .flags = DISPLAY_FLAGS_DE_HIGH, 2580}; 2581 2582static const struct panel_desc kyo_tcg121xglp = { 2583 .timings = &kyo_tcg121xglp_timing, 2584 .num_timings = 1, 2585 .bpc = 8, 2586 .size = { 2587 .width = 246, 2588 .height = 184, 2589 }, 2590 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2591 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2592}; 2593 2594static const struct drm_display_mode lemaker_bl035_rgb_002_mode = { 2595 .clock = 7000, 2596 .hdisplay = 320, 2597 .hsync_start = 320 + 20, 2598 .hsync_end = 320 + 20 + 30, 2599 .htotal = 320 + 20 + 30 + 38, 2600 .vdisplay = 240, 2601 .vsync_start = 240 + 4, 2602 .vsync_end = 240 + 4 + 3, 2603 .vtotal = 240 + 4 + 3 + 15, 2604}; 2605 2606static const struct panel_desc lemaker_bl035_rgb_002 = { 2607 .modes = &lemaker_bl035_rgb_002_mode, 2608 .num_modes = 1, 2609 .size = { 2610 .width = 70, 2611 .height = 52, 2612 }, 2613 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2614 .bus_flags = DRM_BUS_FLAG_DE_LOW, 2615}; 2616 2617static const struct drm_display_mode lg_lb070wv8_mode = { 2618 .clock = 33246, 2619 .hdisplay = 800, 2620 .hsync_start = 800 + 88, 2621 .hsync_end = 800 + 88 + 80, 2622 .htotal = 800 + 88 + 80 + 88, 2623 .vdisplay = 480, 2624 .vsync_start = 480 + 10, 2625 .vsync_end = 480 + 10 + 25, 2626 .vtotal = 480 + 10 + 25 + 10, 2627}; 2628 2629static const struct panel_desc lg_lb070wv8 = { 2630 .modes = &lg_lb070wv8_mode, 2631 .num_modes = 1, 2632 .bpc = 8, 2633 .size = { 2634 .width = 151, 2635 .height = 91, 2636 }, 2637 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2638 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2639}; 2640 2641static const struct display_timing logictechno_lt161010_2nh_timing = { 2642 .pixelclock = { 26400000, 33300000, 46800000 }, 2643 .hactive = { 800, 800, 800 }, 2644 .hfront_porch = { 16, 210, 354 }, 2645 .hback_porch = { 46, 46, 46 }, 2646 .hsync_len = { 1, 20, 40 }, 2647 .vactive = { 480, 480, 480 }, 2648 .vfront_porch = { 7, 22, 147 }, 2649 .vback_porch = { 23, 23, 23 }, 2650 .vsync_len = { 1, 10, 20 }, 2651 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2652 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2653 DISPLAY_FLAGS_SYNC_POSEDGE, 2654}; 2655 2656static const struct panel_desc logictechno_lt161010_2nh = { 2657 .timings = &logictechno_lt161010_2nh_timing, 2658 .num_timings = 1, 2659 .bpc = 6, 2660 .size = { 2661 .width = 154, 2662 .height = 86, 2663 }, 2664 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2665 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 2666 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2667 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 2668 .connector_type = DRM_MODE_CONNECTOR_DPI, 2669}; 2670 2671static const struct display_timing logictechno_lt170410_2whc_timing = { 2672 .pixelclock = { 68900000, 71100000, 73400000 }, 2673 .hactive = { 1280, 1280, 1280 }, 2674 .hfront_porch = { 23, 60, 71 }, 2675 .hback_porch = { 23, 60, 71 }, 2676 .hsync_len = { 15, 40, 47 }, 2677 .vactive = { 800, 800, 800 }, 2678 .vfront_porch = { 5, 7, 10 }, 2679 .vback_porch = { 5, 7, 10 }, 2680 .vsync_len = { 6, 9, 12 }, 2681 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2682 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2683 DISPLAY_FLAGS_SYNC_POSEDGE, 2684}; 2685 2686static const struct panel_desc logictechno_lt170410_2whc = { 2687 .timings = &logictechno_lt170410_2whc_timing, 2688 .num_timings = 1, 2689 .bpc = 8, 2690 .size = { 2691 .width = 217, 2692 .height = 136, 2693 }, 2694 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2695 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2696 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2697}; 2698 2699static const struct drm_display_mode logictechno_lttd800480070_l2rt_mode = { 2700 .clock = 33000, 2701 .hdisplay = 800, 2702 .hsync_start = 800 + 112, 2703 .hsync_end = 800 + 112 + 3, 2704 .htotal = 800 + 112 + 3 + 85, 2705 .vdisplay = 480, 2706 .vsync_start = 480 + 38, 2707 .vsync_end = 480 + 38 + 3, 2708 .vtotal = 480 + 38 + 3 + 29, 2709 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2710}; 2711 2712static const struct panel_desc logictechno_lttd800480070_l2rt = { 2713 .modes = &logictechno_lttd800480070_l2rt_mode, 2714 .num_modes = 1, 2715 .bpc = 8, 2716 .size = { 2717 .width = 154, 2718 .height = 86, 2719 }, 2720 .delay = { 2721 .prepare = 45, 2722 .enable = 100, 2723 .disable = 100, 2724 .unprepare = 45 2725 }, 2726 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2727 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2728 .connector_type = DRM_MODE_CONNECTOR_DPI, 2729}; 2730 2731static const struct drm_display_mode logictechno_lttd800480070_l6wh_rt_mode = { 2732 .clock = 33000, 2733 .hdisplay = 800, 2734 .hsync_start = 800 + 154, 2735 .hsync_end = 800 + 154 + 3, 2736 .htotal = 800 + 154 + 3 + 43, 2737 .vdisplay = 480, 2738 .vsync_start = 480 + 47, 2739 .vsync_end = 480 + 47 + 3, 2740 .vtotal = 480 + 47 + 3 + 20, 2741 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2742}; 2743 2744static const struct panel_desc logictechno_lttd800480070_l6wh_rt = { 2745 .modes = &logictechno_lttd800480070_l6wh_rt_mode, 2746 .num_modes = 1, 2747 .bpc = 8, 2748 .size = { 2749 .width = 154, 2750 .height = 86, 2751 }, 2752 .delay = { 2753 .prepare = 45, 2754 .enable = 100, 2755 .disable = 100, 2756 .unprepare = 45 2757 }, 2758 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2759 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2760 .connector_type = DRM_MODE_CONNECTOR_DPI, 2761}; 2762 2763static const struct drm_display_mode logicpd_type_28_mode = { 2764 .clock = 9107, 2765 .hdisplay = 480, 2766 .hsync_start = 480 + 3, 2767 .hsync_end = 480 + 3 + 42, 2768 .htotal = 480 + 3 + 42 + 2, 2769 2770 .vdisplay = 272, 2771 .vsync_start = 272 + 2, 2772 .vsync_end = 272 + 2 + 11, 2773 .vtotal = 272 + 2 + 11 + 3, 2774 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 2775}; 2776 2777static const struct panel_desc logicpd_type_28 = { 2778 .modes = &logicpd_type_28_mode, 2779 .num_modes = 1, 2780 .bpc = 8, 2781 .size = { 2782 .width = 105, 2783 .height = 67, 2784 }, 2785 .delay = { 2786 .prepare = 200, 2787 .enable = 200, 2788 .unprepare = 200, 2789 .disable = 200, 2790 }, 2791 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2792 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 2793 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE, 2794 .connector_type = DRM_MODE_CONNECTOR_DPI, 2795}; 2796 2797static const struct drm_display_mode mitsubishi_aa070mc01_mode = { 2798 .clock = 30400, 2799 .hdisplay = 800, 2800 .hsync_start = 800 + 0, 2801 .hsync_end = 800 + 1, 2802 .htotal = 800 + 0 + 1 + 160, 2803 .vdisplay = 480, 2804 .vsync_start = 480 + 0, 2805 .vsync_end = 480 + 48 + 1, 2806 .vtotal = 480 + 48 + 1 + 0, 2807 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2808}; 2809 2810static const struct panel_desc mitsubishi_aa070mc01 = { 2811 .modes = &mitsubishi_aa070mc01_mode, 2812 .num_modes = 1, 2813 .bpc = 8, 2814 .size = { 2815 .width = 152, 2816 .height = 91, 2817 }, 2818 2819 .delay = { 2820 .enable = 200, 2821 .unprepare = 200, 2822 .disable = 400, 2823 }, 2824 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2825 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2826 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2827}; 2828 2829static const struct display_timing multi_inno_mi0700s4t_6_timing = { 2830 .pixelclock = { 29000000, 33000000, 38000000 }, 2831 .hactive = { 800, 800, 800 }, 2832 .hfront_porch = { 180, 210, 240 }, 2833 .hback_porch = { 16, 16, 16 }, 2834 .hsync_len = { 30, 30, 30 }, 2835 .vactive = { 480, 480, 480 }, 2836 .vfront_porch = { 12, 22, 32 }, 2837 .vback_porch = { 10, 10, 10 }, 2838 .vsync_len = { 13, 13, 13 }, 2839 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2840 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2841 DISPLAY_FLAGS_SYNC_POSEDGE, 2842}; 2843 2844static const struct panel_desc multi_inno_mi0700s4t_6 = { 2845 .timings = &multi_inno_mi0700s4t_6_timing, 2846 .num_timings = 1, 2847 .bpc = 8, 2848 .size = { 2849 .width = 154, 2850 .height = 86, 2851 }, 2852 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2853 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 2854 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2855 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 2856 .connector_type = DRM_MODE_CONNECTOR_DPI, 2857}; 2858 2859static const struct display_timing multi_inno_mi0800ft_9_timing = { 2860 .pixelclock = { 32000000, 40000000, 50000000 }, 2861 .hactive = { 800, 800, 800 }, 2862 .hfront_porch = { 16, 210, 354 }, 2863 .hback_porch = { 6, 26, 45 }, 2864 .hsync_len = { 1, 20, 40 }, 2865 .vactive = { 600, 600, 600 }, 2866 .vfront_porch = { 1, 12, 77 }, 2867 .vback_porch = { 3, 13, 22 }, 2868 .vsync_len = { 1, 10, 20 }, 2869 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2870 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2871 DISPLAY_FLAGS_SYNC_POSEDGE, 2872}; 2873 2874static const struct panel_desc multi_inno_mi0800ft_9 = { 2875 .timings = &multi_inno_mi0800ft_9_timing, 2876 .num_timings = 1, 2877 .bpc = 8, 2878 .size = { 2879 .width = 162, 2880 .height = 122, 2881 }, 2882 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2883 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 2884 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2885 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 2886 .connector_type = DRM_MODE_CONNECTOR_DPI, 2887}; 2888 2889static const struct display_timing multi_inno_mi1010ait_1cp_timing = { 2890 .pixelclock = { 68900000, 70000000, 73400000 }, 2891 .hactive = { 1280, 1280, 1280 }, 2892 .hfront_porch = { 30, 60, 71 }, 2893 .hback_porch = { 30, 60, 71 }, 2894 .hsync_len = { 10, 10, 48 }, 2895 .vactive = { 800, 800, 800 }, 2896 .vfront_porch = { 5, 10, 10 }, 2897 .vback_porch = { 5, 10, 10 }, 2898 .vsync_len = { 5, 6, 13 }, 2899 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2900 DISPLAY_FLAGS_DE_HIGH, 2901}; 2902 2903static const struct panel_desc multi_inno_mi1010ait_1cp = { 2904 .timings = &multi_inno_mi1010ait_1cp_timing, 2905 .num_timings = 1, 2906 .bpc = 8, 2907 .size = { 2908 .width = 217, 2909 .height = 136, 2910 }, 2911 .delay = { 2912 .enable = 50, 2913 .disable = 50, 2914 }, 2915 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2916 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2917 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2918}; 2919 2920static const struct display_timing nec_nl12880bc20_05_timing = { 2921 .pixelclock = { 67000000, 71000000, 75000000 }, 2922 .hactive = { 1280, 1280, 1280 }, 2923 .hfront_porch = { 2, 30, 30 }, 2924 .hback_porch = { 6, 100, 100 }, 2925 .hsync_len = { 2, 30, 30 }, 2926 .vactive = { 800, 800, 800 }, 2927 .vfront_porch = { 5, 5, 5 }, 2928 .vback_porch = { 11, 11, 11 }, 2929 .vsync_len = { 7, 7, 7 }, 2930}; 2931 2932static const struct panel_desc nec_nl12880bc20_05 = { 2933 .timings = &nec_nl12880bc20_05_timing, 2934 .num_timings = 1, 2935 .bpc = 8, 2936 .size = { 2937 .width = 261, 2938 .height = 163, 2939 }, 2940 .delay = { 2941 .enable = 50, 2942 .disable = 50, 2943 }, 2944 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2945 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2946}; 2947 2948static const struct drm_display_mode nec_nl4827hc19_05b_mode = { 2949 .clock = 10870, 2950 .hdisplay = 480, 2951 .hsync_start = 480 + 2, 2952 .hsync_end = 480 + 2 + 41, 2953 .htotal = 480 + 2 + 41 + 2, 2954 .vdisplay = 272, 2955 .vsync_start = 272 + 2, 2956 .vsync_end = 272 + 2 + 4, 2957 .vtotal = 272 + 2 + 4 + 2, 2958 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2959}; 2960 2961static const struct panel_desc nec_nl4827hc19_05b = { 2962 .modes = &nec_nl4827hc19_05b_mode, 2963 .num_modes = 1, 2964 .bpc = 8, 2965 .size = { 2966 .width = 95, 2967 .height = 54, 2968 }, 2969 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2970 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2971}; 2972 2973static const struct drm_display_mode netron_dy_e231732_mode = { 2974 .clock = 66000, 2975 .hdisplay = 1024, 2976 .hsync_start = 1024 + 160, 2977 .hsync_end = 1024 + 160 + 70, 2978 .htotal = 1024 + 160 + 70 + 90, 2979 .vdisplay = 600, 2980 .vsync_start = 600 + 127, 2981 .vsync_end = 600 + 127 + 20, 2982 .vtotal = 600 + 127 + 20 + 3, 2983}; 2984 2985static const struct panel_desc netron_dy_e231732 = { 2986 .modes = &netron_dy_e231732_mode, 2987 .num_modes = 1, 2988 .size = { 2989 .width = 154, 2990 .height = 87, 2991 }, 2992 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2993}; 2994 2995static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = { 2996 .clock = 9000, 2997 .hdisplay = 480, 2998 .hsync_start = 480 + 2, 2999 .hsync_end = 480 + 2 + 41, 3000 .htotal = 480 + 2 + 41 + 2, 3001 .vdisplay = 272, 3002 .vsync_start = 272 + 2, 3003 .vsync_end = 272 + 2 + 10, 3004 .vtotal = 272 + 2 + 10 + 2, 3005 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3006}; 3007 3008static const struct panel_desc newhaven_nhd_43_480272ef_atxl = { 3009 .modes = &newhaven_nhd_43_480272ef_atxl_mode, 3010 .num_modes = 1, 3011 .bpc = 8, 3012 .size = { 3013 .width = 95, 3014 .height = 54, 3015 }, 3016 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3017 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3018 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3019 .connector_type = DRM_MODE_CONNECTOR_DPI, 3020}; 3021 3022static const struct display_timing nlt_nl192108ac18_02d_timing = { 3023 .pixelclock = { 130000000, 148350000, 163000000 }, 3024 .hactive = { 1920, 1920, 1920 }, 3025 .hfront_porch = { 80, 100, 100 }, 3026 .hback_porch = { 100, 120, 120 }, 3027 .hsync_len = { 50, 60, 60 }, 3028 .vactive = { 1080, 1080, 1080 }, 3029 .vfront_porch = { 12, 30, 30 }, 3030 .vback_porch = { 4, 10, 10 }, 3031 .vsync_len = { 4, 5, 5 }, 3032}; 3033 3034static const struct panel_desc nlt_nl192108ac18_02d = { 3035 .timings = &nlt_nl192108ac18_02d_timing, 3036 .num_timings = 1, 3037 .bpc = 8, 3038 .size = { 3039 .width = 344, 3040 .height = 194, 3041 }, 3042 .delay = { 3043 .unprepare = 500, 3044 }, 3045 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3046 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3047}; 3048 3049static const struct drm_display_mode nvd_9128_mode = { 3050 .clock = 29500, 3051 .hdisplay = 800, 3052 .hsync_start = 800 + 130, 3053 .hsync_end = 800 + 130 + 98, 3054 .htotal = 800 + 0 + 130 + 98, 3055 .vdisplay = 480, 3056 .vsync_start = 480 + 10, 3057 .vsync_end = 480 + 10 + 50, 3058 .vtotal = 480 + 0 + 10 + 50, 3059}; 3060 3061static const struct panel_desc nvd_9128 = { 3062 .modes = &nvd_9128_mode, 3063 .num_modes = 1, 3064 .bpc = 8, 3065 .size = { 3066 .width = 156, 3067 .height = 88, 3068 }, 3069 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3070 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3071}; 3072 3073static const struct display_timing okaya_rs800480t_7x0gp_timing = { 3074 .pixelclock = { 30000000, 30000000, 40000000 }, 3075 .hactive = { 800, 800, 800 }, 3076 .hfront_porch = { 40, 40, 40 }, 3077 .hback_porch = { 40, 40, 40 }, 3078 .hsync_len = { 1, 48, 48 }, 3079 .vactive = { 480, 480, 480 }, 3080 .vfront_porch = { 13, 13, 13 }, 3081 .vback_porch = { 29, 29, 29 }, 3082 .vsync_len = { 3, 3, 3 }, 3083 .flags = DISPLAY_FLAGS_DE_HIGH, 3084}; 3085 3086static const struct panel_desc okaya_rs800480t_7x0gp = { 3087 .timings = &okaya_rs800480t_7x0gp_timing, 3088 .num_timings = 1, 3089 .bpc = 6, 3090 .size = { 3091 .width = 154, 3092 .height = 87, 3093 }, 3094 .delay = { 3095 .prepare = 41, 3096 .enable = 50, 3097 .unprepare = 41, 3098 .disable = 50, 3099 }, 3100 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3101}; 3102 3103static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = { 3104 .clock = 9000, 3105 .hdisplay = 480, 3106 .hsync_start = 480 + 5, 3107 .hsync_end = 480 + 5 + 30, 3108 .htotal = 480 + 5 + 30 + 10, 3109 .vdisplay = 272, 3110 .vsync_start = 272 + 8, 3111 .vsync_end = 272 + 8 + 5, 3112 .vtotal = 272 + 8 + 5 + 3, 3113}; 3114 3115static const struct panel_desc olimex_lcd_olinuxino_43ts = { 3116 .modes = &olimex_lcd_olinuxino_43ts_mode, 3117 .num_modes = 1, 3118 .size = { 3119 .width = 95, 3120 .height = 54, 3121 }, 3122 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3123}; 3124 3125/* 3126 * 800x480 CVT. The panel appears to be quite accepting, at least as far as 3127 * pixel clocks, but this is the timing that was being used in the Adafruit 3128 * installation instructions. 3129 */ 3130static const struct drm_display_mode ontat_yx700wv03_mode = { 3131 .clock = 29500, 3132 .hdisplay = 800, 3133 .hsync_start = 824, 3134 .hsync_end = 896, 3135 .htotal = 992, 3136 .vdisplay = 480, 3137 .vsync_start = 483, 3138 .vsync_end = 493, 3139 .vtotal = 500, 3140 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3141}; 3142 3143/* 3144 * Specification at: 3145 * https://www.adafruit.com/images/product-files/2406/c3163.pdf 3146 */ 3147static const struct panel_desc ontat_yx700wv03 = { 3148 .modes = &ontat_yx700wv03_mode, 3149 .num_modes = 1, 3150 .bpc = 8, 3151 .size = { 3152 .width = 154, 3153 .height = 83, 3154 }, 3155 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3156}; 3157 3158static const struct drm_display_mode ortustech_com37h3m_mode = { 3159 .clock = 22230, 3160 .hdisplay = 480, 3161 .hsync_start = 480 + 40, 3162 .hsync_end = 480 + 40 + 10, 3163 .htotal = 480 + 40 + 10 + 40, 3164 .vdisplay = 640, 3165 .vsync_start = 640 + 4, 3166 .vsync_end = 640 + 4 + 2, 3167 .vtotal = 640 + 4 + 2 + 4, 3168 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3169}; 3170 3171static const struct panel_desc ortustech_com37h3m = { 3172 .modes = &ortustech_com37h3m_mode, 3173 .num_modes = 1, 3174 .bpc = 8, 3175 .size = { 3176 .width = 56, /* 56.16mm */ 3177 .height = 75, /* 74.88mm */ 3178 }, 3179 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3180 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3181 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3182}; 3183 3184static const struct drm_display_mode ortustech_com43h4m85ulc_mode = { 3185 .clock = 25000, 3186 .hdisplay = 480, 3187 .hsync_start = 480 + 10, 3188 .hsync_end = 480 + 10 + 10, 3189 .htotal = 480 + 10 + 10 + 15, 3190 .vdisplay = 800, 3191 .vsync_start = 800 + 3, 3192 .vsync_end = 800 + 3 + 3, 3193 .vtotal = 800 + 3 + 3 + 3, 3194}; 3195 3196static const struct panel_desc ortustech_com43h4m85ulc = { 3197 .modes = &ortustech_com43h4m85ulc_mode, 3198 .num_modes = 1, 3199 .bpc = 6, 3200 .size = { 3201 .width = 56, 3202 .height = 93, 3203 }, 3204 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3205 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3206 .connector_type = DRM_MODE_CONNECTOR_DPI, 3207}; 3208 3209static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = { 3210 .clock = 33000, 3211 .hdisplay = 800, 3212 .hsync_start = 800 + 210, 3213 .hsync_end = 800 + 210 + 30, 3214 .htotal = 800 + 210 + 30 + 16, 3215 .vdisplay = 480, 3216 .vsync_start = 480 + 22, 3217 .vsync_end = 480 + 22 + 13, 3218 .vtotal = 480 + 22 + 13 + 10, 3219 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3220}; 3221 3222static const struct panel_desc osddisplays_osd070t1718_19ts = { 3223 .modes = &osddisplays_osd070t1718_19ts_mode, 3224 .num_modes = 1, 3225 .bpc = 8, 3226 .size = { 3227 .width = 152, 3228 .height = 91, 3229 }, 3230 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3231 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3232 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3233 .connector_type = DRM_MODE_CONNECTOR_DPI, 3234}; 3235 3236static const struct drm_display_mode pda_91_00156_a0_mode = { 3237 .clock = 33300, 3238 .hdisplay = 800, 3239 .hsync_start = 800 + 1, 3240 .hsync_end = 800 + 1 + 64, 3241 .htotal = 800 + 1 + 64 + 64, 3242 .vdisplay = 480, 3243 .vsync_start = 480 + 1, 3244 .vsync_end = 480 + 1 + 23, 3245 .vtotal = 480 + 1 + 23 + 22, 3246}; 3247 3248static const struct panel_desc pda_91_00156_a0 = { 3249 .modes = &pda_91_00156_a0_mode, 3250 .num_modes = 1, 3251 .size = { 3252 .width = 152, 3253 .height = 91, 3254 }, 3255 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3256}; 3257 3258static const struct drm_display_mode powertip_ph800480t013_idf02_mode = { 3259 .clock = 24750, 3260 .hdisplay = 800, 3261 .hsync_start = 800 + 54, 3262 .hsync_end = 800 + 54 + 2, 3263 .htotal = 800 + 54 + 2 + 44, 3264 .vdisplay = 480, 3265 .vsync_start = 480 + 49, 3266 .vsync_end = 480 + 49 + 2, 3267 .vtotal = 480 + 49 + 2 + 22, 3268 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3269}; 3270 3271static const struct panel_desc powertip_ph800480t013_idf02 = { 3272 .modes = &powertip_ph800480t013_idf02_mode, 3273 .num_modes = 1, 3274 .bpc = 8, 3275 .size = { 3276 .width = 152, 3277 .height = 91, 3278 }, 3279 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3280 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3281 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3282 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3283 .connector_type = DRM_MODE_CONNECTOR_DPI, 3284}; 3285 3286static const struct drm_display_mode qd43003c0_40_mode = { 3287 .clock = 9000, 3288 .hdisplay = 480, 3289 .hsync_start = 480 + 8, 3290 .hsync_end = 480 + 8 + 4, 3291 .htotal = 480 + 8 + 4 + 39, 3292 .vdisplay = 272, 3293 .vsync_start = 272 + 4, 3294 .vsync_end = 272 + 4 + 10, 3295 .vtotal = 272 + 4 + 10 + 2, 3296}; 3297 3298static const struct panel_desc qd43003c0_40 = { 3299 .modes = &qd43003c0_40_mode, 3300 .num_modes = 1, 3301 .bpc = 8, 3302 .size = { 3303 .width = 95, 3304 .height = 53, 3305 }, 3306 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3307}; 3308 3309static const struct drm_display_mode qishenglong_gopher2b_lcd_modes[] = { 3310 { /* 60 Hz */ 3311 .clock = 10800, 3312 .hdisplay = 480, 3313 .hsync_start = 480 + 77, 3314 .hsync_end = 480 + 77 + 41, 3315 .htotal = 480 + 77 + 41 + 2, 3316 .vdisplay = 272, 3317 .vsync_start = 272 + 16, 3318 .vsync_end = 272 + 16 + 10, 3319 .vtotal = 272 + 16 + 10 + 2, 3320 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3321 }, 3322 { /* 50 Hz */ 3323 .clock = 10800, 3324 .hdisplay = 480, 3325 .hsync_start = 480 + 17, 3326 .hsync_end = 480 + 17 + 41, 3327 .htotal = 480 + 17 + 41 + 2, 3328 .vdisplay = 272, 3329 .vsync_start = 272 + 116, 3330 .vsync_end = 272 + 116 + 10, 3331 .vtotal = 272 + 116 + 10 + 2, 3332 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3333 }, 3334}; 3335 3336static const struct panel_desc qishenglong_gopher2b_lcd = { 3337 .modes = qishenglong_gopher2b_lcd_modes, 3338 .num_modes = ARRAY_SIZE(qishenglong_gopher2b_lcd_modes), 3339 .bpc = 8, 3340 .size = { 3341 .width = 95, 3342 .height = 54, 3343 }, 3344 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3345 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3346 .connector_type = DRM_MODE_CONNECTOR_DPI, 3347}; 3348 3349static const struct display_timing rocktech_rk043fn48h_timing = { 3350 .pixelclock = { 6000000, 9000000, 12000000 }, 3351 .hactive = { 480, 480, 480 }, 3352 .hback_porch = { 8, 43, 43 }, 3353 .hfront_porch = { 2, 8, 8 }, 3354 .hsync_len = { 1, 1, 1 }, 3355 .vactive = { 272, 272, 272 }, 3356 .vback_porch = { 2, 12, 12 }, 3357 .vfront_porch = { 1, 4, 4 }, 3358 .vsync_len = { 1, 10, 10 }, 3359 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW | 3360 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 3361}; 3362 3363static const struct panel_desc rocktech_rk043fn48h = { 3364 .timings = &rocktech_rk043fn48h_timing, 3365 .num_timings = 1, 3366 .bpc = 8, 3367 .size = { 3368 .width = 95, 3369 .height = 54, 3370 }, 3371 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3372 .connector_type = DRM_MODE_CONNECTOR_DPI, 3373}; 3374 3375static const struct display_timing rocktech_rk070er9427_timing = { 3376 .pixelclock = { 26400000, 33300000, 46800000 }, 3377 .hactive = { 800, 800, 800 }, 3378 .hfront_porch = { 16, 210, 354 }, 3379 .hback_porch = { 46, 46, 46 }, 3380 .hsync_len = { 1, 1, 1 }, 3381 .vactive = { 480, 480, 480 }, 3382 .vfront_porch = { 7, 22, 147 }, 3383 .vback_porch = { 23, 23, 23 }, 3384 .vsync_len = { 1, 1, 1 }, 3385 .flags = DISPLAY_FLAGS_DE_HIGH, 3386}; 3387 3388static const struct panel_desc rocktech_rk070er9427 = { 3389 .timings = &rocktech_rk070er9427_timing, 3390 .num_timings = 1, 3391 .bpc = 6, 3392 .size = { 3393 .width = 154, 3394 .height = 86, 3395 }, 3396 .delay = { 3397 .prepare = 41, 3398 .enable = 50, 3399 .unprepare = 41, 3400 .disable = 50, 3401 }, 3402 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3403}; 3404 3405static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = { 3406 .clock = 71100, 3407 .hdisplay = 1280, 3408 .hsync_start = 1280 + 48, 3409 .hsync_end = 1280 + 48 + 32, 3410 .htotal = 1280 + 48 + 32 + 80, 3411 .vdisplay = 800, 3412 .vsync_start = 800 + 2, 3413 .vsync_end = 800 + 2 + 5, 3414 .vtotal = 800 + 2 + 5 + 16, 3415}; 3416 3417static const struct panel_desc rocktech_rk101ii01d_ct = { 3418 .modes = &rocktech_rk101ii01d_ct_mode, 3419 .bpc = 8, 3420 .num_modes = 1, 3421 .size = { 3422 .width = 217, 3423 .height = 136, 3424 }, 3425 .delay = { 3426 .prepare = 50, 3427 .disable = 50, 3428 }, 3429 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3430 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3431 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3432}; 3433 3434static const struct display_timing samsung_ltl101al01_timing = { 3435 .pixelclock = { 66663000, 66663000, 66663000 }, 3436 .hactive = { 1280, 1280, 1280 }, 3437 .hfront_porch = { 18, 18, 18 }, 3438 .hback_porch = { 36, 36, 36 }, 3439 .hsync_len = { 16, 16, 16 }, 3440 .vactive = { 800, 800, 800 }, 3441 .vfront_porch = { 4, 4, 4 }, 3442 .vback_porch = { 16, 16, 16 }, 3443 .vsync_len = { 3, 3, 3 }, 3444 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 3445}; 3446 3447static const struct panel_desc samsung_ltl101al01 = { 3448 .timings = &samsung_ltl101al01_timing, 3449 .num_timings = 1, 3450 .bpc = 8, 3451 .size = { 3452 .width = 217, 3453 .height = 135, 3454 }, 3455 .delay = { 3456 .prepare = 40, 3457 .enable = 300, 3458 .disable = 200, 3459 .unprepare = 600, 3460 }, 3461 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3462 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3463}; 3464 3465static const struct drm_display_mode samsung_ltn101nt05_mode = { 3466 .clock = 54030, 3467 .hdisplay = 1024, 3468 .hsync_start = 1024 + 24, 3469 .hsync_end = 1024 + 24 + 136, 3470 .htotal = 1024 + 24 + 136 + 160, 3471 .vdisplay = 600, 3472 .vsync_start = 600 + 3, 3473 .vsync_end = 600 + 3 + 6, 3474 .vtotal = 600 + 3 + 6 + 61, 3475}; 3476 3477static const struct panel_desc samsung_ltn101nt05 = { 3478 .modes = &samsung_ltn101nt05_mode, 3479 .num_modes = 1, 3480 .bpc = 6, 3481 .size = { 3482 .width = 223, 3483 .height = 125, 3484 }, 3485 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3486 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3487 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3488}; 3489 3490static const struct display_timing satoz_sat050at40h12r2_timing = { 3491 .pixelclock = {33300000, 33300000, 50000000}, 3492 .hactive = {800, 800, 800}, 3493 .hfront_porch = {16, 210, 354}, 3494 .hback_porch = {46, 46, 46}, 3495 .hsync_len = {1, 1, 40}, 3496 .vactive = {480, 480, 480}, 3497 .vfront_porch = {7, 22, 147}, 3498 .vback_porch = {23, 23, 23}, 3499 .vsync_len = {1, 1, 20}, 3500}; 3501 3502static const struct panel_desc satoz_sat050at40h12r2 = { 3503 .timings = &satoz_sat050at40h12r2_timing, 3504 .num_timings = 1, 3505 .bpc = 8, 3506 .size = { 3507 .width = 108, 3508 .height = 65, 3509 }, 3510 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3511 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3512}; 3513 3514static const struct drm_display_mode sharp_lq070y3dg3b_mode = { 3515 .clock = 33260, 3516 .hdisplay = 800, 3517 .hsync_start = 800 + 64, 3518 .hsync_end = 800 + 64 + 128, 3519 .htotal = 800 + 64 + 128 + 64, 3520 .vdisplay = 480, 3521 .vsync_start = 480 + 8, 3522 .vsync_end = 480 + 8 + 2, 3523 .vtotal = 480 + 8 + 2 + 35, 3524 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 3525}; 3526 3527static const struct panel_desc sharp_lq070y3dg3b = { 3528 .modes = &sharp_lq070y3dg3b_mode, 3529 .num_modes = 1, 3530 .bpc = 8, 3531 .size = { 3532 .width = 152, /* 152.4mm */ 3533 .height = 91, /* 91.4mm */ 3534 }, 3535 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3536 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3537 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3538}; 3539 3540static const struct drm_display_mode sharp_lq035q7db03_mode = { 3541 .clock = 5500, 3542 .hdisplay = 240, 3543 .hsync_start = 240 + 16, 3544 .hsync_end = 240 + 16 + 7, 3545 .htotal = 240 + 16 + 7 + 5, 3546 .vdisplay = 320, 3547 .vsync_start = 320 + 9, 3548 .vsync_end = 320 + 9 + 1, 3549 .vtotal = 320 + 9 + 1 + 7, 3550}; 3551 3552static const struct panel_desc sharp_lq035q7db03 = { 3553 .modes = &sharp_lq035q7db03_mode, 3554 .num_modes = 1, 3555 .bpc = 6, 3556 .size = { 3557 .width = 54, 3558 .height = 72, 3559 }, 3560 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3561}; 3562 3563static const struct display_timing sharp_lq101k1ly04_timing = { 3564 .pixelclock = { 60000000, 65000000, 80000000 }, 3565 .hactive = { 1280, 1280, 1280 }, 3566 .hfront_porch = { 20, 20, 20 }, 3567 .hback_porch = { 20, 20, 20 }, 3568 .hsync_len = { 10, 10, 10 }, 3569 .vactive = { 800, 800, 800 }, 3570 .vfront_porch = { 4, 4, 4 }, 3571 .vback_porch = { 4, 4, 4 }, 3572 .vsync_len = { 4, 4, 4 }, 3573 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 3574}; 3575 3576static const struct panel_desc sharp_lq101k1ly04 = { 3577 .timings = &sharp_lq101k1ly04_timing, 3578 .num_timings = 1, 3579 .bpc = 8, 3580 .size = { 3581 .width = 217, 3582 .height = 136, 3583 }, 3584 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 3585 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3586}; 3587 3588static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = { 3589 { /* 50 Hz */ 3590 .clock = 3000, 3591 .hdisplay = 240, 3592 .hsync_start = 240 + 58, 3593 .hsync_end = 240 + 58 + 1, 3594 .htotal = 240 + 58 + 1 + 1, 3595 .vdisplay = 160, 3596 .vsync_start = 160 + 24, 3597 .vsync_end = 160 + 24 + 10, 3598 .vtotal = 160 + 24 + 10 + 6, 3599 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 3600 }, 3601 { /* 60 Hz */ 3602 .clock = 3000, 3603 .hdisplay = 240, 3604 .hsync_start = 240 + 8, 3605 .hsync_end = 240 + 8 + 1, 3606 .htotal = 240 + 8 + 1 + 1, 3607 .vdisplay = 160, 3608 .vsync_start = 160 + 24, 3609 .vsync_end = 160 + 24 + 10, 3610 .vtotal = 160 + 24 + 10 + 6, 3611 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 3612 }, 3613}; 3614 3615static const struct panel_desc sharp_ls020b1dd01d = { 3616 .modes = sharp_ls020b1dd01d_modes, 3617 .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes), 3618 .bpc = 6, 3619 .size = { 3620 .width = 42, 3621 .height = 28, 3622 }, 3623 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 3624 .bus_flags = DRM_BUS_FLAG_DE_HIGH 3625 | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE 3626 | DRM_BUS_FLAG_SHARP_SIGNALS, 3627}; 3628 3629static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = { 3630 .clock = 33300, 3631 .hdisplay = 800, 3632 .hsync_start = 800 + 1, 3633 .hsync_end = 800 + 1 + 64, 3634 .htotal = 800 + 1 + 64 + 64, 3635 .vdisplay = 480, 3636 .vsync_start = 480 + 1, 3637 .vsync_end = 480 + 1 + 23, 3638 .vtotal = 480 + 1 + 23 + 22, 3639}; 3640 3641static const struct panel_desc shelly_sca07010_bfn_lnn = { 3642 .modes = &shelly_sca07010_bfn_lnn_mode, 3643 .num_modes = 1, 3644 .size = { 3645 .width = 152, 3646 .height = 91, 3647 }, 3648 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3649}; 3650 3651static const struct drm_display_mode starry_kr070pe2t_mode = { 3652 .clock = 33000, 3653 .hdisplay = 800, 3654 .hsync_start = 800 + 209, 3655 .hsync_end = 800 + 209 + 1, 3656 .htotal = 800 + 209 + 1 + 45, 3657 .vdisplay = 480, 3658 .vsync_start = 480 + 22, 3659 .vsync_end = 480 + 22 + 1, 3660 .vtotal = 480 + 22 + 1 + 22, 3661}; 3662 3663static const struct panel_desc starry_kr070pe2t = { 3664 .modes = &starry_kr070pe2t_mode, 3665 .num_modes = 1, 3666 .bpc = 8, 3667 .size = { 3668 .width = 152, 3669 .height = 86, 3670 }, 3671 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3672 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 3673 .connector_type = DRM_MODE_CONNECTOR_DPI, 3674}; 3675 3676static const struct display_timing startek_kd070wvfpa_mode = { 3677 .pixelclock = { 25200000, 27200000, 30500000 }, 3678 .hactive = { 800, 800, 800 }, 3679 .hfront_porch = { 19, 44, 115 }, 3680 .hback_porch = { 5, 16, 101 }, 3681 .hsync_len = { 1, 2, 100 }, 3682 .vactive = { 480, 480, 480 }, 3683 .vfront_porch = { 5, 43, 67 }, 3684 .vback_porch = { 5, 5, 67 }, 3685 .vsync_len = { 1, 2, 66 }, 3686 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3687 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3688 DISPLAY_FLAGS_SYNC_POSEDGE, 3689}; 3690 3691static const struct panel_desc startek_kd070wvfpa = { 3692 .timings = &startek_kd070wvfpa_mode, 3693 .num_timings = 1, 3694 .bpc = 8, 3695 .size = { 3696 .width = 152, 3697 .height = 91, 3698 }, 3699 .delay = { 3700 .prepare = 20, 3701 .enable = 200, 3702 .disable = 200, 3703 }, 3704 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3705 .connector_type = DRM_MODE_CONNECTOR_DPI, 3706 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3707 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3708 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3709}; 3710 3711static const struct display_timing tsd_tst043015cmhx_timing = { 3712 .pixelclock = { 5000000, 9000000, 12000000 }, 3713 .hactive = { 480, 480, 480 }, 3714 .hfront_porch = { 4, 5, 65 }, 3715 .hback_porch = { 36, 40, 255 }, 3716 .hsync_len = { 1, 1, 1 }, 3717 .vactive = { 272, 272, 272 }, 3718 .vfront_porch = { 2, 8, 97 }, 3719 .vback_porch = { 3, 8, 31 }, 3720 .vsync_len = { 1, 1, 1 }, 3721 3722 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3723 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 3724}; 3725 3726static const struct panel_desc tsd_tst043015cmhx = { 3727 .timings = &tsd_tst043015cmhx_timing, 3728 .num_timings = 1, 3729 .bpc = 8, 3730 .size = { 3731 .width = 105, 3732 .height = 67, 3733 }, 3734 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3735 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3736}; 3737 3738static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = { 3739 .clock = 30000, 3740 .hdisplay = 800, 3741 .hsync_start = 800 + 39, 3742 .hsync_end = 800 + 39 + 47, 3743 .htotal = 800 + 39 + 47 + 39, 3744 .vdisplay = 480, 3745 .vsync_start = 480 + 13, 3746 .vsync_end = 480 + 13 + 2, 3747 .vtotal = 480 + 13 + 2 + 29, 3748}; 3749 3750static const struct panel_desc tfc_s9700rtwv43tr_01b = { 3751 .modes = &tfc_s9700rtwv43tr_01b_mode, 3752 .num_modes = 1, 3753 .bpc = 8, 3754 .size = { 3755 .width = 155, 3756 .height = 90, 3757 }, 3758 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3759 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3760}; 3761 3762static const struct display_timing tianma_tm070jdhg30_timing = { 3763 .pixelclock = { 62600000, 68200000, 78100000 }, 3764 .hactive = { 1280, 1280, 1280 }, 3765 .hfront_porch = { 15, 64, 159 }, 3766 .hback_porch = { 5, 5, 5 }, 3767 .hsync_len = { 1, 1, 256 }, 3768 .vactive = { 800, 800, 800 }, 3769 .vfront_porch = { 3, 40, 99 }, 3770 .vback_porch = { 2, 2, 2 }, 3771 .vsync_len = { 1, 1, 128 }, 3772 .flags = DISPLAY_FLAGS_DE_HIGH, 3773}; 3774 3775static const struct panel_desc tianma_tm070jdhg30 = { 3776 .timings = &tianma_tm070jdhg30_timing, 3777 .num_timings = 1, 3778 .bpc = 8, 3779 .size = { 3780 .width = 151, 3781 .height = 95, 3782 }, 3783 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3784 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3785 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3786}; 3787 3788static const struct panel_desc tianma_tm070jvhg33 = { 3789 .timings = &tianma_tm070jdhg30_timing, 3790 .num_timings = 1, 3791 .bpc = 8, 3792 .size = { 3793 .width = 150, 3794 .height = 94, 3795 }, 3796 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3797 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3798 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3799}; 3800 3801static const struct display_timing tianma_tm070rvhg71_timing = { 3802 .pixelclock = { 27700000, 29200000, 39600000 }, 3803 .hactive = { 800, 800, 800 }, 3804 .hfront_porch = { 12, 40, 212 }, 3805 .hback_porch = { 88, 88, 88 }, 3806 .hsync_len = { 1, 1, 40 }, 3807 .vactive = { 480, 480, 480 }, 3808 .vfront_porch = { 1, 13, 88 }, 3809 .vback_porch = { 32, 32, 32 }, 3810 .vsync_len = { 1, 1, 3 }, 3811 .flags = DISPLAY_FLAGS_DE_HIGH, 3812}; 3813 3814static const struct panel_desc tianma_tm070rvhg71 = { 3815 .timings = &tianma_tm070rvhg71_timing, 3816 .num_timings = 1, 3817 .bpc = 8, 3818 .size = { 3819 .width = 154, 3820 .height = 86, 3821 }, 3822 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3823 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3824}; 3825 3826static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = { 3827 { 3828 .clock = 10000, 3829 .hdisplay = 320, 3830 .hsync_start = 320 + 50, 3831 .hsync_end = 320 + 50 + 6, 3832 .htotal = 320 + 50 + 6 + 38, 3833 .vdisplay = 240, 3834 .vsync_start = 240 + 3, 3835 .vsync_end = 240 + 3 + 1, 3836 .vtotal = 240 + 3 + 1 + 17, 3837 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3838 }, 3839}; 3840 3841static const struct panel_desc ti_nspire_cx_lcd_panel = { 3842 .modes = ti_nspire_cx_lcd_mode, 3843 .num_modes = 1, 3844 .bpc = 8, 3845 .size = { 3846 .width = 65, 3847 .height = 49, 3848 }, 3849 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3850 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 3851}; 3852 3853static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = { 3854 { 3855 .clock = 10000, 3856 .hdisplay = 320, 3857 .hsync_start = 320 + 6, 3858 .hsync_end = 320 + 6 + 6, 3859 .htotal = 320 + 6 + 6 + 6, 3860 .vdisplay = 240, 3861 .vsync_start = 240 + 0, 3862 .vsync_end = 240 + 0 + 1, 3863 .vtotal = 240 + 0 + 1 + 0, 3864 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3865 }, 3866}; 3867 3868static const struct panel_desc ti_nspire_classic_lcd_panel = { 3869 .modes = ti_nspire_classic_lcd_mode, 3870 .num_modes = 1, 3871 /* The grayscale panel has 8 bit for the color .. Y (black) */ 3872 .bpc = 8, 3873 .size = { 3874 .width = 71, 3875 .height = 53, 3876 }, 3877 /* This is the grayscale bus format */ 3878 .bus_format = MEDIA_BUS_FMT_Y8_1X8, 3879 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3880}; 3881 3882static const struct drm_display_mode toshiba_lt089ac29000_mode = { 3883 .clock = 79500, 3884 .hdisplay = 1280, 3885 .hsync_start = 1280 + 192, 3886 .hsync_end = 1280 + 192 + 128, 3887 .htotal = 1280 + 192 + 128 + 64, 3888 .vdisplay = 768, 3889 .vsync_start = 768 + 20, 3890 .vsync_end = 768 + 20 + 7, 3891 .vtotal = 768 + 20 + 7 + 3, 3892}; 3893 3894static const struct panel_desc toshiba_lt089ac29000 = { 3895 .modes = &toshiba_lt089ac29000_mode, 3896 .num_modes = 1, 3897 .size = { 3898 .width = 194, 3899 .height = 116, 3900 }, 3901 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 3902 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3903 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3904}; 3905 3906static const struct drm_display_mode tpk_f07a_0102_mode = { 3907 .clock = 33260, 3908 .hdisplay = 800, 3909 .hsync_start = 800 + 40, 3910 .hsync_end = 800 + 40 + 128, 3911 .htotal = 800 + 40 + 128 + 88, 3912 .vdisplay = 480, 3913 .vsync_start = 480 + 10, 3914 .vsync_end = 480 + 10 + 2, 3915 .vtotal = 480 + 10 + 2 + 33, 3916}; 3917 3918static const struct panel_desc tpk_f07a_0102 = { 3919 .modes = &tpk_f07a_0102_mode, 3920 .num_modes = 1, 3921 .size = { 3922 .width = 152, 3923 .height = 91, 3924 }, 3925 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3926}; 3927 3928static const struct drm_display_mode tpk_f10a_0102_mode = { 3929 .clock = 45000, 3930 .hdisplay = 1024, 3931 .hsync_start = 1024 + 176, 3932 .hsync_end = 1024 + 176 + 5, 3933 .htotal = 1024 + 176 + 5 + 88, 3934 .vdisplay = 600, 3935 .vsync_start = 600 + 20, 3936 .vsync_end = 600 + 20 + 5, 3937 .vtotal = 600 + 20 + 5 + 25, 3938}; 3939 3940static const struct panel_desc tpk_f10a_0102 = { 3941 .modes = &tpk_f10a_0102_mode, 3942 .num_modes = 1, 3943 .size = { 3944 .width = 223, 3945 .height = 125, 3946 }, 3947}; 3948 3949static const struct display_timing urt_umsh_8596md_timing = { 3950 .pixelclock = { 33260000, 33260000, 33260000 }, 3951 .hactive = { 800, 800, 800 }, 3952 .hfront_porch = { 41, 41, 41 }, 3953 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 }, 3954 .hsync_len = { 71, 128, 128 }, 3955 .vactive = { 480, 480, 480 }, 3956 .vfront_porch = { 10, 10, 10 }, 3957 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 }, 3958 .vsync_len = { 2, 2, 2 }, 3959 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 3960 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 3961}; 3962 3963static const struct panel_desc urt_umsh_8596md_lvds = { 3964 .timings = &urt_umsh_8596md_timing, 3965 .num_timings = 1, 3966 .bpc = 6, 3967 .size = { 3968 .width = 152, 3969 .height = 91, 3970 }, 3971 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3972 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3973}; 3974 3975static const struct panel_desc urt_umsh_8596md_parallel = { 3976 .timings = &urt_umsh_8596md_timing, 3977 .num_timings = 1, 3978 .bpc = 6, 3979 .size = { 3980 .width = 152, 3981 .height = 91, 3982 }, 3983 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3984}; 3985 3986static const struct drm_display_mode vivax_tpc9150_panel_mode = { 3987 .clock = 60000, 3988 .hdisplay = 1024, 3989 .hsync_start = 1024 + 160, 3990 .hsync_end = 1024 + 160 + 100, 3991 .htotal = 1024 + 160 + 100 + 60, 3992 .vdisplay = 600, 3993 .vsync_start = 600 + 12, 3994 .vsync_end = 600 + 12 + 10, 3995 .vtotal = 600 + 12 + 10 + 13, 3996}; 3997 3998static const struct panel_desc vivax_tpc9150_panel = { 3999 .modes = &vivax_tpc9150_panel_mode, 4000 .num_modes = 1, 4001 .bpc = 6, 4002 .size = { 4003 .width = 200, 4004 .height = 115, 4005 }, 4006 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 4007 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4008 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4009}; 4010 4011static const struct drm_display_mode vl050_8048nt_c01_mode = { 4012 .clock = 33333, 4013 .hdisplay = 800, 4014 .hsync_start = 800 + 210, 4015 .hsync_end = 800 + 210 + 20, 4016 .htotal = 800 + 210 + 20 + 46, 4017 .vdisplay = 480, 4018 .vsync_start = 480 + 22, 4019 .vsync_end = 480 + 22 + 10, 4020 .vtotal = 480 + 22 + 10 + 23, 4021 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 4022}; 4023 4024static const struct panel_desc vl050_8048nt_c01 = { 4025 .modes = &vl050_8048nt_c01_mode, 4026 .num_modes = 1, 4027 .bpc = 8, 4028 .size = { 4029 .width = 120, 4030 .height = 76, 4031 }, 4032 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4033 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4034}; 4035 4036static const struct drm_display_mode winstar_wf35ltiacd_mode = { 4037 .clock = 6410, 4038 .hdisplay = 320, 4039 .hsync_start = 320 + 20, 4040 .hsync_end = 320 + 20 + 30, 4041 .htotal = 320 + 20 + 30 + 38, 4042 .vdisplay = 240, 4043 .vsync_start = 240 + 4, 4044 .vsync_end = 240 + 4 + 3, 4045 .vtotal = 240 + 4 + 3 + 15, 4046 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4047}; 4048 4049static const struct panel_desc winstar_wf35ltiacd = { 4050 .modes = &winstar_wf35ltiacd_mode, 4051 .num_modes = 1, 4052 .bpc = 8, 4053 .size = { 4054 .width = 70, 4055 .height = 53, 4056 }, 4057 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4058}; 4059 4060static const struct drm_display_mode yes_optoelectronics_ytc700tlag_05_201c_mode = { 4061 .clock = 51200, 4062 .hdisplay = 1024, 4063 .hsync_start = 1024 + 100, 4064 .hsync_end = 1024 + 100 + 100, 4065 .htotal = 1024 + 100 + 100 + 120, 4066 .vdisplay = 600, 4067 .vsync_start = 600 + 10, 4068 .vsync_end = 600 + 10 + 10, 4069 .vtotal = 600 + 10 + 10 + 15, 4070 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 4071}; 4072 4073static const struct panel_desc yes_optoelectronics_ytc700tlag_05_201c = { 4074 .modes = &yes_optoelectronics_ytc700tlag_05_201c_mode, 4075 .num_modes = 1, 4076 .bpc = 8, 4077 .size = { 4078 .width = 154, 4079 .height = 90, 4080 }, 4081 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4082 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4083 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4084}; 4085 4086static const struct drm_display_mode arm_rtsm_mode[] = { 4087 { 4088 .clock = 65000, 4089 .hdisplay = 1024, 4090 .hsync_start = 1024 + 24, 4091 .hsync_end = 1024 + 24 + 136, 4092 .htotal = 1024 + 24 + 136 + 160, 4093 .vdisplay = 768, 4094 .vsync_start = 768 + 3, 4095 .vsync_end = 768 + 3 + 6, 4096 .vtotal = 768 + 3 + 6 + 29, 4097 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4098 }, 4099}; 4100 4101static const struct panel_desc arm_rtsm = { 4102 .modes = arm_rtsm_mode, 4103 .num_modes = 1, 4104 .bpc = 8, 4105 .size = { 4106 .width = 400, 4107 .height = 300, 4108 }, 4109 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4110}; 4111 4112static const struct of_device_id platform_of_match[] = { 4113 { 4114 .compatible = "ampire,am-1280800n3tzqw-t00h", 4115 .data = &ire_am_1280800n3tzqw_t00h, 4116 }, { 4117 .compatible = "ampire,am-480272h3tmqw-t01h", 4118 .data = &ire_am_480272h3tmqw_t01h, 4119 }, { 4120 .compatible = "ampire,am-800480l1tmqw-t00h", 4121 .data = &ire_am_800480l1tmqw_t00h, 4122 }, { 4123 .compatible = "ampire,am800480r3tmqwa1h", 4124 .data = &ire_am800480r3tmqwa1h, 4125 }, { 4126 .compatible = "ampire,am800600p5tmqw-tb8h", 4127 .data = &ire_am800600p5tmqwtb8h, 4128 }, { 4129 .compatible = "arm,rtsm-display", 4130 .data = &arm_rtsm, 4131 }, { 4132 .compatible = "armadeus,st0700-adapt", 4133 .data = &armadeus_st0700_adapt, 4134 }, { 4135 .compatible = "auo,b101aw03", 4136 .data = &auo_b101aw03, 4137 }, { 4138 .compatible = "auo,b101xtn01", 4139 .data = &auo_b101xtn01, 4140 }, { 4141 .compatible = "auo,b116xw03", 4142 .data = &auo_b116xw03, 4143 }, { 4144 .compatible = "auo,g070vvn01", 4145 .data = &auo_g070vvn01, 4146 }, { 4147 .compatible = "auo,g101evn010", 4148 .data = &auo_g101evn010, 4149 }, { 4150 .compatible = "auo,g104sn02", 4151 .data = &auo_g104sn02, 4152 }, { 4153 .compatible = "auo,g121ean01", 4154 .data = &auo_g121ean01, 4155 }, { 4156 .compatible = "auo,g133han01", 4157 .data = &auo_g133han01, 4158 }, { 4159 .compatible = "auo,g156xtn01", 4160 .data = &auo_g156xtn01, 4161 }, { 4162 .compatible = "auo,g185han01", 4163 .data = &auo_g185han01, 4164 }, { 4165 .compatible = "auo,g190ean01", 4166 .data = &auo_g190ean01, 4167 }, { 4168 .compatible = "auo,p320hvn03", 4169 .data = &auo_p320hvn03, 4170 }, { 4171 .compatible = "auo,t215hvn01", 4172 .data = &auo_t215hvn01, 4173 }, { 4174 .compatible = "avic,tm070ddh03", 4175 .data = &avic_tm070ddh03, 4176 }, { 4177 .compatible = "bananapi,s070wv20-ct16", 4178 .data = &bananapi_s070wv20_ct16, 4179 }, { 4180 .compatible = "boe,ev121wxm-n10-1850", 4181 .data = &boe_ev121wxm_n10_1850, 4182 }, { 4183 .compatible = "boe,hv070wsa-100", 4184 .data = &boe_hv070wsa 4185 }, { 4186 .compatible = "cdtech,s043wq26h-ct7", 4187 .data = &cdtech_s043wq26h_ct7, 4188 }, { 4189 .compatible = "cdtech,s070pws19hp-fc21", 4190 .data = &cdtech_s070pws19hp_fc21, 4191 }, { 4192 .compatible = "cdtech,s070swv29hg-dc44", 4193 .data = &cdtech_s070swv29hg_dc44, 4194 }, { 4195 .compatible = "cdtech,s070wv95-ct16", 4196 .data = &cdtech_s070wv95_ct16, 4197 }, { 4198 .compatible = "chefree,ch101olhlwh-002", 4199 .data = &chefree_ch101olhlwh_002, 4200 }, { 4201 .compatible = "chunghwa,claa070wp03xg", 4202 .data = &chunghwa_claa070wp03xg, 4203 }, { 4204 .compatible = "chunghwa,claa101wa01a", 4205 .data = &chunghwa_claa101wa01a 4206 }, { 4207 .compatible = "chunghwa,claa101wb01", 4208 .data = &chunghwa_claa101wb01 4209 }, { 4210 .compatible = "dataimage,fg040346dsswbg04", 4211 .data = &dataimage_fg040346dsswbg04, 4212 }, { 4213 .compatible = "dataimage,fg1001l0dsswmg01", 4214 .data = &dataimage_fg1001l0dsswmg01, 4215 }, { 4216 .compatible = "dataimage,scf0700c48ggu18", 4217 .data = &dataimage_scf0700c48ggu18, 4218 }, { 4219 .compatible = "dlc,dlc0700yzg-1", 4220 .data = &dlc_dlc0700yzg_1, 4221 }, { 4222 .compatible = "dlc,dlc1010gig", 4223 .data = &dlc_dlc1010gig, 4224 }, { 4225 .compatible = "edt,et035012dm6", 4226 .data = &edt_et035012dm6, 4227 }, { 4228 .compatible = "edt,etm0350g0dh6", 4229 .data = &edt_etm0350g0dh6, 4230 }, { 4231 .compatible = "edt,etm043080dh6gp", 4232 .data = &edt_etm043080dh6gp, 4233 }, { 4234 .compatible = "edt,etm0430g0dh6", 4235 .data = &edt_etm0430g0dh6, 4236 }, { 4237 .compatible = "edt,et057090dhu", 4238 .data = &edt_et057090dhu, 4239 }, { 4240 .compatible = "edt,et070080dh6", 4241 .data = &edt_etm0700g0dh6, 4242 }, { 4243 .compatible = "edt,etm0700g0dh6", 4244 .data = &edt_etm0700g0dh6, 4245 }, { 4246 .compatible = "edt,etm0700g0bdh6", 4247 .data = &edt_etm0700g0bdh6, 4248 }, { 4249 .compatible = "edt,etm0700g0edh6", 4250 .data = &edt_etm0700g0bdh6, 4251 }, { 4252 .compatible = "edt,etml0700y5dha", 4253 .data = &edt_etml0700y5dha, 4254 }, { 4255 .compatible = "edt,etmv570g2dhu", 4256 .data = &edt_etmv570g2dhu, 4257 }, { 4258 .compatible = "eink,vb3300-kca", 4259 .data = &eink_vb3300_kca, 4260 }, { 4261 .compatible = "evervision,vgg804821", 4262 .data = &evervision_vgg804821, 4263 }, { 4264 .compatible = "foxlink,fl500wvr00-a0t", 4265 .data = &foxlink_fl500wvr00_a0t, 4266 }, { 4267 .compatible = "frida,frd350h54004", 4268 .data = &frida_frd350h54004, 4269 }, { 4270 .compatible = "friendlyarm,hd702e", 4271 .data = &friendlyarm_hd702e, 4272 }, { 4273 .compatible = "giantplus,gpg482739qs5", 4274 .data = &giantplus_gpg482739qs5 4275 }, { 4276 .compatible = "giantplus,gpm940b0", 4277 .data = &giantplus_gpm940b0, 4278 }, { 4279 .compatible = "hannstar,hsd070pww1", 4280 .data = &hannstar_hsd070pww1, 4281 }, { 4282 .compatible = "hannstar,hsd100pxn1", 4283 .data = &hannstar_hsd100pxn1, 4284 }, { 4285 .compatible = "hannstar,hsd101pww2", 4286 .data = &hannstar_hsd101pww2, 4287 }, { 4288 .compatible = "hit,tx23d38vm0caa", 4289 .data = &hitachi_tx23d38vm0caa 4290 }, { 4291 .compatible = "innolux,at043tn24", 4292 .data = &innolux_at043tn24, 4293 }, { 4294 .compatible = "innolux,at070tn92", 4295 .data = &innolux_at070tn92, 4296 }, { 4297 .compatible = "innolux,g070ace-l01", 4298 .data = &innolux_g070ace_l01, 4299 }, { 4300 .compatible = "innolux,g070y2-l01", 4301 .data = &innolux_g070y2_l01, 4302 }, { 4303 .compatible = "innolux,g070y2-t02", 4304 .data = &innolux_g070y2_t02, 4305 }, { 4306 .compatible = "innolux,g101ice-l01", 4307 .data = &innolux_g101ice_l01 4308 }, { 4309 .compatible = "innolux,g121i1-l01", 4310 .data = &innolux_g121i1_l01 4311 }, { 4312 .compatible = "innolux,g121x1-l03", 4313 .data = &innolux_g121x1_l03, 4314 }, { 4315 .compatible = "innolux,g156hce-l01", 4316 .data = &innolux_g156hce_l01, 4317 }, { 4318 .compatible = "innolux,n156bge-l21", 4319 .data = &innolux_n156bge_l21, 4320 }, { 4321 .compatible = "innolux,zj070na-01p", 4322 .data = &innolux_zj070na_01p, 4323 }, { 4324 .compatible = "koe,tx14d24vm1bpa", 4325 .data = &koe_tx14d24vm1bpa, 4326 }, { 4327 .compatible = "koe,tx26d202vm0bwa", 4328 .data = &koe_tx26d202vm0bwa, 4329 }, { 4330 .compatible = "koe,tx31d200vm0baa", 4331 .data = &koe_tx31d200vm0baa, 4332 }, { 4333 .compatible = "kyo,tcg121xglp", 4334 .data = &kyo_tcg121xglp, 4335 }, { 4336 .compatible = "lemaker,bl035-rgb-002", 4337 .data = &lemaker_bl035_rgb_002, 4338 }, { 4339 .compatible = "lg,lb070wv8", 4340 .data = &lg_lb070wv8, 4341 }, { 4342 .compatible = "logicpd,type28", 4343 .data = &logicpd_type_28, 4344 }, { 4345 .compatible = "logictechno,lt161010-2nhc", 4346 .data = &logictechno_lt161010_2nh, 4347 }, { 4348 .compatible = "logictechno,lt161010-2nhr", 4349 .data = &logictechno_lt161010_2nh, 4350 }, { 4351 .compatible = "logictechno,lt170410-2whc", 4352 .data = &logictechno_lt170410_2whc, 4353 }, { 4354 .compatible = "logictechno,lttd800480070-l2rt", 4355 .data = &logictechno_lttd800480070_l2rt, 4356 }, { 4357 .compatible = "logictechno,lttd800480070-l6wh-rt", 4358 .data = &logictechno_lttd800480070_l6wh_rt, 4359 }, { 4360 .compatible = "mitsubishi,aa070mc01-ca1", 4361 .data = &mitsubishi_aa070mc01, 4362 }, { 4363 .compatible = "multi-inno,mi0700s4t-6", 4364 .data = &multi_inno_mi0700s4t_6, 4365 }, { 4366 .compatible = "multi-inno,mi0800ft-9", 4367 .data = &multi_inno_mi0800ft_9, 4368 }, { 4369 .compatible = "multi-inno,mi1010ait-1cp", 4370 .data = &multi_inno_mi1010ait_1cp, 4371 }, { 4372 .compatible = "nec,nl12880bc20-05", 4373 .data = &nec_nl12880bc20_05, 4374 }, { 4375 .compatible = "nec,nl4827hc19-05b", 4376 .data = &nec_nl4827hc19_05b, 4377 }, { 4378 .compatible = "netron-dy,e231732", 4379 .data = &netron_dy_e231732, 4380 }, { 4381 .compatible = "newhaven,nhd-4.3-480272ef-atxl", 4382 .data = &newhaven_nhd_43_480272ef_atxl, 4383 }, { 4384 .compatible = "nlt,nl192108ac18-02d", 4385 .data = &nlt_nl192108ac18_02d, 4386 }, { 4387 .compatible = "nvd,9128", 4388 .data = &nvd_9128, 4389 }, { 4390 .compatible = "okaya,rs800480t-7x0gp", 4391 .data = &okaya_rs800480t_7x0gp, 4392 }, { 4393 .compatible = "olimex,lcd-olinuxino-43-ts", 4394 .data = &olimex_lcd_olinuxino_43ts, 4395 }, { 4396 .compatible = "ontat,yx700wv03", 4397 .data = &ontat_yx700wv03, 4398 }, { 4399 .compatible = "ortustech,com37h3m05dtc", 4400 .data = &ortustech_com37h3m, 4401 }, { 4402 .compatible = "ortustech,com37h3m99dtc", 4403 .data = &ortustech_com37h3m, 4404 }, { 4405 .compatible = "ortustech,com43h4m85ulc", 4406 .data = &ortustech_com43h4m85ulc, 4407 }, { 4408 .compatible = "osddisplays,osd070t1718-19ts", 4409 .data = &osddisplays_osd070t1718_19ts, 4410 }, { 4411 .compatible = "pda,91-00156-a0", 4412 .data = &pda_91_00156_a0, 4413 }, { 4414 .compatible = "powertip,ph800480t013-idf02", 4415 .data = &powertip_ph800480t013_idf02, 4416 }, { 4417 .compatible = "qiaodian,qd43003c0-40", 4418 .data = &qd43003c0_40, 4419 }, { 4420 .compatible = "qishenglong,gopher2b-lcd", 4421 .data = &qishenglong_gopher2b_lcd, 4422 }, { 4423 .compatible = "rocktech,rk043fn48h", 4424 .data = &rocktech_rk043fn48h, 4425 }, { 4426 .compatible = "rocktech,rk070er9427", 4427 .data = &rocktech_rk070er9427, 4428 }, { 4429 .compatible = "rocktech,rk101ii01d-ct", 4430 .data = &rocktech_rk101ii01d_ct, 4431 }, { 4432 .compatible = "samsung,ltl101al01", 4433 .data = &samsung_ltl101al01, 4434 }, { 4435 .compatible = "samsung,ltn101nt05", 4436 .data = &samsung_ltn101nt05, 4437 }, { 4438 .compatible = "satoz,sat050at40h12r2", 4439 .data = &satoz_sat050at40h12r2, 4440 }, { 4441 .compatible = "sharp,lq035q7db03", 4442 .data = &sharp_lq035q7db03, 4443 }, { 4444 .compatible = "sharp,lq070y3dg3b", 4445 .data = &sharp_lq070y3dg3b, 4446 }, { 4447 .compatible = "sharp,lq101k1ly04", 4448 .data = &sharp_lq101k1ly04, 4449 }, { 4450 .compatible = "sharp,ls020b1dd01d", 4451 .data = &sharp_ls020b1dd01d, 4452 }, { 4453 .compatible = "shelly,sca07010-bfn-lnn", 4454 .data = &shelly_sca07010_bfn_lnn, 4455 }, { 4456 .compatible = "starry,kr070pe2t", 4457 .data = &starry_kr070pe2t, 4458 }, { 4459 .compatible = "startek,kd070wvfpa", 4460 .data = &startek_kd070wvfpa, 4461 }, { 4462 .compatible = "team-source-display,tst043015cmhx", 4463 .data = &tsd_tst043015cmhx, 4464 }, { 4465 .compatible = "tfc,s9700rtwv43tr-01b", 4466 .data = &tfc_s9700rtwv43tr_01b, 4467 }, { 4468 .compatible = "tianma,tm070jdhg30", 4469 .data = &tianma_tm070jdhg30, 4470 }, { 4471 .compatible = "tianma,tm070jvhg33", 4472 .data = &tianma_tm070jvhg33, 4473 }, { 4474 .compatible = "tianma,tm070rvhg71", 4475 .data = &tianma_tm070rvhg71, 4476 }, { 4477 .compatible = "ti,nspire-cx-lcd-panel", 4478 .data = &ti_nspire_cx_lcd_panel, 4479 }, { 4480 .compatible = "ti,nspire-classic-lcd-panel", 4481 .data = &ti_nspire_classic_lcd_panel, 4482 }, { 4483 .compatible = "toshiba,lt089ac29000", 4484 .data = &toshiba_lt089ac29000, 4485 }, { 4486 .compatible = "tpk,f07a-0102", 4487 .data = &tpk_f07a_0102, 4488 }, { 4489 .compatible = "tpk,f10a-0102", 4490 .data = &tpk_f10a_0102, 4491 }, { 4492 .compatible = "urt,umsh-8596md-t", 4493 .data = &urt_umsh_8596md_parallel, 4494 }, { 4495 .compatible = "urt,umsh-8596md-1t", 4496 .data = &urt_umsh_8596md_parallel, 4497 }, { 4498 .compatible = "urt,umsh-8596md-7t", 4499 .data = &urt_umsh_8596md_parallel, 4500 }, { 4501 .compatible = "urt,umsh-8596md-11t", 4502 .data = &urt_umsh_8596md_lvds, 4503 }, { 4504 .compatible = "urt,umsh-8596md-19t", 4505 .data = &urt_umsh_8596md_lvds, 4506 }, { 4507 .compatible = "urt,umsh-8596md-20t", 4508 .data = &urt_umsh_8596md_parallel, 4509 }, { 4510 .compatible = "vivax,tpc9150-panel", 4511 .data = &vivax_tpc9150_panel, 4512 }, { 4513 .compatible = "vxt,vl050-8048nt-c01", 4514 .data = &vl050_8048nt_c01, 4515 }, { 4516 .compatible = "winstar,wf35ltiacd", 4517 .data = &winstar_wf35ltiacd, 4518 }, { 4519 .compatible = "yes-optoelectronics,ytc700tlag-05-201c", 4520 .data = &yes_optoelectronics_ytc700tlag_05_201c, 4521 }, { 4522 /* Must be the last entry */ 4523 .compatible = "panel-dpi", 4524 .data = &panel_dpi, 4525 }, { 4526 /* sentinel */ 4527 } 4528}; 4529MODULE_DEVICE_TABLE(of, platform_of_match); 4530 4531static int panel_simple_platform_probe(struct platform_device *pdev) 4532{ 4533 const struct panel_desc *desc; 4534 4535 desc = of_device_get_match_data(&pdev->dev); 4536 if (!desc) 4537 return -ENODEV; 4538 4539 return panel_simple_probe(&pdev->dev, desc); 4540} 4541 4542static void panel_simple_platform_remove(struct platform_device *pdev) 4543{ 4544 panel_simple_remove(&pdev->dev); 4545} 4546 4547static void panel_simple_platform_shutdown(struct platform_device *pdev) 4548{ 4549 panel_simple_shutdown(&pdev->dev); 4550} 4551 4552static const struct dev_pm_ops panel_simple_pm_ops = { 4553 SET_RUNTIME_PM_OPS(panel_simple_suspend, panel_simple_resume, NULL) 4554 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 4555 pm_runtime_force_resume) 4556}; 4557 4558static struct platform_driver panel_simple_platform_driver = { 4559 .driver = { 4560 .name = "panel-simple", 4561 .of_match_table = platform_of_match, 4562 .pm = &panel_simple_pm_ops, 4563 }, 4564 .probe = panel_simple_platform_probe, 4565 .remove_new = panel_simple_platform_remove, 4566 .shutdown = panel_simple_platform_shutdown, 4567}; 4568 4569struct panel_desc_dsi { 4570 struct panel_desc desc; 4571 4572 unsigned long flags; 4573 enum mipi_dsi_pixel_format format; 4574 unsigned int lanes; 4575}; 4576 4577static const struct drm_display_mode auo_b080uan01_mode = { 4578 .clock = 154500, 4579 .hdisplay = 1200, 4580 .hsync_start = 1200 + 62, 4581 .hsync_end = 1200 + 62 + 4, 4582 .htotal = 1200 + 62 + 4 + 62, 4583 .vdisplay = 1920, 4584 .vsync_start = 1920 + 9, 4585 .vsync_end = 1920 + 9 + 2, 4586 .vtotal = 1920 + 9 + 2 + 8, 4587}; 4588 4589static const struct panel_desc_dsi auo_b080uan01 = { 4590 .desc = { 4591 .modes = &auo_b080uan01_mode, 4592 .num_modes = 1, 4593 .bpc = 8, 4594 .size = { 4595 .width = 108, 4596 .height = 272, 4597 }, 4598 .connector_type = DRM_MODE_CONNECTOR_DSI, 4599 }, 4600 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 4601 .format = MIPI_DSI_FMT_RGB888, 4602 .lanes = 4, 4603}; 4604 4605static const struct drm_display_mode boe_tv080wum_nl0_mode = { 4606 .clock = 160000, 4607 .hdisplay = 1200, 4608 .hsync_start = 1200 + 120, 4609 .hsync_end = 1200 + 120 + 20, 4610 .htotal = 1200 + 120 + 20 + 21, 4611 .vdisplay = 1920, 4612 .vsync_start = 1920 + 21, 4613 .vsync_end = 1920 + 21 + 3, 4614 .vtotal = 1920 + 21 + 3 + 18, 4615 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4616}; 4617 4618static const struct panel_desc_dsi boe_tv080wum_nl0 = { 4619 .desc = { 4620 .modes = &boe_tv080wum_nl0_mode, 4621 .num_modes = 1, 4622 .size = { 4623 .width = 107, 4624 .height = 172, 4625 }, 4626 .connector_type = DRM_MODE_CONNECTOR_DSI, 4627 }, 4628 .flags = MIPI_DSI_MODE_VIDEO | 4629 MIPI_DSI_MODE_VIDEO_BURST | 4630 MIPI_DSI_MODE_VIDEO_SYNC_PULSE, 4631 .format = MIPI_DSI_FMT_RGB888, 4632 .lanes = 4, 4633}; 4634 4635static const struct drm_display_mode lg_ld070wx3_sl01_mode = { 4636 .clock = 71000, 4637 .hdisplay = 800, 4638 .hsync_start = 800 + 32, 4639 .hsync_end = 800 + 32 + 1, 4640 .htotal = 800 + 32 + 1 + 57, 4641 .vdisplay = 1280, 4642 .vsync_start = 1280 + 28, 4643 .vsync_end = 1280 + 28 + 1, 4644 .vtotal = 1280 + 28 + 1 + 14, 4645}; 4646 4647static const struct panel_desc_dsi lg_ld070wx3_sl01 = { 4648 .desc = { 4649 .modes = &lg_ld070wx3_sl01_mode, 4650 .num_modes = 1, 4651 .bpc = 8, 4652 .size = { 4653 .width = 94, 4654 .height = 151, 4655 }, 4656 .connector_type = DRM_MODE_CONNECTOR_DSI, 4657 }, 4658 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 4659 .format = MIPI_DSI_FMT_RGB888, 4660 .lanes = 4, 4661}; 4662 4663static const struct drm_display_mode lg_lh500wx1_sd03_mode = { 4664 .clock = 67000, 4665 .hdisplay = 720, 4666 .hsync_start = 720 + 12, 4667 .hsync_end = 720 + 12 + 4, 4668 .htotal = 720 + 12 + 4 + 112, 4669 .vdisplay = 1280, 4670 .vsync_start = 1280 + 8, 4671 .vsync_end = 1280 + 8 + 4, 4672 .vtotal = 1280 + 8 + 4 + 12, 4673}; 4674 4675static const struct panel_desc_dsi lg_lh500wx1_sd03 = { 4676 .desc = { 4677 .modes = &lg_lh500wx1_sd03_mode, 4678 .num_modes = 1, 4679 .bpc = 8, 4680 .size = { 4681 .width = 62, 4682 .height = 110, 4683 }, 4684 .connector_type = DRM_MODE_CONNECTOR_DSI, 4685 }, 4686 .flags = MIPI_DSI_MODE_VIDEO, 4687 .format = MIPI_DSI_FMT_RGB888, 4688 .lanes = 4, 4689}; 4690 4691static const struct drm_display_mode panasonic_vvx10f004b00_mode = { 4692 .clock = 157200, 4693 .hdisplay = 1920, 4694 .hsync_start = 1920 + 154, 4695 .hsync_end = 1920 + 154 + 16, 4696 .htotal = 1920 + 154 + 16 + 32, 4697 .vdisplay = 1200, 4698 .vsync_start = 1200 + 17, 4699 .vsync_end = 1200 + 17 + 2, 4700 .vtotal = 1200 + 17 + 2 + 16, 4701}; 4702 4703static const struct panel_desc_dsi panasonic_vvx10f004b00 = { 4704 .desc = { 4705 .modes = &panasonic_vvx10f004b00_mode, 4706 .num_modes = 1, 4707 .bpc = 8, 4708 .size = { 4709 .width = 217, 4710 .height = 136, 4711 }, 4712 .connector_type = DRM_MODE_CONNECTOR_DSI, 4713 }, 4714 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 4715 MIPI_DSI_CLOCK_NON_CONTINUOUS, 4716 .format = MIPI_DSI_FMT_RGB888, 4717 .lanes = 4, 4718}; 4719 4720static const struct drm_display_mode lg_acx467akm_7_mode = { 4721 .clock = 150000, 4722 .hdisplay = 1080, 4723 .hsync_start = 1080 + 2, 4724 .hsync_end = 1080 + 2 + 2, 4725 .htotal = 1080 + 2 + 2 + 2, 4726 .vdisplay = 1920, 4727 .vsync_start = 1920 + 2, 4728 .vsync_end = 1920 + 2 + 2, 4729 .vtotal = 1920 + 2 + 2 + 2, 4730}; 4731 4732static const struct panel_desc_dsi lg_acx467akm_7 = { 4733 .desc = { 4734 .modes = &lg_acx467akm_7_mode, 4735 .num_modes = 1, 4736 .bpc = 8, 4737 .size = { 4738 .width = 62, 4739 .height = 110, 4740 }, 4741 .connector_type = DRM_MODE_CONNECTOR_DSI, 4742 }, 4743 .flags = 0, 4744 .format = MIPI_DSI_FMT_RGB888, 4745 .lanes = 4, 4746}; 4747 4748static const struct drm_display_mode osd101t2045_53ts_mode = { 4749 .clock = 154500, 4750 .hdisplay = 1920, 4751 .hsync_start = 1920 + 112, 4752 .hsync_end = 1920 + 112 + 16, 4753 .htotal = 1920 + 112 + 16 + 32, 4754 .vdisplay = 1200, 4755 .vsync_start = 1200 + 16, 4756 .vsync_end = 1200 + 16 + 2, 4757 .vtotal = 1200 + 16 + 2 + 16, 4758 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 4759}; 4760 4761static const struct panel_desc_dsi osd101t2045_53ts = { 4762 .desc = { 4763 .modes = &osd101t2045_53ts_mode, 4764 .num_modes = 1, 4765 .bpc = 8, 4766 .size = { 4767 .width = 217, 4768 .height = 136, 4769 }, 4770 .connector_type = DRM_MODE_CONNECTOR_DSI, 4771 }, 4772 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 4773 MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 4774 MIPI_DSI_MODE_NO_EOT_PACKET, 4775 .format = MIPI_DSI_FMT_RGB888, 4776 .lanes = 4, 4777}; 4778 4779static const struct of_device_id dsi_of_match[] = { 4780 { 4781 .compatible = "auo,b080uan01", 4782 .data = &auo_b080uan01 4783 }, { 4784 .compatible = "boe,tv080wum-nl0", 4785 .data = &boe_tv080wum_nl0 4786 }, { 4787 .compatible = "lg,ld070wx3-sl01", 4788 .data = &lg_ld070wx3_sl01 4789 }, { 4790 .compatible = "lg,lh500wx1-sd03", 4791 .data = &lg_lh500wx1_sd03 4792 }, { 4793 .compatible = "panasonic,vvx10f004b00", 4794 .data = &panasonic_vvx10f004b00 4795 }, { 4796 .compatible = "lg,acx467akm-7", 4797 .data = &lg_acx467akm_7 4798 }, { 4799 .compatible = "osddisplays,osd101t2045-53ts", 4800 .data = &osd101t2045_53ts 4801 }, { 4802 /* sentinel */ 4803 } 4804}; 4805MODULE_DEVICE_TABLE(of, dsi_of_match); 4806 4807static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi) 4808{ 4809 const struct panel_desc_dsi *desc; 4810 int err; 4811 4812 desc = of_device_get_match_data(&dsi->dev); 4813 if (!desc) 4814 return -ENODEV; 4815 4816 err = panel_simple_probe(&dsi->dev, &desc->desc); 4817 if (err < 0) 4818 return err; 4819 4820 dsi->mode_flags = desc->flags; 4821 dsi->format = desc->format; 4822 dsi->lanes = desc->lanes; 4823 4824 err = mipi_dsi_attach(dsi); 4825 if (err) { 4826 struct panel_simple *panel = mipi_dsi_get_drvdata(dsi); 4827 4828 drm_panel_remove(&panel->base); 4829 } 4830 4831 return err; 4832} 4833 4834static void panel_simple_dsi_remove(struct mipi_dsi_device *dsi) 4835{ 4836 int err; 4837 4838 err = mipi_dsi_detach(dsi); 4839 if (err < 0) 4840 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err); 4841 4842 panel_simple_remove(&dsi->dev); 4843} 4844 4845static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi) 4846{ 4847 panel_simple_shutdown(&dsi->dev); 4848} 4849 4850static struct mipi_dsi_driver panel_simple_dsi_driver = { 4851 .driver = { 4852 .name = "panel-simple-dsi", 4853 .of_match_table = dsi_of_match, 4854 .pm = &panel_simple_pm_ops, 4855 }, 4856 .probe = panel_simple_dsi_probe, 4857 .remove = panel_simple_dsi_remove, 4858 .shutdown = panel_simple_dsi_shutdown, 4859}; 4860 4861static int __init panel_simple_init(void) 4862{ 4863 int err; 4864 4865 err = platform_driver_register(&panel_simple_platform_driver); 4866 if (err < 0) 4867 return err; 4868 4869 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) { 4870 err = mipi_dsi_driver_register(&panel_simple_dsi_driver); 4871 if (err < 0) 4872 goto err_did_platform_register; 4873 } 4874 4875 return 0; 4876 4877err_did_platform_register: 4878 platform_driver_unregister(&panel_simple_platform_driver); 4879 4880 return err; 4881} 4882module_init(panel_simple_init); 4883 4884static void __exit panel_simple_exit(void) 4885{ 4886 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) 4887 mipi_dsi_driver_unregister(&panel_simple_dsi_driver); 4888 4889 platform_driver_unregister(&panel_simple_platform_driver); 4890} 4891module_exit(panel_simple_exit); 4892 4893MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 4894MODULE_DESCRIPTION("DRM Driver for Simple Panels"); 4895MODULE_LICENSE("GPL and additional rights"); 4896