1// SPDX-License-Identifier: GPL-2.0
2/*
3 * NewVision NV3052C IPS LCD panel driver
4 *
5 * Copyright (C) 2020, Paul Cercueil <paul@crapouillou.net>
6 * Copyright (C) 2022, Christophe Branchereau <cbranchereau@gmail.com>
7 */
8
9#include <linux/delay.h>
10#include <linux/device.h>
11#include <linux/gpio/consumer.h>
12#include <linux/media-bus-format.h>
13#include <linux/module.h>
14#include <linux/of.h>
15#include <linux/platform_device.h>
16#include <linux/regulator/consumer.h>
17#include <linux/spi/spi.h>
18#include <video/mipi_display.h>
19#include <drm/drm_mipi_dbi.h>
20#include <drm/drm_modes.h>
21#include <drm/drm_panel.h>
22
23struct nv3052c_panel_info {
24	const struct drm_display_mode *display_modes;
25	unsigned int num_modes;
26	u16 width_mm, height_mm;
27	u32 bus_format, bus_flags;
28};
29
30struct nv3052c {
31	struct device *dev;
32	struct drm_panel panel;
33	struct mipi_dbi dbi;
34	const struct nv3052c_panel_info *panel_info;
35	struct regulator *supply;
36	struct gpio_desc *reset_gpio;
37};
38
39struct nv3052c_reg {
40	u8 cmd;
41	u8 val;
42};
43
44static const struct nv3052c_reg nv3052c_panel_regs[] = {
45	{ 0xff, 0x30 },
46	{ 0xff, 0x52 },
47	{ 0xff, 0x01 },
48	{ 0xe3, 0x00 },
49	{ 0x40, 0x00 },
50	{ 0x03, 0x40 },
51	{ 0x04, 0x00 },
52	{ 0x05, 0x03 },
53	{ 0x08, 0x00 },
54	{ 0x09, 0x07 },
55	{ 0x0a, 0x01 },
56	{ 0x0b, 0x32 },
57	{ 0x0c, 0x32 },
58	{ 0x0d, 0x0b },
59	{ 0x0e, 0x00 },
60	{ 0x23, 0xa0 },
61	{ 0x24, 0x0c },
62	{ 0x25, 0x06 },
63	{ 0x26, 0x14 },
64	{ 0x27, 0x14 },
65	{ 0x38, 0xcc },
66	{ 0x39, 0xd7 },
67	{ 0x3a, 0x4a },
68	{ 0x28, 0x40 },
69	{ 0x29, 0x01 },
70	{ 0x2a, 0xdf },
71	{ 0x49, 0x3c },
72	{ 0x91, 0x77 },
73	{ 0x92, 0x77 },
74	{ 0xa0, 0x55 },
75	{ 0xa1, 0x50 },
76	{ 0xa4, 0x9c },
77	{ 0xa7, 0x02 },
78	{ 0xa8, 0x01 },
79	{ 0xa9, 0x01 },
80	{ 0xaa, 0xfc },
81	{ 0xab, 0x28 },
82	{ 0xac, 0x06 },
83	{ 0xad, 0x06 },
84	{ 0xae, 0x06 },
85	{ 0xaf, 0x03 },
86	{ 0xb0, 0x08 },
87	{ 0xb1, 0x26 },
88	{ 0xb2, 0x28 },
89	{ 0xb3, 0x28 },
90	{ 0xb4, 0x33 },
91	{ 0xb5, 0x08 },
92	{ 0xb6, 0x26 },
93	{ 0xb7, 0x08 },
94	{ 0xb8, 0x26 },
95	{ 0xf0, 0x00 },
96	{ 0xf6, 0xc0 },
97	{ 0xff, 0x30 },
98	{ 0xff, 0x52 },
99	{ 0xff, 0x02 },
100	{ 0xb0, 0x0b },
101	{ 0xb1, 0x16 },
102	{ 0xb2, 0x17 },
103	{ 0xb3, 0x2c },
104	{ 0xb4, 0x32 },
105	{ 0xb5, 0x3b },
106	{ 0xb6, 0x29 },
107	{ 0xb7, 0x40 },
108	{ 0xb8, 0x0d },
109	{ 0xb9, 0x05 },
110	{ 0xba, 0x12 },
111	{ 0xbb, 0x10 },
112	{ 0xbc, 0x12 },
113	{ 0xbd, 0x15 },
114	{ 0xbe, 0x19 },
115	{ 0xbf, 0x0e },
116	{ 0xc0, 0x16 },
117	{ 0xc1, 0x0a },
118	{ 0xd0, 0x0c },
119	{ 0xd1, 0x17 },
120	{ 0xd2, 0x14 },
121	{ 0xd3, 0x2e },
122	{ 0xd4, 0x32 },
123	{ 0xd5, 0x3c },
124	{ 0xd6, 0x22 },
125	{ 0xd7, 0x3d },
126	{ 0xd8, 0x0d },
127	{ 0xd9, 0x07 },
128	{ 0xda, 0x13 },
129	{ 0xdb, 0x13 },
130	{ 0xdc, 0x11 },
131	{ 0xdd, 0x15 },
132	{ 0xde, 0x19 },
133	{ 0xdf, 0x10 },
134	{ 0xe0, 0x17 },
135	{ 0xe1, 0x0a },
136	{ 0xff, 0x30 },
137	{ 0xff, 0x52 },
138	{ 0xff, 0x03 },
139	{ 0x00, 0x2a },
140	{ 0x01, 0x2a },
141	{ 0x02, 0x2a },
142	{ 0x03, 0x2a },
143	{ 0x04, 0x61 },
144	{ 0x05, 0x80 },
145	{ 0x06, 0xc7 },
146	{ 0x07, 0x01 },
147	{ 0x08, 0x03 },
148	{ 0x09, 0x04 },
149	{ 0x70, 0x22 },
150	{ 0x71, 0x80 },
151	{ 0x30, 0x2a },
152	{ 0x31, 0x2a },
153	{ 0x32, 0x2a },
154	{ 0x33, 0x2a },
155	{ 0x34, 0x61 },
156	{ 0x35, 0xc5 },
157	{ 0x36, 0x80 },
158	{ 0x37, 0x23 },
159	{ 0x40, 0x03 },
160	{ 0x41, 0x04 },
161	{ 0x42, 0x05 },
162	{ 0x43, 0x06 },
163	{ 0x44, 0x11 },
164	{ 0x45, 0xe8 },
165	{ 0x46, 0xe9 },
166	{ 0x47, 0x11 },
167	{ 0x48, 0xea },
168	{ 0x49, 0xeb },
169	{ 0x50, 0x07 },
170	{ 0x51, 0x08 },
171	{ 0x52, 0x09 },
172	{ 0x53, 0x0a },
173	{ 0x54, 0x11 },
174	{ 0x55, 0xec },
175	{ 0x56, 0xed },
176	{ 0x57, 0x11 },
177	{ 0x58, 0xef },
178	{ 0x59, 0xf0 },
179	{ 0xb1, 0x01 },
180	{ 0xb4, 0x15 },
181	{ 0xb5, 0x16 },
182	{ 0xb6, 0x09 },
183	{ 0xb7, 0x0f },
184	{ 0xb8, 0x0d },
185	{ 0xb9, 0x0b },
186	{ 0xba, 0x00 },
187	{ 0xc7, 0x02 },
188	{ 0xca, 0x17 },
189	{ 0xcb, 0x18 },
190	{ 0xcc, 0x0a },
191	{ 0xcd, 0x10 },
192	{ 0xce, 0x0e },
193	{ 0xcf, 0x0c },
194	{ 0xd0, 0x00 },
195	{ 0x81, 0x00 },
196	{ 0x84, 0x15 },
197	{ 0x85, 0x16 },
198	{ 0x86, 0x10 },
199	{ 0x87, 0x0a },
200	{ 0x88, 0x0c },
201	{ 0x89, 0x0e },
202	{ 0x8a, 0x02 },
203	{ 0x97, 0x00 },
204	{ 0x9a, 0x17 },
205	{ 0x9b, 0x18 },
206	{ 0x9c, 0x0f },
207	{ 0x9d, 0x09 },
208	{ 0x9e, 0x0b },
209	{ 0x9f, 0x0d },
210	{ 0xa0, 0x01 },
211	{ 0xff, 0x30 },
212	{ 0xff, 0x52 },
213	{ 0xff, 0x02 },
214	{ 0x01, 0x01 },
215	{ 0x02, 0xda },
216	{ 0x03, 0xba },
217	{ 0x04, 0xa8 },
218	{ 0x05, 0x9a },
219	{ 0x06, 0x70 },
220	{ 0x07, 0xff },
221	{ 0x08, 0x91 },
222	{ 0x09, 0x90 },
223	{ 0x0a, 0xff },
224	{ 0x0b, 0x8f },
225	{ 0x0c, 0x60 },
226	{ 0x0d, 0x58 },
227	{ 0x0e, 0x48 },
228	{ 0x0f, 0x38 },
229	{ 0x10, 0x2b },
230	{ 0xff, 0x30 },
231	{ 0xff, 0x52 },
232	{ 0xff, 0x00 },
233	{ 0x36, 0x0a },
234};
235
236static inline struct nv3052c *to_nv3052c(struct drm_panel *panel)
237{
238	return container_of(panel, struct nv3052c, panel);
239}
240
241static int nv3052c_prepare(struct drm_panel *panel)
242{
243	struct nv3052c *priv = to_nv3052c(panel);
244	struct mipi_dbi *dbi = &priv->dbi;
245	unsigned int i;
246	int err;
247
248	err = regulator_enable(priv->supply);
249	if (err) {
250		dev_err(priv->dev, "Failed to enable power supply: %d\n", err);
251		return err;
252	}
253
254	/* Reset the chip */
255	gpiod_set_value_cansleep(priv->reset_gpio, 1);
256	usleep_range(10, 1000);
257	gpiod_set_value_cansleep(priv->reset_gpio, 0);
258	usleep_range(5000, 20000);
259
260	for (i = 0; i < ARRAY_SIZE(nv3052c_panel_regs); i++) {
261		err = mipi_dbi_command(dbi, nv3052c_panel_regs[i].cmd,
262				       nv3052c_panel_regs[i].val);
263
264		if (err) {
265			dev_err(priv->dev, "Unable to set register: %d\n", err);
266			goto err_disable_regulator;
267		}
268	}
269
270	err = mipi_dbi_command(dbi, MIPI_DCS_EXIT_SLEEP_MODE);
271	if (err) {
272		dev_err(priv->dev, "Unable to exit sleep mode: %d\n", err);
273		goto err_disable_regulator;
274	}
275
276	return 0;
277
278err_disable_regulator:
279	regulator_disable(priv->supply);
280	return err;
281}
282
283static int nv3052c_unprepare(struct drm_panel *panel)
284{
285	struct nv3052c *priv = to_nv3052c(panel);
286	struct mipi_dbi *dbi = &priv->dbi;
287	int err;
288
289	err = mipi_dbi_command(dbi, MIPI_DCS_ENTER_SLEEP_MODE);
290	if (err)
291		dev_err(priv->dev, "Unable to enter sleep mode: %d\n", err);
292
293	gpiod_set_value_cansleep(priv->reset_gpio, 1);
294	regulator_disable(priv->supply);
295
296	return 0;
297}
298
299static int nv3052c_enable(struct drm_panel *panel)
300{
301	struct nv3052c *priv = to_nv3052c(panel);
302	struct mipi_dbi *dbi = &priv->dbi;
303	int err;
304
305	err = mipi_dbi_command(dbi, MIPI_DCS_SET_DISPLAY_ON);
306	if (err) {
307		dev_err(priv->dev, "Unable to enable display: %d\n", err);
308		return err;
309	}
310
311	if (panel->backlight) {
312		/* Wait for the picture to be ready before enabling backlight */
313		msleep(120);
314	}
315
316	return 0;
317}
318
319static int nv3052c_disable(struct drm_panel *panel)
320{
321	struct nv3052c *priv = to_nv3052c(panel);
322	struct mipi_dbi *dbi = &priv->dbi;
323	int err;
324
325	err = mipi_dbi_command(dbi, MIPI_DCS_SET_DISPLAY_OFF);
326	if (err) {
327		dev_err(priv->dev, "Unable to disable display: %d\n", err);
328		return err;
329	}
330
331	return 0;
332}
333
334static int nv3052c_get_modes(struct drm_panel *panel,
335			     struct drm_connector *connector)
336{
337	struct nv3052c *priv = to_nv3052c(panel);
338	const struct nv3052c_panel_info *panel_info = priv->panel_info;
339	struct drm_display_mode *mode;
340	unsigned int i;
341
342	for (i = 0; i < panel_info->num_modes; i++) {
343		mode = drm_mode_duplicate(connector->dev,
344					  &panel_info->display_modes[i]);
345		if (!mode)
346			return -ENOMEM;
347
348		drm_mode_set_name(mode);
349
350		mode->type = DRM_MODE_TYPE_DRIVER;
351		if (panel_info->num_modes == 1)
352			mode->type |= DRM_MODE_TYPE_PREFERRED;
353
354		drm_mode_probed_add(connector, mode);
355	}
356
357	connector->display_info.bpc = 8;
358	connector->display_info.width_mm = panel_info->width_mm;
359	connector->display_info.height_mm = panel_info->height_mm;
360
361	drm_display_info_set_bus_formats(&connector->display_info,
362					 &panel_info->bus_format, 1);
363	connector->display_info.bus_flags = panel_info->bus_flags;
364
365	return panel_info->num_modes;
366}
367
368static const struct drm_panel_funcs nv3052c_funcs = {
369	.prepare	= nv3052c_prepare,
370	.unprepare	= nv3052c_unprepare,
371	.enable		= nv3052c_enable,
372	.disable	= nv3052c_disable,
373	.get_modes	= nv3052c_get_modes,
374};
375
376static int nv3052c_probe(struct spi_device *spi)
377{
378	struct device *dev = &spi->dev;
379	struct nv3052c *priv;
380	int err;
381
382	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
383	if (!priv)
384		return -ENOMEM;
385
386	priv->dev = dev;
387
388	priv->panel_info = of_device_get_match_data(dev);
389	if (!priv->panel_info)
390		return -EINVAL;
391
392	priv->supply = devm_regulator_get(dev, "power");
393	if (IS_ERR(priv->supply))
394		return dev_err_probe(dev, PTR_ERR(priv->supply), "Failed to get power supply\n");
395
396	priv->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
397	if (IS_ERR(priv->reset_gpio))
398		return dev_err_probe(dev, PTR_ERR(priv->reset_gpio), "Failed to get reset GPIO\n");
399
400	err = mipi_dbi_spi_init(spi, &priv->dbi, NULL);
401	if (err)
402		return dev_err_probe(dev, err, "MIPI DBI init failed\n");
403
404	priv->dbi.read_commands = NULL;
405
406	spi_set_drvdata(spi, priv);
407
408	drm_panel_init(&priv->panel, dev, &nv3052c_funcs,
409		       DRM_MODE_CONNECTOR_DPI);
410
411	err = drm_panel_of_backlight(&priv->panel);
412	if (err)
413		return dev_err_probe(dev, err, "Failed to attach backlight\n");
414
415	drm_panel_add(&priv->panel);
416
417	return 0;
418}
419
420static void nv3052c_remove(struct spi_device *spi)
421{
422	struct nv3052c *priv = spi_get_drvdata(spi);
423
424	drm_panel_remove(&priv->panel);
425	drm_panel_disable(&priv->panel);
426	drm_panel_unprepare(&priv->panel);
427}
428
429static const struct drm_display_mode ltk035c5444t_modes[] = {
430	{ /* 60 Hz */
431		.clock = 24000,
432		.hdisplay = 640,
433		.hsync_start = 640 + 96,
434		.hsync_end = 640 + 96 + 16,
435		.htotal = 640 + 96 + 16 + 48,
436		.vdisplay = 480,
437		.vsync_start = 480 + 5,
438		.vsync_end = 480 + 5 + 2,
439		.vtotal = 480 + 5 + 2 + 13,
440		.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
441	},
442	{ /* 50 Hz */
443		.clock = 18000,
444		.hdisplay = 640,
445		.hsync_start = 640 + 39,
446		.hsync_end = 640 + 39 + 2,
447		.htotal = 640 + 39 + 2 + 39,
448		.vdisplay = 480,
449		.vsync_start = 480 + 5,
450		.vsync_end = 480 + 5 + 2,
451		.vtotal = 480 + 5 + 2 + 13,
452		.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
453	},
454};
455
456static const struct nv3052c_panel_info ltk035c5444t_panel_info = {
457	.display_modes = ltk035c5444t_modes,
458	.num_modes = ARRAY_SIZE(ltk035c5444t_modes),
459	.width_mm = 77,
460	.height_mm = 64,
461	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
462	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
463};
464
465static const struct of_device_id nv3052c_of_match[] = {
466	{ .compatible = "leadtek,ltk035c5444t", .data = &ltk035c5444t_panel_info },
467	{ /* sentinel */ }
468};
469MODULE_DEVICE_TABLE(of, nv3052c_of_match);
470
471static struct spi_driver nv3052c_driver = {
472	.driver = {
473		.name = "nv3052c",
474		.of_match_table = nv3052c_of_match,
475	},
476	.probe = nv3052c_probe,
477	.remove = nv3052c_remove,
478};
479module_spi_driver(nv3052c_driver);
480
481MODULE_AUTHOR("Paul Cercueil <paul@crapouillou.net>");
482MODULE_AUTHOR("Christophe Branchereau <cbranchereau@gmail.com>");
483MODULE_LICENSE("GPL v2");
484