1/* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 25#include <linux/delay.h> 26#include <linux/module.h> 27#include <linux/pci.h> 28#include <linux/pm_runtime.h> 29#include <linux/vga_switcheroo.h> 30#include <linux/mmu_notifier.h> 31#include <linux/dynamic_debug.h> 32 33#include <drm/drm_aperture.h> 34#include <drm/drm_drv.h> 35#include <drm/drm_fbdev_generic.h> 36#include <drm/drm_gem_ttm_helper.h> 37#include <drm/drm_ioctl.h> 38#include <drm/drm_vblank.h> 39 40#include <core/gpuobj.h> 41#include <core/option.h> 42#include <core/pci.h> 43#include <core/tegra.h> 44 45#include <nvif/driver.h> 46#include <nvif/fifo.h> 47#include <nvif/push006c.h> 48#include <nvif/user.h> 49 50#include <nvif/class.h> 51#include <nvif/cl0002.h> 52 53#include "nouveau_drv.h" 54#include "nouveau_dma.h" 55#include "nouveau_ttm.h" 56#include "nouveau_gem.h" 57#include "nouveau_vga.h" 58#include "nouveau_led.h" 59#include "nouveau_hwmon.h" 60#include "nouveau_acpi.h" 61#include "nouveau_bios.h" 62#include "nouveau_ioctl.h" 63#include "nouveau_abi16.h" 64#include "nouveau_fence.h" 65#include "nouveau_debugfs.h" 66#include "nouveau_usif.h" 67#include "nouveau_connector.h" 68#include "nouveau_platform.h" 69#include "nouveau_svm.h" 70#include "nouveau_dmem.h" 71#include "nouveau_exec.h" 72#include "nouveau_uvmm.h" 73#include "nouveau_sched.h" 74 75DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0, 76 "DRM_UT_CORE", 77 "DRM_UT_DRIVER", 78 "DRM_UT_KMS", 79 "DRM_UT_PRIME", 80 "DRM_UT_ATOMIC", 81 "DRM_UT_VBL", 82 "DRM_UT_STATE", 83 "DRM_UT_LEASE", 84 "DRM_UT_DP", 85 "DRM_UT_DRMRES"); 86 87MODULE_PARM_DESC(config, "option string to pass to driver core"); 88static char *nouveau_config; 89module_param_named(config, nouveau_config, charp, 0400); 90 91MODULE_PARM_DESC(debug, "debug string to pass to driver core"); 92static char *nouveau_debug; 93module_param_named(debug, nouveau_debug, charp, 0400); 94 95MODULE_PARM_DESC(noaccel, "disable kernel/abi16 acceleration"); 96static int nouveau_noaccel = 0; 97module_param_named(noaccel, nouveau_noaccel, int, 0400); 98 99MODULE_PARM_DESC(modeset, "enable driver (default: auto, " 100 "0 = disabled, 1 = enabled, 2 = headless)"); 101int nouveau_modeset = -1; 102module_param_named(modeset, nouveau_modeset, int, 0400); 103 104MODULE_PARM_DESC(atomic, "Expose atomic ioctl (default: disabled)"); 105static int nouveau_atomic = 0; 106module_param_named(atomic, nouveau_atomic, int, 0400); 107 108MODULE_PARM_DESC(runpm, "disable (0), force enable (1), optimus only default (-1)"); 109static int nouveau_runtime_pm = -1; 110module_param_named(runpm, nouveau_runtime_pm, int, 0400); 111 112static struct drm_driver driver_stub; 113static struct drm_driver driver_pci; 114static struct drm_driver driver_platform; 115 116static u64 117nouveau_pci_name(struct pci_dev *pdev) 118{ 119 u64 name = (u64)pci_domain_nr(pdev->bus) << 32; 120 name |= pdev->bus->number << 16; 121 name |= PCI_SLOT(pdev->devfn) << 8; 122 return name | PCI_FUNC(pdev->devfn); 123} 124 125static u64 126nouveau_platform_name(struct platform_device *platformdev) 127{ 128 return platformdev->id; 129} 130 131static u64 132nouveau_name(struct drm_device *dev) 133{ 134 if (dev_is_pci(dev->dev)) 135 return nouveau_pci_name(to_pci_dev(dev->dev)); 136 else 137 return nouveau_platform_name(to_platform_device(dev->dev)); 138} 139 140static inline bool 141nouveau_cli_work_ready(struct dma_fence *fence) 142{ 143 bool ret = true; 144 145 spin_lock_irq(fence->lock); 146 if (!dma_fence_is_signaled_locked(fence)) 147 ret = false; 148 spin_unlock_irq(fence->lock); 149 150 if (ret == true) 151 dma_fence_put(fence); 152 return ret; 153} 154 155static void 156nouveau_cli_work(struct work_struct *w) 157{ 158 struct nouveau_cli *cli = container_of(w, typeof(*cli), work); 159 struct nouveau_cli_work *work, *wtmp; 160 mutex_lock(&cli->lock); 161 list_for_each_entry_safe(work, wtmp, &cli->worker, head) { 162 if (!work->fence || nouveau_cli_work_ready(work->fence)) { 163 list_del(&work->head); 164 work->func(work); 165 } 166 } 167 mutex_unlock(&cli->lock); 168} 169 170static void 171nouveau_cli_work_fence(struct dma_fence *fence, struct dma_fence_cb *cb) 172{ 173 struct nouveau_cli_work *work = container_of(cb, typeof(*work), cb); 174 schedule_work(&work->cli->work); 175} 176 177void 178nouveau_cli_work_queue(struct nouveau_cli *cli, struct dma_fence *fence, 179 struct nouveau_cli_work *work) 180{ 181 work->fence = dma_fence_get(fence); 182 work->cli = cli; 183 mutex_lock(&cli->lock); 184 list_add_tail(&work->head, &cli->worker); 185 if (dma_fence_add_callback(fence, &work->cb, nouveau_cli_work_fence)) 186 nouveau_cli_work_fence(fence, &work->cb); 187 mutex_unlock(&cli->lock); 188} 189 190static void 191nouveau_cli_fini(struct nouveau_cli *cli) 192{ 193 /* All our channels are dead now, which means all the fences they 194 * own are signalled, and all callback functions have been called. 195 * 196 * So, after flushing the workqueue, there should be nothing left. 197 */ 198 flush_work(&cli->work); 199 WARN_ON(!list_empty(&cli->worker)); 200 201 usif_client_fini(cli); 202 nouveau_uvmm_fini(&cli->uvmm); 203 nouveau_sched_entity_fini(&cli->sched_entity); 204 nouveau_vmm_fini(&cli->svm); 205 nouveau_vmm_fini(&cli->vmm); 206 nvif_mmu_dtor(&cli->mmu); 207 nvif_device_dtor(&cli->device); 208 mutex_lock(&cli->drm->master.lock); 209 nvif_client_dtor(&cli->base); 210 mutex_unlock(&cli->drm->master.lock); 211} 212 213static int 214nouveau_cli_init(struct nouveau_drm *drm, const char *sname, 215 struct nouveau_cli *cli) 216{ 217 static const struct nvif_mclass 218 mems[] = { 219 { NVIF_CLASS_MEM_GF100, -1 }, 220 { NVIF_CLASS_MEM_NV50 , -1 }, 221 { NVIF_CLASS_MEM_NV04 , -1 }, 222 {} 223 }; 224 static const struct nvif_mclass 225 mmus[] = { 226 { NVIF_CLASS_MMU_GF100, -1 }, 227 { NVIF_CLASS_MMU_NV50 , -1 }, 228 { NVIF_CLASS_MMU_NV04 , -1 }, 229 {} 230 }; 231 static const struct nvif_mclass 232 vmms[] = { 233 { NVIF_CLASS_VMM_GP100, -1 }, 234 { NVIF_CLASS_VMM_GM200, -1 }, 235 { NVIF_CLASS_VMM_GF100, -1 }, 236 { NVIF_CLASS_VMM_NV50 , -1 }, 237 { NVIF_CLASS_VMM_NV04 , -1 }, 238 {} 239 }; 240 u64 device = nouveau_name(drm->dev); 241 int ret; 242 243 snprintf(cli->name, sizeof(cli->name), "%s", sname); 244 cli->drm = drm; 245 mutex_init(&cli->mutex); 246 usif_client_init(cli); 247 248 INIT_WORK(&cli->work, nouveau_cli_work); 249 INIT_LIST_HEAD(&cli->worker); 250 mutex_init(&cli->lock); 251 252 if (cli == &drm->master) { 253 ret = nvif_driver_init(NULL, nouveau_config, nouveau_debug, 254 cli->name, device, &cli->base); 255 } else { 256 mutex_lock(&drm->master.lock); 257 ret = nvif_client_ctor(&drm->master.base, cli->name, device, 258 &cli->base); 259 mutex_unlock(&drm->master.lock); 260 } 261 if (ret) { 262 NV_PRINTK(err, cli, "Client allocation failed: %d\n", ret); 263 goto done; 264 } 265 266 ret = nvif_device_ctor(&cli->base.object, "drmDevice", 0, NV_DEVICE, 267 &(struct nv_device_v0) { 268 .device = ~0, 269 .priv = true, 270 }, sizeof(struct nv_device_v0), 271 &cli->device); 272 if (ret) { 273 NV_PRINTK(err, cli, "Device allocation failed: %d\n", ret); 274 goto done; 275 } 276 277 ret = nvif_mclass(&cli->device.object, mmus); 278 if (ret < 0) { 279 NV_PRINTK(err, cli, "No supported MMU class\n"); 280 goto done; 281 } 282 283 ret = nvif_mmu_ctor(&cli->device.object, "drmMmu", mmus[ret].oclass, 284 &cli->mmu); 285 if (ret) { 286 NV_PRINTK(err, cli, "MMU allocation failed: %d\n", ret); 287 goto done; 288 } 289 290 ret = nvif_mclass(&cli->mmu.object, vmms); 291 if (ret < 0) { 292 NV_PRINTK(err, cli, "No supported VMM class\n"); 293 goto done; 294 } 295 296 ret = nouveau_vmm_init(cli, vmms[ret].oclass, &cli->vmm); 297 if (ret) { 298 NV_PRINTK(err, cli, "VMM allocation failed: %d\n", ret); 299 goto done; 300 } 301 302 ret = nvif_mclass(&cli->mmu.object, mems); 303 if (ret < 0) { 304 NV_PRINTK(err, cli, "No supported MEM class\n"); 305 goto done; 306 } 307 308 cli->mem = &mems[ret]; 309 310 ret = nouveau_sched_entity_init(&cli->sched_entity, &drm->sched, 311 drm->sched_wq); 312 if (ret) 313 goto done; 314 315 return 0; 316done: 317 if (ret) 318 nouveau_cli_fini(cli); 319 return ret; 320} 321 322static void 323nouveau_accel_ce_fini(struct nouveau_drm *drm) 324{ 325 nouveau_channel_idle(drm->cechan); 326 nvif_object_dtor(&drm->ttm.copy); 327 nouveau_channel_del(&drm->cechan); 328} 329 330static void 331nouveau_accel_ce_init(struct nouveau_drm *drm) 332{ 333 struct nvif_device *device = &drm->client.device; 334 u64 runm; 335 int ret = 0; 336 337 /* Allocate channel that has access to a (preferably async) copy 338 * engine, to use for TTM buffer moves. 339 */ 340 runm = nvif_fifo_runlist_ce(device); 341 if (!runm) { 342 NV_DEBUG(drm, "no ce runlist\n"); 343 return; 344 } 345 346 ret = nouveau_channel_new(drm, device, false, runm, NvDmaFB, NvDmaTT, &drm->cechan); 347 if (ret) 348 NV_ERROR(drm, "failed to create ce channel, %d\n", ret); 349} 350 351static void 352nouveau_accel_gr_fini(struct nouveau_drm *drm) 353{ 354 nouveau_channel_idle(drm->channel); 355 nvif_object_dtor(&drm->ntfy); 356 nvkm_gpuobj_del(&drm->notify); 357 nouveau_channel_del(&drm->channel); 358} 359 360static void 361nouveau_accel_gr_init(struct nouveau_drm *drm) 362{ 363 struct nvif_device *device = &drm->client.device; 364 u64 runm; 365 int ret; 366 367 /* Allocate channel that has access to the graphics engine. */ 368 runm = nvif_fifo_runlist(device, NV_DEVICE_HOST_RUNLIST_ENGINES_GR); 369 if (!runm) { 370 NV_DEBUG(drm, "no gr runlist\n"); 371 return; 372 } 373 374 ret = nouveau_channel_new(drm, device, false, runm, NvDmaFB, NvDmaTT, &drm->channel); 375 if (ret) { 376 NV_ERROR(drm, "failed to create kernel channel, %d\n", ret); 377 nouveau_accel_gr_fini(drm); 378 return; 379 } 380 381 /* A SW class is used on pre-NV50 HW to assist with handling the 382 * synchronisation of page flips, as well as to implement fences 383 * on TNT/TNT2 HW that lacks any kind of support in host. 384 */ 385 if (!drm->channel->nvsw.client && device->info.family < NV_DEVICE_INFO_V0_TESLA) { 386 ret = nvif_object_ctor(&drm->channel->user, "drmNvsw", 387 NVDRM_NVSW, nouveau_abi16_swclass(drm), 388 NULL, 0, &drm->channel->nvsw); 389 390 if (ret == 0 && device->info.chipset >= 0x11) { 391 ret = nvif_object_ctor(&drm->channel->user, "drmBlit", 392 0x005f, 0x009f, 393 NULL, 0, &drm->channel->blit); 394 } 395 396 if (ret == 0) { 397 struct nvif_push *push = drm->channel->chan.push; 398 ret = PUSH_WAIT(push, 8); 399 if (ret == 0) { 400 if (device->info.chipset >= 0x11) { 401 PUSH_NVSQ(push, NV05F, 0x0000, drm->channel->blit.handle); 402 PUSH_NVSQ(push, NV09F, 0x0120, 0, 403 0x0124, 1, 404 0x0128, 2); 405 } 406 PUSH_NVSQ(push, NV_SW, 0x0000, drm->channel->nvsw.handle); 407 } 408 } 409 410 if (ret) { 411 NV_ERROR(drm, "failed to allocate sw or blit class, %d\n", ret); 412 nouveau_accel_gr_fini(drm); 413 return; 414 } 415 } 416 417 /* NvMemoryToMemoryFormat requires a notifier ctxdma for some reason, 418 * even if notification is never requested, so, allocate a ctxdma on 419 * any GPU where it's possible we'll end up using M2MF for BO moves. 420 */ 421 if (device->info.family < NV_DEVICE_INFO_V0_FERMI) { 422 ret = nvkm_gpuobj_new(nvxx_device(device), 32, 0, false, NULL, 423 &drm->notify); 424 if (ret) { 425 NV_ERROR(drm, "failed to allocate notifier, %d\n", ret); 426 nouveau_accel_gr_fini(drm); 427 return; 428 } 429 430 ret = nvif_object_ctor(&drm->channel->user, "drmM2mfNtfy", 431 NvNotify0, NV_DMA_IN_MEMORY, 432 &(struct nv_dma_v0) { 433 .target = NV_DMA_V0_TARGET_VRAM, 434 .access = NV_DMA_V0_ACCESS_RDWR, 435 .start = drm->notify->addr, 436 .limit = drm->notify->addr + 31 437 }, sizeof(struct nv_dma_v0), 438 &drm->ntfy); 439 if (ret) { 440 nouveau_accel_gr_fini(drm); 441 return; 442 } 443 } 444} 445 446static void 447nouveau_accel_fini(struct nouveau_drm *drm) 448{ 449 nouveau_accel_ce_fini(drm); 450 nouveau_accel_gr_fini(drm); 451 if (drm->fence) 452 nouveau_fence(drm)->dtor(drm); 453 nouveau_channels_fini(drm); 454} 455 456static void 457nouveau_accel_init(struct nouveau_drm *drm) 458{ 459 struct nvif_device *device = &drm->client.device; 460 struct nvif_sclass *sclass; 461 int ret, i, n; 462 463 if (nouveau_noaccel) 464 return; 465 466 /* Initialise global support for channels, and synchronisation. */ 467 ret = nouveau_channels_init(drm); 468 if (ret) 469 return; 470 471 /*XXX: this is crap, but the fence/channel stuff is a little 472 * backwards in some places. this will be fixed. 473 */ 474 ret = n = nvif_object_sclass_get(&device->object, &sclass); 475 if (ret < 0) 476 return; 477 478 for (ret = -ENOSYS, i = 0; i < n; i++) { 479 switch (sclass[i].oclass) { 480 case NV03_CHANNEL_DMA: 481 ret = nv04_fence_create(drm); 482 break; 483 case NV10_CHANNEL_DMA: 484 ret = nv10_fence_create(drm); 485 break; 486 case NV17_CHANNEL_DMA: 487 case NV40_CHANNEL_DMA: 488 ret = nv17_fence_create(drm); 489 break; 490 case NV50_CHANNEL_GPFIFO: 491 ret = nv50_fence_create(drm); 492 break; 493 case G82_CHANNEL_GPFIFO: 494 ret = nv84_fence_create(drm); 495 break; 496 case FERMI_CHANNEL_GPFIFO: 497 case KEPLER_CHANNEL_GPFIFO_A: 498 case KEPLER_CHANNEL_GPFIFO_B: 499 case MAXWELL_CHANNEL_GPFIFO_A: 500 case PASCAL_CHANNEL_GPFIFO_A: 501 case VOLTA_CHANNEL_GPFIFO_A: 502 case TURING_CHANNEL_GPFIFO_A: 503 case AMPERE_CHANNEL_GPFIFO_A: 504 case AMPERE_CHANNEL_GPFIFO_B: 505 ret = nvc0_fence_create(drm); 506 break; 507 default: 508 break; 509 } 510 } 511 512 nvif_object_sclass_put(&sclass); 513 if (ret) { 514 NV_ERROR(drm, "failed to initialise sync subsystem, %d\n", ret); 515 nouveau_accel_fini(drm); 516 return; 517 } 518 519 /* Volta requires access to a doorbell register for kickoff. */ 520 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_VOLTA) { 521 ret = nvif_user_ctor(device, "drmUsermode"); 522 if (ret) 523 return; 524 } 525 526 /* Allocate channels we need to support various functions. */ 527 nouveau_accel_gr_init(drm); 528 nouveau_accel_ce_init(drm); 529 530 /* Initialise accelerated TTM buffer moves. */ 531 nouveau_bo_move_init(drm); 532} 533 534static void __printf(2, 3) 535nouveau_drm_errorf(struct nvif_object *object, const char *fmt, ...) 536{ 537 struct nouveau_drm *drm = container_of(object->parent, typeof(*drm), parent); 538 struct va_format vaf; 539 va_list va; 540 541 va_start(va, fmt); 542 vaf.fmt = fmt; 543 vaf.va = &va; 544 NV_ERROR(drm, "%pV", &vaf); 545 va_end(va); 546} 547 548static void __printf(2, 3) 549nouveau_drm_debugf(struct nvif_object *object, const char *fmt, ...) 550{ 551 struct nouveau_drm *drm = container_of(object->parent, typeof(*drm), parent); 552 struct va_format vaf; 553 va_list va; 554 555 va_start(va, fmt); 556 vaf.fmt = fmt; 557 vaf.va = &va; 558 NV_DEBUG(drm, "%pV", &vaf); 559 va_end(va); 560} 561 562static const struct nvif_parent_func 563nouveau_parent = { 564 .debugf = nouveau_drm_debugf, 565 .errorf = nouveau_drm_errorf, 566}; 567 568static int 569nouveau_drm_device_init(struct drm_device *dev) 570{ 571 struct nouveau_drm *drm; 572 int ret; 573 574 if (!(drm = kzalloc(sizeof(*drm), GFP_KERNEL))) 575 return -ENOMEM; 576 dev->dev_private = drm; 577 drm->dev = dev; 578 579 nvif_parent_ctor(&nouveau_parent, &drm->parent); 580 drm->master.base.object.parent = &drm->parent; 581 582 ret = nouveau_sched_init(drm); 583 if (ret) 584 goto fail_alloc; 585 586 ret = nouveau_cli_init(drm, "DRM-master", &drm->master); 587 if (ret) 588 goto fail_sched; 589 590 ret = nouveau_cli_init(drm, "DRM", &drm->client); 591 if (ret) 592 goto fail_master; 593 594 nvxx_client(&drm->client.base)->debug = 595 nvkm_dbgopt(nouveau_debug, "DRM"); 596 597 INIT_LIST_HEAD(&drm->clients); 598 mutex_init(&drm->clients_lock); 599 spin_lock_init(&drm->tile.lock); 600 601 /* workaround an odd issue on nvc1 by disabling the device's 602 * nosnoop capability. hopefully won't cause issues until a 603 * better fix is found - assuming there is one... 604 */ 605 if (drm->client.device.info.chipset == 0xc1) 606 nvif_mask(&drm->client.device.object, 0x00088080, 0x00000800, 0x00000000); 607 608 nouveau_vga_init(drm); 609 610 ret = nouveau_ttm_init(drm); 611 if (ret) 612 goto fail_ttm; 613 614 ret = nouveau_bios_init(dev); 615 if (ret) 616 goto fail_bios; 617 618 nouveau_accel_init(drm); 619 620 ret = nouveau_display_create(dev); 621 if (ret) 622 goto fail_dispctor; 623 624 if (dev->mode_config.num_crtc) { 625 ret = nouveau_display_init(dev, false, false); 626 if (ret) 627 goto fail_dispinit; 628 } 629 630 nouveau_debugfs_init(drm); 631 nouveau_hwmon_init(dev); 632 nouveau_svm_init(drm); 633 nouveau_dmem_init(drm); 634 nouveau_led_init(dev); 635 636 if (nouveau_pmops_runtime()) { 637 pm_runtime_use_autosuspend(dev->dev); 638 pm_runtime_set_autosuspend_delay(dev->dev, 5000); 639 pm_runtime_set_active(dev->dev); 640 pm_runtime_allow(dev->dev); 641 pm_runtime_mark_last_busy(dev->dev); 642 pm_runtime_put(dev->dev); 643 } 644 645 return 0; 646fail_dispinit: 647 nouveau_display_destroy(dev); 648fail_dispctor: 649 nouveau_accel_fini(drm); 650 nouveau_bios_takedown(dev); 651fail_bios: 652 nouveau_ttm_fini(drm); 653fail_ttm: 654 nouveau_vga_fini(drm); 655 nouveau_cli_fini(&drm->client); 656fail_master: 657 nouveau_cli_fini(&drm->master); 658fail_sched: 659 nouveau_sched_fini(drm); 660fail_alloc: 661 nvif_parent_dtor(&drm->parent); 662 kfree(drm); 663 return ret; 664} 665 666static void 667nouveau_drm_device_fini(struct drm_device *dev) 668{ 669 struct nouveau_cli *cli, *temp_cli; 670 struct nouveau_drm *drm = nouveau_drm(dev); 671 672 if (nouveau_pmops_runtime()) { 673 pm_runtime_get_sync(dev->dev); 674 pm_runtime_forbid(dev->dev); 675 } 676 677 nouveau_led_fini(dev); 678 nouveau_dmem_fini(drm); 679 nouveau_svm_fini(drm); 680 nouveau_hwmon_fini(dev); 681 nouveau_debugfs_fini(drm); 682 683 if (dev->mode_config.num_crtc) 684 nouveau_display_fini(dev, false, false); 685 nouveau_display_destroy(dev); 686 687 nouveau_accel_fini(drm); 688 nouveau_bios_takedown(dev); 689 690 nouveau_ttm_fini(drm); 691 nouveau_vga_fini(drm); 692 693 /* 694 * There may be existing clients from as-yet unclosed files. For now, 695 * clean them up here rather than deferring until the file is closed, 696 * but this likely not correct if we want to support hot-unplugging 697 * properly. 698 */ 699 mutex_lock(&drm->clients_lock); 700 list_for_each_entry_safe(cli, temp_cli, &drm->clients, head) { 701 list_del(&cli->head); 702 mutex_lock(&cli->mutex); 703 if (cli->abi16) 704 nouveau_abi16_fini(cli->abi16); 705 mutex_unlock(&cli->mutex); 706 nouveau_cli_fini(cli); 707 kfree(cli); 708 } 709 mutex_unlock(&drm->clients_lock); 710 711 nouveau_cli_fini(&drm->client); 712 nouveau_cli_fini(&drm->master); 713 714 nouveau_sched_fini(drm); 715 716 nvif_parent_dtor(&drm->parent); 717 mutex_destroy(&drm->clients_lock); 718 kfree(drm); 719} 720 721/* 722 * On some Intel PCIe bridge controllers doing a 723 * D0 -> D3hot -> D3cold -> D0 sequence causes Nvidia GPUs to not reappear. 724 * Skipping the intermediate D3hot step seems to make it work again. This is 725 * probably caused by not meeting the expectation the involved AML code has 726 * when the GPU is put into D3hot state before invoking it. 727 * 728 * This leads to various manifestations of this issue: 729 * - AML code execution to power on the GPU hits an infinite loop (as the 730 * code waits on device memory to change). 731 * - kernel crashes, as all PCI reads return -1, which most code isn't able 732 * to handle well enough. 733 * 734 * In all cases dmesg will contain at least one line like this: 735 * 'nouveau 0000:01:00.0: Refused to change power state, currently in D3' 736 * followed by a lot of nouveau timeouts. 737 * 738 * In the \_SB.PCI0.PEG0.PG00._OFF code deeper down writes bit 0x80 to the not 739 * documented PCI config space register 0x248 of the Intel PCIe bridge 740 * controller (0x1901) in order to change the state of the PCIe link between 741 * the PCIe port and the GPU. There are alternative code paths using other 742 * registers, which seem to work fine (executed pre Windows 8): 743 * - 0xbc bit 0x20 (publicly available documentation claims 'reserved') 744 * - 0xb0 bit 0x10 (link disable) 745 * Changing the conditions inside the firmware by poking into the relevant 746 * addresses does resolve the issue, but it seemed to be ACPI private memory 747 * and not any device accessible memory at all, so there is no portable way of 748 * changing the conditions. 749 * On a XPS 9560 that means bits [0,3] on \CPEX need to be cleared. 750 * 751 * The only systems where this behavior can be seen are hybrid graphics laptops 752 * with a secondary Nvidia Maxwell, Pascal or Turing GPU. It's unclear whether 753 * this issue only occurs in combination with listed Intel PCIe bridge 754 * controllers and the mentioned GPUs or other devices as well. 755 * 756 * documentation on the PCIe bridge controller can be found in the 757 * "7th Generation Intel® Processor Families for H Platforms Datasheet Volume 2" 758 * Section "12 PCI Express* Controller (x16) Registers" 759 */ 760 761static void quirk_broken_nv_runpm(struct pci_dev *pdev) 762{ 763 struct drm_device *dev = pci_get_drvdata(pdev); 764 struct nouveau_drm *drm = nouveau_drm(dev); 765 struct pci_dev *bridge = pci_upstream_bridge(pdev); 766 767 if (!bridge || bridge->vendor != PCI_VENDOR_ID_INTEL) 768 return; 769 770 switch (bridge->device) { 771 case 0x1901: 772 drm->old_pm_cap = pdev->pm_cap; 773 pdev->pm_cap = 0; 774 NV_INFO(drm, "Disabling PCI power management to avoid bug\n"); 775 break; 776 } 777} 778 779static int nouveau_drm_probe(struct pci_dev *pdev, 780 const struct pci_device_id *pent) 781{ 782 struct nvkm_device *device; 783 struct drm_device *drm_dev; 784 int ret; 785 786 if (vga_switcheroo_client_probe_defer(pdev)) 787 return -EPROBE_DEFER; 788 789 /* We need to check that the chipset is supported before booting 790 * fbdev off the hardware, as there's no way to put it back. 791 */ 792 ret = nvkm_device_pci_new(pdev, nouveau_config, "error", 793 true, false, 0, &device); 794 if (ret) 795 return ret; 796 797 nvkm_device_del(&device); 798 799 /* Remove conflicting drivers (vesafb, efifb etc). */ 800 ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, &driver_pci); 801 if (ret) 802 return ret; 803 804 ret = nvkm_device_pci_new(pdev, nouveau_config, nouveau_debug, 805 true, true, ~0ULL, &device); 806 if (ret) 807 return ret; 808 809 pci_set_master(pdev); 810 811 if (nouveau_atomic) 812 driver_pci.driver_features |= DRIVER_ATOMIC; 813 814 drm_dev = drm_dev_alloc(&driver_pci, &pdev->dev); 815 if (IS_ERR(drm_dev)) { 816 ret = PTR_ERR(drm_dev); 817 goto fail_nvkm; 818 } 819 820 ret = pci_enable_device(pdev); 821 if (ret) 822 goto fail_drm; 823 824 pci_set_drvdata(pdev, drm_dev); 825 826 ret = nouveau_drm_device_init(drm_dev); 827 if (ret) 828 goto fail_pci; 829 830 ret = drm_dev_register(drm_dev, pent->driver_data); 831 if (ret) 832 goto fail_drm_dev_init; 833 834 if (nouveau_drm(drm_dev)->client.device.info.ram_size <= 32 * 1024 * 1024) 835 drm_fbdev_generic_setup(drm_dev, 8); 836 else 837 drm_fbdev_generic_setup(drm_dev, 32); 838 839 quirk_broken_nv_runpm(pdev); 840 return 0; 841 842fail_drm_dev_init: 843 nouveau_drm_device_fini(drm_dev); 844fail_pci: 845 pci_disable_device(pdev); 846fail_drm: 847 drm_dev_put(drm_dev); 848fail_nvkm: 849 nvkm_device_del(&device); 850 return ret; 851} 852 853void 854nouveau_drm_device_remove(struct drm_device *dev) 855{ 856 struct nouveau_drm *drm = nouveau_drm(dev); 857 struct nvkm_client *client; 858 struct nvkm_device *device; 859 860 drm_dev_unplug(dev); 861 862 client = nvxx_client(&drm->client.base); 863 device = nvkm_device_find(client->device); 864 865 nouveau_drm_device_fini(dev); 866 drm_dev_put(dev); 867 nvkm_device_del(&device); 868} 869 870static void 871nouveau_drm_remove(struct pci_dev *pdev) 872{ 873 struct drm_device *dev = pci_get_drvdata(pdev); 874 struct nouveau_drm *drm = nouveau_drm(dev); 875 876 /* revert our workaround */ 877 if (drm->old_pm_cap) 878 pdev->pm_cap = drm->old_pm_cap; 879 nouveau_drm_device_remove(dev); 880 pci_disable_device(pdev); 881} 882 883static int 884nouveau_do_suspend(struct drm_device *dev, bool runtime) 885{ 886 struct nouveau_drm *drm = nouveau_drm(dev); 887 struct ttm_resource_manager *man; 888 int ret; 889 890 nouveau_svm_suspend(drm); 891 nouveau_dmem_suspend(drm); 892 nouveau_led_suspend(dev); 893 894 if (dev->mode_config.num_crtc) { 895 NV_DEBUG(drm, "suspending display...\n"); 896 ret = nouveau_display_suspend(dev, runtime); 897 if (ret) 898 return ret; 899 } 900 901 NV_DEBUG(drm, "evicting buffers...\n"); 902 903 man = ttm_manager_type(&drm->ttm.bdev, TTM_PL_VRAM); 904 ttm_resource_manager_evict_all(&drm->ttm.bdev, man); 905 906 NV_DEBUG(drm, "waiting for kernel channels to go idle...\n"); 907 if (drm->cechan) { 908 ret = nouveau_channel_idle(drm->cechan); 909 if (ret) 910 goto fail_display; 911 } 912 913 if (drm->channel) { 914 ret = nouveau_channel_idle(drm->channel); 915 if (ret) 916 goto fail_display; 917 } 918 919 NV_DEBUG(drm, "suspending fence...\n"); 920 if (drm->fence && nouveau_fence(drm)->suspend) { 921 if (!nouveau_fence(drm)->suspend(drm)) { 922 ret = -ENOMEM; 923 goto fail_display; 924 } 925 } 926 927 NV_DEBUG(drm, "suspending object tree...\n"); 928 ret = nvif_client_suspend(&drm->master.base); 929 if (ret) 930 goto fail_client; 931 932 return 0; 933 934fail_client: 935 if (drm->fence && nouveau_fence(drm)->resume) 936 nouveau_fence(drm)->resume(drm); 937 938fail_display: 939 if (dev->mode_config.num_crtc) { 940 NV_DEBUG(drm, "resuming display...\n"); 941 nouveau_display_resume(dev, runtime); 942 } 943 return ret; 944} 945 946static int 947nouveau_do_resume(struct drm_device *dev, bool runtime) 948{ 949 int ret = 0; 950 struct nouveau_drm *drm = nouveau_drm(dev); 951 952 NV_DEBUG(drm, "resuming object tree...\n"); 953 ret = nvif_client_resume(&drm->master.base); 954 if (ret) { 955 NV_ERROR(drm, "Client resume failed with error: %d\n", ret); 956 return ret; 957 } 958 959 NV_DEBUG(drm, "resuming fence...\n"); 960 if (drm->fence && nouveau_fence(drm)->resume) 961 nouveau_fence(drm)->resume(drm); 962 963 nouveau_run_vbios_init(dev); 964 965 if (dev->mode_config.num_crtc) { 966 NV_DEBUG(drm, "resuming display...\n"); 967 nouveau_display_resume(dev, runtime); 968 } 969 970 nouveau_led_resume(dev); 971 nouveau_dmem_resume(drm); 972 nouveau_svm_resume(drm); 973 return 0; 974} 975 976int 977nouveau_pmops_suspend(struct device *dev) 978{ 979 struct pci_dev *pdev = to_pci_dev(dev); 980 struct drm_device *drm_dev = pci_get_drvdata(pdev); 981 int ret; 982 983 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF || 984 drm_dev->switch_power_state == DRM_SWITCH_POWER_DYNAMIC_OFF) 985 return 0; 986 987 ret = nouveau_do_suspend(drm_dev, false); 988 if (ret) 989 return ret; 990 991 pci_save_state(pdev); 992 pci_disable_device(pdev); 993 pci_set_power_state(pdev, PCI_D3hot); 994 udelay(200); 995 return 0; 996} 997 998int 999nouveau_pmops_resume(struct device *dev) 1000{ 1001 struct pci_dev *pdev = to_pci_dev(dev); 1002 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1003 int ret; 1004 1005 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF || 1006 drm_dev->switch_power_state == DRM_SWITCH_POWER_DYNAMIC_OFF) 1007 return 0; 1008 1009 pci_set_power_state(pdev, PCI_D0); 1010 pci_restore_state(pdev); 1011 ret = pci_enable_device(pdev); 1012 if (ret) 1013 return ret; 1014 pci_set_master(pdev); 1015 1016 ret = nouveau_do_resume(drm_dev, false); 1017 1018 /* Monitors may have been connected / disconnected during suspend */ 1019 nouveau_display_hpd_resume(drm_dev); 1020 1021 return ret; 1022} 1023 1024static int 1025nouveau_pmops_freeze(struct device *dev) 1026{ 1027 struct pci_dev *pdev = to_pci_dev(dev); 1028 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1029 return nouveau_do_suspend(drm_dev, false); 1030} 1031 1032static int 1033nouveau_pmops_thaw(struct device *dev) 1034{ 1035 struct pci_dev *pdev = to_pci_dev(dev); 1036 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1037 return nouveau_do_resume(drm_dev, false); 1038} 1039 1040bool 1041nouveau_pmops_runtime(void) 1042{ 1043 if (nouveau_runtime_pm == -1) 1044 return nouveau_is_optimus() || nouveau_is_v1_dsm(); 1045 return nouveau_runtime_pm == 1; 1046} 1047 1048static int 1049nouveau_pmops_runtime_suspend(struct device *dev) 1050{ 1051 struct pci_dev *pdev = to_pci_dev(dev); 1052 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1053 int ret; 1054 1055 if (!nouveau_pmops_runtime()) { 1056 pm_runtime_forbid(dev); 1057 return -EBUSY; 1058 } 1059 1060 nouveau_switcheroo_optimus_dsm(); 1061 ret = nouveau_do_suspend(drm_dev, true); 1062 pci_save_state(pdev); 1063 pci_disable_device(pdev); 1064 pci_ignore_hotplug(pdev); 1065 pci_set_power_state(pdev, PCI_D3cold); 1066 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 1067 return ret; 1068} 1069 1070static int 1071nouveau_pmops_runtime_resume(struct device *dev) 1072{ 1073 struct pci_dev *pdev = to_pci_dev(dev); 1074 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1075 struct nouveau_drm *drm = nouveau_drm(drm_dev); 1076 struct nvif_device *device = &nouveau_drm(drm_dev)->client.device; 1077 int ret; 1078 1079 if (!nouveau_pmops_runtime()) { 1080 pm_runtime_forbid(dev); 1081 return -EBUSY; 1082 } 1083 1084 pci_set_power_state(pdev, PCI_D0); 1085 pci_restore_state(pdev); 1086 ret = pci_enable_device(pdev); 1087 if (ret) 1088 return ret; 1089 pci_set_master(pdev); 1090 1091 ret = nouveau_do_resume(drm_dev, true); 1092 if (ret) { 1093 NV_ERROR(drm, "resume failed with: %d\n", ret); 1094 return ret; 1095 } 1096 1097 /* do magic */ 1098 nvif_mask(&device->object, 0x088488, (1 << 25), (1 << 25)); 1099 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 1100 1101 /* Monitors may have been connected / disconnected during suspend */ 1102 nouveau_display_hpd_resume(drm_dev); 1103 1104 return ret; 1105} 1106 1107static int 1108nouveau_pmops_runtime_idle(struct device *dev) 1109{ 1110 if (!nouveau_pmops_runtime()) { 1111 pm_runtime_forbid(dev); 1112 return -EBUSY; 1113 } 1114 1115 pm_runtime_mark_last_busy(dev); 1116 pm_runtime_autosuspend(dev); 1117 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 1118 return 1; 1119} 1120 1121static int 1122nouveau_drm_open(struct drm_device *dev, struct drm_file *fpriv) 1123{ 1124 struct nouveau_drm *drm = nouveau_drm(dev); 1125 struct nouveau_cli *cli; 1126 char name[32], tmpname[TASK_COMM_LEN]; 1127 int ret; 1128 1129 /* need to bring up power immediately if opening device */ 1130 ret = pm_runtime_get_sync(dev->dev); 1131 if (ret < 0 && ret != -EACCES) { 1132 pm_runtime_put_autosuspend(dev->dev); 1133 return ret; 1134 } 1135 1136 get_task_comm(tmpname, current); 1137 rcu_read_lock(); 1138 snprintf(name, sizeof(name), "%s[%d]", 1139 tmpname, pid_nr(rcu_dereference(fpriv->pid))); 1140 rcu_read_unlock(); 1141 1142 if (!(cli = kzalloc(sizeof(*cli), GFP_KERNEL))) { 1143 ret = -ENOMEM; 1144 goto done; 1145 } 1146 1147 ret = nouveau_cli_init(drm, name, cli); 1148 if (ret) 1149 goto done; 1150 1151 fpriv->driver_priv = cli; 1152 1153 mutex_lock(&drm->clients_lock); 1154 list_add(&cli->head, &drm->clients); 1155 mutex_unlock(&drm->clients_lock); 1156 1157done: 1158 if (ret && cli) { 1159 nouveau_cli_fini(cli); 1160 kfree(cli); 1161 } 1162 1163 pm_runtime_mark_last_busy(dev->dev); 1164 pm_runtime_put_autosuspend(dev->dev); 1165 return ret; 1166} 1167 1168static void 1169nouveau_drm_postclose(struct drm_device *dev, struct drm_file *fpriv) 1170{ 1171 struct nouveau_cli *cli = nouveau_cli(fpriv); 1172 struct nouveau_drm *drm = nouveau_drm(dev); 1173 int dev_index; 1174 1175 /* 1176 * The device is gone, and as it currently stands all clients are 1177 * cleaned up in the removal codepath. In the future this may change 1178 * so that we can support hot-unplugging, but for now we immediately 1179 * return to avoid a double-free situation. 1180 */ 1181 if (!drm_dev_enter(dev, &dev_index)) 1182 return; 1183 1184 pm_runtime_get_sync(dev->dev); 1185 1186 mutex_lock(&cli->mutex); 1187 if (cli->abi16) 1188 nouveau_abi16_fini(cli->abi16); 1189 mutex_unlock(&cli->mutex); 1190 1191 mutex_lock(&drm->clients_lock); 1192 list_del(&cli->head); 1193 mutex_unlock(&drm->clients_lock); 1194 1195 nouveau_cli_fini(cli); 1196 kfree(cli); 1197 pm_runtime_mark_last_busy(dev->dev); 1198 pm_runtime_put_autosuspend(dev->dev); 1199 drm_dev_exit(dev_index); 1200} 1201 1202static const struct drm_ioctl_desc 1203nouveau_ioctls[] = { 1204 DRM_IOCTL_DEF_DRV(NOUVEAU_GETPARAM, nouveau_abi16_ioctl_getparam, DRM_RENDER_ALLOW), 1205 DRM_IOCTL_DEF_DRV(NOUVEAU_SETPARAM, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1206 DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_ALLOC, nouveau_abi16_ioctl_channel_alloc, DRM_RENDER_ALLOW), 1207 DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_FREE, nouveau_abi16_ioctl_channel_free, DRM_RENDER_ALLOW), 1208 DRM_IOCTL_DEF_DRV(NOUVEAU_GROBJ_ALLOC, nouveau_abi16_ioctl_grobj_alloc, DRM_RENDER_ALLOW), 1209 DRM_IOCTL_DEF_DRV(NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_abi16_ioctl_notifierobj_alloc, DRM_RENDER_ALLOW), 1210 DRM_IOCTL_DEF_DRV(NOUVEAU_GPUOBJ_FREE, nouveau_abi16_ioctl_gpuobj_free, DRM_RENDER_ALLOW), 1211 DRM_IOCTL_DEF_DRV(NOUVEAU_SVM_INIT, nouveau_svmm_init, DRM_RENDER_ALLOW), 1212 DRM_IOCTL_DEF_DRV(NOUVEAU_SVM_BIND, nouveau_svmm_bind, DRM_RENDER_ALLOW), 1213 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_RENDER_ALLOW), 1214 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_RENDER_ALLOW), 1215 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_RENDER_ALLOW), 1216 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_RENDER_ALLOW), 1217 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_RENDER_ALLOW), 1218 DRM_IOCTL_DEF_DRV(NOUVEAU_VM_INIT, nouveau_uvmm_ioctl_vm_init, DRM_RENDER_ALLOW), 1219 DRM_IOCTL_DEF_DRV(NOUVEAU_VM_BIND, nouveau_uvmm_ioctl_vm_bind, DRM_RENDER_ALLOW), 1220 DRM_IOCTL_DEF_DRV(NOUVEAU_EXEC, nouveau_exec_ioctl_exec, DRM_RENDER_ALLOW), 1221}; 1222 1223long 1224nouveau_drm_ioctl(struct file *file, unsigned int cmd, unsigned long arg) 1225{ 1226 struct drm_file *filp = file->private_data; 1227 struct drm_device *dev = filp->minor->dev; 1228 long ret; 1229 1230 ret = pm_runtime_get_sync(dev->dev); 1231 if (ret < 0 && ret != -EACCES) { 1232 pm_runtime_put_autosuspend(dev->dev); 1233 return ret; 1234 } 1235 1236 switch (_IOC_NR(cmd) - DRM_COMMAND_BASE) { 1237 case DRM_NOUVEAU_NVIF: 1238 ret = usif_ioctl(filp, (void __user *)arg, _IOC_SIZE(cmd)); 1239 break; 1240 default: 1241 ret = drm_ioctl(file, cmd, arg); 1242 break; 1243 } 1244 1245 pm_runtime_mark_last_busy(dev->dev); 1246 pm_runtime_put_autosuspend(dev->dev); 1247 return ret; 1248} 1249 1250static const struct file_operations 1251nouveau_driver_fops = { 1252 .owner = THIS_MODULE, 1253 .open = drm_open, 1254 .release = drm_release, 1255 .unlocked_ioctl = nouveau_drm_ioctl, 1256 .mmap = drm_gem_mmap, 1257 .poll = drm_poll, 1258 .read = drm_read, 1259#if defined(CONFIG_COMPAT) 1260 .compat_ioctl = nouveau_compat_ioctl, 1261#endif 1262 .llseek = noop_llseek, 1263}; 1264 1265static struct drm_driver 1266driver_stub = { 1267 .driver_features = DRIVER_GEM | 1268 DRIVER_SYNCOBJ | DRIVER_SYNCOBJ_TIMELINE | 1269 DRIVER_GEM_GPUVA | 1270 DRIVER_MODESET | 1271 DRIVER_RENDER, 1272 .open = nouveau_drm_open, 1273 .postclose = nouveau_drm_postclose, 1274 .lastclose = nouveau_vga_lastclose, 1275 1276#if defined(CONFIG_DEBUG_FS) 1277 .debugfs_init = nouveau_drm_debugfs_init, 1278#endif 1279 1280 .ioctls = nouveau_ioctls, 1281 .num_ioctls = ARRAY_SIZE(nouveau_ioctls), 1282 .fops = &nouveau_driver_fops, 1283 1284 .gem_prime_import_sg_table = nouveau_gem_prime_import_sg_table, 1285 1286 .dumb_create = nouveau_display_dumb_create, 1287 .dumb_map_offset = drm_gem_ttm_dumb_map_offset, 1288 1289 .name = DRIVER_NAME, 1290 .desc = DRIVER_DESC, 1291#ifdef GIT_REVISION 1292 .date = GIT_REVISION, 1293#else 1294 .date = DRIVER_DATE, 1295#endif 1296 .major = DRIVER_MAJOR, 1297 .minor = DRIVER_MINOR, 1298 .patchlevel = DRIVER_PATCHLEVEL, 1299}; 1300 1301static struct pci_device_id 1302nouveau_drm_pci_table[] = { 1303 { 1304 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID), 1305 .class = PCI_BASE_CLASS_DISPLAY << 16, 1306 .class_mask = 0xff << 16, 1307 }, 1308 { 1309 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA_SGS, PCI_ANY_ID), 1310 .class = PCI_BASE_CLASS_DISPLAY << 16, 1311 .class_mask = 0xff << 16, 1312 }, 1313 {} 1314}; 1315 1316static void nouveau_display_options(void) 1317{ 1318 DRM_DEBUG_DRIVER("Loading Nouveau with parameters:\n"); 1319 1320 DRM_DEBUG_DRIVER("... tv_disable : %d\n", nouveau_tv_disable); 1321 DRM_DEBUG_DRIVER("... ignorelid : %d\n", nouveau_ignorelid); 1322 DRM_DEBUG_DRIVER("... duallink : %d\n", nouveau_duallink); 1323 DRM_DEBUG_DRIVER("... config : %s\n", nouveau_config); 1324 DRM_DEBUG_DRIVER("... debug : %s\n", nouveau_debug); 1325 DRM_DEBUG_DRIVER("... noaccel : %d\n", nouveau_noaccel); 1326 DRM_DEBUG_DRIVER("... modeset : %d\n", nouveau_modeset); 1327 DRM_DEBUG_DRIVER("... runpm : %d\n", nouveau_runtime_pm); 1328 DRM_DEBUG_DRIVER("... vram_pushbuf : %d\n", nouveau_vram_pushbuf); 1329 DRM_DEBUG_DRIVER("... hdmimhz : %d\n", nouveau_hdmimhz); 1330} 1331 1332static const struct dev_pm_ops nouveau_pm_ops = { 1333 .suspend = nouveau_pmops_suspend, 1334 .resume = nouveau_pmops_resume, 1335 .freeze = nouveau_pmops_freeze, 1336 .thaw = nouveau_pmops_thaw, 1337 .poweroff = nouveau_pmops_freeze, 1338 .restore = nouveau_pmops_resume, 1339 .runtime_suspend = nouveau_pmops_runtime_suspend, 1340 .runtime_resume = nouveau_pmops_runtime_resume, 1341 .runtime_idle = nouveau_pmops_runtime_idle, 1342}; 1343 1344static struct pci_driver 1345nouveau_drm_pci_driver = { 1346 .name = "nouveau", 1347 .id_table = nouveau_drm_pci_table, 1348 .probe = nouveau_drm_probe, 1349 .remove = nouveau_drm_remove, 1350 .driver.pm = &nouveau_pm_ops, 1351}; 1352 1353struct drm_device * 1354nouveau_platform_device_create(const struct nvkm_device_tegra_func *func, 1355 struct platform_device *pdev, 1356 struct nvkm_device **pdevice) 1357{ 1358 struct drm_device *drm; 1359 int err; 1360 1361 err = nvkm_device_tegra_new(func, pdev, nouveau_config, nouveau_debug, 1362 true, true, ~0ULL, pdevice); 1363 if (err) 1364 goto err_free; 1365 1366 drm = drm_dev_alloc(&driver_platform, &pdev->dev); 1367 if (IS_ERR(drm)) { 1368 err = PTR_ERR(drm); 1369 goto err_free; 1370 } 1371 1372 err = nouveau_drm_device_init(drm); 1373 if (err) 1374 goto err_put; 1375 1376 platform_set_drvdata(pdev, drm); 1377 1378 return drm; 1379 1380err_put: 1381 drm_dev_put(drm); 1382err_free: 1383 nvkm_device_del(pdevice); 1384 1385 return ERR_PTR(err); 1386} 1387 1388static int __init 1389nouveau_drm_init(void) 1390{ 1391 driver_pci = driver_stub; 1392 driver_platform = driver_stub; 1393 1394 nouveau_display_options(); 1395 1396 if (nouveau_modeset == -1) { 1397 if (drm_firmware_drivers_only()) 1398 nouveau_modeset = 0; 1399 } 1400 1401 if (!nouveau_modeset) 1402 return 0; 1403 1404#ifdef CONFIG_NOUVEAU_PLATFORM_DRIVER 1405 platform_driver_register(&nouveau_platform_driver); 1406#endif 1407 1408 nouveau_register_dsm_handler(); 1409 nouveau_backlight_ctor(); 1410 1411#ifdef CONFIG_PCI 1412 return pci_register_driver(&nouveau_drm_pci_driver); 1413#else 1414 return 0; 1415#endif 1416} 1417 1418static void __exit 1419nouveau_drm_exit(void) 1420{ 1421 if (!nouveau_modeset) 1422 return; 1423 1424#ifdef CONFIG_PCI 1425 pci_unregister_driver(&nouveau_drm_pci_driver); 1426#endif 1427 nouveau_backlight_dtor(); 1428 nouveau_unregister_dsm_handler(); 1429 1430#ifdef CONFIG_NOUVEAU_PLATFORM_DRIVER 1431 platform_driver_unregister(&nouveau_platform_driver); 1432#endif 1433 if (IS_ENABLED(CONFIG_DRM_NOUVEAU_SVM)) 1434 mmu_notifier_synchronize(); 1435} 1436 1437module_init(nouveau_drm_init); 1438module_exit(nouveau_drm_exit); 1439 1440MODULE_DEVICE_TABLE(pci, nouveau_drm_pci_table); 1441MODULE_AUTHOR(DRIVER_AUTHOR); 1442MODULE_DESCRIPTION(DRIVER_DESC); 1443MODULE_LICENSE("GPL and additional rights"); 1444