1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. 4 * Copyright (C) 2013 Red Hat 5 * Author: Rob Clark <robdclark@gmail.com> 6 */ 7 8#ifndef __MSM_DRV_H__ 9#define __MSM_DRV_H__ 10 11#include <linux/kernel.h> 12#include <linux/clk.h> 13#include <linux/cpufreq.h> 14#include <linux/devfreq.h> 15#include <linux/module.h> 16#include <linux/component.h> 17#include <linux/platform_device.h> 18#include <linux/pm.h> 19#include <linux/pm_runtime.h> 20#include <linux/slab.h> 21#include <linux/list.h> 22#include <linux/iommu.h> 23#include <linux/types.h> 24#include <linux/of_graph.h> 25#include <linux/of_device.h> 26#include <linux/sizes.h> 27#include <linux/kthread.h> 28 29#include <drm/drm_atomic.h> 30#include <drm/drm_atomic_helper.h> 31#include <drm/drm_probe_helper.h> 32#include <drm/display/drm_dsc.h> 33#include <drm/msm_drm.h> 34#include <drm/drm_gem.h> 35 36#ifdef CONFIG_FAULT_INJECTION 37extern struct fault_attr fail_gem_alloc; 38extern struct fault_attr fail_gem_iova; 39#else 40# define should_fail(attr, size) 0 41#endif 42 43struct msm_kms; 44struct msm_gpu; 45struct msm_mmu; 46struct msm_mdss; 47struct msm_rd_state; 48struct msm_perf_state; 49struct msm_gem_submit; 50struct msm_fence_context; 51struct msm_gem_address_space; 52struct msm_gem_vma; 53struct msm_disp_state; 54 55#define MAX_CRTCS 8 56#define MAX_BRIDGES 8 57 58#define FRAC_16_16(mult, div) (((mult) << 16) / (div)) 59 60enum msm_dp_controller { 61 MSM_DP_CONTROLLER_0, 62 MSM_DP_CONTROLLER_1, 63 MSM_DP_CONTROLLER_2, 64 MSM_DP_CONTROLLER_3, 65 MSM_DP_CONTROLLER_COUNT, 66}; 67 68enum msm_dsi_controller { 69 MSM_DSI_CONTROLLER_0, 70 MSM_DSI_CONTROLLER_1, 71 MSM_DSI_CONTROLLER_COUNT, 72}; 73 74#define MSM_GPU_MAX_RINGS 4 75#define MAX_H_TILES_PER_DISPLAY 2 76 77/** 78 * enum msm_event_wait - type of HW events to wait for 79 * @MSM_ENC_COMMIT_DONE - wait for the driver to flush the registers to HW 80 * @MSM_ENC_TX_COMPLETE - wait for the HW to transfer the frame to panel 81 * @MSM_ENC_VBLANK - wait for the HW VBLANK event (for driver-internal waiters) 82 */ 83enum msm_event_wait { 84 MSM_ENC_COMMIT_DONE = 0, 85 MSM_ENC_TX_COMPLETE, 86 MSM_ENC_VBLANK, 87}; 88 89/** 90 * struct msm_display_topology - defines a display topology pipeline 91 * @num_lm: number of layer mixers used 92 * @num_intf: number of interfaces the panel is mounted on 93 * @num_dspp: number of dspp blocks used 94 * @num_dsc: number of Display Stream Compression (DSC) blocks used 95 */ 96struct msm_display_topology { 97 u32 num_lm; 98 u32 num_intf; 99 u32 num_dspp; 100 u32 num_dsc; 101}; 102 103/* Commit/Event thread specific structure */ 104struct msm_drm_thread { 105 struct drm_device *dev; 106 struct kthread_worker *worker; 107}; 108 109struct msm_drm_private { 110 111 struct drm_device *dev; 112 113 struct msm_kms *kms; 114 int (*kms_init)(struct drm_device *dev); 115 116 /* subordinate devices, if present: */ 117 struct platform_device *gpu_pdev; 118 119 /* possibly this should be in the kms component, but it is 120 * shared by both mdp4 and mdp5.. 121 */ 122 struct hdmi *hdmi; 123 124 /* DSI is shared by mdp4 and mdp5 */ 125 struct msm_dsi *dsi[MSM_DSI_CONTROLLER_COUNT]; 126 127 struct msm_dp *dp[MSM_DP_CONTROLLER_COUNT]; 128 129 /* when we have more than one 'msm_gpu' these need to be an array: */ 130 struct msm_gpu *gpu; 131 132 /* gpu is only set on open(), but we need this info earlier */ 133 bool is_a2xx; 134 bool has_cached_coherent; 135 136 struct msm_rd_state *rd; /* debugfs to dump all submits */ 137 struct msm_rd_state *hangrd; /* debugfs to dump hanging submits */ 138 struct msm_perf_state *perf; 139 140 /** 141 * List of all GEM objects (mainly for debugfs, protected by obj_lock 142 * (acquire before per GEM object lock) 143 */ 144 struct list_head objects; 145 struct mutex obj_lock; 146 147 /** 148 * lru: 149 * 150 * The various LRU's that a GEM object is in at various stages of 151 * it's lifetime. Objects start out in the unbacked LRU. When 152 * pinned (for scannout or permanently mapped GPU buffers, like 153 * ringbuffer, memptr, fw, etc) it moves to the pinned LRU. When 154 * unpinned, it moves into willneed or dontneed LRU depending on 155 * madvise state. When backing pages are evicted (willneed) or 156 * purged (dontneed) it moves back into the unbacked LRU. 157 * 158 * The dontneed LRU is considered by the shrinker for objects 159 * that are candidate for purging, and the willneed LRU is 160 * considered for objects that could be evicted. 161 */ 162 struct { 163 /** 164 * unbacked: 165 * 166 * The LRU for GEM objects without backing pages allocated. 167 * This mostly exists so that objects are always is one 168 * LRU. 169 */ 170 struct drm_gem_lru unbacked; 171 172 /** 173 * pinned: 174 * 175 * The LRU for pinned GEM objects 176 */ 177 struct drm_gem_lru pinned; 178 179 /** 180 * willneed: 181 * 182 * The LRU for unpinned GEM objects which are in madvise 183 * WILLNEED state (ie. can be evicted) 184 */ 185 struct drm_gem_lru willneed; 186 187 /** 188 * dontneed: 189 * 190 * The LRU for unpinned GEM objects which are in madvise 191 * DONTNEED state (ie. can be purged) 192 */ 193 struct drm_gem_lru dontneed; 194 195 /** 196 * lock: 197 * 198 * Protects manipulation of all of the LRUs. 199 */ 200 struct mutex lock; 201 } lru; 202 203 struct workqueue_struct *wq; 204 205 unsigned int num_crtcs; 206 207 struct msm_drm_thread event_thread[MAX_CRTCS]; 208 209 unsigned int num_bridges; 210 struct drm_bridge *bridges[MAX_BRIDGES]; 211 212 /* VRAM carveout, used when no IOMMU: */ 213 struct { 214 unsigned long size; 215 dma_addr_t paddr; 216 /* NOTE: mm managed at the page level, size is in # of pages 217 * and position mm_node->start is in # of pages: 218 */ 219 struct drm_mm mm; 220 spinlock_t lock; /* Protects drm_mm node allocation/removal */ 221 } vram; 222 223 struct notifier_block vmap_notifier; 224 struct shrinker shrinker; 225 226 struct drm_atomic_state *pm_state; 227 228 /** 229 * hangcheck_period: For hang detection, in ms 230 * 231 * Note that in practice, a submit/job will get at least two hangcheck 232 * periods, due to checking for progress being implemented as simply 233 * "have the CP position registers changed since last time?" 234 */ 235 unsigned int hangcheck_period; 236 237 /** gpu_devfreq_config: Devfreq tuning config for the GPU. */ 238 struct devfreq_simple_ondemand_data gpu_devfreq_config; 239 240 /** 241 * gpu_clamp_to_idle: Enable clamping to idle freq when inactive 242 */ 243 bool gpu_clamp_to_idle; 244 245 /** 246 * disable_err_irq: 247 * 248 * Disable handling of GPU hw error interrupts, to force fallback to 249 * sw hangcheck timer. Written (via debugfs) by igt tests to test 250 * the sw hangcheck mechanism. 251 */ 252 bool disable_err_irq; 253}; 254 255struct msm_format { 256 uint32_t pixel_format; 257}; 258 259struct msm_pending_timer; 260 261int msm_atomic_init_pending_timer(struct msm_pending_timer *timer, 262 struct msm_kms *kms, int crtc_idx); 263void msm_atomic_destroy_pending_timer(struct msm_pending_timer *timer); 264void msm_atomic_commit_tail(struct drm_atomic_state *state); 265int msm_atomic_check(struct drm_device *dev, struct drm_atomic_state *state); 266struct drm_atomic_state *msm_atomic_state_alloc(struct drm_device *dev); 267void msm_atomic_state_clear(struct drm_atomic_state *state); 268void msm_atomic_state_free(struct drm_atomic_state *state); 269 270int msm_crtc_enable_vblank(struct drm_crtc *crtc); 271void msm_crtc_disable_vblank(struct drm_crtc *crtc); 272 273int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu); 274void msm_unregister_mmu(struct drm_device *dev, struct msm_mmu *mmu); 275 276struct msm_gem_address_space *msm_kms_init_aspace(struct drm_device *dev); 277bool msm_use_mmu(struct drm_device *dev); 278 279int msm_ioctl_gem_submit(struct drm_device *dev, void *data, 280 struct drm_file *file); 281 282#ifdef CONFIG_DEBUG_FS 283unsigned long msm_gem_shrinker_shrink(struct drm_device *dev, unsigned long nr_to_scan); 284#endif 285 286void msm_gem_shrinker_init(struct drm_device *dev); 287void msm_gem_shrinker_cleanup(struct drm_device *dev); 288 289struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj); 290int msm_gem_prime_vmap(struct drm_gem_object *obj, struct iosys_map *map); 291void msm_gem_prime_vunmap(struct drm_gem_object *obj, struct iosys_map *map); 292struct drm_gem_object *msm_gem_prime_import_sg_table(struct drm_device *dev, 293 struct dma_buf_attachment *attach, struct sg_table *sg); 294int msm_gem_prime_pin(struct drm_gem_object *obj); 295void msm_gem_prime_unpin(struct drm_gem_object *obj); 296 297int msm_framebuffer_prepare(struct drm_framebuffer *fb, 298 struct msm_gem_address_space *aspace, bool needs_dirtyfb); 299void msm_framebuffer_cleanup(struct drm_framebuffer *fb, 300 struct msm_gem_address_space *aspace, bool needed_dirtyfb); 301uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb, 302 struct msm_gem_address_space *aspace, int plane); 303struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane); 304const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb); 305struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev, 306 struct drm_file *file, const struct drm_mode_fb_cmd2 *mode_cmd); 307struct drm_framebuffer * msm_alloc_stolen_fb(struct drm_device *dev, 308 int w, int h, int p, uint32_t format); 309 310#ifdef CONFIG_DRM_FBDEV_EMULATION 311void msm_fbdev_setup(struct drm_device *dev); 312#else 313static inline void msm_fbdev_setup(struct drm_device *dev) 314{ 315} 316#endif 317 318struct hdmi; 319#ifdef CONFIG_DRM_MSM_HDMI 320int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev, 321 struct drm_encoder *encoder); 322void __init msm_hdmi_register(void); 323void __exit msm_hdmi_unregister(void); 324#else 325static inline int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev, 326 struct drm_encoder *encoder) 327{ 328 return -EINVAL; 329} 330static inline void __init msm_hdmi_register(void) {} 331static inline void __exit msm_hdmi_unregister(void) {} 332#endif 333 334struct msm_dsi; 335#ifdef CONFIG_DRM_MSM_DSI 336int dsi_dev_attach(struct platform_device *pdev); 337void dsi_dev_detach(struct platform_device *pdev); 338void __init msm_dsi_register(void); 339void __exit msm_dsi_unregister(void); 340int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct drm_device *dev, 341 struct drm_encoder *encoder); 342void msm_dsi_snapshot(struct msm_disp_state *disp_state, struct msm_dsi *msm_dsi); 343bool msm_dsi_is_cmd_mode(struct msm_dsi *msm_dsi); 344bool msm_dsi_is_bonded_dsi(struct msm_dsi *msm_dsi); 345bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi); 346struct drm_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi); 347#else 348static inline void __init msm_dsi_register(void) 349{ 350} 351static inline void __exit msm_dsi_unregister(void) 352{ 353} 354static inline int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, 355 struct drm_device *dev, 356 struct drm_encoder *encoder) 357{ 358 return -EINVAL; 359} 360static inline void msm_dsi_snapshot(struct msm_disp_state *disp_state, struct msm_dsi *msm_dsi) 361{ 362} 363static inline bool msm_dsi_is_cmd_mode(struct msm_dsi *msm_dsi) 364{ 365 return false; 366} 367static inline bool msm_dsi_is_bonded_dsi(struct msm_dsi *msm_dsi) 368{ 369 return false; 370} 371static inline bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi) 372{ 373 return false; 374} 375 376static inline struct drm_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi) 377{ 378 return NULL; 379} 380#endif 381 382#ifdef CONFIG_DRM_MSM_DP 383int __init msm_dp_register(void); 384void __exit msm_dp_unregister(void); 385int msm_dp_modeset_init(struct msm_dp *dp_display, struct drm_device *dev, 386 struct drm_encoder *encoder); 387void msm_dp_irq_postinstall(struct msm_dp *dp_display); 388void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp_display); 389 390void msm_dp_debugfs_init(struct msm_dp *dp_display, struct drm_minor *minor); 391bool msm_dp_wide_bus_available(const struct msm_dp *dp_display); 392 393#else 394static inline int __init msm_dp_register(void) 395{ 396 return -EINVAL; 397} 398static inline void __exit msm_dp_unregister(void) 399{ 400} 401static inline int msm_dp_modeset_init(struct msm_dp *dp_display, 402 struct drm_device *dev, 403 struct drm_encoder *encoder) 404{ 405 return -EINVAL; 406} 407 408static inline void msm_dp_irq_postinstall(struct msm_dp *dp_display) 409{ 410} 411 412static inline void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp_display) 413{ 414} 415 416static inline void msm_dp_debugfs_init(struct msm_dp *dp_display, 417 struct drm_minor *minor) 418{ 419} 420 421static inline bool msm_dp_wide_bus_available(const struct msm_dp *dp_display) 422{ 423 return false; 424} 425 426#endif 427 428#ifdef CONFIG_DRM_MSM_MDP4 429void msm_mdp4_register(void); 430void msm_mdp4_unregister(void); 431#else 432static inline void msm_mdp4_register(void) {} 433static inline void msm_mdp4_unregister(void) {} 434#endif 435 436#ifdef CONFIG_DRM_MSM_MDP5 437void msm_mdp_register(void); 438void msm_mdp_unregister(void); 439#else 440static inline void msm_mdp_register(void) {} 441static inline void msm_mdp_unregister(void) {} 442#endif 443 444#ifdef CONFIG_DRM_MSM_DPU 445void msm_dpu_register(void); 446void msm_dpu_unregister(void); 447#else 448static inline void msm_dpu_register(void) {} 449static inline void msm_dpu_unregister(void) {} 450#endif 451 452#ifdef CONFIG_DRM_MSM_MDSS 453void msm_mdss_register(void); 454void msm_mdss_unregister(void); 455#else 456static inline void msm_mdss_register(void) {} 457static inline void msm_mdss_unregister(void) {} 458#endif 459 460#ifdef CONFIG_DEBUG_FS 461void msm_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m); 462int msm_debugfs_late_init(struct drm_device *dev); 463int msm_rd_debugfs_init(struct drm_minor *minor); 464void msm_rd_debugfs_cleanup(struct msm_drm_private *priv); 465__printf(3, 4) 466void msm_rd_dump_submit(struct msm_rd_state *rd, struct msm_gem_submit *submit, 467 const char *fmt, ...); 468int msm_perf_debugfs_init(struct drm_minor *minor); 469void msm_perf_debugfs_cleanup(struct msm_drm_private *priv); 470#else 471static inline int msm_debugfs_late_init(struct drm_device *dev) { return 0; } 472__printf(3, 4) 473static inline void msm_rd_dump_submit(struct msm_rd_state *rd, 474 struct msm_gem_submit *submit, 475 const char *fmt, ...) {} 476static inline void msm_rd_debugfs_cleanup(struct msm_drm_private *priv) {} 477static inline void msm_perf_debugfs_cleanup(struct msm_drm_private *priv) {} 478#endif 479 480struct clk *msm_clk_get(struct platform_device *pdev, const char *name); 481 482struct clk *msm_clk_bulk_get_clock(struct clk_bulk_data *bulk, int count, 483 const char *name); 484void __iomem *msm_ioremap(struct platform_device *pdev, const char *name); 485void __iomem *msm_ioremap_size(struct platform_device *pdev, const char *name, 486 phys_addr_t *size); 487void __iomem *msm_ioremap_quiet(struct platform_device *pdev, const char *name); 488 489struct icc_path *msm_icc_get(struct device *dev, const char *name); 490 491#define msm_writel(data, addr) writel((data), (addr)) 492#define msm_readl(addr) readl((addr)) 493 494static inline void msm_rmw(void __iomem *addr, u32 mask, u32 or) 495{ 496 u32 val = msm_readl(addr); 497 498 val &= ~mask; 499 msm_writel(val | or, addr); 500} 501 502/** 503 * struct msm_hrtimer_work - a helper to combine an hrtimer with kthread_work 504 * 505 * @timer: hrtimer to control when the kthread work is triggered 506 * @work: the kthread work 507 * @worker: the kthread worker the work will be scheduled on 508 */ 509struct msm_hrtimer_work { 510 struct hrtimer timer; 511 struct kthread_work work; 512 struct kthread_worker *worker; 513}; 514 515void msm_hrtimer_queue_work(struct msm_hrtimer_work *work, 516 ktime_t wakeup_time, 517 enum hrtimer_mode mode); 518void msm_hrtimer_work_init(struct msm_hrtimer_work *work, 519 struct kthread_worker *worker, 520 kthread_work_func_t fn, 521 clockid_t clock_id, 522 enum hrtimer_mode mode); 523 524#define DBG(fmt, ...) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__) 525#define VERB(fmt, ...) if (0) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__) 526 527static inline int align_pitch(int width, int bpp) 528{ 529 int bytespp = (bpp + 7) / 8; 530 /* adreno needs pitch aligned to 32 pixels: */ 531 return bytespp * ALIGN(width, 32); 532} 533 534/* for the generated headers: */ 535#define INVALID_IDX(idx) ({BUG(); 0;}) 536#define fui(x) ({BUG(); 0;}) 537#define _mesa_float_to_half(x) ({BUG(); 0;}) 538 539 540#define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT) 541 542/* for conditionally setting boolean flag(s): */ 543#define COND(bool, val) ((bool) ? (val) : 0) 544 545static inline unsigned long timeout_to_jiffies(const ktime_t *timeout) 546{ 547 ktime_t now = ktime_get(); 548 s64 remaining_jiffies; 549 550 if (ktime_compare(*timeout, now) < 0) { 551 remaining_jiffies = 0; 552 } else { 553 ktime_t rem = ktime_sub(*timeout, now); 554 remaining_jiffies = ktime_divns(rem, NSEC_PER_SEC / HZ); 555 } 556 557 return clamp(remaining_jiffies, 1LL, (s64)INT_MAX); 558} 559 560/* Driver helpers */ 561 562extern const struct component_master_ops msm_drm_ops; 563 564int msm_pm_prepare(struct device *dev); 565void msm_pm_complete(struct device *dev); 566 567int msm_drv_probe(struct device *dev, 568 int (*kms_init)(struct drm_device *dev)); 569void msm_drv_shutdown(struct platform_device *pdev); 570 571 572#endif /* __MSM_DRV_H__ */ 573