1#ifndef HDMI_XML 2#define HDMI_XML 3 4/* Autogenerated file, DO NOT EDIT manually! 5 6This file was generated by the rules-ng-ng headergen tool in this git repository: 7http://github.com/freedreno/envytools/ 8git clone https://github.com/freedreno/envytools.git 9 10The rules-ng-ng source files this header was generated from are: 11- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 944 bytes, from 2022-07-23 20:21:46) 12- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2022-07-23 20:21:46) 13- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2022-03-08 17:40:42) 14- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2022-03-08 17:40:42) 15- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2022-03-08 17:40:42) 16- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 18746 bytes, from 2022-04-28 17:29:36) 17- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2022-03-08 17:40:42) 18- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2022-03-08 17:40:42) 19- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2022-03-08 17:40:42) 20- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2022-03-08 17:40:42) 21- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2022-03-08 17:40:42) 22- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2022-03-08 17:40:42) 23- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 11007 bytes, from 2022-03-08 17:40:42) 24- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2022-03-08 17:40:42) 25- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2022-03-08 17:40:42) 26- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2022-03-08 17:40:42) 27- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 42350 bytes, from 2022-09-20 17:45:56) 28- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2022-03-08 17:40:42) 29 30Copyright (C) 2013-2022 by the following authors: 31- Rob Clark <robdclark@gmail.com> (robclark) 32- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) 33 34Permission is hereby granted, free of charge, to any person obtaining 35a copy of this software and associated documentation files (the 36"Software"), to deal in the Software without restriction, including 37without limitation the rights to use, copy, modify, merge, publish, 38distribute, sublicense, and/or sell copies of the Software, and to 39permit persons to whom the Software is furnished to do so, subject to 40the following conditions: 41 42The above copyright notice and this permission notice (including the 43next paragraph) shall be included in all copies or substantial 44portions of the Software. 45 46THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 47EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 48MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 49IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 50LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 51OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 52WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 53*/ 54 55 56enum hdmi_hdcp_key_state { 57 HDCP_KEYS_STATE_NO_KEYS = 0, 58 HDCP_KEYS_STATE_NOT_CHECKED = 1, 59 HDCP_KEYS_STATE_CHECKING = 2, 60 HDCP_KEYS_STATE_VALID = 3, 61 HDCP_KEYS_STATE_AKSV_NOT_VALID = 4, 62 HDCP_KEYS_STATE_CHKSUM_MISMATCH = 5, 63 HDCP_KEYS_STATE_PROD_AKSV = 6, 64 HDCP_KEYS_STATE_RESERVED = 7, 65}; 66 67enum hdmi_ddc_read_write { 68 DDC_WRITE = 0, 69 DDC_READ = 1, 70}; 71 72enum hdmi_acr_cts { 73 ACR_NONE = 0, 74 ACR_32 = 1, 75 ACR_44 = 2, 76 ACR_48 = 3, 77}; 78 79#define REG_HDMI_CTRL 0x00000000 80#define HDMI_CTRL_ENABLE 0x00000001 81#define HDMI_CTRL_HDMI 0x00000002 82#define HDMI_CTRL_ENCRYPTED 0x00000004 83 84#define REG_HDMI_AUDIO_PKT_CTRL1 0x00000020 85#define HDMI_AUDIO_PKT_CTRL1_AUDIO_SAMPLE_SEND 0x00000001 86 87#define REG_HDMI_ACR_PKT_CTRL 0x00000024 88#define HDMI_ACR_PKT_CTRL_CONT 0x00000001 89#define HDMI_ACR_PKT_CTRL_SEND 0x00000002 90#define HDMI_ACR_PKT_CTRL_SELECT__MASK 0x00000030 91#define HDMI_ACR_PKT_CTRL_SELECT__SHIFT 4 92static inline uint32_t HDMI_ACR_PKT_CTRL_SELECT(enum hdmi_acr_cts val) 93{ 94 return ((val) << HDMI_ACR_PKT_CTRL_SELECT__SHIFT) & HDMI_ACR_PKT_CTRL_SELECT__MASK; 95} 96#define HDMI_ACR_PKT_CTRL_SOURCE 0x00000100 97#define HDMI_ACR_PKT_CTRL_N_MULTIPLIER__MASK 0x00070000 98#define HDMI_ACR_PKT_CTRL_N_MULTIPLIER__SHIFT 16 99static inline uint32_t HDMI_ACR_PKT_CTRL_N_MULTIPLIER(uint32_t val) 100{ 101 return ((val) << HDMI_ACR_PKT_CTRL_N_MULTIPLIER__SHIFT) & HDMI_ACR_PKT_CTRL_N_MULTIPLIER__MASK; 102} 103#define HDMI_ACR_PKT_CTRL_AUDIO_PRIORITY 0x80000000 104 105#define REG_HDMI_VBI_PKT_CTRL 0x00000028 106#define HDMI_VBI_PKT_CTRL_GC_ENABLE 0x00000010 107#define HDMI_VBI_PKT_CTRL_GC_EVERY_FRAME 0x00000020 108#define HDMI_VBI_PKT_CTRL_ISRC_SEND 0x00000100 109#define HDMI_VBI_PKT_CTRL_ISRC_CONTINUOUS 0x00000200 110#define HDMI_VBI_PKT_CTRL_ACP_SEND 0x00001000 111#define HDMI_VBI_PKT_CTRL_ACP_SRC_SW 0x00002000 112 113#define REG_HDMI_INFOFRAME_CTRL0 0x0000002c 114#define HDMI_INFOFRAME_CTRL0_AVI_SEND 0x00000001 115#define HDMI_INFOFRAME_CTRL0_AVI_CONT 0x00000002 116#define HDMI_INFOFRAME_CTRL0_AUDIO_INFO_SEND 0x00000010 117#define HDMI_INFOFRAME_CTRL0_AUDIO_INFO_CONT 0x00000020 118#define HDMI_INFOFRAME_CTRL0_AUDIO_INFO_SOURCE 0x00000040 119#define HDMI_INFOFRAME_CTRL0_AUDIO_INFO_UPDATE 0x00000080 120 121#define REG_HDMI_INFOFRAME_CTRL1 0x00000030 122#define HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE__MASK 0x0000003f 123#define HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE__SHIFT 0 124static inline uint32_t HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE(uint32_t val) 125{ 126 return ((val) << HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE__SHIFT) & HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE__MASK; 127} 128#define HDMI_INFOFRAME_CTRL1_AUDIO_INFO_LINE__MASK 0x00003f00 129#define HDMI_INFOFRAME_CTRL1_AUDIO_INFO_LINE__SHIFT 8 130static inline uint32_t HDMI_INFOFRAME_CTRL1_AUDIO_INFO_LINE(uint32_t val) 131{ 132 return ((val) << HDMI_INFOFRAME_CTRL1_AUDIO_INFO_LINE__SHIFT) & HDMI_INFOFRAME_CTRL1_AUDIO_INFO_LINE__MASK; 133} 134#define HDMI_INFOFRAME_CTRL1_MPEG_INFO_LINE__MASK 0x003f0000 135#define HDMI_INFOFRAME_CTRL1_MPEG_INFO_LINE__SHIFT 16 136static inline uint32_t HDMI_INFOFRAME_CTRL1_MPEG_INFO_LINE(uint32_t val) 137{ 138 return ((val) << HDMI_INFOFRAME_CTRL1_MPEG_INFO_LINE__SHIFT) & HDMI_INFOFRAME_CTRL1_MPEG_INFO_LINE__MASK; 139} 140#define HDMI_INFOFRAME_CTRL1_VENSPEC_INFO_LINE__MASK 0x3f000000 141#define HDMI_INFOFRAME_CTRL1_VENSPEC_INFO_LINE__SHIFT 24 142static inline uint32_t HDMI_INFOFRAME_CTRL1_VENSPEC_INFO_LINE(uint32_t val) 143{ 144 return ((val) << HDMI_INFOFRAME_CTRL1_VENSPEC_INFO_LINE__SHIFT) & HDMI_INFOFRAME_CTRL1_VENSPEC_INFO_LINE__MASK; 145} 146 147#define REG_HDMI_GEN_PKT_CTRL 0x00000034 148#define HDMI_GEN_PKT_CTRL_GENERIC0_SEND 0x00000001 149#define HDMI_GEN_PKT_CTRL_GENERIC0_CONT 0x00000002 150#define HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE__MASK 0x0000000c 151#define HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE__SHIFT 2 152static inline uint32_t HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE(uint32_t val) 153{ 154 return ((val) << HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE__SHIFT) & HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE__MASK; 155} 156#define HDMI_GEN_PKT_CTRL_GENERIC1_SEND 0x00000010 157#define HDMI_GEN_PKT_CTRL_GENERIC1_CONT 0x00000020 158#define HDMI_GEN_PKT_CTRL_GENERIC0_LINE__MASK 0x003f0000 159#define HDMI_GEN_PKT_CTRL_GENERIC0_LINE__SHIFT 16 160static inline uint32_t HDMI_GEN_PKT_CTRL_GENERIC0_LINE(uint32_t val) 161{ 162 return ((val) << HDMI_GEN_PKT_CTRL_GENERIC0_LINE__SHIFT) & HDMI_GEN_PKT_CTRL_GENERIC0_LINE__MASK; 163} 164#define HDMI_GEN_PKT_CTRL_GENERIC1_LINE__MASK 0x3f000000 165#define HDMI_GEN_PKT_CTRL_GENERIC1_LINE__SHIFT 24 166static inline uint32_t HDMI_GEN_PKT_CTRL_GENERIC1_LINE(uint32_t val) 167{ 168 return ((val) << HDMI_GEN_PKT_CTRL_GENERIC1_LINE__SHIFT) & HDMI_GEN_PKT_CTRL_GENERIC1_LINE__MASK; 169} 170 171#define REG_HDMI_GC 0x00000040 172#define HDMI_GC_MUTE 0x00000001 173 174#define REG_HDMI_AUDIO_PKT_CTRL2 0x00000044 175#define HDMI_AUDIO_PKT_CTRL2_OVERRIDE 0x00000001 176#define HDMI_AUDIO_PKT_CTRL2_LAYOUT 0x00000002 177 178static inline uint32_t REG_HDMI_AVI_INFO(uint32_t i0) { return 0x0000006c + 0x4*i0; } 179 180#define REG_HDMI_GENERIC0_HDR 0x00000084 181 182static inline uint32_t REG_HDMI_GENERIC0(uint32_t i0) { return 0x00000088 + 0x4*i0; } 183 184#define REG_HDMI_GENERIC1_HDR 0x000000a4 185 186static inline uint32_t REG_HDMI_GENERIC1(uint32_t i0) { return 0x000000a8 + 0x4*i0; } 187 188static inline uint32_t REG_HDMI_ACR(enum hdmi_acr_cts i0) { return 0x000000c4 + 0x8*i0; } 189 190static inline uint32_t REG_HDMI_ACR_0(enum hdmi_acr_cts i0) { return 0x000000c4 + 0x8*i0; } 191#define HDMI_ACR_0_CTS__MASK 0xfffff000 192#define HDMI_ACR_0_CTS__SHIFT 12 193static inline uint32_t HDMI_ACR_0_CTS(uint32_t val) 194{ 195 return ((val) << HDMI_ACR_0_CTS__SHIFT) & HDMI_ACR_0_CTS__MASK; 196} 197 198static inline uint32_t REG_HDMI_ACR_1(enum hdmi_acr_cts i0) { return 0x000000c8 + 0x8*i0; } 199#define HDMI_ACR_1_N__MASK 0xffffffff 200#define HDMI_ACR_1_N__SHIFT 0 201static inline uint32_t HDMI_ACR_1_N(uint32_t val) 202{ 203 return ((val) << HDMI_ACR_1_N__SHIFT) & HDMI_ACR_1_N__MASK; 204} 205 206#define REG_HDMI_AUDIO_INFO0 0x000000e4 207#define HDMI_AUDIO_INFO0_CHECKSUM__MASK 0x000000ff 208#define HDMI_AUDIO_INFO0_CHECKSUM__SHIFT 0 209static inline uint32_t HDMI_AUDIO_INFO0_CHECKSUM(uint32_t val) 210{ 211 return ((val) << HDMI_AUDIO_INFO0_CHECKSUM__SHIFT) & HDMI_AUDIO_INFO0_CHECKSUM__MASK; 212} 213#define HDMI_AUDIO_INFO0_CC__MASK 0x00000700 214#define HDMI_AUDIO_INFO0_CC__SHIFT 8 215static inline uint32_t HDMI_AUDIO_INFO0_CC(uint32_t val) 216{ 217 return ((val) << HDMI_AUDIO_INFO0_CC__SHIFT) & HDMI_AUDIO_INFO0_CC__MASK; 218} 219 220#define REG_HDMI_AUDIO_INFO1 0x000000e8 221#define HDMI_AUDIO_INFO1_CA__MASK 0x000000ff 222#define HDMI_AUDIO_INFO1_CA__SHIFT 0 223static inline uint32_t HDMI_AUDIO_INFO1_CA(uint32_t val) 224{ 225 return ((val) << HDMI_AUDIO_INFO1_CA__SHIFT) & HDMI_AUDIO_INFO1_CA__MASK; 226} 227#define HDMI_AUDIO_INFO1_LSV__MASK 0x00007800 228#define HDMI_AUDIO_INFO1_LSV__SHIFT 11 229static inline uint32_t HDMI_AUDIO_INFO1_LSV(uint32_t val) 230{ 231 return ((val) << HDMI_AUDIO_INFO1_LSV__SHIFT) & HDMI_AUDIO_INFO1_LSV__MASK; 232} 233#define HDMI_AUDIO_INFO1_DM_INH 0x00008000 234 235#define REG_HDMI_HDCP_CTRL 0x00000110 236#define HDMI_HDCP_CTRL_ENABLE 0x00000001 237#define HDMI_HDCP_CTRL_ENCRYPTION_ENABLE 0x00000100 238 239#define REG_HDMI_HDCP_DEBUG_CTRL 0x00000114 240#define HDMI_HDCP_DEBUG_CTRL_RNG_CIPHER 0x00000004 241 242#define REG_HDMI_HDCP_INT_CTRL 0x00000118 243#define HDMI_HDCP_INT_CTRL_AUTH_SUCCESS_INT 0x00000001 244#define HDMI_HDCP_INT_CTRL_AUTH_SUCCESS_ACK 0x00000002 245#define HDMI_HDCP_INT_CTRL_AUTH_SUCCESS_MASK 0x00000004 246#define HDMI_HDCP_INT_CTRL_AUTH_FAIL_INT 0x00000010 247#define HDMI_HDCP_INT_CTRL_AUTH_FAIL_ACK 0x00000020 248#define HDMI_HDCP_INT_CTRL_AUTH_FAIL_MASK 0x00000040 249#define HDMI_HDCP_INT_CTRL_AUTH_FAIL_INFO_ACK 0x00000080 250#define HDMI_HDCP_INT_CTRL_AUTH_XFER_REQ_INT 0x00000100 251#define HDMI_HDCP_INT_CTRL_AUTH_XFER_REQ_ACK 0x00000200 252#define HDMI_HDCP_INT_CTRL_AUTH_XFER_REQ_MASK 0x00000400 253#define HDMI_HDCP_INT_CTRL_AUTH_XFER_DONE_INT 0x00001000 254#define HDMI_HDCP_INT_CTRL_AUTH_XFER_DONE_ACK 0x00002000 255#define HDMI_HDCP_INT_CTRL_AUTH_XFER_DONE_MASK 0x00004000 256 257#define REG_HDMI_HDCP_LINK0_STATUS 0x0000011c 258#define HDMI_HDCP_LINK0_STATUS_AN_0_READY 0x00000100 259#define HDMI_HDCP_LINK0_STATUS_AN_1_READY 0x00000200 260#define HDMI_HDCP_LINK0_STATUS_RI_MATCHES 0x00001000 261#define HDMI_HDCP_LINK0_STATUS_V_MATCHES 0x00100000 262#define HDMI_HDCP_LINK0_STATUS_KEY_STATE__MASK 0x70000000 263#define HDMI_HDCP_LINK0_STATUS_KEY_STATE__SHIFT 28 264static inline uint32_t HDMI_HDCP_LINK0_STATUS_KEY_STATE(enum hdmi_hdcp_key_state val) 265{ 266 return ((val) << HDMI_HDCP_LINK0_STATUS_KEY_STATE__SHIFT) & HDMI_HDCP_LINK0_STATUS_KEY_STATE__MASK; 267} 268 269#define REG_HDMI_HDCP_DDC_CTRL_0 0x00000120 270#define HDMI_HDCP_DDC_CTRL_0_DISABLE 0x00000001 271 272#define REG_HDMI_HDCP_DDC_CTRL_1 0x00000124 273#define HDMI_HDCP_DDC_CTRL_1_FAILED_ACK 0x00000001 274 275#define REG_HDMI_HDCP_DDC_STATUS 0x00000128 276#define HDMI_HDCP_DDC_STATUS_XFER_REQ 0x00000010 277#define HDMI_HDCP_DDC_STATUS_XFER_DONE 0x00000400 278#define HDMI_HDCP_DDC_STATUS_ABORTED 0x00001000 279#define HDMI_HDCP_DDC_STATUS_TIMEOUT 0x00002000 280#define HDMI_HDCP_DDC_STATUS_NACK0 0x00004000 281#define HDMI_HDCP_DDC_STATUS_NACK1 0x00008000 282#define HDMI_HDCP_DDC_STATUS_FAILED 0x00010000 283 284#define REG_HDMI_HDCP_ENTROPY_CTRL0 0x0000012c 285 286#define REG_HDMI_HDCP_ENTROPY_CTRL1 0x0000025c 287 288#define REG_HDMI_HDCP_RESET 0x00000130 289#define HDMI_HDCP_RESET_LINK0_DEAUTHENTICATE 0x00000001 290 291#define REG_HDMI_HDCP_RCVPORT_DATA0 0x00000134 292 293#define REG_HDMI_HDCP_RCVPORT_DATA1 0x00000138 294 295#define REG_HDMI_HDCP_RCVPORT_DATA2_0 0x0000013c 296 297#define REG_HDMI_HDCP_RCVPORT_DATA2_1 0x00000140 298 299#define REG_HDMI_HDCP_RCVPORT_DATA3 0x00000144 300 301#define REG_HDMI_HDCP_RCVPORT_DATA4 0x00000148 302 303#define REG_HDMI_HDCP_RCVPORT_DATA5 0x0000014c 304 305#define REG_HDMI_HDCP_RCVPORT_DATA6 0x00000150 306 307#define REG_HDMI_HDCP_RCVPORT_DATA7 0x00000154 308 309#define REG_HDMI_HDCP_RCVPORT_DATA8 0x00000158 310 311#define REG_HDMI_HDCP_RCVPORT_DATA9 0x0000015c 312 313#define REG_HDMI_HDCP_RCVPORT_DATA10 0x00000160 314 315#define REG_HDMI_HDCP_RCVPORT_DATA11 0x00000164 316 317#define REG_HDMI_HDCP_RCVPORT_DATA12 0x00000168 318 319#define REG_HDMI_VENSPEC_INFO0 0x0000016c 320 321#define REG_HDMI_VENSPEC_INFO1 0x00000170 322 323#define REG_HDMI_VENSPEC_INFO2 0x00000174 324 325#define REG_HDMI_VENSPEC_INFO3 0x00000178 326 327#define REG_HDMI_VENSPEC_INFO4 0x0000017c 328 329#define REG_HDMI_VENSPEC_INFO5 0x00000180 330 331#define REG_HDMI_VENSPEC_INFO6 0x00000184 332 333#define REG_HDMI_AUDIO_CFG 0x000001d0 334#define HDMI_AUDIO_CFG_ENGINE_ENABLE 0x00000001 335#define HDMI_AUDIO_CFG_FIFO_WATERMARK__MASK 0x000000f0 336#define HDMI_AUDIO_CFG_FIFO_WATERMARK__SHIFT 4 337static inline uint32_t HDMI_AUDIO_CFG_FIFO_WATERMARK(uint32_t val) 338{ 339 return ((val) << HDMI_AUDIO_CFG_FIFO_WATERMARK__SHIFT) & HDMI_AUDIO_CFG_FIFO_WATERMARK__MASK; 340} 341 342#define REG_HDMI_USEC_REFTIMER 0x00000208 343 344#define REG_HDMI_DDC_CTRL 0x0000020c 345#define HDMI_DDC_CTRL_GO 0x00000001 346#define HDMI_DDC_CTRL_SOFT_RESET 0x00000002 347#define HDMI_DDC_CTRL_SEND_RESET 0x00000004 348#define HDMI_DDC_CTRL_SW_STATUS_RESET 0x00000008 349#define HDMI_DDC_CTRL_TRANSACTION_CNT__MASK 0x00300000 350#define HDMI_DDC_CTRL_TRANSACTION_CNT__SHIFT 20 351static inline uint32_t HDMI_DDC_CTRL_TRANSACTION_CNT(uint32_t val) 352{ 353 return ((val) << HDMI_DDC_CTRL_TRANSACTION_CNT__SHIFT) & HDMI_DDC_CTRL_TRANSACTION_CNT__MASK; 354} 355 356#define REG_HDMI_DDC_ARBITRATION 0x00000210 357#define HDMI_DDC_ARBITRATION_HW_ARBITRATION 0x00000010 358 359#define REG_HDMI_DDC_INT_CTRL 0x00000214 360#define HDMI_DDC_INT_CTRL_SW_DONE_INT 0x00000001 361#define HDMI_DDC_INT_CTRL_SW_DONE_ACK 0x00000002 362#define HDMI_DDC_INT_CTRL_SW_DONE_MASK 0x00000004 363 364#define REG_HDMI_DDC_SW_STATUS 0x00000218 365#define HDMI_DDC_SW_STATUS_NACK0 0x00001000 366#define HDMI_DDC_SW_STATUS_NACK1 0x00002000 367#define HDMI_DDC_SW_STATUS_NACK2 0x00004000 368#define HDMI_DDC_SW_STATUS_NACK3 0x00008000 369 370#define REG_HDMI_DDC_HW_STATUS 0x0000021c 371#define HDMI_DDC_HW_STATUS_DONE 0x00000008 372 373#define REG_HDMI_DDC_SPEED 0x00000220 374#define HDMI_DDC_SPEED_THRESHOLD__MASK 0x00000003 375#define HDMI_DDC_SPEED_THRESHOLD__SHIFT 0 376static inline uint32_t HDMI_DDC_SPEED_THRESHOLD(uint32_t val) 377{ 378 return ((val) << HDMI_DDC_SPEED_THRESHOLD__SHIFT) & HDMI_DDC_SPEED_THRESHOLD__MASK; 379} 380#define HDMI_DDC_SPEED_PRESCALE__MASK 0xffff0000 381#define HDMI_DDC_SPEED_PRESCALE__SHIFT 16 382static inline uint32_t HDMI_DDC_SPEED_PRESCALE(uint32_t val) 383{ 384 return ((val) << HDMI_DDC_SPEED_PRESCALE__SHIFT) & HDMI_DDC_SPEED_PRESCALE__MASK; 385} 386 387#define REG_HDMI_DDC_SETUP 0x00000224 388#define HDMI_DDC_SETUP_TIMEOUT__MASK 0xff000000 389#define HDMI_DDC_SETUP_TIMEOUT__SHIFT 24 390static inline uint32_t HDMI_DDC_SETUP_TIMEOUT(uint32_t val) 391{ 392 return ((val) << HDMI_DDC_SETUP_TIMEOUT__SHIFT) & HDMI_DDC_SETUP_TIMEOUT__MASK; 393} 394 395static inline uint32_t REG_HDMI_I2C_TRANSACTION(uint32_t i0) { return 0x00000228 + 0x4*i0; } 396 397static inline uint32_t REG_HDMI_I2C_TRANSACTION_REG(uint32_t i0) { return 0x00000228 + 0x4*i0; } 398#define HDMI_I2C_TRANSACTION_REG_RW__MASK 0x00000001 399#define HDMI_I2C_TRANSACTION_REG_RW__SHIFT 0 400static inline uint32_t HDMI_I2C_TRANSACTION_REG_RW(enum hdmi_ddc_read_write val) 401{ 402 return ((val) << HDMI_I2C_TRANSACTION_REG_RW__SHIFT) & HDMI_I2C_TRANSACTION_REG_RW__MASK; 403} 404#define HDMI_I2C_TRANSACTION_REG_STOP_ON_NACK 0x00000100 405#define HDMI_I2C_TRANSACTION_REG_START 0x00001000 406#define HDMI_I2C_TRANSACTION_REG_STOP 0x00002000 407#define HDMI_I2C_TRANSACTION_REG_CNT__MASK 0x00ff0000 408#define HDMI_I2C_TRANSACTION_REG_CNT__SHIFT 16 409static inline uint32_t HDMI_I2C_TRANSACTION_REG_CNT(uint32_t val) 410{ 411 return ((val) << HDMI_I2C_TRANSACTION_REG_CNT__SHIFT) & HDMI_I2C_TRANSACTION_REG_CNT__MASK; 412} 413 414#define REG_HDMI_DDC_DATA 0x00000238 415#define HDMI_DDC_DATA_DATA_RW__MASK 0x00000001 416#define HDMI_DDC_DATA_DATA_RW__SHIFT 0 417static inline uint32_t HDMI_DDC_DATA_DATA_RW(enum hdmi_ddc_read_write val) 418{ 419 return ((val) << HDMI_DDC_DATA_DATA_RW__SHIFT) & HDMI_DDC_DATA_DATA_RW__MASK; 420} 421#define HDMI_DDC_DATA_DATA__MASK 0x0000ff00 422#define HDMI_DDC_DATA_DATA__SHIFT 8 423static inline uint32_t HDMI_DDC_DATA_DATA(uint32_t val) 424{ 425 return ((val) << HDMI_DDC_DATA_DATA__SHIFT) & HDMI_DDC_DATA_DATA__MASK; 426} 427#define HDMI_DDC_DATA_INDEX__MASK 0x00ff0000 428#define HDMI_DDC_DATA_INDEX__SHIFT 16 429static inline uint32_t HDMI_DDC_DATA_INDEX(uint32_t val) 430{ 431 return ((val) << HDMI_DDC_DATA_INDEX__SHIFT) & HDMI_DDC_DATA_INDEX__MASK; 432} 433#define HDMI_DDC_DATA_INDEX_WRITE 0x80000000 434 435#define REG_HDMI_HDCP_SHA_CTRL 0x0000023c 436 437#define REG_HDMI_HDCP_SHA_STATUS 0x00000240 438#define HDMI_HDCP_SHA_STATUS_BLOCK_DONE 0x00000001 439#define HDMI_HDCP_SHA_STATUS_COMP_DONE 0x00000010 440 441#define REG_HDMI_HDCP_SHA_DATA 0x00000244 442#define HDMI_HDCP_SHA_DATA_DONE 0x00000001 443 444#define REG_HDMI_HPD_INT_STATUS 0x00000250 445#define HDMI_HPD_INT_STATUS_INT 0x00000001 446#define HDMI_HPD_INT_STATUS_CABLE_DETECTED 0x00000002 447 448#define REG_HDMI_HPD_INT_CTRL 0x00000254 449#define HDMI_HPD_INT_CTRL_INT_ACK 0x00000001 450#define HDMI_HPD_INT_CTRL_INT_CONNECT 0x00000002 451#define HDMI_HPD_INT_CTRL_INT_EN 0x00000004 452#define HDMI_HPD_INT_CTRL_RX_INT_ACK 0x00000010 453#define HDMI_HPD_INT_CTRL_RX_INT_EN 0x00000020 454#define HDMI_HPD_INT_CTRL_RCV_PLUGIN_DET_MASK 0x00000200 455 456#define REG_HDMI_HPD_CTRL 0x00000258 457#define HDMI_HPD_CTRL_TIMEOUT__MASK 0x00001fff 458#define HDMI_HPD_CTRL_TIMEOUT__SHIFT 0 459static inline uint32_t HDMI_HPD_CTRL_TIMEOUT(uint32_t val) 460{ 461 return ((val) << HDMI_HPD_CTRL_TIMEOUT__SHIFT) & HDMI_HPD_CTRL_TIMEOUT__MASK; 462} 463#define HDMI_HPD_CTRL_ENABLE 0x10000000 464 465#define REG_HDMI_DDC_REF 0x0000027c 466#define HDMI_DDC_REF_REFTIMER_ENABLE 0x00010000 467#define HDMI_DDC_REF_REFTIMER__MASK 0x0000ffff 468#define HDMI_DDC_REF_REFTIMER__SHIFT 0 469static inline uint32_t HDMI_DDC_REF_REFTIMER(uint32_t val) 470{ 471 return ((val) << HDMI_DDC_REF_REFTIMER__SHIFT) & HDMI_DDC_REF_REFTIMER__MASK; 472} 473 474#define REG_HDMI_HDCP_SW_UPPER_AKSV 0x00000284 475 476#define REG_HDMI_HDCP_SW_LOWER_AKSV 0x00000288 477 478#define REG_HDMI_CEC_CTRL 0x0000028c 479 480#define REG_HDMI_CEC_WR_DATA 0x00000290 481 482#define REG_HDMI_CEC_CEC_RETRANSMIT 0x00000294 483 484#define REG_HDMI_CEC_STATUS 0x00000298 485 486#define REG_HDMI_CEC_INT 0x0000029c 487 488#define REG_HDMI_CEC_ADDR 0x000002a0 489 490#define REG_HDMI_CEC_TIME 0x000002a4 491 492#define REG_HDMI_CEC_REFTIMER 0x000002a8 493 494#define REG_HDMI_CEC_RD_DATA 0x000002ac 495 496#define REG_HDMI_CEC_RD_FILTER 0x000002b0 497 498#define REG_HDMI_ACTIVE_HSYNC 0x000002b4 499#define HDMI_ACTIVE_HSYNC_START__MASK 0x00001fff 500#define HDMI_ACTIVE_HSYNC_START__SHIFT 0 501static inline uint32_t HDMI_ACTIVE_HSYNC_START(uint32_t val) 502{ 503 return ((val) << HDMI_ACTIVE_HSYNC_START__SHIFT) & HDMI_ACTIVE_HSYNC_START__MASK; 504} 505#define HDMI_ACTIVE_HSYNC_END__MASK 0x0fff0000 506#define HDMI_ACTIVE_HSYNC_END__SHIFT 16 507static inline uint32_t HDMI_ACTIVE_HSYNC_END(uint32_t val) 508{ 509 return ((val) << HDMI_ACTIVE_HSYNC_END__SHIFT) & HDMI_ACTIVE_HSYNC_END__MASK; 510} 511 512#define REG_HDMI_ACTIVE_VSYNC 0x000002b8 513#define HDMI_ACTIVE_VSYNC_START__MASK 0x00001fff 514#define HDMI_ACTIVE_VSYNC_START__SHIFT 0 515static inline uint32_t HDMI_ACTIVE_VSYNC_START(uint32_t val) 516{ 517 return ((val) << HDMI_ACTIVE_VSYNC_START__SHIFT) & HDMI_ACTIVE_VSYNC_START__MASK; 518} 519#define HDMI_ACTIVE_VSYNC_END__MASK 0x1fff0000 520#define HDMI_ACTIVE_VSYNC_END__SHIFT 16 521static inline uint32_t HDMI_ACTIVE_VSYNC_END(uint32_t val) 522{ 523 return ((val) << HDMI_ACTIVE_VSYNC_END__SHIFT) & HDMI_ACTIVE_VSYNC_END__MASK; 524} 525 526#define REG_HDMI_VSYNC_ACTIVE_F2 0x000002bc 527#define HDMI_VSYNC_ACTIVE_F2_START__MASK 0x00001fff 528#define HDMI_VSYNC_ACTIVE_F2_START__SHIFT 0 529static inline uint32_t HDMI_VSYNC_ACTIVE_F2_START(uint32_t val) 530{ 531 return ((val) << HDMI_VSYNC_ACTIVE_F2_START__SHIFT) & HDMI_VSYNC_ACTIVE_F2_START__MASK; 532} 533#define HDMI_VSYNC_ACTIVE_F2_END__MASK 0x1fff0000 534#define HDMI_VSYNC_ACTIVE_F2_END__SHIFT 16 535static inline uint32_t HDMI_VSYNC_ACTIVE_F2_END(uint32_t val) 536{ 537 return ((val) << HDMI_VSYNC_ACTIVE_F2_END__SHIFT) & HDMI_VSYNC_ACTIVE_F2_END__MASK; 538} 539 540#define REG_HDMI_TOTAL 0x000002c0 541#define HDMI_TOTAL_H_TOTAL__MASK 0x00001fff 542#define HDMI_TOTAL_H_TOTAL__SHIFT 0 543static inline uint32_t HDMI_TOTAL_H_TOTAL(uint32_t val) 544{ 545 return ((val) << HDMI_TOTAL_H_TOTAL__SHIFT) & HDMI_TOTAL_H_TOTAL__MASK; 546} 547#define HDMI_TOTAL_V_TOTAL__MASK 0x1fff0000 548#define HDMI_TOTAL_V_TOTAL__SHIFT 16 549static inline uint32_t HDMI_TOTAL_V_TOTAL(uint32_t val) 550{ 551 return ((val) << HDMI_TOTAL_V_TOTAL__SHIFT) & HDMI_TOTAL_V_TOTAL__MASK; 552} 553 554#define REG_HDMI_VSYNC_TOTAL_F2 0x000002c4 555#define HDMI_VSYNC_TOTAL_F2_V_TOTAL__MASK 0x00001fff 556#define HDMI_VSYNC_TOTAL_F2_V_TOTAL__SHIFT 0 557static inline uint32_t HDMI_VSYNC_TOTAL_F2_V_TOTAL(uint32_t val) 558{ 559 return ((val) << HDMI_VSYNC_TOTAL_F2_V_TOTAL__SHIFT) & HDMI_VSYNC_TOTAL_F2_V_TOTAL__MASK; 560} 561 562#define REG_HDMI_FRAME_CTRL 0x000002c8 563#define HDMI_FRAME_CTRL_RGB_MUX_SEL_BGR 0x00001000 564#define HDMI_FRAME_CTRL_VSYNC_LOW 0x10000000 565#define HDMI_FRAME_CTRL_HSYNC_LOW 0x20000000 566#define HDMI_FRAME_CTRL_INTERLACED_EN 0x80000000 567 568#define REG_HDMI_AUD_INT 0x000002cc 569#define HDMI_AUD_INT_AUD_FIFO_URUN_INT 0x00000001 570#define HDMI_AUD_INT_AUD_FIFO_URAN_MASK 0x00000002 571#define HDMI_AUD_INT_AUD_SAM_DROP_INT 0x00000004 572#define HDMI_AUD_INT_AUD_SAM_DROP_MASK 0x00000008 573 574#define REG_HDMI_PHY_CTRL 0x000002d4 575#define HDMI_PHY_CTRL_SW_RESET_PLL 0x00000001 576#define HDMI_PHY_CTRL_SW_RESET_PLL_LOW 0x00000002 577#define HDMI_PHY_CTRL_SW_RESET 0x00000004 578#define HDMI_PHY_CTRL_SW_RESET_LOW 0x00000008 579 580#define REG_HDMI_CEC_WR_RANGE 0x000002dc 581 582#define REG_HDMI_CEC_RD_RANGE 0x000002e0 583 584#define REG_HDMI_VERSION 0x000002e4 585 586#define REG_HDMI_CEC_COMPL_CTL 0x00000360 587 588#define REG_HDMI_CEC_RD_START_RANGE 0x00000364 589 590#define REG_HDMI_CEC_RD_TOTAL_RANGE 0x00000368 591 592#define REG_HDMI_CEC_RD_ERR_RESP_LO 0x0000036c 593 594#define REG_HDMI_CEC_WR_CHECK_CONFIG 0x00000370 595 596#define REG_HDMI_8x60_PHY_REG0 0x00000000 597#define HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__MASK 0x0000001c 598#define HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__SHIFT 2 599static inline uint32_t HDMI_8x60_PHY_REG0_DESER_DEL_CTRL(uint32_t val) 600{ 601 return ((val) << HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__SHIFT) & HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__MASK; 602} 603 604#define REG_HDMI_8x60_PHY_REG1 0x00000004 605#define HDMI_8x60_PHY_REG1_DTEST_MUX_SEL__MASK 0x000000f0 606#define HDMI_8x60_PHY_REG1_DTEST_MUX_SEL__SHIFT 4 607static inline uint32_t HDMI_8x60_PHY_REG1_DTEST_MUX_SEL(uint32_t val) 608{ 609 return ((val) << HDMI_8x60_PHY_REG1_DTEST_MUX_SEL__SHIFT) & HDMI_8x60_PHY_REG1_DTEST_MUX_SEL__MASK; 610} 611#define HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL__MASK 0x0000000f 612#define HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL__SHIFT 0 613static inline uint32_t HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL(uint32_t val) 614{ 615 return ((val) << HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL__SHIFT) & HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL__MASK; 616} 617 618#define REG_HDMI_8x60_PHY_REG2 0x00000008 619#define HDMI_8x60_PHY_REG2_PD_DESER 0x00000001 620#define HDMI_8x60_PHY_REG2_PD_DRIVE_1 0x00000002 621#define HDMI_8x60_PHY_REG2_PD_DRIVE_2 0x00000004 622#define HDMI_8x60_PHY_REG2_PD_DRIVE_3 0x00000008 623#define HDMI_8x60_PHY_REG2_PD_DRIVE_4 0x00000010 624#define HDMI_8x60_PHY_REG2_PD_PLL 0x00000020 625#define HDMI_8x60_PHY_REG2_PD_PWRGEN 0x00000040 626#define HDMI_8x60_PHY_REG2_RCV_SENSE_EN 0x00000080 627 628#define REG_HDMI_8x60_PHY_REG3 0x0000000c 629#define HDMI_8x60_PHY_REG3_PLL_ENABLE 0x00000001 630 631#define REG_HDMI_8x60_PHY_REG4 0x00000010 632 633#define REG_HDMI_8x60_PHY_REG5 0x00000014 634 635#define REG_HDMI_8x60_PHY_REG6 0x00000018 636 637#define REG_HDMI_8x60_PHY_REG7 0x0000001c 638 639#define REG_HDMI_8x60_PHY_REG8 0x00000020 640 641#define REG_HDMI_8x60_PHY_REG9 0x00000024 642 643#define REG_HDMI_8x60_PHY_REG10 0x00000028 644 645#define REG_HDMI_8x60_PHY_REG11 0x0000002c 646 647#define REG_HDMI_8x60_PHY_REG12 0x00000030 648#define HDMI_8x60_PHY_REG12_RETIMING_EN 0x00000001 649#define HDMI_8x60_PHY_REG12_PLL_LOCK_DETECT_EN 0x00000002 650#define HDMI_8x60_PHY_REG12_FORCE_LOCK 0x00000010 651 652#define REG_HDMI_8960_PHY_REG0 0x00000000 653 654#define REG_HDMI_8960_PHY_REG1 0x00000004 655 656#define REG_HDMI_8960_PHY_REG2 0x00000008 657 658#define REG_HDMI_8960_PHY_REG3 0x0000000c 659 660#define REG_HDMI_8960_PHY_REG4 0x00000010 661 662#define REG_HDMI_8960_PHY_REG5 0x00000014 663 664#define REG_HDMI_8960_PHY_REG6 0x00000018 665 666#define REG_HDMI_8960_PHY_REG7 0x0000001c 667 668#define REG_HDMI_8960_PHY_REG8 0x00000020 669 670#define REG_HDMI_8960_PHY_REG9 0x00000024 671 672#define REG_HDMI_8960_PHY_REG10 0x00000028 673 674#define REG_HDMI_8960_PHY_REG11 0x0000002c 675 676#define REG_HDMI_8960_PHY_REG12 0x00000030 677#define HDMI_8960_PHY_REG12_SW_RESET 0x00000020 678#define HDMI_8960_PHY_REG12_PWRDN_B 0x00000080 679 680#define REG_HDMI_8960_PHY_REG_BIST_CFG 0x00000034 681 682#define REG_HDMI_8960_PHY_DEBUG_BUS_SEL 0x00000038 683 684#define REG_HDMI_8960_PHY_REG_MISC0 0x0000003c 685 686#define REG_HDMI_8960_PHY_REG13 0x00000040 687 688#define REG_HDMI_8960_PHY_REG14 0x00000044 689 690#define REG_HDMI_8960_PHY_REG15 0x00000048 691 692#define REG_HDMI_8960_PHY_PLL_REFCLK_CFG 0x00000000 693 694#define REG_HDMI_8960_PHY_PLL_CHRG_PUMP_CFG 0x00000004 695 696#define REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG0 0x00000008 697 698#define REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG1 0x0000000c 699 700#define REG_HDMI_8960_PHY_PLL_IDAC_ADJ_CFG 0x00000010 701 702#define REG_HDMI_8960_PHY_PLL_I_VI_KVCO_CFG 0x00000014 703 704#define REG_HDMI_8960_PHY_PLL_PWRDN_B 0x00000018 705#define HDMI_8960_PHY_PLL_PWRDN_B_PD_PLL 0x00000002 706#define HDMI_8960_PHY_PLL_PWRDN_B_PLL_PWRDN_B 0x00000008 707 708#define REG_HDMI_8960_PHY_PLL_SDM_CFG0 0x0000001c 709 710#define REG_HDMI_8960_PHY_PLL_SDM_CFG1 0x00000020 711 712#define REG_HDMI_8960_PHY_PLL_SDM_CFG2 0x00000024 713 714#define REG_HDMI_8960_PHY_PLL_SDM_CFG3 0x00000028 715 716#define REG_HDMI_8960_PHY_PLL_SDM_CFG4 0x0000002c 717 718#define REG_HDMI_8960_PHY_PLL_SSC_CFG0 0x00000030 719 720#define REG_HDMI_8960_PHY_PLL_SSC_CFG1 0x00000034 721 722#define REG_HDMI_8960_PHY_PLL_SSC_CFG2 0x00000038 723 724#define REG_HDMI_8960_PHY_PLL_SSC_CFG3 0x0000003c 725 726#define REG_HDMI_8960_PHY_PLL_LOCKDET_CFG0 0x00000040 727 728#define REG_HDMI_8960_PHY_PLL_LOCKDET_CFG1 0x00000044 729 730#define REG_HDMI_8960_PHY_PLL_LOCKDET_CFG2 0x00000048 731 732#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG0 0x0000004c 733 734#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG1 0x00000050 735 736#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG2 0x00000054 737 738#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG3 0x00000058 739 740#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG4 0x0000005c 741 742#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG5 0x00000060 743 744#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG6 0x00000064 745 746#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG7 0x00000068 747 748#define REG_HDMI_8960_PHY_PLL_DEBUG_SEL 0x0000006c 749 750#define REG_HDMI_8960_PHY_PLL_MISC0 0x00000070 751 752#define REG_HDMI_8960_PHY_PLL_MISC1 0x00000074 753 754#define REG_HDMI_8960_PHY_PLL_MISC2 0x00000078 755 756#define REG_HDMI_8960_PHY_PLL_MISC3 0x0000007c 757 758#define REG_HDMI_8960_PHY_PLL_MISC4 0x00000080 759 760#define REG_HDMI_8960_PHY_PLL_MISC5 0x00000084 761 762#define REG_HDMI_8960_PHY_PLL_MISC6 0x00000088 763 764#define REG_HDMI_8960_PHY_PLL_DEBUG_BUS0 0x0000008c 765 766#define REG_HDMI_8960_PHY_PLL_DEBUG_BUS1 0x00000090 767 768#define REG_HDMI_8960_PHY_PLL_DEBUG_BUS2 0x00000094 769 770#define REG_HDMI_8960_PHY_PLL_STATUS0 0x00000098 771#define HDMI_8960_PHY_PLL_STATUS0_PLL_LOCK 0x00000001 772 773#define REG_HDMI_8960_PHY_PLL_STATUS1 0x0000009c 774 775#define REG_HDMI_8x74_ANA_CFG0 0x00000000 776 777#define REG_HDMI_8x74_ANA_CFG1 0x00000004 778 779#define REG_HDMI_8x74_ANA_CFG2 0x00000008 780 781#define REG_HDMI_8x74_ANA_CFG3 0x0000000c 782 783#define REG_HDMI_8x74_PD_CTRL0 0x00000010 784 785#define REG_HDMI_8x74_PD_CTRL1 0x00000014 786 787#define REG_HDMI_8x74_GLB_CFG 0x00000018 788 789#define REG_HDMI_8x74_DCC_CFG0 0x0000001c 790 791#define REG_HDMI_8x74_DCC_CFG1 0x00000020 792 793#define REG_HDMI_8x74_TXCAL_CFG0 0x00000024 794 795#define REG_HDMI_8x74_TXCAL_CFG1 0x00000028 796 797#define REG_HDMI_8x74_TXCAL_CFG2 0x0000002c 798 799#define REG_HDMI_8x74_TXCAL_CFG3 0x00000030 800 801#define REG_HDMI_8x74_BIST_CFG0 0x00000034 802 803#define REG_HDMI_8x74_BIST_PATN0 0x0000003c 804 805#define REG_HDMI_8x74_BIST_PATN1 0x00000040 806 807#define REG_HDMI_8x74_BIST_PATN2 0x00000044 808 809#define REG_HDMI_8x74_BIST_PATN3 0x00000048 810 811#define REG_HDMI_8x74_STATUS 0x0000005c 812 813#define REG_HDMI_28nm_PHY_PLL_REFCLK_CFG 0x00000000 814 815#define REG_HDMI_28nm_PHY_PLL_POSTDIV1_CFG 0x00000004 816 817#define REG_HDMI_28nm_PHY_PLL_CHGPUMP_CFG 0x00000008 818 819#define REG_HDMI_28nm_PHY_PLL_VCOLPF_CFG 0x0000000c 820 821#define REG_HDMI_28nm_PHY_PLL_VREG_CFG 0x00000010 822 823#define REG_HDMI_28nm_PHY_PLL_PWRGEN_CFG 0x00000014 824 825#define REG_HDMI_28nm_PHY_PLL_DMUX_CFG 0x00000018 826 827#define REG_HDMI_28nm_PHY_PLL_AMUX_CFG 0x0000001c 828 829#define REG_HDMI_28nm_PHY_PLL_GLB_CFG 0x00000020 830#define HDMI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B 0x00000001 831#define HDMI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B 0x00000002 832#define HDMI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B 0x00000004 833#define HDMI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE 0x00000008 834 835#define REG_HDMI_28nm_PHY_PLL_POSTDIV2_CFG 0x00000024 836 837#define REG_HDMI_28nm_PHY_PLL_POSTDIV3_CFG 0x00000028 838 839#define REG_HDMI_28nm_PHY_PLL_LPFR_CFG 0x0000002c 840 841#define REG_HDMI_28nm_PHY_PLL_LPFC1_CFG 0x00000030 842 843#define REG_HDMI_28nm_PHY_PLL_LPFC2_CFG 0x00000034 844 845#define REG_HDMI_28nm_PHY_PLL_SDM_CFG0 0x00000038 846 847#define REG_HDMI_28nm_PHY_PLL_SDM_CFG1 0x0000003c 848 849#define REG_HDMI_28nm_PHY_PLL_SDM_CFG2 0x00000040 850 851#define REG_HDMI_28nm_PHY_PLL_SDM_CFG3 0x00000044 852 853#define REG_HDMI_28nm_PHY_PLL_SDM_CFG4 0x00000048 854 855#define REG_HDMI_28nm_PHY_PLL_SSC_CFG0 0x0000004c 856 857#define REG_HDMI_28nm_PHY_PLL_SSC_CFG1 0x00000050 858 859#define REG_HDMI_28nm_PHY_PLL_SSC_CFG2 0x00000054 860 861#define REG_HDMI_28nm_PHY_PLL_SSC_CFG3 0x00000058 862 863#define REG_HDMI_28nm_PHY_PLL_LKDET_CFG0 0x0000005c 864 865#define REG_HDMI_28nm_PHY_PLL_LKDET_CFG1 0x00000060 866 867#define REG_HDMI_28nm_PHY_PLL_LKDET_CFG2 0x00000064 868 869#define REG_HDMI_28nm_PHY_PLL_TEST_CFG 0x00000068 870#define HDMI_28nm_PHY_PLL_TEST_CFG_PLL_SW_RESET 0x00000001 871 872#define REG_HDMI_28nm_PHY_PLL_CAL_CFG0 0x0000006c 873 874#define REG_HDMI_28nm_PHY_PLL_CAL_CFG1 0x00000070 875 876#define REG_HDMI_28nm_PHY_PLL_CAL_CFG2 0x00000074 877 878#define REG_HDMI_28nm_PHY_PLL_CAL_CFG3 0x00000078 879 880#define REG_HDMI_28nm_PHY_PLL_CAL_CFG4 0x0000007c 881 882#define REG_HDMI_28nm_PHY_PLL_CAL_CFG5 0x00000080 883 884#define REG_HDMI_28nm_PHY_PLL_CAL_CFG6 0x00000084 885 886#define REG_HDMI_28nm_PHY_PLL_CAL_CFG7 0x00000088 887 888#define REG_HDMI_28nm_PHY_PLL_CAL_CFG8 0x0000008c 889 890#define REG_HDMI_28nm_PHY_PLL_CAL_CFG9 0x00000090 891 892#define REG_HDMI_28nm_PHY_PLL_CAL_CFG10 0x00000094 893 894#define REG_HDMI_28nm_PHY_PLL_CAL_CFG11 0x00000098 895 896#define REG_HDMI_28nm_PHY_PLL_EFUSE_CFG 0x0000009c 897 898#define REG_HDMI_28nm_PHY_PLL_DEBUG_BUS_SEL 0x000000a0 899 900#define REG_HDMI_28nm_PHY_PLL_STATUS 0x000000c0 901 902#define REG_HDMI_8996_PHY_CFG 0x00000000 903 904#define REG_HDMI_8996_PHY_PD_CTL 0x00000004 905 906#define REG_HDMI_8996_PHY_MODE 0x00000008 907 908#define REG_HDMI_8996_PHY_MISR_CLEAR 0x0000000c 909 910#define REG_HDMI_8996_PHY_TX0_TX1_BIST_CFG0 0x00000010 911 912#define REG_HDMI_8996_PHY_TX0_TX1_BIST_CFG1 0x00000014 913 914#define REG_HDMI_8996_PHY_TX0_TX1_PRBS_SEED_BYTE0 0x00000018 915 916#define REG_HDMI_8996_PHY_TX0_TX1_PRBS_SEED_BYTE1 0x0000001c 917 918#define REG_HDMI_8996_PHY_TX0_TX1_BIST_PATTERN0 0x00000020 919 920#define REG_HDMI_8996_PHY_TX0_TX1_BIST_PATTERN1 0x00000024 921 922#define REG_HDMI_8996_PHY_TX2_TX3_BIST_CFG0 0x00000028 923 924#define REG_HDMI_8996_PHY_TX2_TX3_BIST_CFG1 0x0000002c 925 926#define REG_HDMI_8996_PHY_TX2_TX3_PRBS_SEED_BYTE0 0x00000030 927 928#define REG_HDMI_8996_PHY_TX2_TX3_PRBS_SEED_BYTE1 0x00000034 929 930#define REG_HDMI_8996_PHY_TX2_TX3_BIST_PATTERN0 0x00000038 931 932#define REG_HDMI_8996_PHY_TX2_TX3_BIST_PATTERN1 0x0000003c 933 934#define REG_HDMI_8996_PHY_DEBUG_BUS_SEL 0x00000040 935 936#define REG_HDMI_8996_PHY_TXCAL_CFG0 0x00000044 937 938#define REG_HDMI_8996_PHY_TXCAL_CFG1 0x00000048 939 940#define REG_HDMI_8996_PHY_TX0_TX1_LANE_CTL 0x0000004c 941 942#define REG_HDMI_8996_PHY_TX2_TX3_LANE_CTL 0x00000050 943 944#define REG_HDMI_8996_PHY_LANE_BIST_CONFIG 0x00000054 945 946#define REG_HDMI_8996_PHY_CLOCK 0x00000058 947 948#define REG_HDMI_8996_PHY_MISC1 0x0000005c 949 950#define REG_HDMI_8996_PHY_MISC2 0x00000060 951 952#define REG_HDMI_8996_PHY_TX0_TX1_BIST_STATUS0 0x00000064 953 954#define REG_HDMI_8996_PHY_TX0_TX1_BIST_STATUS1 0x00000068 955 956#define REG_HDMI_8996_PHY_TX0_TX1_BIST_STATUS2 0x0000006c 957 958#define REG_HDMI_8996_PHY_TX2_TX3_BIST_STATUS0 0x00000070 959 960#define REG_HDMI_8996_PHY_TX2_TX3_BIST_STATUS1 0x00000074 961 962#define REG_HDMI_8996_PHY_TX2_TX3_BIST_STATUS2 0x00000078 963 964#define REG_HDMI_8996_PHY_PRE_MISR_STATUS0 0x0000007c 965 966#define REG_HDMI_8996_PHY_PRE_MISR_STATUS1 0x00000080 967 968#define REG_HDMI_8996_PHY_PRE_MISR_STATUS2 0x00000084 969 970#define REG_HDMI_8996_PHY_PRE_MISR_STATUS3 0x00000088 971 972#define REG_HDMI_8996_PHY_POST_MISR_STATUS0 0x0000008c 973 974#define REG_HDMI_8996_PHY_POST_MISR_STATUS1 0x00000090 975 976#define REG_HDMI_8996_PHY_POST_MISR_STATUS2 0x00000094 977 978#define REG_HDMI_8996_PHY_POST_MISR_STATUS3 0x00000098 979 980#define REG_HDMI_8996_PHY_STATUS 0x0000009c 981 982#define REG_HDMI_8996_PHY_MISC3_STATUS 0x000000a0 983 984#define REG_HDMI_8996_PHY_MISC4_STATUS 0x000000a4 985 986#define REG_HDMI_8996_PHY_DEBUG_BUS0 0x000000a8 987 988#define REG_HDMI_8996_PHY_DEBUG_BUS1 0x000000ac 989 990#define REG_HDMI_8996_PHY_DEBUG_BUS2 0x000000b0 991 992#define REG_HDMI_8996_PHY_DEBUG_BUS3 0x000000b4 993 994#define REG_HDMI_8996_PHY_PHY_REVISION_ID0 0x000000b8 995 996#define REG_HDMI_8996_PHY_PHY_REVISION_ID1 0x000000bc 997 998#define REG_HDMI_8996_PHY_PHY_REVISION_ID2 0x000000c0 999 1000#define REG_HDMI_8996_PHY_PHY_REVISION_ID3 0x000000c4 1001 1002#define REG_HDMI_PHY_QSERDES_COM_ATB_SEL1 0x00000000 1003 1004#define REG_HDMI_PHY_QSERDES_COM_ATB_SEL2 0x00000004 1005 1006#define REG_HDMI_PHY_QSERDES_COM_FREQ_UPDATE 0x00000008 1007 1008#define REG_HDMI_PHY_QSERDES_COM_BG_TIMER 0x0000000c 1009 1010#define REG_HDMI_PHY_QSERDES_COM_SSC_EN_CENTER 0x00000010 1011 1012#define REG_HDMI_PHY_QSERDES_COM_SSC_ADJ_PER1 0x00000014 1013 1014#define REG_HDMI_PHY_QSERDES_COM_SSC_ADJ_PER2 0x00000018 1015 1016#define REG_HDMI_PHY_QSERDES_COM_SSC_PER1 0x0000001c 1017 1018#define REG_HDMI_PHY_QSERDES_COM_SSC_PER2 0x00000020 1019 1020#define REG_HDMI_PHY_QSERDES_COM_SSC_STEP_SIZE1 0x00000024 1021 1022#define REG_HDMI_PHY_QSERDES_COM_SSC_STEP_SIZE2 0x00000028 1023 1024#define REG_HDMI_PHY_QSERDES_COM_POST_DIV 0x0000002c 1025 1026#define REG_HDMI_PHY_QSERDES_COM_POST_DIV_MUX 0x00000030 1027 1028#define REG_HDMI_PHY_QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x00000034 1029 1030#define REG_HDMI_PHY_QSERDES_COM_CLK_ENABLE1 0x00000038 1031 1032#define REG_HDMI_PHY_QSERDES_COM_SYS_CLK_CTRL 0x0000003c 1033 1034#define REG_HDMI_PHY_QSERDES_COM_SYSCLK_BUF_ENABLE 0x00000040 1035 1036#define REG_HDMI_PHY_QSERDES_COM_PLL_EN 0x00000044 1037 1038#define REG_HDMI_PHY_QSERDES_COM_PLL_IVCO 0x00000048 1039 1040#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP1_MODE0 0x0000004c 1041 1042#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP2_MODE0 0x00000050 1043 1044#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP3_MODE0 0x00000054 1045 1046#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP1_MODE1 0x00000058 1047 1048#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP2_MODE1 0x0000005c 1049 1050#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP3_MODE1 0x00000060 1051 1052#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP1_MODE2 0x00000064 1053 1054#define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD0 0x00000064 1055 1056#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP2_MODE2 0x00000068 1057 1058#define REG_HDMI_PHY_QSERDES_COM_EP_CLOCK_DETECT_CTRL 0x00000068 1059 1060#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP3_MODE2 0x0000006c 1061 1062#define REG_HDMI_PHY_QSERDES_COM_SYSCLK_DET_COMP_STATUS 0x0000006c 1063 1064#define REG_HDMI_PHY_QSERDES_COM_BG_TRIM 0x00000070 1065 1066#define REG_HDMI_PHY_QSERDES_COM_CLK_EP_DIV 0x00000074 1067 1068#define REG_HDMI_PHY_QSERDES_COM_CP_CTRL_MODE0 0x00000078 1069 1070#define REG_HDMI_PHY_QSERDES_COM_CP_CTRL_MODE1 0x0000007c 1071 1072#define REG_HDMI_PHY_QSERDES_COM_CP_CTRL_MODE2 0x00000080 1073 1074#define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD1 0x00000080 1075 1076#define REG_HDMI_PHY_QSERDES_COM_PLL_RCTRL_MODE0 0x00000084 1077 1078#define REG_HDMI_PHY_QSERDES_COM_PLL_RCTRL_MODE1 0x00000088 1079 1080#define REG_HDMI_PHY_QSERDES_COM_PLL_RCTRL_MODE2 0x0000008c 1081 1082#define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD2 0x0000008c 1083 1084#define REG_HDMI_PHY_QSERDES_COM_PLL_CCTRL_MODE0 0x00000090 1085 1086#define REG_HDMI_PHY_QSERDES_COM_PLL_CCTRL_MODE1 0x00000094 1087 1088#define REG_HDMI_PHY_QSERDES_COM_PLL_CCTRL_MODE2 0x00000098 1089 1090#define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD3 0x00000098 1091 1092#define REG_HDMI_PHY_QSERDES_COM_PLL_CNTRL 0x0000009c 1093 1094#define REG_HDMI_PHY_QSERDES_COM_PHASE_SEL_CTRL 0x000000a0 1095 1096#define REG_HDMI_PHY_QSERDES_COM_PHASE_SEL_DC 0x000000a4 1097 1098#define REG_HDMI_PHY_QSERDES_COM_CORE_CLK_IN_SYNC_SEL 0x000000a8 1099 1100#define REG_HDMI_PHY_QSERDES_COM_BIAS_EN_CTRL_BY_PSM 0x000000a8 1101 1102#define REG_HDMI_PHY_QSERDES_COM_SYSCLK_EN_SEL 0x000000ac 1103 1104#define REG_HDMI_PHY_QSERDES_COM_CML_SYSCLK_SEL 0x000000b0 1105 1106#define REG_HDMI_PHY_QSERDES_COM_RESETSM_CNTRL 0x000000b4 1107 1108#define REG_HDMI_PHY_QSERDES_COM_RESETSM_CNTRL2 0x000000b8 1109 1110#define REG_HDMI_PHY_QSERDES_COM_RESTRIM_CTRL 0x000000bc 1111 1112#define REG_HDMI_PHY_QSERDES_COM_RESTRIM_CTRL2 0x000000c0 1113 1114#define REG_HDMI_PHY_QSERDES_COM_RESCODE_DIV_NUM 0x000000c4 1115 1116#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP_EN 0x000000c8 1117 1118#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP_CFG 0x000000cc 1119 1120#define REG_HDMI_PHY_QSERDES_COM_DEC_START_MODE0 0x000000d0 1121 1122#define REG_HDMI_PHY_QSERDES_COM_DEC_START_MODE1 0x000000d4 1123 1124#define REG_HDMI_PHY_QSERDES_COM_DEC_START_MODE2 0x000000d8 1125 1126#define REG_HDMI_PHY_QSERDES_COM_VCOCAL_DEADMAN_CTRL 0x000000d8 1127 1128#define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START1_MODE0 0x000000dc 1129 1130#define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START2_MODE0 0x000000e0 1131 1132#define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START3_MODE0 0x000000e4 1133 1134#define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START1_MODE1 0x000000e8 1135 1136#define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START2_MODE1 0x000000ec 1137 1138#define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START3_MODE1 0x000000f0 1139 1140#define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START1_MODE2 0x000000f4 1141 1142#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MINVAL1 0x000000f4 1143 1144#define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START2_MODE2 0x000000f8 1145 1146#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MINVAL2 0x000000f8 1147 1148#define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START3_MODE2 0x000000fc 1149 1150#define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD4 0x000000fc 1151 1152#define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_INITVAL 0x00000100 1153 1154#define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_EN 0x00000104 1155 1156#define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN0_MODE0 0x00000108 1157 1158#define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE0 0x0000010c 1159 1160#define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN0_MODE1 0x00000110 1161 1162#define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE1 0x00000114 1163 1164#define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN0_MODE2 0x00000118 1165 1166#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MAXVAL1 0x00000118 1167 1168#define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE2 0x0000011c 1169 1170#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MAXVAL2 0x0000011c 1171 1172#define REG_HDMI_PHY_QSERDES_COM_RES_TRIM_CONTROL2 0x00000120 1173 1174#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_CTRL 0x00000124 1175 1176#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MAP 0x00000128 1177 1178#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE1_MODE0 0x0000012c 1179 1180#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE2_MODE0 0x00000130 1181 1182#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE1_MODE1 0x00000134 1183 1184#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE2_MODE1 0x00000138 1185 1186#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE1_MODE2 0x0000013c 1187 1188#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_INITVAL1 0x0000013c 1189 1190#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE2_MODE2 0x00000140 1191 1192#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_INITVAL2 0x00000140 1193 1194#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_TIMER1 0x00000144 1195 1196#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_TIMER2 0x00000148 1197 1198#define REG_HDMI_PHY_QSERDES_COM_SAR 0x0000014c 1199 1200#define REG_HDMI_PHY_QSERDES_COM_SAR_CLK 0x00000150 1201 1202#define REG_HDMI_PHY_QSERDES_COM_SAR_CODE_OUT_STATUS 0x00000154 1203 1204#define REG_HDMI_PHY_QSERDES_COM_SAR_CODE_READY_STATUS 0x00000158 1205 1206#define REG_HDMI_PHY_QSERDES_COM_CMN_STATUS 0x0000015c 1207 1208#define REG_HDMI_PHY_QSERDES_COM_RESET_SM_STATUS 0x00000160 1209 1210#define REG_HDMI_PHY_QSERDES_COM_RESTRIM_CODE_STATUS 0x00000164 1211 1212#define REG_HDMI_PHY_QSERDES_COM_PLLCAL_CODE1_STATUS 0x00000168 1213 1214#define REG_HDMI_PHY_QSERDES_COM_PLLCAL_CODE2_STATUS 0x0000016c 1215 1216#define REG_HDMI_PHY_QSERDES_COM_BG_CTRL 0x00000170 1217 1218#define REG_HDMI_PHY_QSERDES_COM_CLK_SELECT 0x00000174 1219 1220#define REG_HDMI_PHY_QSERDES_COM_HSCLK_SEL 0x00000178 1221 1222#define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_BINCODE_STATUS 0x0000017c 1223 1224#define REG_HDMI_PHY_QSERDES_COM_PLL_ANALOG 0x00000180 1225 1226#define REG_HDMI_PHY_QSERDES_COM_CORECLK_DIV 0x00000184 1227 1228#define REG_HDMI_PHY_QSERDES_COM_SW_RESET 0x00000188 1229 1230#define REG_HDMI_PHY_QSERDES_COM_CORE_CLK_EN 0x0000018c 1231 1232#define REG_HDMI_PHY_QSERDES_COM_C_READY_STATUS 0x00000190 1233 1234#define REG_HDMI_PHY_QSERDES_COM_CMN_CONFIG 0x00000194 1235 1236#define REG_HDMI_PHY_QSERDES_COM_CMN_RATE_OVERRIDE 0x00000198 1237 1238#define REG_HDMI_PHY_QSERDES_COM_SVS_MODE_CLK_SEL 0x0000019c 1239 1240#define REG_HDMI_PHY_QSERDES_COM_DEBUG_BUS0 0x000001a0 1241 1242#define REG_HDMI_PHY_QSERDES_COM_DEBUG_BUS1 0x000001a4 1243 1244#define REG_HDMI_PHY_QSERDES_COM_DEBUG_BUS2 0x000001a8 1245 1246#define REG_HDMI_PHY_QSERDES_COM_DEBUG_BUS3 0x000001ac 1247 1248#define REG_HDMI_PHY_QSERDES_COM_DEBUG_BUS_SEL 0x000001b0 1249 1250#define REG_HDMI_PHY_QSERDES_COM_CMN_MISC1 0x000001b4 1251 1252#define REG_HDMI_PHY_QSERDES_COM_CMN_MISC2 0x000001b8 1253 1254#define REG_HDMI_PHY_QSERDES_COM_CORECLK_DIV_MODE1 0x000001bc 1255 1256#define REG_HDMI_PHY_QSERDES_COM_CORECLK_DIV_MODE2 0x000001c0 1257 1258#define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD5 0x000001c4 1259 1260#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_MODE_LANENO 0x00000000 1261 1262#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_INVERT 0x00000004 1263 1264#define REG_HDMI_PHY_QSERDES_TX_LX_CLKBUF_ENABLE 0x00000008 1265 1266#define REG_HDMI_PHY_QSERDES_TX_LX_CMN_CONTROL_ONE 0x0000000c 1267 1268#define REG_HDMI_PHY_QSERDES_TX_LX_CMN_CONTROL_TWO 0x00000010 1269 1270#define REG_HDMI_PHY_QSERDES_TX_LX_CMN_CONTROL_THREE 0x00000014 1271 1272#define REG_HDMI_PHY_QSERDES_TX_LX_TX_EMP_POST1_LVL 0x00000018 1273 1274#define REG_HDMI_PHY_QSERDES_TX_LX_TX_POST2_EMPH 0x0000001c 1275 1276#define REG_HDMI_PHY_QSERDES_TX_LX_TX_BOOST_LVL_UP_DN 0x00000020 1277 1278#define REG_HDMI_PHY_QSERDES_TX_LX_HP_PD_ENABLES 0x00000024 1279 1280#define REG_HDMI_PHY_QSERDES_TX_LX_TX_IDLE_LVL_LARGE_AMP 0x00000028 1281 1282#define REG_HDMI_PHY_QSERDES_TX_LX_TX_DRV_LVL 0x0000002c 1283 1284#define REG_HDMI_PHY_QSERDES_TX_LX_TX_DRV_LVL_OFFSET 0x00000030 1285 1286#define REG_HDMI_PHY_QSERDES_TX_LX_RESET_TSYNC_EN 0x00000034 1287 1288#define REG_HDMI_PHY_QSERDES_TX_LX_PRE_STALL_LDO_BOOST_EN 0x00000038 1289 1290#define REG_HDMI_PHY_QSERDES_TX_LX_TX_BAND 0x0000003c 1291 1292#define REG_HDMI_PHY_QSERDES_TX_LX_SLEW_CNTL 0x00000040 1293 1294#define REG_HDMI_PHY_QSERDES_TX_LX_INTERFACE_SELECT 0x00000044 1295 1296#define REG_HDMI_PHY_QSERDES_TX_LX_LPB_EN 0x00000048 1297 1298#define REG_HDMI_PHY_QSERDES_TX_LX_RES_CODE_LANE_TX 0x0000004c 1299 1300#define REG_HDMI_PHY_QSERDES_TX_LX_RES_CODE_LANE_RX 0x00000050 1301 1302#define REG_HDMI_PHY_QSERDES_TX_LX_RES_CODE_LANE_OFFSET 0x00000054 1303 1304#define REG_HDMI_PHY_QSERDES_TX_LX_PERL_LENGTH1 0x00000058 1305 1306#define REG_HDMI_PHY_QSERDES_TX_LX_PERL_LENGTH2 0x0000005c 1307 1308#define REG_HDMI_PHY_QSERDES_TX_LX_SERDES_BYP_EN_OUT 0x00000060 1309 1310#define REG_HDMI_PHY_QSERDES_TX_LX_DEBUG_BUS_SEL 0x00000064 1311 1312#define REG_HDMI_PHY_QSERDES_TX_LX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN 0x00000068 1313 1314#define REG_HDMI_PHY_QSERDES_TX_LX_TX_POL_INV 0x0000006c 1315 1316#define REG_HDMI_PHY_QSERDES_TX_LX_PARRATE_REC_DETECT_IDLE_EN 0x00000070 1317 1318#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN1 0x00000074 1319 1320#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN2 0x00000078 1321 1322#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN3 0x0000007c 1323 1324#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN4 0x00000080 1325 1326#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN5 0x00000084 1327 1328#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN6 0x00000088 1329 1330#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN7 0x0000008c 1331 1332#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN8 0x00000090 1333 1334#define REG_HDMI_PHY_QSERDES_TX_LX_LANE_MODE 0x00000094 1335 1336#define REG_HDMI_PHY_QSERDES_TX_LX_IDAC_CAL_LANE_MODE 0x00000098 1337 1338#define REG_HDMI_PHY_QSERDES_TX_LX_IDAC_CAL_LANE_MODE_CONFIGURATION 0x0000009c 1339 1340#define REG_HDMI_PHY_QSERDES_TX_LX_ATB_SEL1 0x000000a0 1341 1342#define REG_HDMI_PHY_QSERDES_TX_LX_ATB_SEL2 0x000000a4 1343 1344#define REG_HDMI_PHY_QSERDES_TX_LX_RCV_DETECT_LVL 0x000000a8 1345 1346#define REG_HDMI_PHY_QSERDES_TX_LX_RCV_DETECT_LVL_2 0x000000ac 1347 1348#define REG_HDMI_PHY_QSERDES_TX_LX_PRBS_SEED1 0x000000b0 1349 1350#define REG_HDMI_PHY_QSERDES_TX_LX_PRBS_SEED2 0x000000b4 1351 1352#define REG_HDMI_PHY_QSERDES_TX_LX_PRBS_SEED3 0x000000b8 1353 1354#define REG_HDMI_PHY_QSERDES_TX_LX_PRBS_SEED4 0x000000bc 1355 1356#define REG_HDMI_PHY_QSERDES_TX_LX_RESET_GEN 0x000000c0 1357 1358#define REG_HDMI_PHY_QSERDES_TX_LX_RESET_GEN_MUXES 0x000000c4 1359 1360#define REG_HDMI_PHY_QSERDES_TX_LX_TRAN_DRVR_EMP_EN 0x000000c8 1361 1362#define REG_HDMI_PHY_QSERDES_TX_LX_TX_INTERFACE_MODE 0x000000cc 1363 1364#define REG_HDMI_PHY_QSERDES_TX_LX_PWM_CTRL 0x000000d0 1365 1366#define REG_HDMI_PHY_QSERDES_TX_LX_PWM_ENCODED_OR_DATA 0x000000d4 1367 1368#define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_1_DIVIDER_BAND2 0x000000d8 1369 1370#define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_2_DIVIDER_BAND2 0x000000dc 1371 1372#define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_3_DIVIDER_BAND2 0x000000e0 1373 1374#define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_4_DIVIDER_BAND2 0x000000e4 1375 1376#define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_1_DIVIDER_BAND0_1 0x000000e8 1377 1378#define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_2_DIVIDER_BAND0_1 0x000000ec 1379 1380#define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_3_DIVIDER_BAND0_1 0x000000f0 1381 1382#define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_4_DIVIDER_BAND0_1 0x000000f4 1383 1384#define REG_HDMI_PHY_QSERDES_TX_LX_VMODE_CTRL1 0x000000f8 1385 1386#define REG_HDMI_PHY_QSERDES_TX_LX_VMODE_CTRL2 0x000000fc 1387 1388#define REG_HDMI_PHY_QSERDES_TX_LX_TX_ALOG_INTF_OBSV_CNTL 0x00000100 1389 1390#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_STATUS 0x00000104 1391 1392#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_ERROR_COUNT1 0x00000108 1393 1394#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_ERROR_COUNT2 0x0000010c 1395 1396#define REG_HDMI_PHY_QSERDES_TX_LX_TX_ALOG_INTF_OBSV 0x00000110 1397 1398 1399#endif /* HDMI_XML */ 1400