1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2015, The Linux Foundation. All rights reserved. 4 */ 5 6#include <linux/clk.h> 7#include <linux/delay.h> 8#include <linux/dma-mapping.h> 9#include <linux/err.h> 10#include <linux/gpio/consumer.h> 11#include <linux/interrupt.h> 12#include <linux/mfd/syscon.h> 13#include <linux/of.h> 14#include <linux/of_graph.h> 15#include <linux/of_irq.h> 16#include <linux/pinctrl/consumer.h> 17#include <linux/pm_opp.h> 18#include <linux/regmap.h> 19#include <linux/regulator/consumer.h> 20#include <linux/spinlock.h> 21 22#include <video/mipi_display.h> 23 24#include <drm/display/drm_dsc_helper.h> 25#include <drm/drm_of.h> 26 27#include "dsi.h" 28#include "dsi.xml.h" 29#include "sfpb.xml.h" 30#include "dsi_cfg.h" 31#include "msm_dsc_helper.h" 32#include "msm_kms.h" 33#include "msm_gem.h" 34#include "phy/dsi_phy.h" 35 36#define DSI_RESET_TOGGLE_DELAY_MS 20 37 38static int dsi_populate_dsc_params(struct msm_dsi_host *msm_host, struct drm_dsc_config *dsc); 39 40static int dsi_get_version(const void __iomem *base, u32 *major, u32 *minor) 41{ 42 u32 ver; 43 44 if (!major || !minor) 45 return -EINVAL; 46 47 /* 48 * From DSI6G(v3), addition of a 6G_HW_VERSION register at offset 0 49 * makes all other registers 4-byte shifted down. 50 * 51 * In order to identify between DSI6G(v3) and beyond, and DSIv2 and 52 * older, we read the DSI_VERSION register without any shift(offset 53 * 0x1f0). In the case of DSIv2, this hast to be a non-zero value. In 54 * the case of DSI6G, this has to be zero (the offset points to a 55 * scratch register which we never touch) 56 */ 57 58 ver = msm_readl(base + REG_DSI_VERSION); 59 if (ver) { 60 /* older dsi host, there is no register shift */ 61 ver = FIELD(ver, DSI_VERSION_MAJOR); 62 if (ver <= MSM_DSI_VER_MAJOR_V2) { 63 /* old versions */ 64 *major = ver; 65 *minor = 0; 66 return 0; 67 } else { 68 return -EINVAL; 69 } 70 } else { 71 /* 72 * newer host, offset 0 has 6G_HW_VERSION, the rest of the 73 * registers are shifted down, read DSI_VERSION again with 74 * the shifted offset 75 */ 76 ver = msm_readl(base + DSI_6G_REG_SHIFT + REG_DSI_VERSION); 77 ver = FIELD(ver, DSI_VERSION_MAJOR); 78 if (ver == MSM_DSI_VER_MAJOR_6G) { 79 /* 6G version */ 80 *major = ver; 81 *minor = msm_readl(base + REG_DSI_6G_HW_VERSION); 82 return 0; 83 } else { 84 return -EINVAL; 85 } 86 } 87} 88 89#define DSI_ERR_STATE_ACK 0x0000 90#define DSI_ERR_STATE_TIMEOUT 0x0001 91#define DSI_ERR_STATE_DLN0_PHY 0x0002 92#define DSI_ERR_STATE_FIFO 0x0004 93#define DSI_ERR_STATE_MDP_FIFO_UNDERFLOW 0x0008 94#define DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION 0x0010 95#define DSI_ERR_STATE_PLL_UNLOCKED 0x0020 96 97#define DSI_CLK_CTRL_ENABLE_CLKS \ 98 (DSI_CLK_CTRL_AHBS_HCLK_ON | DSI_CLK_CTRL_AHBM_SCLK_ON | \ 99 DSI_CLK_CTRL_PCLK_ON | DSI_CLK_CTRL_DSICLK_ON | \ 100 DSI_CLK_CTRL_BYTECLK_ON | DSI_CLK_CTRL_ESCCLK_ON | \ 101 DSI_CLK_CTRL_FORCE_ON_DYN_AHBM_HCLK) 102 103struct msm_dsi_host { 104 struct mipi_dsi_host base; 105 106 struct platform_device *pdev; 107 struct drm_device *dev; 108 109 int id; 110 111 void __iomem *ctrl_base; 112 phys_addr_t ctrl_size; 113 struct regulator_bulk_data *supplies; 114 115 int num_bus_clks; 116 struct clk_bulk_data bus_clks[DSI_BUS_CLK_MAX]; 117 118 struct clk *byte_clk; 119 struct clk *esc_clk; 120 struct clk *pixel_clk; 121 struct clk *byte_intf_clk; 122 123 unsigned long byte_clk_rate; 124 unsigned long byte_intf_clk_rate; 125 unsigned long pixel_clk_rate; 126 unsigned long esc_clk_rate; 127 128 /* DSI v2 specific clocks */ 129 struct clk *src_clk; 130 131 unsigned long src_clk_rate; 132 133 struct gpio_desc *disp_en_gpio; 134 struct gpio_desc *te_gpio; 135 136 const struct msm_dsi_cfg_handler *cfg_hnd; 137 138 struct completion dma_comp; 139 struct completion video_comp; 140 struct mutex dev_mutex; 141 struct mutex cmd_mutex; 142 spinlock_t intr_lock; /* Protect interrupt ctrl register */ 143 144 u32 err_work_state; 145 struct work_struct err_work; 146 struct workqueue_struct *workqueue; 147 148 /* DSI 6G TX buffer*/ 149 struct drm_gem_object *tx_gem_obj; 150 struct msm_gem_address_space *aspace; 151 152 /* DSI v2 TX buffer */ 153 void *tx_buf; 154 dma_addr_t tx_buf_paddr; 155 156 int tx_size; 157 158 u8 *rx_buf; 159 160 struct regmap *sfpb; 161 162 struct drm_display_mode *mode; 163 struct drm_dsc_config *dsc; 164 165 /* connected device info */ 166 unsigned int channel; 167 unsigned int lanes; 168 enum mipi_dsi_pixel_format format; 169 unsigned long mode_flags; 170 171 /* lane data parsed via DT */ 172 int dlane_swap; 173 int num_data_lanes; 174 175 /* from phy DT */ 176 bool cphy_mode; 177 178 u32 dma_cmd_ctrl_restore; 179 180 bool registered; 181 bool power_on; 182 bool enabled; 183 int irq; 184}; 185 186static u32 dsi_get_bpp(const enum mipi_dsi_pixel_format fmt) 187{ 188 switch (fmt) { 189 case MIPI_DSI_FMT_RGB565: return 16; 190 case MIPI_DSI_FMT_RGB666_PACKED: return 18; 191 case MIPI_DSI_FMT_RGB666: 192 case MIPI_DSI_FMT_RGB888: 193 default: return 24; 194 } 195} 196 197static inline u32 dsi_read(struct msm_dsi_host *msm_host, u32 reg) 198{ 199 return msm_readl(msm_host->ctrl_base + reg); 200} 201static inline void dsi_write(struct msm_dsi_host *msm_host, u32 reg, u32 data) 202{ 203 msm_writel(data, msm_host->ctrl_base + reg); 204} 205 206static const struct msm_dsi_cfg_handler *dsi_get_config( 207 struct msm_dsi_host *msm_host) 208{ 209 const struct msm_dsi_cfg_handler *cfg_hnd = NULL; 210 struct device *dev = &msm_host->pdev->dev; 211 struct clk *ahb_clk; 212 int ret; 213 u32 major = 0, minor = 0; 214 215 ahb_clk = msm_clk_get(msm_host->pdev, "iface"); 216 if (IS_ERR(ahb_clk)) { 217 pr_err("%s: cannot get interface clock\n", __func__); 218 goto exit; 219 } 220 221 pm_runtime_get_sync(dev); 222 223 ret = clk_prepare_enable(ahb_clk); 224 if (ret) { 225 pr_err("%s: unable to enable ahb_clk\n", __func__); 226 goto runtime_put; 227 } 228 229 ret = dsi_get_version(msm_host->ctrl_base, &major, &minor); 230 if (ret) { 231 pr_err("%s: Invalid version\n", __func__); 232 goto disable_clks; 233 } 234 235 cfg_hnd = msm_dsi_cfg_get(major, minor); 236 237 DBG("%s: Version %x:%x\n", __func__, major, minor); 238 239disable_clks: 240 clk_disable_unprepare(ahb_clk); 241runtime_put: 242 pm_runtime_put_sync(dev); 243exit: 244 return cfg_hnd; 245} 246 247static inline struct msm_dsi_host *to_msm_dsi_host(struct mipi_dsi_host *host) 248{ 249 return container_of(host, struct msm_dsi_host, base); 250} 251 252int dsi_clk_init_v2(struct msm_dsi_host *msm_host) 253{ 254 struct platform_device *pdev = msm_host->pdev; 255 int ret = 0; 256 257 msm_host->src_clk = msm_clk_get(pdev, "src"); 258 259 if (IS_ERR(msm_host->src_clk)) { 260 ret = PTR_ERR(msm_host->src_clk); 261 pr_err("%s: can't find src clock. ret=%d\n", 262 __func__, ret); 263 msm_host->src_clk = NULL; 264 return ret; 265 } 266 267 return ret; 268} 269 270int dsi_clk_init_6g_v2(struct msm_dsi_host *msm_host) 271{ 272 struct platform_device *pdev = msm_host->pdev; 273 int ret = 0; 274 275 msm_host->byte_intf_clk = msm_clk_get(pdev, "byte_intf"); 276 if (IS_ERR(msm_host->byte_intf_clk)) { 277 ret = PTR_ERR(msm_host->byte_intf_clk); 278 pr_err("%s: can't find byte_intf clock. ret=%d\n", 279 __func__, ret); 280 } 281 282 return ret; 283} 284 285static int dsi_clk_init(struct msm_dsi_host *msm_host) 286{ 287 struct platform_device *pdev = msm_host->pdev; 288 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 289 const struct msm_dsi_config *cfg = cfg_hnd->cfg; 290 int i, ret = 0; 291 292 /* get bus clocks */ 293 for (i = 0; i < cfg->num_bus_clks; i++) 294 msm_host->bus_clks[i].id = cfg->bus_clk_names[i]; 295 msm_host->num_bus_clks = cfg->num_bus_clks; 296 297 ret = devm_clk_bulk_get(&pdev->dev, msm_host->num_bus_clks, msm_host->bus_clks); 298 if (ret < 0) { 299 dev_err(&pdev->dev, "Unable to get clocks, ret = %d\n", ret); 300 goto exit; 301 } 302 303 /* get link and source clocks */ 304 msm_host->byte_clk = msm_clk_get(pdev, "byte"); 305 if (IS_ERR(msm_host->byte_clk)) { 306 ret = PTR_ERR(msm_host->byte_clk); 307 pr_err("%s: can't find dsi_byte clock. ret=%d\n", 308 __func__, ret); 309 msm_host->byte_clk = NULL; 310 goto exit; 311 } 312 313 msm_host->pixel_clk = msm_clk_get(pdev, "pixel"); 314 if (IS_ERR(msm_host->pixel_clk)) { 315 ret = PTR_ERR(msm_host->pixel_clk); 316 pr_err("%s: can't find dsi_pixel clock. ret=%d\n", 317 __func__, ret); 318 msm_host->pixel_clk = NULL; 319 goto exit; 320 } 321 322 msm_host->esc_clk = msm_clk_get(pdev, "core"); 323 if (IS_ERR(msm_host->esc_clk)) { 324 ret = PTR_ERR(msm_host->esc_clk); 325 pr_err("%s: can't find dsi_esc clock. ret=%d\n", 326 __func__, ret); 327 msm_host->esc_clk = NULL; 328 goto exit; 329 } 330 331 if (cfg_hnd->ops->clk_init_ver) 332 ret = cfg_hnd->ops->clk_init_ver(msm_host); 333exit: 334 return ret; 335} 336 337int msm_dsi_runtime_suspend(struct device *dev) 338{ 339 struct platform_device *pdev = to_platform_device(dev); 340 struct msm_dsi *msm_dsi = platform_get_drvdata(pdev); 341 struct mipi_dsi_host *host = msm_dsi->host; 342 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 343 344 if (!msm_host->cfg_hnd) 345 return 0; 346 347 clk_bulk_disable_unprepare(msm_host->num_bus_clks, msm_host->bus_clks); 348 349 return 0; 350} 351 352int msm_dsi_runtime_resume(struct device *dev) 353{ 354 struct platform_device *pdev = to_platform_device(dev); 355 struct msm_dsi *msm_dsi = platform_get_drvdata(pdev); 356 struct mipi_dsi_host *host = msm_dsi->host; 357 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 358 359 if (!msm_host->cfg_hnd) 360 return 0; 361 362 return clk_bulk_prepare_enable(msm_host->num_bus_clks, msm_host->bus_clks); 363} 364 365int dsi_link_clk_set_rate_6g(struct msm_dsi_host *msm_host) 366{ 367 int ret; 368 369 DBG("Set clk rates: pclk=%d, byteclk=%lu", 370 msm_host->mode->clock, msm_host->byte_clk_rate); 371 372 ret = dev_pm_opp_set_rate(&msm_host->pdev->dev, 373 msm_host->byte_clk_rate); 374 if (ret) { 375 pr_err("%s: dev_pm_opp_set_rate failed %d\n", __func__, ret); 376 return ret; 377 } 378 379 ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate); 380 if (ret) { 381 pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret); 382 return ret; 383 } 384 385 if (msm_host->byte_intf_clk) { 386 ret = clk_set_rate(msm_host->byte_intf_clk, msm_host->byte_intf_clk_rate); 387 if (ret) { 388 pr_err("%s: Failed to set rate byte intf clk, %d\n", 389 __func__, ret); 390 return ret; 391 } 392 } 393 394 return 0; 395} 396 397 398int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host) 399{ 400 int ret; 401 402 ret = clk_prepare_enable(msm_host->esc_clk); 403 if (ret) { 404 pr_err("%s: Failed to enable dsi esc clk\n", __func__); 405 goto error; 406 } 407 408 ret = clk_prepare_enable(msm_host->byte_clk); 409 if (ret) { 410 pr_err("%s: Failed to enable dsi byte clk\n", __func__); 411 goto byte_clk_err; 412 } 413 414 ret = clk_prepare_enable(msm_host->pixel_clk); 415 if (ret) { 416 pr_err("%s: Failed to enable dsi pixel clk\n", __func__); 417 goto pixel_clk_err; 418 } 419 420 ret = clk_prepare_enable(msm_host->byte_intf_clk); 421 if (ret) { 422 pr_err("%s: Failed to enable byte intf clk\n", 423 __func__); 424 goto byte_intf_clk_err; 425 } 426 427 return 0; 428 429byte_intf_clk_err: 430 clk_disable_unprepare(msm_host->pixel_clk); 431pixel_clk_err: 432 clk_disable_unprepare(msm_host->byte_clk); 433byte_clk_err: 434 clk_disable_unprepare(msm_host->esc_clk); 435error: 436 return ret; 437} 438 439int dsi_link_clk_set_rate_v2(struct msm_dsi_host *msm_host) 440{ 441 int ret; 442 443 DBG("Set clk rates: pclk=%d, byteclk=%lu, esc_clk=%lu, dsi_src_clk=%lu", 444 msm_host->mode->clock, msm_host->byte_clk_rate, 445 msm_host->esc_clk_rate, msm_host->src_clk_rate); 446 447 ret = clk_set_rate(msm_host->byte_clk, msm_host->byte_clk_rate); 448 if (ret) { 449 pr_err("%s: Failed to set rate byte clk, %d\n", __func__, ret); 450 return ret; 451 } 452 453 ret = clk_set_rate(msm_host->esc_clk, msm_host->esc_clk_rate); 454 if (ret) { 455 pr_err("%s: Failed to set rate esc clk, %d\n", __func__, ret); 456 return ret; 457 } 458 459 ret = clk_set_rate(msm_host->src_clk, msm_host->src_clk_rate); 460 if (ret) { 461 pr_err("%s: Failed to set rate src clk, %d\n", __func__, ret); 462 return ret; 463 } 464 465 ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate); 466 if (ret) { 467 pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret); 468 return ret; 469 } 470 471 return 0; 472} 473 474int dsi_link_clk_enable_v2(struct msm_dsi_host *msm_host) 475{ 476 int ret; 477 478 ret = clk_prepare_enable(msm_host->byte_clk); 479 if (ret) { 480 pr_err("%s: Failed to enable dsi byte clk\n", __func__); 481 goto error; 482 } 483 484 ret = clk_prepare_enable(msm_host->esc_clk); 485 if (ret) { 486 pr_err("%s: Failed to enable dsi esc clk\n", __func__); 487 goto esc_clk_err; 488 } 489 490 ret = clk_prepare_enable(msm_host->src_clk); 491 if (ret) { 492 pr_err("%s: Failed to enable dsi src clk\n", __func__); 493 goto src_clk_err; 494 } 495 496 ret = clk_prepare_enable(msm_host->pixel_clk); 497 if (ret) { 498 pr_err("%s: Failed to enable dsi pixel clk\n", __func__); 499 goto pixel_clk_err; 500 } 501 502 return 0; 503 504pixel_clk_err: 505 clk_disable_unprepare(msm_host->src_clk); 506src_clk_err: 507 clk_disable_unprepare(msm_host->esc_clk); 508esc_clk_err: 509 clk_disable_unprepare(msm_host->byte_clk); 510error: 511 return ret; 512} 513 514void dsi_link_clk_disable_6g(struct msm_dsi_host *msm_host) 515{ 516 /* Drop the performance state vote */ 517 dev_pm_opp_set_rate(&msm_host->pdev->dev, 0); 518 clk_disable_unprepare(msm_host->esc_clk); 519 clk_disable_unprepare(msm_host->pixel_clk); 520 clk_disable_unprepare(msm_host->byte_intf_clk); 521 clk_disable_unprepare(msm_host->byte_clk); 522} 523 524void dsi_link_clk_disable_v2(struct msm_dsi_host *msm_host) 525{ 526 clk_disable_unprepare(msm_host->pixel_clk); 527 clk_disable_unprepare(msm_host->src_clk); 528 clk_disable_unprepare(msm_host->esc_clk); 529 clk_disable_unprepare(msm_host->byte_clk); 530} 531 532static unsigned long dsi_adjust_pclk_for_compression(const struct drm_display_mode *mode, 533 const struct drm_dsc_config *dsc) 534{ 535 int new_hdisplay = DIV_ROUND_UP(mode->hdisplay * drm_dsc_get_bpp_int(dsc), 536 dsc->bits_per_component * 3); 537 538 int new_htotal = mode->htotal - mode->hdisplay + new_hdisplay; 539 540 return new_htotal * mode->vtotal * drm_mode_vrefresh(mode); 541} 542 543static unsigned long dsi_get_pclk_rate(const struct drm_display_mode *mode, 544 const struct drm_dsc_config *dsc, bool is_bonded_dsi) 545{ 546 unsigned long pclk_rate; 547 548 pclk_rate = mode->clock * 1000; 549 550 if (dsc) 551 pclk_rate = dsi_adjust_pclk_for_compression(mode, dsc); 552 553 /* 554 * For bonded DSI mode, the current DRM mode has the complete width of the 555 * panel. Since, the complete panel is driven by two DSI controllers, 556 * the clock rates have to be split between the two dsi controllers. 557 * Adjust the byte and pixel clock rates for each dsi host accordingly. 558 */ 559 if (is_bonded_dsi) 560 pclk_rate /= 2; 561 562 return pclk_rate; 563} 564 565unsigned long dsi_byte_clk_get_rate(struct mipi_dsi_host *host, bool is_bonded_dsi, 566 const struct drm_display_mode *mode) 567{ 568 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 569 u8 lanes = msm_host->lanes; 570 u32 bpp = dsi_get_bpp(msm_host->format); 571 unsigned long pclk_rate = dsi_get_pclk_rate(mode, msm_host->dsc, is_bonded_dsi); 572 unsigned long pclk_bpp; 573 574 if (lanes == 0) { 575 pr_err("%s: forcing mdss_dsi lanes to 1\n", __func__); 576 lanes = 1; 577 } 578 579 /* CPHY "byte_clk" is in units of 16 bits */ 580 if (msm_host->cphy_mode) 581 pclk_bpp = mult_frac(pclk_rate, bpp, 16 * lanes); 582 else 583 pclk_bpp = mult_frac(pclk_rate, bpp, 8 * lanes); 584 585 return pclk_bpp; 586} 587 588static void dsi_calc_pclk(struct msm_dsi_host *msm_host, bool is_bonded_dsi) 589{ 590 msm_host->pixel_clk_rate = dsi_get_pclk_rate(msm_host->mode, msm_host->dsc, is_bonded_dsi); 591 msm_host->byte_clk_rate = dsi_byte_clk_get_rate(&msm_host->base, is_bonded_dsi, 592 msm_host->mode); 593 594 DBG("pclk=%lu, bclk=%lu", msm_host->pixel_clk_rate, 595 msm_host->byte_clk_rate); 596 597} 598 599int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool is_bonded_dsi) 600{ 601 if (!msm_host->mode) { 602 pr_err("%s: mode not set\n", __func__); 603 return -EINVAL; 604 } 605 606 dsi_calc_pclk(msm_host, is_bonded_dsi); 607 msm_host->esc_clk_rate = clk_get_rate(msm_host->esc_clk); 608 return 0; 609} 610 611int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool is_bonded_dsi) 612{ 613 u32 bpp = dsi_get_bpp(msm_host->format); 614 unsigned int esc_mhz, esc_div; 615 unsigned long byte_mhz; 616 617 dsi_calc_pclk(msm_host, is_bonded_dsi); 618 619 msm_host->src_clk_rate = mult_frac(msm_host->pixel_clk_rate, bpp, 8); 620 621 /* 622 * esc clock is byte clock followed by a 4 bit divider, 623 * we need to find an escape clock frequency within the 624 * mipi DSI spec range within the maximum divider limit 625 * We iterate here between an escape clock frequencey 626 * between 20 Mhz to 5 Mhz and pick up the first one 627 * that can be supported by our divider 628 */ 629 630 byte_mhz = msm_host->byte_clk_rate / 1000000; 631 632 for (esc_mhz = 20; esc_mhz >= 5; esc_mhz--) { 633 esc_div = DIV_ROUND_UP(byte_mhz, esc_mhz); 634 635 /* 636 * TODO: Ideally, we shouldn't know what sort of divider 637 * is available in mmss_cc, we're just assuming that 638 * it'll always be a 4 bit divider. Need to come up with 639 * a better way here. 640 */ 641 if (esc_div >= 1 && esc_div <= 16) 642 break; 643 } 644 645 if (esc_mhz < 5) 646 return -EINVAL; 647 648 msm_host->esc_clk_rate = msm_host->byte_clk_rate / esc_div; 649 650 DBG("esc=%lu, src=%lu", msm_host->esc_clk_rate, 651 msm_host->src_clk_rate); 652 653 return 0; 654} 655 656static void dsi_intr_ctrl(struct msm_dsi_host *msm_host, u32 mask, int enable) 657{ 658 u32 intr; 659 unsigned long flags; 660 661 spin_lock_irqsave(&msm_host->intr_lock, flags); 662 intr = dsi_read(msm_host, REG_DSI_INTR_CTRL); 663 664 if (enable) 665 intr |= mask; 666 else 667 intr &= ~mask; 668 669 DBG("intr=%x enable=%d", intr, enable); 670 671 dsi_write(msm_host, REG_DSI_INTR_CTRL, intr); 672 spin_unlock_irqrestore(&msm_host->intr_lock, flags); 673} 674 675static inline enum dsi_traffic_mode dsi_get_traffic_mode(const u32 mode_flags) 676{ 677 if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 678 return BURST_MODE; 679 else if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) 680 return NON_BURST_SYNCH_PULSE; 681 682 return NON_BURST_SYNCH_EVENT; 683} 684 685static inline enum dsi_vid_dst_format dsi_get_vid_fmt( 686 const enum mipi_dsi_pixel_format mipi_fmt) 687{ 688 switch (mipi_fmt) { 689 case MIPI_DSI_FMT_RGB888: return VID_DST_FORMAT_RGB888; 690 case MIPI_DSI_FMT_RGB666: return VID_DST_FORMAT_RGB666_LOOSE; 691 case MIPI_DSI_FMT_RGB666_PACKED: return VID_DST_FORMAT_RGB666; 692 case MIPI_DSI_FMT_RGB565: return VID_DST_FORMAT_RGB565; 693 default: return VID_DST_FORMAT_RGB888; 694 } 695} 696 697static inline enum dsi_cmd_dst_format dsi_get_cmd_fmt( 698 const enum mipi_dsi_pixel_format mipi_fmt) 699{ 700 switch (mipi_fmt) { 701 case MIPI_DSI_FMT_RGB888: return CMD_DST_FORMAT_RGB888; 702 case MIPI_DSI_FMT_RGB666_PACKED: 703 case MIPI_DSI_FMT_RGB666: return CMD_DST_FORMAT_RGB666; 704 case MIPI_DSI_FMT_RGB565: return CMD_DST_FORMAT_RGB565; 705 default: return CMD_DST_FORMAT_RGB888; 706 } 707} 708 709static void dsi_ctrl_disable(struct msm_dsi_host *msm_host) 710{ 711 dsi_write(msm_host, REG_DSI_CTRL, 0); 712} 713 714static void dsi_ctrl_enable(struct msm_dsi_host *msm_host, 715 struct msm_dsi_phy_shared_timings *phy_shared_timings, struct msm_dsi_phy *phy) 716{ 717 u32 flags = msm_host->mode_flags; 718 enum mipi_dsi_pixel_format mipi_fmt = msm_host->format; 719 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 720 u32 data = 0, lane_ctrl = 0; 721 722 if (flags & MIPI_DSI_MODE_VIDEO) { 723 if (flags & MIPI_DSI_MODE_VIDEO_HSE) 724 data |= DSI_VID_CFG0_PULSE_MODE_HSA_HE; 725 if (flags & MIPI_DSI_MODE_VIDEO_NO_HFP) 726 data |= DSI_VID_CFG0_HFP_POWER_STOP; 727 if (flags & MIPI_DSI_MODE_VIDEO_NO_HBP) 728 data |= DSI_VID_CFG0_HBP_POWER_STOP; 729 if (flags & MIPI_DSI_MODE_VIDEO_NO_HSA) 730 data |= DSI_VID_CFG0_HSA_POWER_STOP; 731 /* Always set low power stop mode for BLLP 732 * to let command engine send packets 733 */ 734 data |= DSI_VID_CFG0_EOF_BLLP_POWER_STOP | 735 DSI_VID_CFG0_BLLP_POWER_STOP; 736 data |= DSI_VID_CFG0_TRAFFIC_MODE(dsi_get_traffic_mode(flags)); 737 data |= DSI_VID_CFG0_DST_FORMAT(dsi_get_vid_fmt(mipi_fmt)); 738 data |= DSI_VID_CFG0_VIRT_CHANNEL(msm_host->channel); 739 dsi_write(msm_host, REG_DSI_VID_CFG0, data); 740 741 /* Do not swap RGB colors */ 742 data = DSI_VID_CFG1_RGB_SWAP(SWAP_RGB); 743 dsi_write(msm_host, REG_DSI_VID_CFG1, 0); 744 } else { 745 /* Do not swap RGB colors */ 746 data = DSI_CMD_CFG0_RGB_SWAP(SWAP_RGB); 747 data |= DSI_CMD_CFG0_DST_FORMAT(dsi_get_cmd_fmt(mipi_fmt)); 748 dsi_write(msm_host, REG_DSI_CMD_CFG0, data); 749 750 data = DSI_CMD_CFG1_WR_MEM_START(MIPI_DCS_WRITE_MEMORY_START) | 751 DSI_CMD_CFG1_WR_MEM_CONTINUE( 752 MIPI_DCS_WRITE_MEMORY_CONTINUE); 753 /* Always insert DCS command */ 754 data |= DSI_CMD_CFG1_INSERT_DCS_COMMAND; 755 dsi_write(msm_host, REG_DSI_CMD_CFG1, data); 756 757 if (msm_host->cfg_hnd->major == MSM_DSI_VER_MAJOR_6G && 758 msm_host->cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_3) { 759 data = dsi_read(msm_host, REG_DSI_CMD_MODE_MDP_CTRL2); 760 data |= DSI_CMD_MODE_MDP_CTRL2_BURST_MODE; 761 dsi_write(msm_host, REG_DSI_CMD_MODE_MDP_CTRL2, data); 762 } 763 } 764 765 dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL, 766 DSI_CMD_DMA_CTRL_FROM_FRAME_BUFFER | 767 DSI_CMD_DMA_CTRL_LOW_POWER); 768 769 data = 0; 770 /* Always assume dedicated TE pin */ 771 data |= DSI_TRIG_CTRL_TE; 772 data |= DSI_TRIG_CTRL_MDP_TRIGGER(TRIGGER_NONE); 773 data |= DSI_TRIG_CTRL_DMA_TRIGGER(TRIGGER_SW); 774 data |= DSI_TRIG_CTRL_STREAM(msm_host->channel); 775 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) && 776 (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_2)) 777 data |= DSI_TRIG_CTRL_BLOCK_DMA_WITHIN_FRAME; 778 dsi_write(msm_host, REG_DSI_TRIG_CTRL, data); 779 780 data = DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(phy_shared_timings->clk_post) | 781 DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE(phy_shared_timings->clk_pre); 782 dsi_write(msm_host, REG_DSI_CLKOUT_TIMING_CTRL, data); 783 784 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) && 785 (cfg_hnd->minor > MSM_DSI_6G_VER_MINOR_V1_0) && 786 phy_shared_timings->clk_pre_inc_by_2) 787 dsi_write(msm_host, REG_DSI_T_CLK_PRE_EXTEND, 788 DSI_T_CLK_PRE_EXTEND_INC_BY_2_BYTECLK); 789 790 data = 0; 791 if (!(flags & MIPI_DSI_MODE_NO_EOT_PACKET)) 792 data |= DSI_EOT_PACKET_CTRL_TX_EOT_APPEND; 793 dsi_write(msm_host, REG_DSI_EOT_PACKET_CTRL, data); 794 795 /* allow only ack-err-status to generate interrupt */ 796 dsi_write(msm_host, REG_DSI_ERR_INT_MASK0, 0x13ff3fe0); 797 798 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1); 799 800 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS); 801 802 data = DSI_CTRL_CLK_EN; 803 804 DBG("lane number=%d", msm_host->lanes); 805 data |= ((DSI_CTRL_LANE0 << msm_host->lanes) - DSI_CTRL_LANE0); 806 807 dsi_write(msm_host, REG_DSI_LANE_SWAP_CTRL, 808 DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(msm_host->dlane_swap)); 809 810 if (!(flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) { 811 lane_ctrl = dsi_read(msm_host, REG_DSI_LANE_CTRL); 812 813 if (msm_dsi_phy_set_continuous_clock(phy, true)) 814 lane_ctrl &= ~DSI_LANE_CTRL_HS_REQ_SEL_PHY; 815 816 dsi_write(msm_host, REG_DSI_LANE_CTRL, 817 lane_ctrl | DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST); 818 } 819 820 data |= DSI_CTRL_ENABLE; 821 822 dsi_write(msm_host, REG_DSI_CTRL, data); 823 824 if (msm_host->cphy_mode) 825 dsi_write(msm_host, REG_DSI_CPHY_MODE_CTRL, BIT(0)); 826} 827 828static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mode, u32 hdisplay) 829{ 830 struct drm_dsc_config *dsc = msm_host->dsc; 831 u32 reg, reg_ctrl, reg_ctrl2; 832 u32 slice_per_intf, total_bytes_per_intf; 833 u32 pkt_per_line; 834 u32 eol_byte_num; 835 836 /* first calculate dsc parameters and then program 837 * compress mode registers 838 */ 839 slice_per_intf = msm_dsc_get_slices_per_intf(dsc, hdisplay); 840 841 total_bytes_per_intf = dsc->slice_chunk_size * slice_per_intf; 842 843 eol_byte_num = total_bytes_per_intf % 3; 844 845 /* 846 * Typically, pkt_per_line = slice_per_intf * slice_per_pkt. 847 * 848 * Since the current driver only supports slice_per_pkt = 1, 849 * pkt_per_line will be equal to slice per intf for now. 850 */ 851 pkt_per_line = slice_per_intf; 852 853 if (is_cmd_mode) /* packet data type */ 854 reg = DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_DATATYPE(MIPI_DSI_DCS_LONG_WRITE); 855 else 856 reg = DSI_VIDEO_COMPRESSION_MODE_CTRL_DATATYPE(MIPI_DSI_COMPRESSED_PIXEL_STREAM); 857 858 /* DSI_VIDEO_COMPRESSION_MODE & DSI_COMMAND_COMPRESSION_MODE 859 * registers have similar offsets, so for below common code use 860 * DSI_VIDEO_COMPRESSION_MODE_XXXX for setting bits 861 */ 862 reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_PKT_PER_LINE(pkt_per_line >> 1); 863 reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_EOL_BYTE_NUM(eol_byte_num); 864 reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_EN; 865 866 if (is_cmd_mode) { 867 reg_ctrl = dsi_read(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL); 868 reg_ctrl2 = dsi_read(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2); 869 870 reg_ctrl &= ~0xffff; 871 reg_ctrl |= reg; 872 873 reg_ctrl2 &= ~DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH__MASK; 874 reg_ctrl2 |= DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH(dsc->slice_chunk_size); 875 876 dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL, reg_ctrl); 877 dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2, reg_ctrl2); 878 } else { 879 dsi_write(msm_host, REG_DSI_VIDEO_COMPRESSION_MODE_CTRL, reg); 880 } 881} 882 883static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi) 884{ 885 struct drm_display_mode *mode = msm_host->mode; 886 u32 hs_start = 0, vs_start = 0; /* take sync start as 0 */ 887 u32 h_total = mode->htotal; 888 u32 v_total = mode->vtotal; 889 u32 hs_end = mode->hsync_end - mode->hsync_start; 890 u32 vs_end = mode->vsync_end - mode->vsync_start; 891 u32 ha_start = h_total - mode->hsync_start; 892 u32 ha_end = ha_start + mode->hdisplay; 893 u32 va_start = v_total - mode->vsync_start; 894 u32 va_end = va_start + mode->vdisplay; 895 u32 hdisplay = mode->hdisplay; 896 u32 wc; 897 int ret; 898 899 DBG(""); 900 901 /* 902 * For bonded DSI mode, the current DRM mode has 903 * the complete width of the panel. Since, the complete 904 * panel is driven by two DSI controllers, the horizontal 905 * timings have to be split between the two dsi controllers. 906 * Adjust the DSI host timing values accordingly. 907 */ 908 if (is_bonded_dsi) { 909 h_total /= 2; 910 hs_end /= 2; 911 ha_start /= 2; 912 ha_end /= 2; 913 hdisplay /= 2; 914 } 915 916 if (msm_host->dsc) { 917 struct drm_dsc_config *dsc = msm_host->dsc; 918 919 /* update dsc params with timing params */ 920 if (!dsc || !mode->hdisplay || !mode->vdisplay) { 921 pr_err("DSI: invalid input: pic_width: %d pic_height: %d\n", 922 mode->hdisplay, mode->vdisplay); 923 return; 924 } 925 926 dsc->pic_width = mode->hdisplay; 927 dsc->pic_height = mode->vdisplay; 928 DBG("Mode %dx%d\n", dsc->pic_width, dsc->pic_height); 929 930 /* we do the calculations for dsc parameters here so that 931 * panel can use these parameters 932 */ 933 ret = dsi_populate_dsc_params(msm_host, dsc); 934 if (ret) 935 return; 936 937 /* Divide the display by 3 but keep back/font porch and 938 * pulse width same 939 */ 940 h_total -= hdisplay; 941 hdisplay = DIV_ROUND_UP(msm_dsc_get_bytes_per_line(msm_host->dsc), 3); 942 h_total += hdisplay; 943 ha_end = ha_start + hdisplay; 944 } 945 946 if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) { 947 if (msm_host->dsc) 948 dsi_update_dsc_timing(msm_host, false, mode->hdisplay); 949 950 dsi_write(msm_host, REG_DSI_ACTIVE_H, 951 DSI_ACTIVE_H_START(ha_start) | 952 DSI_ACTIVE_H_END(ha_end)); 953 dsi_write(msm_host, REG_DSI_ACTIVE_V, 954 DSI_ACTIVE_V_START(va_start) | 955 DSI_ACTIVE_V_END(va_end)); 956 dsi_write(msm_host, REG_DSI_TOTAL, 957 DSI_TOTAL_H_TOTAL(h_total - 1) | 958 DSI_TOTAL_V_TOTAL(v_total - 1)); 959 960 dsi_write(msm_host, REG_DSI_ACTIVE_HSYNC, 961 DSI_ACTIVE_HSYNC_START(hs_start) | 962 DSI_ACTIVE_HSYNC_END(hs_end)); 963 dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_HPOS, 0); 964 dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_VPOS, 965 DSI_ACTIVE_VSYNC_VPOS_START(vs_start) | 966 DSI_ACTIVE_VSYNC_VPOS_END(vs_end)); 967 } else { /* command mode */ 968 if (msm_host->dsc) 969 dsi_update_dsc_timing(msm_host, true, mode->hdisplay); 970 971 /* image data and 1 byte write_memory_start cmd */ 972 if (!msm_host->dsc) 973 wc = hdisplay * dsi_get_bpp(msm_host->format) / 8 + 1; 974 else 975 /* 976 * When DSC is enabled, WC = slice_chunk_size * slice_per_pkt + 1. 977 * Currently, the driver only supports default value of slice_per_pkt = 1 978 * 979 * TODO: Expand mipi_dsi_device struct to hold slice_per_pkt info 980 * and adjust DSC math to account for slice_per_pkt. 981 */ 982 wc = msm_host->dsc->slice_chunk_size + 1; 983 984 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_CTRL, 985 DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT(wc) | 986 DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL( 987 msm_host->channel) | 988 DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE( 989 MIPI_DSI_DCS_LONG_WRITE)); 990 991 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_TOTAL, 992 DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL(hdisplay) | 993 DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL(mode->vdisplay)); 994 } 995} 996 997static void dsi_sw_reset(struct msm_dsi_host *msm_host) 998{ 999 u32 ctrl; 1000 1001 ctrl = dsi_read(msm_host, REG_DSI_CTRL); 1002 1003 if (ctrl & DSI_CTRL_ENABLE) { 1004 dsi_write(msm_host, REG_DSI_CTRL, ctrl & ~DSI_CTRL_ENABLE); 1005 /* 1006 * dsi controller need to be disabled before 1007 * clocks turned on 1008 */ 1009 wmb(); 1010 } 1011 1012 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS); 1013 wmb(); /* clocks need to be enabled before reset */ 1014 1015 /* dsi controller can only be reset while clocks are running */ 1016 dsi_write(msm_host, REG_DSI_RESET, 1); 1017 msleep(DSI_RESET_TOGGLE_DELAY_MS); /* make sure reset happen */ 1018 dsi_write(msm_host, REG_DSI_RESET, 0); 1019 wmb(); /* controller out of reset */ 1020 1021 if (ctrl & DSI_CTRL_ENABLE) { 1022 dsi_write(msm_host, REG_DSI_CTRL, ctrl); 1023 wmb(); /* make sure dsi controller enabled again */ 1024 } 1025} 1026 1027static void dsi_op_mode_config(struct msm_dsi_host *msm_host, 1028 bool video_mode, bool enable) 1029{ 1030 u32 dsi_ctrl; 1031 1032 dsi_ctrl = dsi_read(msm_host, REG_DSI_CTRL); 1033 1034 if (!enable) { 1035 dsi_ctrl &= ~(DSI_CTRL_ENABLE | DSI_CTRL_VID_MODE_EN | 1036 DSI_CTRL_CMD_MODE_EN); 1037 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE | 1038 DSI_IRQ_MASK_VIDEO_DONE, 0); 1039 } else { 1040 if (video_mode) { 1041 dsi_ctrl |= DSI_CTRL_VID_MODE_EN; 1042 } else { /* command mode */ 1043 dsi_ctrl |= DSI_CTRL_CMD_MODE_EN; 1044 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE, 1); 1045 } 1046 dsi_ctrl |= DSI_CTRL_ENABLE; 1047 } 1048 1049 dsi_write(msm_host, REG_DSI_CTRL, dsi_ctrl); 1050} 1051 1052static void dsi_set_tx_power_mode(int mode, struct msm_dsi_host *msm_host) 1053{ 1054 u32 data; 1055 1056 data = dsi_read(msm_host, REG_DSI_CMD_DMA_CTRL); 1057 1058 if (mode == 0) 1059 data &= ~DSI_CMD_DMA_CTRL_LOW_POWER; 1060 else 1061 data |= DSI_CMD_DMA_CTRL_LOW_POWER; 1062 1063 dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL, data); 1064} 1065 1066static void dsi_wait4video_done(struct msm_dsi_host *msm_host) 1067{ 1068 u32 ret = 0; 1069 struct device *dev = &msm_host->pdev->dev; 1070 1071 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 1); 1072 1073 reinit_completion(&msm_host->video_comp); 1074 1075 ret = wait_for_completion_timeout(&msm_host->video_comp, 1076 msecs_to_jiffies(70)); 1077 1078 if (ret == 0) 1079 DRM_DEV_ERROR(dev, "wait for video done timed out\n"); 1080 1081 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 0); 1082} 1083 1084static void dsi_wait4video_eng_busy(struct msm_dsi_host *msm_host) 1085{ 1086 u32 data; 1087 1088 if (!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO)) 1089 return; 1090 1091 data = dsi_read(msm_host, REG_DSI_STATUS0); 1092 1093 /* if video mode engine is not busy, its because 1094 * either timing engine was not turned on or the 1095 * DSI controller has finished transmitting the video 1096 * data already, so no need to wait in those cases 1097 */ 1098 if (!(data & DSI_STATUS0_VIDEO_MODE_ENGINE_BUSY)) 1099 return; 1100 1101 if (msm_host->power_on && msm_host->enabled) { 1102 dsi_wait4video_done(msm_host); 1103 /* delay 4 ms to skip BLLP */ 1104 usleep_range(2000, 4000); 1105 } 1106} 1107 1108int dsi_tx_buf_alloc_6g(struct msm_dsi_host *msm_host, int size) 1109{ 1110 struct drm_device *dev = msm_host->dev; 1111 struct msm_drm_private *priv = dev->dev_private; 1112 uint64_t iova; 1113 u8 *data; 1114 1115 msm_host->aspace = msm_gem_address_space_get(priv->kms->aspace); 1116 1117 data = msm_gem_kernel_new(dev, size, MSM_BO_WC, 1118 msm_host->aspace, 1119 &msm_host->tx_gem_obj, &iova); 1120 1121 if (IS_ERR(data)) { 1122 msm_host->tx_gem_obj = NULL; 1123 return PTR_ERR(data); 1124 } 1125 1126 msm_gem_object_set_name(msm_host->tx_gem_obj, "tx_gem"); 1127 1128 msm_host->tx_size = msm_host->tx_gem_obj->size; 1129 1130 return 0; 1131} 1132 1133int dsi_tx_buf_alloc_v2(struct msm_dsi_host *msm_host, int size) 1134{ 1135 struct drm_device *dev = msm_host->dev; 1136 1137 msm_host->tx_buf = dma_alloc_coherent(dev->dev, size, 1138 &msm_host->tx_buf_paddr, GFP_KERNEL); 1139 if (!msm_host->tx_buf) 1140 return -ENOMEM; 1141 1142 msm_host->tx_size = size; 1143 1144 return 0; 1145} 1146 1147void msm_dsi_tx_buf_free(struct mipi_dsi_host *host) 1148{ 1149 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1150 struct drm_device *dev = msm_host->dev; 1151 1152 /* 1153 * This is possible if we're tearing down before we've had a chance to 1154 * fully initialize. A very real possibility if our probe is deferred, 1155 * in which case we'll hit msm_dsi_host_destroy() without having run 1156 * through the dsi_tx_buf_alloc(). 1157 */ 1158 if (!dev) 1159 return; 1160 1161 if (msm_host->tx_gem_obj) { 1162 msm_gem_kernel_put(msm_host->tx_gem_obj, msm_host->aspace); 1163 msm_gem_address_space_put(msm_host->aspace); 1164 msm_host->tx_gem_obj = NULL; 1165 msm_host->aspace = NULL; 1166 } 1167 1168 if (msm_host->tx_buf) 1169 dma_free_coherent(dev->dev, msm_host->tx_size, msm_host->tx_buf, 1170 msm_host->tx_buf_paddr); 1171} 1172 1173void *dsi_tx_buf_get_6g(struct msm_dsi_host *msm_host) 1174{ 1175 return msm_gem_get_vaddr(msm_host->tx_gem_obj); 1176} 1177 1178void *dsi_tx_buf_get_v2(struct msm_dsi_host *msm_host) 1179{ 1180 return msm_host->tx_buf; 1181} 1182 1183void dsi_tx_buf_put_6g(struct msm_dsi_host *msm_host) 1184{ 1185 msm_gem_put_vaddr(msm_host->tx_gem_obj); 1186} 1187 1188/* 1189 * prepare cmd buffer to be txed 1190 */ 1191static int dsi_cmd_dma_add(struct msm_dsi_host *msm_host, 1192 const struct mipi_dsi_msg *msg) 1193{ 1194 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 1195 struct mipi_dsi_packet packet; 1196 int len; 1197 int ret; 1198 u8 *data; 1199 1200 ret = mipi_dsi_create_packet(&packet, msg); 1201 if (ret) { 1202 pr_err("%s: create packet failed, %d\n", __func__, ret); 1203 return ret; 1204 } 1205 len = (packet.size + 3) & (~0x3); 1206 1207 if (len > msm_host->tx_size) { 1208 pr_err("%s: packet size is too big\n", __func__); 1209 return -EINVAL; 1210 } 1211 1212 data = cfg_hnd->ops->tx_buf_get(msm_host); 1213 if (IS_ERR(data)) { 1214 ret = PTR_ERR(data); 1215 pr_err("%s: get vaddr failed, %d\n", __func__, ret); 1216 return ret; 1217 } 1218 1219 /* MSM specific command format in memory */ 1220 data[0] = packet.header[1]; 1221 data[1] = packet.header[2]; 1222 data[2] = packet.header[0]; 1223 data[3] = BIT(7); /* Last packet */ 1224 if (mipi_dsi_packet_format_is_long(msg->type)) 1225 data[3] |= BIT(6); 1226 if (msg->rx_buf && msg->rx_len) 1227 data[3] |= BIT(5); 1228 1229 /* Long packet */ 1230 if (packet.payload && packet.payload_length) 1231 memcpy(data + 4, packet.payload, packet.payload_length); 1232 1233 /* Append 0xff to the end */ 1234 if (packet.size < len) 1235 memset(data + packet.size, 0xff, len - packet.size); 1236 1237 if (cfg_hnd->ops->tx_buf_put) 1238 cfg_hnd->ops->tx_buf_put(msm_host); 1239 1240 return len; 1241} 1242 1243/* 1244 * dsi_short_read1_resp: 1 parameter 1245 */ 1246static int dsi_short_read1_resp(u8 *buf, const struct mipi_dsi_msg *msg) 1247{ 1248 u8 *data = msg->rx_buf; 1249 if (data && (msg->rx_len >= 1)) { 1250 *data = buf[1]; /* strip out dcs type */ 1251 return 1; 1252 } else { 1253 pr_err("%s: read data does not match with rx_buf len %zu\n", 1254 __func__, msg->rx_len); 1255 return -EINVAL; 1256 } 1257} 1258 1259/* 1260 * dsi_short_read2_resp: 2 parameter 1261 */ 1262static int dsi_short_read2_resp(u8 *buf, const struct mipi_dsi_msg *msg) 1263{ 1264 u8 *data = msg->rx_buf; 1265 if (data && (msg->rx_len >= 2)) { 1266 data[0] = buf[1]; /* strip out dcs type */ 1267 data[1] = buf[2]; 1268 return 2; 1269 } else { 1270 pr_err("%s: read data does not match with rx_buf len %zu\n", 1271 __func__, msg->rx_len); 1272 return -EINVAL; 1273 } 1274} 1275 1276static int dsi_long_read_resp(u8 *buf, const struct mipi_dsi_msg *msg) 1277{ 1278 /* strip out 4 byte dcs header */ 1279 if (msg->rx_buf && msg->rx_len) 1280 memcpy(msg->rx_buf, buf + 4, msg->rx_len); 1281 1282 return msg->rx_len; 1283} 1284 1285int dsi_dma_base_get_6g(struct msm_dsi_host *msm_host, uint64_t *dma_base) 1286{ 1287 struct drm_device *dev = msm_host->dev; 1288 struct msm_drm_private *priv = dev->dev_private; 1289 1290 if (!dma_base) 1291 return -EINVAL; 1292 1293 return msm_gem_get_and_pin_iova(msm_host->tx_gem_obj, 1294 priv->kms->aspace, dma_base); 1295} 1296 1297int dsi_dma_base_get_v2(struct msm_dsi_host *msm_host, uint64_t *dma_base) 1298{ 1299 if (!dma_base) 1300 return -EINVAL; 1301 1302 *dma_base = msm_host->tx_buf_paddr; 1303 return 0; 1304} 1305 1306static int dsi_cmd_dma_tx(struct msm_dsi_host *msm_host, int len) 1307{ 1308 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 1309 int ret; 1310 uint64_t dma_base; 1311 bool triggered; 1312 1313 ret = cfg_hnd->ops->dma_base_get(msm_host, &dma_base); 1314 if (ret) { 1315 pr_err("%s: failed to get iova: %d\n", __func__, ret); 1316 return ret; 1317 } 1318 1319 reinit_completion(&msm_host->dma_comp); 1320 1321 dsi_wait4video_eng_busy(msm_host); 1322 1323 triggered = msm_dsi_manager_cmd_xfer_trigger( 1324 msm_host->id, dma_base, len); 1325 if (triggered) { 1326 ret = wait_for_completion_timeout(&msm_host->dma_comp, 1327 msecs_to_jiffies(200)); 1328 DBG("ret=%d", ret); 1329 if (ret == 0) 1330 ret = -ETIMEDOUT; 1331 else 1332 ret = len; 1333 } else 1334 ret = len; 1335 1336 return ret; 1337} 1338 1339static int dsi_cmd_dma_rx(struct msm_dsi_host *msm_host, 1340 u8 *buf, int rx_byte, int pkt_size) 1341{ 1342 u32 *temp, data; 1343 int i, j = 0, cnt; 1344 u32 read_cnt; 1345 u8 reg[16]; 1346 int repeated_bytes = 0; 1347 int buf_offset = buf - msm_host->rx_buf; 1348 1349 temp = (u32 *)reg; 1350 cnt = (rx_byte + 3) >> 2; 1351 if (cnt > 4) 1352 cnt = 4; /* 4 x 32 bits registers only */ 1353 1354 if (rx_byte == 4) 1355 read_cnt = 4; 1356 else 1357 read_cnt = pkt_size + 6; 1358 1359 /* 1360 * In case of multiple reads from the panel, after the first read, there 1361 * is possibility that there are some bytes in the payload repeating in 1362 * the RDBK_DATA registers. Since we read all the parameters from the 1363 * panel right from the first byte for every pass. We need to skip the 1364 * repeating bytes and then append the new parameters to the rx buffer. 1365 */ 1366 if (read_cnt > 16) { 1367 int bytes_shifted; 1368 /* Any data more than 16 bytes will be shifted out. 1369 * The temp read buffer should already contain these bytes. 1370 * The remaining bytes in read buffer are the repeated bytes. 1371 */ 1372 bytes_shifted = read_cnt - 16; 1373 repeated_bytes = buf_offset - bytes_shifted; 1374 } 1375 1376 for (i = cnt - 1; i >= 0; i--) { 1377 data = dsi_read(msm_host, REG_DSI_RDBK_DATA(i)); 1378 *temp++ = ntohl(data); /* to host byte order */ 1379 DBG("data = 0x%x and ntohl(data) = 0x%x", data, ntohl(data)); 1380 } 1381 1382 for (i = repeated_bytes; i < 16; i++) 1383 buf[j++] = reg[i]; 1384 1385 return j; 1386} 1387 1388static int dsi_cmds2buf_tx(struct msm_dsi_host *msm_host, 1389 const struct mipi_dsi_msg *msg) 1390{ 1391 int len, ret; 1392 int bllp_len = msm_host->mode->hdisplay * 1393 dsi_get_bpp(msm_host->format) / 8; 1394 1395 len = dsi_cmd_dma_add(msm_host, msg); 1396 if (len < 0) { 1397 pr_err("%s: failed to add cmd type = 0x%x\n", 1398 __func__, msg->type); 1399 return len; 1400 } 1401 1402 /* for video mode, do not send cmds more than 1403 * one pixel line, since it only transmit it 1404 * during BLLP. 1405 */ 1406 /* TODO: if the command is sent in LP mode, the bit rate is only 1407 * half of esc clk rate. In this case, if the video is already 1408 * actively streaming, we need to check more carefully if the 1409 * command can be fit into one BLLP. 1410 */ 1411 if ((msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) && (len > bllp_len)) { 1412 pr_err("%s: cmd cannot fit into BLLP period, len=%d\n", 1413 __func__, len); 1414 return -EINVAL; 1415 } 1416 1417 ret = dsi_cmd_dma_tx(msm_host, len); 1418 if (ret < 0) { 1419 pr_err("%s: cmd dma tx failed, type=0x%x, data0=0x%x, len=%d, ret=%d\n", 1420 __func__, msg->type, (*(u8 *)(msg->tx_buf)), len, ret); 1421 return ret; 1422 } else if (ret < len) { 1423 pr_err("%s: cmd dma tx failed, type=0x%x, data0=0x%x, ret=%d len=%d\n", 1424 __func__, msg->type, (*(u8 *)(msg->tx_buf)), ret, len); 1425 return -EIO; 1426 } 1427 1428 return len; 1429} 1430 1431static void dsi_err_worker(struct work_struct *work) 1432{ 1433 struct msm_dsi_host *msm_host = 1434 container_of(work, struct msm_dsi_host, err_work); 1435 u32 status = msm_host->err_work_state; 1436 1437 pr_err_ratelimited("%s: status=%x\n", __func__, status); 1438 if (status & DSI_ERR_STATE_MDP_FIFO_UNDERFLOW) 1439 dsi_sw_reset(msm_host); 1440 1441 /* It is safe to clear here because error irq is disabled. */ 1442 msm_host->err_work_state = 0; 1443 1444 /* enable dsi error interrupt */ 1445 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1); 1446} 1447 1448static void dsi_ack_err_status(struct msm_dsi_host *msm_host) 1449{ 1450 u32 status; 1451 1452 status = dsi_read(msm_host, REG_DSI_ACK_ERR_STATUS); 1453 1454 if (status) { 1455 dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, status); 1456 /* Writing of an extra 0 needed to clear error bits */ 1457 dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, 0); 1458 msm_host->err_work_state |= DSI_ERR_STATE_ACK; 1459 } 1460} 1461 1462static void dsi_timeout_status(struct msm_dsi_host *msm_host) 1463{ 1464 u32 status; 1465 1466 status = dsi_read(msm_host, REG_DSI_TIMEOUT_STATUS); 1467 1468 if (status) { 1469 dsi_write(msm_host, REG_DSI_TIMEOUT_STATUS, status); 1470 msm_host->err_work_state |= DSI_ERR_STATE_TIMEOUT; 1471 } 1472} 1473 1474static void dsi_dln0_phy_err(struct msm_dsi_host *msm_host) 1475{ 1476 u32 status; 1477 1478 status = dsi_read(msm_host, REG_DSI_DLN0_PHY_ERR); 1479 1480 if (status & (DSI_DLN0_PHY_ERR_DLN0_ERR_ESC | 1481 DSI_DLN0_PHY_ERR_DLN0_ERR_SYNC_ESC | 1482 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTROL | 1483 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP0 | 1484 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP1)) { 1485 dsi_write(msm_host, REG_DSI_DLN0_PHY_ERR, status); 1486 msm_host->err_work_state |= DSI_ERR_STATE_DLN0_PHY; 1487 } 1488} 1489 1490static void dsi_fifo_status(struct msm_dsi_host *msm_host) 1491{ 1492 u32 status; 1493 1494 status = dsi_read(msm_host, REG_DSI_FIFO_STATUS); 1495 1496 /* fifo underflow, overflow */ 1497 if (status) { 1498 dsi_write(msm_host, REG_DSI_FIFO_STATUS, status); 1499 msm_host->err_work_state |= DSI_ERR_STATE_FIFO; 1500 if (status & DSI_FIFO_STATUS_CMD_MDP_FIFO_UNDERFLOW) 1501 msm_host->err_work_state |= 1502 DSI_ERR_STATE_MDP_FIFO_UNDERFLOW; 1503 } 1504} 1505 1506static void dsi_status(struct msm_dsi_host *msm_host) 1507{ 1508 u32 status; 1509 1510 status = dsi_read(msm_host, REG_DSI_STATUS0); 1511 1512 if (status & DSI_STATUS0_INTERLEAVE_OP_CONTENTION) { 1513 dsi_write(msm_host, REG_DSI_STATUS0, status); 1514 msm_host->err_work_state |= 1515 DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION; 1516 } 1517} 1518 1519static void dsi_clk_status(struct msm_dsi_host *msm_host) 1520{ 1521 u32 status; 1522 1523 status = dsi_read(msm_host, REG_DSI_CLK_STATUS); 1524 1525 if (status & DSI_CLK_STATUS_PLL_UNLOCKED) { 1526 dsi_write(msm_host, REG_DSI_CLK_STATUS, status); 1527 msm_host->err_work_state |= DSI_ERR_STATE_PLL_UNLOCKED; 1528 } 1529} 1530 1531static void dsi_error(struct msm_dsi_host *msm_host) 1532{ 1533 /* disable dsi error interrupt */ 1534 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 0); 1535 1536 dsi_clk_status(msm_host); 1537 dsi_fifo_status(msm_host); 1538 dsi_ack_err_status(msm_host); 1539 dsi_timeout_status(msm_host); 1540 dsi_status(msm_host); 1541 dsi_dln0_phy_err(msm_host); 1542 1543 queue_work(msm_host->workqueue, &msm_host->err_work); 1544} 1545 1546static irqreturn_t dsi_host_irq(int irq, void *ptr) 1547{ 1548 struct msm_dsi_host *msm_host = ptr; 1549 u32 isr; 1550 unsigned long flags; 1551 1552 if (!msm_host->ctrl_base) 1553 return IRQ_HANDLED; 1554 1555 spin_lock_irqsave(&msm_host->intr_lock, flags); 1556 isr = dsi_read(msm_host, REG_DSI_INTR_CTRL); 1557 dsi_write(msm_host, REG_DSI_INTR_CTRL, isr); 1558 spin_unlock_irqrestore(&msm_host->intr_lock, flags); 1559 1560 DBG("isr=0x%x, id=%d", isr, msm_host->id); 1561 1562 if (isr & DSI_IRQ_ERROR) 1563 dsi_error(msm_host); 1564 1565 if (isr & DSI_IRQ_VIDEO_DONE) 1566 complete(&msm_host->video_comp); 1567 1568 if (isr & DSI_IRQ_CMD_DMA_DONE) 1569 complete(&msm_host->dma_comp); 1570 1571 return IRQ_HANDLED; 1572} 1573 1574static int dsi_host_init_panel_gpios(struct msm_dsi_host *msm_host, 1575 struct device *panel_device) 1576{ 1577 msm_host->disp_en_gpio = devm_gpiod_get_optional(panel_device, 1578 "disp-enable", 1579 GPIOD_OUT_LOW); 1580 if (IS_ERR(msm_host->disp_en_gpio)) { 1581 DBG("cannot get disp-enable-gpios %ld", 1582 PTR_ERR(msm_host->disp_en_gpio)); 1583 return PTR_ERR(msm_host->disp_en_gpio); 1584 } 1585 1586 msm_host->te_gpio = devm_gpiod_get_optional(panel_device, "disp-te", 1587 GPIOD_IN); 1588 if (IS_ERR(msm_host->te_gpio)) { 1589 DBG("cannot get disp-te-gpios %ld", PTR_ERR(msm_host->te_gpio)); 1590 return PTR_ERR(msm_host->te_gpio); 1591 } 1592 1593 return 0; 1594} 1595 1596static int dsi_host_attach(struct mipi_dsi_host *host, 1597 struct mipi_dsi_device *dsi) 1598{ 1599 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1600 int ret; 1601 1602 if (dsi->lanes > msm_host->num_data_lanes) 1603 return -EINVAL; 1604 1605 msm_host->channel = dsi->channel; 1606 msm_host->lanes = dsi->lanes; 1607 msm_host->format = dsi->format; 1608 msm_host->mode_flags = dsi->mode_flags; 1609 if (dsi->dsc) 1610 msm_host->dsc = dsi->dsc; 1611 1612 /* Some gpios defined in panel DT need to be controlled by host */ 1613 ret = dsi_host_init_panel_gpios(msm_host, &dsi->dev); 1614 if (ret) 1615 return ret; 1616 1617 ret = dsi_dev_attach(msm_host->pdev); 1618 if (ret) 1619 return ret; 1620 1621 DBG("id=%d", msm_host->id); 1622 1623 return 0; 1624} 1625 1626static int dsi_host_detach(struct mipi_dsi_host *host, 1627 struct mipi_dsi_device *dsi) 1628{ 1629 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1630 1631 dsi_dev_detach(msm_host->pdev); 1632 1633 DBG("id=%d", msm_host->id); 1634 1635 return 0; 1636} 1637 1638static ssize_t dsi_host_transfer(struct mipi_dsi_host *host, 1639 const struct mipi_dsi_msg *msg) 1640{ 1641 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1642 int ret; 1643 1644 if (!msg || !msm_host->power_on) 1645 return -EINVAL; 1646 1647 mutex_lock(&msm_host->cmd_mutex); 1648 ret = msm_dsi_manager_cmd_xfer(msm_host->id, msg); 1649 mutex_unlock(&msm_host->cmd_mutex); 1650 1651 return ret; 1652} 1653 1654static const struct mipi_dsi_host_ops dsi_host_ops = { 1655 .attach = dsi_host_attach, 1656 .detach = dsi_host_detach, 1657 .transfer = dsi_host_transfer, 1658}; 1659 1660/* 1661 * List of supported physical to logical lane mappings. 1662 * For example, the 2nd entry represents the following mapping: 1663 * 1664 * "3012": Logic 3->Phys 0; Logic 0->Phys 1; Logic 1->Phys 2; Logic 2->Phys 3; 1665 */ 1666static const int supported_data_lane_swaps[][4] = { 1667 { 0, 1, 2, 3 }, 1668 { 3, 0, 1, 2 }, 1669 { 2, 3, 0, 1 }, 1670 { 1, 2, 3, 0 }, 1671 { 0, 3, 2, 1 }, 1672 { 1, 0, 3, 2 }, 1673 { 2, 1, 0, 3 }, 1674 { 3, 2, 1, 0 }, 1675}; 1676 1677static int dsi_host_parse_lane_data(struct msm_dsi_host *msm_host, 1678 struct device_node *ep) 1679{ 1680 struct device *dev = &msm_host->pdev->dev; 1681 struct property *prop; 1682 u32 lane_map[4]; 1683 int ret, i, len, num_lanes; 1684 1685 prop = of_find_property(ep, "data-lanes", &len); 1686 if (!prop) { 1687 DRM_DEV_DEBUG(dev, 1688 "failed to find data lane mapping, using default\n"); 1689 /* Set the number of date lanes to 4 by default. */ 1690 msm_host->num_data_lanes = 4; 1691 return 0; 1692 } 1693 1694 num_lanes = drm_of_get_data_lanes_count(ep, 1, 4); 1695 if (num_lanes < 0) { 1696 DRM_DEV_ERROR(dev, "bad number of data lanes\n"); 1697 return num_lanes; 1698 } 1699 1700 msm_host->num_data_lanes = num_lanes; 1701 1702 ret = of_property_read_u32_array(ep, "data-lanes", lane_map, 1703 num_lanes); 1704 if (ret) { 1705 DRM_DEV_ERROR(dev, "failed to read lane data\n"); 1706 return ret; 1707 } 1708 1709 /* 1710 * compare DT specified physical-logical lane mappings with the ones 1711 * supported by hardware 1712 */ 1713 for (i = 0; i < ARRAY_SIZE(supported_data_lane_swaps); i++) { 1714 const int *swap = supported_data_lane_swaps[i]; 1715 int j; 1716 1717 /* 1718 * the data-lanes array we get from DT has a logical->physical 1719 * mapping. The "data lane swap" register field represents 1720 * supported configurations in a physical->logical mapping. 1721 * Translate the DT mapping to what we understand and find a 1722 * configuration that works. 1723 */ 1724 for (j = 0; j < num_lanes; j++) { 1725 if (lane_map[j] < 0 || lane_map[j] > 3) 1726 DRM_DEV_ERROR(dev, "bad physical lane entry %u\n", 1727 lane_map[j]); 1728 1729 if (swap[lane_map[j]] != j) 1730 break; 1731 } 1732 1733 if (j == num_lanes) { 1734 msm_host->dlane_swap = i; 1735 return 0; 1736 } 1737 } 1738 1739 return -EINVAL; 1740} 1741 1742static int dsi_populate_dsc_params(struct msm_dsi_host *msm_host, struct drm_dsc_config *dsc) 1743{ 1744 int ret; 1745 1746 if (dsc->bits_per_pixel & 0xf) { 1747 DRM_DEV_ERROR(&msm_host->pdev->dev, "DSI does not support fractional bits_per_pixel\n"); 1748 return -EINVAL; 1749 } 1750 1751 if (dsc->bits_per_component != 8) { 1752 DRM_DEV_ERROR(&msm_host->pdev->dev, "DSI does not support bits_per_component != 8 yet\n"); 1753 return -EOPNOTSUPP; 1754 } 1755 1756 dsc->simple_422 = 0; 1757 dsc->convert_rgb = 1; 1758 dsc->vbr_enable = 0; 1759 1760 drm_dsc_set_const_params(dsc); 1761 drm_dsc_set_rc_buf_thresh(dsc); 1762 1763 /* handle only bpp = bpc = 8, pre-SCR panels */ 1764 ret = drm_dsc_setup_rc_params(dsc, DRM_DSC_1_1_PRE_SCR); 1765 if (ret) { 1766 DRM_DEV_ERROR(&msm_host->pdev->dev, "could not find DSC RC parameters\n"); 1767 return ret; 1768 } 1769 1770 dsc->initial_scale_value = drm_dsc_initial_scale_value(dsc); 1771 dsc->line_buf_depth = dsc->bits_per_component + 1; 1772 1773 return drm_dsc_compute_rc_parameters(dsc); 1774} 1775 1776static int dsi_host_parse_dt(struct msm_dsi_host *msm_host) 1777{ 1778 struct device *dev = &msm_host->pdev->dev; 1779 struct device_node *np = dev->of_node; 1780 struct device_node *endpoint; 1781 int ret = 0; 1782 1783 /* 1784 * Get the endpoint of the output port of the DSI host. In our case, 1785 * this is mapped to port number with reg = 1. Don't return an error if 1786 * the remote endpoint isn't defined. It's possible that there is 1787 * nothing connected to the dsi output. 1788 */ 1789 endpoint = of_graph_get_endpoint_by_regs(np, 1, -1); 1790 if (!endpoint) { 1791 DRM_DEV_DEBUG(dev, "%s: no endpoint\n", __func__); 1792 return 0; 1793 } 1794 1795 ret = dsi_host_parse_lane_data(msm_host, endpoint); 1796 if (ret) { 1797 DRM_DEV_ERROR(dev, "%s: invalid lane configuration %d\n", 1798 __func__, ret); 1799 ret = -EINVAL; 1800 goto err; 1801 } 1802 1803 if (of_property_read_bool(np, "syscon-sfpb")) { 1804 msm_host->sfpb = syscon_regmap_lookup_by_phandle(np, 1805 "syscon-sfpb"); 1806 if (IS_ERR(msm_host->sfpb)) { 1807 DRM_DEV_ERROR(dev, "%s: failed to get sfpb regmap\n", 1808 __func__); 1809 ret = PTR_ERR(msm_host->sfpb); 1810 } 1811 } 1812 1813err: 1814 of_node_put(endpoint); 1815 1816 return ret; 1817} 1818 1819static int dsi_host_get_id(struct msm_dsi_host *msm_host) 1820{ 1821 struct platform_device *pdev = msm_host->pdev; 1822 const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg; 1823 struct resource *res; 1824 int i, j; 1825 1826 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dsi_ctrl"); 1827 if (!res) 1828 return -EINVAL; 1829 1830 for (i = 0; i < VARIANTS_MAX; i++) 1831 for (j = 0; j < DSI_MAX; j++) 1832 if (cfg->io_start[i][j] == res->start) 1833 return j; 1834 1835 return -EINVAL; 1836} 1837 1838int msm_dsi_host_init(struct msm_dsi *msm_dsi) 1839{ 1840 struct msm_dsi_host *msm_host = NULL; 1841 struct platform_device *pdev = msm_dsi->pdev; 1842 const struct msm_dsi_config *cfg; 1843 int ret; 1844 1845 msm_host = devm_kzalloc(&pdev->dev, sizeof(*msm_host), GFP_KERNEL); 1846 if (!msm_host) { 1847 return -ENOMEM; 1848 } 1849 1850 msm_host->pdev = pdev; 1851 msm_dsi->host = &msm_host->base; 1852 1853 ret = dsi_host_parse_dt(msm_host); 1854 if (ret) { 1855 pr_err("%s: failed to parse dt\n", __func__); 1856 return ret; 1857 } 1858 1859 msm_host->ctrl_base = msm_ioremap_size(pdev, "dsi_ctrl", &msm_host->ctrl_size); 1860 if (IS_ERR(msm_host->ctrl_base)) { 1861 pr_err("%s: unable to map Dsi ctrl base\n", __func__); 1862 return PTR_ERR(msm_host->ctrl_base); 1863 } 1864 1865 pm_runtime_enable(&pdev->dev); 1866 1867 msm_host->cfg_hnd = dsi_get_config(msm_host); 1868 if (!msm_host->cfg_hnd) { 1869 pr_err("%s: get config failed\n", __func__); 1870 return -EINVAL; 1871 } 1872 cfg = msm_host->cfg_hnd->cfg; 1873 1874 msm_host->id = dsi_host_get_id(msm_host); 1875 if (msm_host->id < 0) { 1876 pr_err("%s: unable to identify DSI host index\n", __func__); 1877 return msm_host->id; 1878 } 1879 1880 /* fixup base address by io offset */ 1881 msm_host->ctrl_base += cfg->io_offset; 1882 1883 ret = devm_regulator_bulk_get_const(&pdev->dev, cfg->num_regulators, 1884 cfg->regulator_data, 1885 &msm_host->supplies); 1886 if (ret) 1887 return ret; 1888 1889 ret = dsi_clk_init(msm_host); 1890 if (ret) { 1891 pr_err("%s: unable to initialize dsi clks\n", __func__); 1892 return ret; 1893 } 1894 1895 msm_host->rx_buf = devm_kzalloc(&pdev->dev, SZ_4K, GFP_KERNEL); 1896 if (!msm_host->rx_buf) { 1897 pr_err("%s: alloc rx temp buf failed\n", __func__); 1898 return -ENOMEM; 1899 } 1900 1901 ret = devm_pm_opp_set_clkname(&pdev->dev, "byte"); 1902 if (ret) 1903 return ret; 1904 /* OPP table is optional */ 1905 ret = devm_pm_opp_of_add_table(&pdev->dev); 1906 if (ret && ret != -ENODEV) { 1907 dev_err(&pdev->dev, "invalid OPP table in device tree\n"); 1908 return ret; 1909 } 1910 1911 msm_host->irq = irq_of_parse_and_map(pdev->dev.of_node, 0); 1912 if (!msm_host->irq) { 1913 dev_err(&pdev->dev, "failed to get irq\n"); 1914 return -EINVAL; 1915 } 1916 1917 /* do not autoenable, will be enabled later */ 1918 ret = devm_request_irq(&pdev->dev, msm_host->irq, dsi_host_irq, 1919 IRQF_TRIGGER_HIGH | IRQF_NO_AUTOEN, 1920 "dsi_isr", msm_host); 1921 if (ret < 0) { 1922 dev_err(&pdev->dev, "failed to request IRQ%u: %d\n", 1923 msm_host->irq, ret); 1924 return ret; 1925 } 1926 1927 init_completion(&msm_host->dma_comp); 1928 init_completion(&msm_host->video_comp); 1929 mutex_init(&msm_host->dev_mutex); 1930 mutex_init(&msm_host->cmd_mutex); 1931 spin_lock_init(&msm_host->intr_lock); 1932 1933 /* setup workqueue */ 1934 msm_host->workqueue = alloc_ordered_workqueue("dsi_drm_work", 0); 1935 if (!msm_host->workqueue) 1936 return -ENOMEM; 1937 1938 INIT_WORK(&msm_host->err_work, dsi_err_worker); 1939 1940 msm_dsi->id = msm_host->id; 1941 1942 DBG("Dsi Host %d initialized", msm_host->id); 1943 return 0; 1944} 1945 1946void msm_dsi_host_destroy(struct mipi_dsi_host *host) 1947{ 1948 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1949 1950 DBG(""); 1951 if (msm_host->workqueue) { 1952 destroy_workqueue(msm_host->workqueue); 1953 msm_host->workqueue = NULL; 1954 } 1955 1956 mutex_destroy(&msm_host->cmd_mutex); 1957 mutex_destroy(&msm_host->dev_mutex); 1958 1959 pm_runtime_disable(&msm_host->pdev->dev); 1960} 1961 1962int msm_dsi_host_modeset_init(struct mipi_dsi_host *host, 1963 struct drm_device *dev) 1964{ 1965 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1966 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 1967 int ret; 1968 1969 msm_host->dev = dev; 1970 1971 ret = cfg_hnd->ops->tx_buf_alloc(msm_host, SZ_4K); 1972 if (ret) { 1973 pr_err("%s: alloc tx gem obj failed, %d\n", __func__, ret); 1974 return ret; 1975 } 1976 1977 return 0; 1978} 1979 1980int msm_dsi_host_register(struct mipi_dsi_host *host) 1981{ 1982 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1983 int ret; 1984 1985 /* Register mipi dsi host */ 1986 if (!msm_host->registered) { 1987 host->dev = &msm_host->pdev->dev; 1988 host->ops = &dsi_host_ops; 1989 ret = mipi_dsi_host_register(host); 1990 if (ret) 1991 return ret; 1992 1993 msm_host->registered = true; 1994 } 1995 1996 return 0; 1997} 1998 1999void msm_dsi_host_unregister(struct mipi_dsi_host *host) 2000{ 2001 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2002 2003 if (msm_host->registered) { 2004 mipi_dsi_host_unregister(host); 2005 host->dev = NULL; 2006 host->ops = NULL; 2007 msm_host->registered = false; 2008 } 2009} 2010 2011int msm_dsi_host_xfer_prepare(struct mipi_dsi_host *host, 2012 const struct mipi_dsi_msg *msg) 2013{ 2014 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2015 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2016 2017 /* TODO: make sure dsi_cmd_mdp is idle. 2018 * Since DSI6G v1.2.0, we can set DSI_TRIG_CTRL.BLOCK_DMA_WITHIN_FRAME 2019 * to ask H/W to wait until cmd mdp is idle. S/W wait is not needed. 2020 * How to handle the old versions? Wait for mdp cmd done? 2021 */ 2022 2023 /* 2024 * mdss interrupt is generated in mdp core clock domain 2025 * mdp clock need to be enabled to receive dsi interrupt 2026 */ 2027 pm_runtime_get_sync(&msm_host->pdev->dev); 2028 cfg_hnd->ops->link_clk_set_rate(msm_host); 2029 cfg_hnd->ops->link_clk_enable(msm_host); 2030 2031 /* TODO: vote for bus bandwidth */ 2032 2033 if (!(msg->flags & MIPI_DSI_MSG_USE_LPM)) 2034 dsi_set_tx_power_mode(0, msm_host); 2035 2036 msm_host->dma_cmd_ctrl_restore = dsi_read(msm_host, REG_DSI_CTRL); 2037 dsi_write(msm_host, REG_DSI_CTRL, 2038 msm_host->dma_cmd_ctrl_restore | 2039 DSI_CTRL_CMD_MODE_EN | 2040 DSI_CTRL_ENABLE); 2041 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 1); 2042 2043 return 0; 2044} 2045 2046void msm_dsi_host_xfer_restore(struct mipi_dsi_host *host, 2047 const struct mipi_dsi_msg *msg) 2048{ 2049 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2050 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2051 2052 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 0); 2053 dsi_write(msm_host, REG_DSI_CTRL, msm_host->dma_cmd_ctrl_restore); 2054 2055 if (!(msg->flags & MIPI_DSI_MSG_USE_LPM)) 2056 dsi_set_tx_power_mode(1, msm_host); 2057 2058 /* TODO: unvote for bus bandwidth */ 2059 2060 cfg_hnd->ops->link_clk_disable(msm_host); 2061 pm_runtime_put(&msm_host->pdev->dev); 2062} 2063 2064int msm_dsi_host_cmd_tx(struct mipi_dsi_host *host, 2065 const struct mipi_dsi_msg *msg) 2066{ 2067 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2068 2069 return dsi_cmds2buf_tx(msm_host, msg); 2070} 2071 2072int msm_dsi_host_cmd_rx(struct mipi_dsi_host *host, 2073 const struct mipi_dsi_msg *msg) 2074{ 2075 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2076 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2077 int data_byte, rx_byte, dlen, end; 2078 int short_response, diff, pkt_size, ret = 0; 2079 char cmd; 2080 int rlen = msg->rx_len; 2081 u8 *buf; 2082 2083 if (rlen <= 2) { 2084 short_response = 1; 2085 pkt_size = rlen; 2086 rx_byte = 4; 2087 } else { 2088 short_response = 0; 2089 data_byte = 10; /* first read */ 2090 if (rlen < data_byte) 2091 pkt_size = rlen; 2092 else 2093 pkt_size = data_byte; 2094 rx_byte = data_byte + 6; /* 4 header + 2 crc */ 2095 } 2096 2097 buf = msm_host->rx_buf; 2098 end = 0; 2099 while (!end) { 2100 u8 tx[2] = {pkt_size & 0xff, pkt_size >> 8}; 2101 struct mipi_dsi_msg max_pkt_size_msg = { 2102 .channel = msg->channel, 2103 .type = MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, 2104 .tx_len = 2, 2105 .tx_buf = tx, 2106 }; 2107 2108 DBG("rlen=%d pkt_size=%d rx_byte=%d", 2109 rlen, pkt_size, rx_byte); 2110 2111 ret = dsi_cmds2buf_tx(msm_host, &max_pkt_size_msg); 2112 if (ret < 2) { 2113 pr_err("%s: Set max pkt size failed, %d\n", 2114 __func__, ret); 2115 return -EINVAL; 2116 } 2117 2118 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) && 2119 (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_1)) { 2120 /* Clear the RDBK_DATA registers */ 2121 dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL, 2122 DSI_RDBK_DATA_CTRL_CLR); 2123 wmb(); /* make sure the RDBK registers are cleared */ 2124 dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL, 0); 2125 wmb(); /* release cleared status before transfer */ 2126 } 2127 2128 ret = dsi_cmds2buf_tx(msm_host, msg); 2129 if (ret < 0) { 2130 pr_err("%s: Read cmd Tx failed, %d\n", __func__, ret); 2131 return ret; 2132 } else if (ret < msg->tx_len) { 2133 pr_err("%s: Read cmd Tx failed, too short: %d\n", __func__, ret); 2134 return -ECOMM; 2135 } 2136 2137 /* 2138 * once cmd_dma_done interrupt received, 2139 * return data from client is ready and stored 2140 * at RDBK_DATA register already 2141 * since rx fifo is 16 bytes, dcs header is kept at first loop, 2142 * after that dcs header lost during shift into registers 2143 */ 2144 dlen = dsi_cmd_dma_rx(msm_host, buf, rx_byte, pkt_size); 2145 2146 if (dlen <= 0) 2147 return 0; 2148 2149 if (short_response) 2150 break; 2151 2152 if (rlen <= data_byte) { 2153 diff = data_byte - rlen; 2154 end = 1; 2155 } else { 2156 diff = 0; 2157 rlen -= data_byte; 2158 } 2159 2160 if (!end) { 2161 dlen -= 2; /* 2 crc */ 2162 dlen -= diff; 2163 buf += dlen; /* next start position */ 2164 data_byte = 14; /* NOT first read */ 2165 if (rlen < data_byte) 2166 pkt_size += rlen; 2167 else 2168 pkt_size += data_byte; 2169 DBG("buf=%p dlen=%d diff=%d", buf, dlen, diff); 2170 } 2171 } 2172 2173 /* 2174 * For single Long read, if the requested rlen < 10, 2175 * we need to shift the start position of rx 2176 * data buffer to skip the bytes which are not 2177 * updated. 2178 */ 2179 if (pkt_size < 10 && !short_response) 2180 buf = msm_host->rx_buf + (10 - rlen); 2181 else 2182 buf = msm_host->rx_buf; 2183 2184 cmd = buf[0]; 2185 switch (cmd) { 2186 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT: 2187 pr_err("%s: rx ACK_ERR_PACLAGE\n", __func__); 2188 ret = 0; 2189 break; 2190 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE: 2191 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE: 2192 ret = dsi_short_read1_resp(buf, msg); 2193 break; 2194 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE: 2195 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE: 2196 ret = dsi_short_read2_resp(buf, msg); 2197 break; 2198 case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE: 2199 case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE: 2200 ret = dsi_long_read_resp(buf, msg); 2201 break; 2202 default: 2203 pr_warn("%s:Invalid response cmd\n", __func__); 2204 ret = 0; 2205 } 2206 2207 return ret; 2208} 2209 2210void msm_dsi_host_cmd_xfer_commit(struct mipi_dsi_host *host, u32 dma_base, 2211 u32 len) 2212{ 2213 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2214 2215 dsi_write(msm_host, REG_DSI_DMA_BASE, dma_base); 2216 dsi_write(msm_host, REG_DSI_DMA_LEN, len); 2217 dsi_write(msm_host, REG_DSI_TRIG_DMA, 1); 2218 2219 /* Make sure trigger happens */ 2220 wmb(); 2221} 2222 2223void msm_dsi_host_set_phy_mode(struct mipi_dsi_host *host, 2224 struct msm_dsi_phy *src_phy) 2225{ 2226 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2227 2228 msm_host->cphy_mode = src_phy->cphy_mode; 2229} 2230 2231void msm_dsi_host_reset_phy(struct mipi_dsi_host *host) 2232{ 2233 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2234 2235 DBG(""); 2236 dsi_write(msm_host, REG_DSI_PHY_RESET, DSI_PHY_RESET_RESET); 2237 /* Make sure fully reset */ 2238 wmb(); 2239 udelay(1000); 2240 dsi_write(msm_host, REG_DSI_PHY_RESET, 0); 2241 udelay(100); 2242} 2243 2244void msm_dsi_host_get_phy_clk_req(struct mipi_dsi_host *host, 2245 struct msm_dsi_phy_clk_request *clk_req, 2246 bool is_bonded_dsi) 2247{ 2248 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2249 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2250 int ret; 2251 2252 ret = cfg_hnd->ops->calc_clk_rate(msm_host, is_bonded_dsi); 2253 if (ret) { 2254 pr_err("%s: unable to calc clk rate, %d\n", __func__, ret); 2255 return; 2256 } 2257 2258 /* CPHY transmits 16 bits over 7 clock cycles 2259 * "byte_clk" is in units of 16-bits (see dsi_calc_pclk), 2260 * so multiply by 7 to get the "bitclk rate" 2261 */ 2262 if (msm_host->cphy_mode) 2263 clk_req->bitclk_rate = msm_host->byte_clk_rate * 7; 2264 else 2265 clk_req->bitclk_rate = msm_host->byte_clk_rate * 8; 2266 clk_req->escclk_rate = msm_host->esc_clk_rate; 2267} 2268 2269void msm_dsi_host_enable_irq(struct mipi_dsi_host *host) 2270{ 2271 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2272 2273 enable_irq(msm_host->irq); 2274} 2275 2276void msm_dsi_host_disable_irq(struct mipi_dsi_host *host) 2277{ 2278 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2279 2280 disable_irq(msm_host->irq); 2281} 2282 2283int msm_dsi_host_enable(struct mipi_dsi_host *host) 2284{ 2285 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2286 2287 dsi_op_mode_config(msm_host, 2288 !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), true); 2289 2290 /* TODO: clock should be turned off for command mode, 2291 * and only turned on before MDP START. 2292 * This part of code should be enabled once mdp driver support it. 2293 */ 2294 /* if (msm_panel->mode == MSM_DSI_CMD_MODE) { 2295 * dsi_link_clk_disable(msm_host); 2296 * pm_runtime_put(&msm_host->pdev->dev); 2297 * } 2298 */ 2299 msm_host->enabled = true; 2300 return 0; 2301} 2302 2303int msm_dsi_host_disable(struct mipi_dsi_host *host) 2304{ 2305 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2306 2307 msm_host->enabled = false; 2308 dsi_op_mode_config(msm_host, 2309 !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), false); 2310 2311 /* Since we have disabled INTF, the video engine won't stop so that 2312 * the cmd engine will be blocked. 2313 * Reset to disable video engine so that we can send off cmd. 2314 */ 2315 dsi_sw_reset(msm_host); 2316 2317 return 0; 2318} 2319 2320static void msm_dsi_sfpb_config(struct msm_dsi_host *msm_host, bool enable) 2321{ 2322 enum sfpb_ahb_arb_master_port_en en; 2323 2324 if (!msm_host->sfpb) 2325 return; 2326 2327 en = enable ? SFPB_MASTER_PORT_ENABLE : SFPB_MASTER_PORT_DISABLE; 2328 2329 regmap_update_bits(msm_host->sfpb, REG_SFPB_GPREG, 2330 SFPB_GPREG_MASTER_PORT_EN__MASK, 2331 SFPB_GPREG_MASTER_PORT_EN(en)); 2332} 2333 2334int msm_dsi_host_power_on(struct mipi_dsi_host *host, 2335 struct msm_dsi_phy_shared_timings *phy_shared_timings, 2336 bool is_bonded_dsi, struct msm_dsi_phy *phy) 2337{ 2338 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2339 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2340 int ret = 0; 2341 2342 mutex_lock(&msm_host->dev_mutex); 2343 if (msm_host->power_on) { 2344 DBG("dsi host already on"); 2345 goto unlock_ret; 2346 } 2347 2348 msm_host->byte_intf_clk_rate = msm_host->byte_clk_rate; 2349 if (phy_shared_timings->byte_intf_clk_div_2) 2350 msm_host->byte_intf_clk_rate /= 2; 2351 2352 msm_dsi_sfpb_config(msm_host, true); 2353 2354 ret = regulator_bulk_enable(msm_host->cfg_hnd->cfg->num_regulators, 2355 msm_host->supplies); 2356 if (ret) { 2357 pr_err("%s:Failed to enable vregs.ret=%d\n", 2358 __func__, ret); 2359 goto unlock_ret; 2360 } 2361 2362 pm_runtime_get_sync(&msm_host->pdev->dev); 2363 ret = cfg_hnd->ops->link_clk_set_rate(msm_host); 2364 if (!ret) 2365 ret = cfg_hnd->ops->link_clk_enable(msm_host); 2366 if (ret) { 2367 pr_err("%s: failed to enable link clocks. ret=%d\n", 2368 __func__, ret); 2369 goto fail_disable_reg; 2370 } 2371 2372 ret = pinctrl_pm_select_default_state(&msm_host->pdev->dev); 2373 if (ret) { 2374 pr_err("%s: failed to set pinctrl default state, %d\n", 2375 __func__, ret); 2376 goto fail_disable_clk; 2377 } 2378 2379 dsi_timing_setup(msm_host, is_bonded_dsi); 2380 dsi_sw_reset(msm_host); 2381 dsi_ctrl_enable(msm_host, phy_shared_timings, phy); 2382 2383 if (msm_host->disp_en_gpio) 2384 gpiod_set_value(msm_host->disp_en_gpio, 1); 2385 2386 msm_host->power_on = true; 2387 mutex_unlock(&msm_host->dev_mutex); 2388 2389 return 0; 2390 2391fail_disable_clk: 2392 cfg_hnd->ops->link_clk_disable(msm_host); 2393 pm_runtime_put(&msm_host->pdev->dev); 2394fail_disable_reg: 2395 regulator_bulk_disable(msm_host->cfg_hnd->cfg->num_regulators, 2396 msm_host->supplies); 2397unlock_ret: 2398 mutex_unlock(&msm_host->dev_mutex); 2399 return ret; 2400} 2401 2402int msm_dsi_host_power_off(struct mipi_dsi_host *host) 2403{ 2404 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2405 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2406 2407 mutex_lock(&msm_host->dev_mutex); 2408 if (!msm_host->power_on) { 2409 DBG("dsi host already off"); 2410 goto unlock_ret; 2411 } 2412 2413 dsi_ctrl_disable(msm_host); 2414 2415 if (msm_host->disp_en_gpio) 2416 gpiod_set_value(msm_host->disp_en_gpio, 0); 2417 2418 pinctrl_pm_select_sleep_state(&msm_host->pdev->dev); 2419 2420 cfg_hnd->ops->link_clk_disable(msm_host); 2421 pm_runtime_put(&msm_host->pdev->dev); 2422 2423 regulator_bulk_disable(msm_host->cfg_hnd->cfg->num_regulators, 2424 msm_host->supplies); 2425 2426 msm_dsi_sfpb_config(msm_host, false); 2427 2428 DBG("-"); 2429 2430 msm_host->power_on = false; 2431 2432unlock_ret: 2433 mutex_unlock(&msm_host->dev_mutex); 2434 return 0; 2435} 2436 2437int msm_dsi_host_set_display_mode(struct mipi_dsi_host *host, 2438 const struct drm_display_mode *mode) 2439{ 2440 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2441 2442 if (msm_host->mode) { 2443 drm_mode_destroy(msm_host->dev, msm_host->mode); 2444 msm_host->mode = NULL; 2445 } 2446 2447 msm_host->mode = drm_mode_duplicate(msm_host->dev, mode); 2448 if (!msm_host->mode) { 2449 pr_err("%s: cannot duplicate mode\n", __func__); 2450 return -ENOMEM; 2451 } 2452 2453 return 0; 2454} 2455 2456enum drm_mode_status msm_dsi_host_check_dsc(struct mipi_dsi_host *host, 2457 const struct drm_display_mode *mode) 2458{ 2459 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2460 struct drm_dsc_config *dsc = msm_host->dsc; 2461 int pic_width = mode->hdisplay; 2462 int pic_height = mode->vdisplay; 2463 2464 if (!msm_host->dsc) 2465 return MODE_OK; 2466 2467 if (pic_width % dsc->slice_width) { 2468 pr_err("DSI: pic_width %d has to be multiple of slice %d\n", 2469 pic_width, dsc->slice_width); 2470 return MODE_H_ILLEGAL; 2471 } 2472 2473 if (pic_height % dsc->slice_height) { 2474 pr_err("DSI: pic_height %d has to be multiple of slice %d\n", 2475 pic_height, dsc->slice_height); 2476 return MODE_V_ILLEGAL; 2477 } 2478 2479 return MODE_OK; 2480} 2481 2482unsigned long msm_dsi_host_get_mode_flags(struct mipi_dsi_host *host) 2483{ 2484 return to_msm_dsi_host(host)->mode_flags; 2485} 2486 2487void msm_dsi_host_snapshot(struct msm_disp_state *disp_state, struct mipi_dsi_host *host) 2488{ 2489 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2490 2491 pm_runtime_get_sync(&msm_host->pdev->dev); 2492 2493 msm_disp_snapshot_add_block(disp_state, msm_host->ctrl_size, 2494 msm_host->ctrl_base, "dsi%d_ctrl", msm_host->id); 2495 2496 pm_runtime_put_sync(&msm_host->pdev->dev); 2497} 2498 2499static void msm_dsi_host_video_test_pattern_setup(struct msm_dsi_host *msm_host) 2500{ 2501 u32 reg; 2502 2503 reg = dsi_read(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL); 2504 2505 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_VIDEO_INIT_VAL, 0xff); 2506 /* draw checkered rectangle pattern */ 2507 dsi_write(msm_host, REG_DSI_TPG_MAIN_CONTROL, 2508 DSI_TPG_MAIN_CONTROL_CHECKERED_RECTANGLE_PATTERN); 2509 /* use 24-bit RGB test pttern */ 2510 dsi_write(msm_host, REG_DSI_TPG_VIDEO_CONFIG, 2511 DSI_TPG_VIDEO_CONFIG_BPP(VIDEO_CONFIG_24BPP) | 2512 DSI_TPG_VIDEO_CONFIG_RGB); 2513 2514 reg |= DSI_TEST_PATTERN_GEN_CTRL_VIDEO_PATTERN_SEL(VID_MDSS_GENERAL_PATTERN); 2515 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL, reg); 2516 2517 DBG("Video test pattern setup done\n"); 2518} 2519 2520static void msm_dsi_host_cmd_test_pattern_setup(struct msm_dsi_host *msm_host) 2521{ 2522 u32 reg; 2523 2524 reg = dsi_read(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL); 2525 2526 /* initial value for test pattern */ 2527 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CMD_MDP_INIT_VAL0, 0xff); 2528 2529 reg |= DSI_TEST_PATTERN_GEN_CTRL_CMD_MDP_STREAM0_PATTERN_SEL(CMD_MDP_MDSS_GENERAL_PATTERN); 2530 2531 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL, reg); 2532 /* draw checkered rectangle pattern */ 2533 dsi_write(msm_host, REG_DSI_TPG_MAIN_CONTROL2, 2534 DSI_TPG_MAIN_CONTROL2_CMD_MDP0_CHECKERED_RECTANGLE_PATTERN); 2535 2536 DBG("Cmd test pattern setup done\n"); 2537} 2538 2539void msm_dsi_host_test_pattern_en(struct mipi_dsi_host *host) 2540{ 2541 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2542 bool is_video_mode = !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO); 2543 u32 reg; 2544 2545 if (is_video_mode) 2546 msm_dsi_host_video_test_pattern_setup(msm_host); 2547 else 2548 msm_dsi_host_cmd_test_pattern_setup(msm_host); 2549 2550 reg = dsi_read(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL); 2551 /* enable the test pattern generator */ 2552 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL, (reg | DSI_TEST_PATTERN_GEN_CTRL_EN)); 2553 2554 /* for command mode need to trigger one frame from tpg */ 2555 if (!is_video_mode) 2556 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER, 2557 DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER_SW_TRIGGER); 2558} 2559 2560struct drm_dsc_config *msm_dsi_host_get_dsc_config(struct mipi_dsi_host *host) 2561{ 2562 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2563 2564 return msm_host->dsc; 2565} 2566