1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Copyright (C) 2013 Red Hat 4 * Author: Rob Clark <robdclark@gmail.com> 5 * 6 * Copyright (c) 2014,2017, 2019 The Linux Foundation. All rights reserved. 7 */ 8 9#ifndef __ADRENO_GPU_H__ 10#define __ADRENO_GPU_H__ 11 12#include <linux/firmware.h> 13#include <linux/iopoll.h> 14 15#include "msm_gpu.h" 16 17#include "adreno_common.xml.h" 18#include "adreno_pm4.xml.h" 19 20extern bool snapshot_debugbus; 21extern bool allow_vram_carveout; 22 23enum { 24 ADRENO_FW_PM4 = 0, 25 ADRENO_FW_SQE = 0, /* a6xx */ 26 ADRENO_FW_PFP = 1, 27 ADRENO_FW_GMU = 1, /* a6xx */ 28 ADRENO_FW_GPMU = 2, 29 ADRENO_FW_MAX, 30}; 31 32/** 33 * @enum adreno_family: identify generation and possibly sub-generation 34 * 35 * In some cases there are distinct sub-generations within a major revision 36 * so it helps to be able to group the GPU devices by generation and if 37 * necessary sub-generation. 38 */ 39enum adreno_family { 40 ADRENO_2XX_GEN1, /* a20x */ 41 ADRENO_2XX_GEN2, /* a22x */ 42 ADRENO_3XX, 43 ADRENO_4XX, 44 ADRENO_5XX, 45 ADRENO_6XX_GEN1, /* a630 family */ 46 ADRENO_6XX_GEN2, /* a640 family */ 47 ADRENO_6XX_GEN3, /* a650 family */ 48 ADRENO_6XX_GEN4, /* a660 family */ 49}; 50 51#define ADRENO_QUIRK_TWO_PASS_USE_WFI BIT(0) 52#define ADRENO_QUIRK_FAULT_DETECT_MASK BIT(1) 53#define ADRENO_QUIRK_LMLOADKILL_DISABLE BIT(2) 54#define ADRENO_QUIRK_HAS_HW_APRIV BIT(3) 55#define ADRENO_QUIRK_HAS_CACHED_COHERENT BIT(4) 56 57/* Helper for formating the chip_id in the way that userspace tools like 58 * crashdec expect. 59 */ 60#define ADRENO_CHIPID_FMT "u.%u.%u.%u" 61#define ADRENO_CHIPID_ARGS(_c) \ 62 (((_c) >> 24) & 0xff), \ 63 (((_c) >> 16) & 0xff), \ 64 (((_c) >> 8) & 0xff), \ 65 ((_c) & 0xff) 66 67struct adreno_gpu_funcs { 68 struct msm_gpu_funcs base; 69 int (*get_timestamp)(struct msm_gpu *gpu, uint64_t *value); 70}; 71 72struct adreno_reglist { 73 u32 offset; 74 u32 value; 75}; 76 77extern const struct adreno_reglist a612_hwcg[], a615_hwcg[], a630_hwcg[], a640_hwcg[], a650_hwcg[]; 78extern const struct adreno_reglist a660_hwcg[], a690_hwcg[]; 79 80struct adreno_speedbin { 81 uint16_t fuse; 82 uint16_t speedbin; 83}; 84 85struct adreno_info { 86 const char *machine; 87 /** 88 * @chipids: Table of matching chip-ids 89 * 90 * Terminated with 0 sentinal 91 */ 92 uint32_t *chip_ids; 93 enum adreno_family family; 94 uint32_t revn; 95 const char *fw[ADRENO_FW_MAX]; 96 uint32_t gmem; 97 u64 quirks; 98 struct msm_gpu *(*init)(struct drm_device *dev); 99 const char *zapfw; 100 u32 inactive_period; 101 const struct adreno_reglist *hwcg; 102 u64 address_space_size; 103 /** 104 * @speedbins: Optional table of fuse to speedbin mappings 105 * 106 * Consists of pairs of fuse, index mappings, terminated with 107 * {SHRT_MAX, 0} sentinal. 108 */ 109 struct adreno_speedbin *speedbins; 110}; 111 112#define ADRENO_CHIP_IDS(tbl...) (uint32_t[]) { tbl, 0 } 113 114/* 115 * Helper to build a speedbin table, ie. the table: 116 * fuse | speedbin 117 * -----+--------- 118 * 0 | 0 119 * 169 | 1 120 * 174 | 2 121 * 122 * would be declared as: 123 * 124 * .speedbins = ADRENO_SPEEDBINS( 125 * { 0, 0 }, 126 * { 169, 1 }, 127 * { 174, 2 }, 128 * ), 129 */ 130#define ADRENO_SPEEDBINS(tbl...) (struct adreno_speedbin[]) { tbl {SHRT_MAX, 0} } 131 132struct adreno_gpu { 133 struct msm_gpu base; 134 const struct adreno_info *info; 135 uint32_t chip_id; 136 uint16_t speedbin; 137 const struct adreno_gpu_funcs *funcs; 138 139 /* interesting register offsets to dump: */ 140 const unsigned int *registers; 141 142 /* 143 * Are we loading fw from legacy path? Prior to addition 144 * of gpu firmware to linux-firmware, the fw files were 145 * placed in toplevel firmware directory, following qcom's 146 * android kernel. But linux-firmware preferred they be 147 * placed in a 'qcom' subdirectory. 148 * 149 * For backwards compatibility, we try first to load from 150 * the new path, using request_firmware_direct() to avoid 151 * any potential timeout waiting for usermode helper, then 152 * fall back to the old path (with direct load). And 153 * finally fall back to request_firmware() with the new 154 * path to allow the usermode helper. 155 */ 156 enum { 157 FW_LOCATION_UNKNOWN = 0, 158 FW_LOCATION_NEW, /* /lib/firmware/qcom/$fwfile */ 159 FW_LOCATION_LEGACY, /* /lib/firmware/$fwfile */ 160 FW_LOCATION_HELPER, 161 } fwloc; 162 163 /* firmware: */ 164 const struct firmware *fw[ADRENO_FW_MAX]; 165 166 /* 167 * Register offsets are different between some GPUs. 168 * GPU specific offsets will be exported by GPU specific 169 * code (a3xx_gpu.c) and stored in this common location. 170 */ 171 const unsigned int *reg_offsets; 172 bool gmu_is_wrapper; 173}; 174#define to_adreno_gpu(x) container_of(x, struct adreno_gpu, base) 175 176struct adreno_ocmem { 177 struct ocmem *ocmem; 178 unsigned long base; 179 void *hdl; 180}; 181 182/* platform config data (ie. from DT, or pdata) */ 183struct adreno_platform_config { 184 uint32_t chip_id; 185 const struct adreno_info *info; 186}; 187 188#define ADRENO_IDLE_TIMEOUT msecs_to_jiffies(1000) 189 190#define spin_until(X) ({ \ 191 int __ret = -ETIMEDOUT; \ 192 unsigned long __t = jiffies + ADRENO_IDLE_TIMEOUT; \ 193 do { \ 194 if (X) { \ 195 __ret = 0; \ 196 break; \ 197 } \ 198 } while (time_before(jiffies, __t)); \ 199 __ret; \ 200}) 201 202static inline uint8_t adreno_patchid(const struct adreno_gpu *gpu) 203{ 204 /* It is probably ok to assume legacy "adreno_rev" format 205 * for all a6xx devices, but probably best to limit this 206 * to older things. 207 */ 208 WARN_ON_ONCE(gpu->info->family >= ADRENO_6XX_GEN1); 209 return gpu->chip_id & 0xff; 210} 211 212static inline bool adreno_is_revn(const struct adreno_gpu *gpu, uint32_t revn) 213{ 214 if (WARN_ON_ONCE(!gpu->info)) 215 return false; 216 return gpu->info->revn == revn; 217} 218 219static inline bool adreno_has_gmu_wrapper(const struct adreno_gpu *gpu) 220{ 221 return gpu->gmu_is_wrapper; 222} 223 224static inline bool adreno_is_a2xx(const struct adreno_gpu *gpu) 225{ 226 if (WARN_ON_ONCE(!gpu->info)) 227 return false; 228 return gpu->info->family <= ADRENO_2XX_GEN2; 229} 230 231static inline bool adreno_is_a20x(const struct adreno_gpu *gpu) 232{ 233 if (WARN_ON_ONCE(!gpu->info)) 234 return false; 235 return gpu->info->family == ADRENO_2XX_GEN1; 236} 237 238static inline bool adreno_is_a225(const struct adreno_gpu *gpu) 239{ 240 return adreno_is_revn(gpu, 225); 241} 242 243static inline bool adreno_is_a305(const struct adreno_gpu *gpu) 244{ 245 return adreno_is_revn(gpu, 305); 246} 247 248static inline bool adreno_is_a306(const struct adreno_gpu *gpu) 249{ 250 /* yes, 307, because a305c is 306 */ 251 return adreno_is_revn(gpu, 307); 252} 253 254static inline bool adreno_is_a320(const struct adreno_gpu *gpu) 255{ 256 return adreno_is_revn(gpu, 320); 257} 258 259static inline bool adreno_is_a330(const struct adreno_gpu *gpu) 260{ 261 return adreno_is_revn(gpu, 330); 262} 263 264static inline bool adreno_is_a330v2(const struct adreno_gpu *gpu) 265{ 266 return adreno_is_a330(gpu) && (adreno_patchid(gpu) > 0); 267} 268 269static inline int adreno_is_a405(const struct adreno_gpu *gpu) 270{ 271 return adreno_is_revn(gpu, 405); 272} 273 274static inline int adreno_is_a420(const struct adreno_gpu *gpu) 275{ 276 return adreno_is_revn(gpu, 420); 277} 278 279static inline int adreno_is_a430(const struct adreno_gpu *gpu) 280{ 281 return adreno_is_revn(gpu, 430); 282} 283 284static inline int adreno_is_a506(const struct adreno_gpu *gpu) 285{ 286 return adreno_is_revn(gpu, 506); 287} 288 289static inline int adreno_is_a508(const struct adreno_gpu *gpu) 290{ 291 return adreno_is_revn(gpu, 508); 292} 293 294static inline int adreno_is_a509(const struct adreno_gpu *gpu) 295{ 296 return adreno_is_revn(gpu, 509); 297} 298 299static inline int adreno_is_a510(const struct adreno_gpu *gpu) 300{ 301 return adreno_is_revn(gpu, 510); 302} 303 304static inline int adreno_is_a512(const struct adreno_gpu *gpu) 305{ 306 return adreno_is_revn(gpu, 512); 307} 308 309static inline int adreno_is_a530(const struct adreno_gpu *gpu) 310{ 311 return adreno_is_revn(gpu, 530); 312} 313 314static inline int adreno_is_a540(const struct adreno_gpu *gpu) 315{ 316 return adreno_is_revn(gpu, 540); 317} 318 319static inline int adreno_is_a610(const struct adreno_gpu *gpu) 320{ 321 return adreno_is_revn(gpu, 610); 322} 323 324static inline int adreno_is_a618(const struct adreno_gpu *gpu) 325{ 326 return adreno_is_revn(gpu, 618); 327} 328 329static inline int adreno_is_a619(const struct adreno_gpu *gpu) 330{ 331 return adreno_is_revn(gpu, 619); 332} 333 334static inline int adreno_is_a619_holi(const struct adreno_gpu *gpu) 335{ 336 return adreno_is_a619(gpu) && adreno_has_gmu_wrapper(gpu); 337} 338 339static inline int adreno_is_a630(const struct adreno_gpu *gpu) 340{ 341 return adreno_is_revn(gpu, 630); 342} 343 344static inline int adreno_is_a640(const struct adreno_gpu *gpu) 345{ 346 return adreno_is_revn(gpu, 640); 347} 348 349static inline int adreno_is_a650(const struct adreno_gpu *gpu) 350{ 351 return adreno_is_revn(gpu, 650); 352} 353 354static inline int adreno_is_7c3(const struct adreno_gpu *gpu) 355{ 356 return gpu->info->chip_ids[0] == 0x06030500; 357} 358 359static inline int adreno_is_a660(const struct adreno_gpu *gpu) 360{ 361 return adreno_is_revn(gpu, 660); 362} 363 364static inline int adreno_is_a680(const struct adreno_gpu *gpu) 365{ 366 return adreno_is_revn(gpu, 680); 367} 368 369static inline int adreno_is_a690(const struct adreno_gpu *gpu) 370{ 371 return gpu->info->chip_ids[0] == 0x06090000; 372} 373 374/* check for a615, a616, a618, a619 or any a630 derivatives */ 375static inline int adreno_is_a630_family(const struct adreno_gpu *gpu) 376{ 377 if (WARN_ON_ONCE(!gpu->info)) 378 return false; 379 return gpu->info->family == ADRENO_6XX_GEN1; 380} 381 382static inline int adreno_is_a660_family(const struct adreno_gpu *gpu) 383{ 384 if (WARN_ON_ONCE(!gpu->info)) 385 return false; 386 return gpu->info->family == ADRENO_6XX_GEN4; 387} 388 389/* check for a650, a660, or any derivatives */ 390static inline int adreno_is_a650_family(const struct adreno_gpu *gpu) 391{ 392 if (WARN_ON_ONCE(!gpu->info)) 393 return false; 394 return gpu->info->family >= ADRENO_6XX_GEN3; 395} 396 397static inline int adreno_is_a640_family(const struct adreno_gpu *gpu) 398{ 399 if (WARN_ON_ONCE(!gpu->info)) 400 return false; 401 return gpu->info->family == ADRENO_6XX_GEN2; 402} 403 404u64 adreno_private_address_space_size(struct msm_gpu *gpu); 405int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx, 406 uint32_t param, uint64_t *value, uint32_t *len); 407int adreno_set_param(struct msm_gpu *gpu, struct msm_file_private *ctx, 408 uint32_t param, uint64_t value, uint32_t len); 409const struct firmware *adreno_request_fw(struct adreno_gpu *adreno_gpu, 410 const char *fwname); 411struct drm_gem_object *adreno_fw_create_bo(struct msm_gpu *gpu, 412 const struct firmware *fw, u64 *iova); 413int adreno_hw_init(struct msm_gpu *gpu); 414void adreno_recover(struct msm_gpu *gpu); 415void adreno_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring, u32 reg); 416bool adreno_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring); 417#if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP) 418void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state, 419 struct drm_printer *p); 420#endif 421void adreno_dump_info(struct msm_gpu *gpu); 422void adreno_dump(struct msm_gpu *gpu); 423void adreno_wait_ring(struct msm_ringbuffer *ring, uint32_t ndwords); 424struct msm_ringbuffer *adreno_active_ring(struct msm_gpu *gpu); 425 426int adreno_gpu_ocmem_init(struct device *dev, struct adreno_gpu *adreno_gpu, 427 struct adreno_ocmem *ocmem); 428void adreno_gpu_ocmem_cleanup(struct adreno_ocmem *ocmem); 429 430int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, 431 struct adreno_gpu *gpu, const struct adreno_gpu_funcs *funcs, 432 int nr_rings); 433void adreno_gpu_cleanup(struct adreno_gpu *gpu); 434int adreno_load_fw(struct adreno_gpu *adreno_gpu); 435 436void adreno_gpu_state_destroy(struct msm_gpu_state *state); 437 438int adreno_gpu_state_get(struct msm_gpu *gpu, struct msm_gpu_state *state); 439int adreno_gpu_state_put(struct msm_gpu_state *state); 440void adreno_show_object(struct drm_printer *p, void **ptr, int len, 441 bool *encoded); 442 443/* 444 * Common helper function to initialize the default address space for arm-smmu 445 * attached targets 446 */ 447struct msm_gem_address_space * 448adreno_create_address_space(struct msm_gpu *gpu, 449 struct platform_device *pdev); 450 451struct msm_gem_address_space * 452adreno_iommu_create_address_space(struct msm_gpu *gpu, 453 struct platform_device *pdev, 454 unsigned long quirks); 455 456int adreno_fault_handler(struct msm_gpu *gpu, unsigned long iova, int flags, 457 struct adreno_smmu_fault_info *info, const char *block, 458 u32 scratch[4]); 459 460int adreno_read_speedbin(struct device *dev, u32 *speedbin); 461 462/* 463 * For a5xx and a6xx targets load the zap shader that is used to pull the GPU 464 * out of secure mode 465 */ 466int adreno_zap_shader_load(struct msm_gpu *gpu, u32 pasid); 467 468/* ringbuffer helpers (the parts that are adreno specific) */ 469 470static inline void 471OUT_PKT0(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt) 472{ 473 adreno_wait_ring(ring, cnt+1); 474 OUT_RING(ring, CP_TYPE0_PKT | ((cnt-1) << 16) | (regindx & 0x7FFF)); 475} 476 477/* no-op packet: */ 478static inline void 479OUT_PKT2(struct msm_ringbuffer *ring) 480{ 481 adreno_wait_ring(ring, 1); 482 OUT_RING(ring, CP_TYPE2_PKT); 483} 484 485static inline void 486OUT_PKT3(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt) 487{ 488 adreno_wait_ring(ring, cnt+1); 489 OUT_RING(ring, CP_TYPE3_PKT | ((cnt-1) << 16) | ((opcode & 0xFF) << 8)); 490} 491 492static inline u32 PM4_PARITY(u32 val) 493{ 494 return (0x9669 >> (0xF & (val ^ 495 (val >> 4) ^ (val >> 8) ^ (val >> 12) ^ 496 (val >> 16) ^ ((val) >> 20) ^ (val >> 24) ^ 497 (val >> 28)))) & 1; 498} 499 500/* Maximum number of values that can be executed for one opcode */ 501#define TYPE4_MAX_PAYLOAD 127 502 503#define PKT4(_reg, _cnt) \ 504 (CP_TYPE4_PKT | ((_cnt) << 0) | (PM4_PARITY((_cnt)) << 7) | \ 505 (((_reg) & 0x3FFFF) << 8) | (PM4_PARITY((_reg)) << 27)) 506 507static inline void 508OUT_PKT4(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt) 509{ 510 adreno_wait_ring(ring, cnt + 1); 511 OUT_RING(ring, PKT4(regindx, cnt)); 512} 513 514static inline void 515OUT_PKT7(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt) 516{ 517 adreno_wait_ring(ring, cnt + 1); 518 OUT_RING(ring, CP_TYPE7_PKT | (cnt << 0) | (PM4_PARITY(cnt) << 15) | 519 ((opcode & 0x7F) << 16) | (PM4_PARITY(opcode) << 23)); 520} 521 522struct msm_gpu *a2xx_gpu_init(struct drm_device *dev); 523struct msm_gpu *a3xx_gpu_init(struct drm_device *dev); 524struct msm_gpu *a4xx_gpu_init(struct drm_device *dev); 525struct msm_gpu *a5xx_gpu_init(struct drm_device *dev); 526struct msm_gpu *a6xx_gpu_init(struct drm_device *dev); 527 528static inline uint32_t get_wptr(struct msm_ringbuffer *ring) 529{ 530 return (ring->cur - ring->start) % (MSM_GPU_RINGBUFFER_SZ >> 2); 531} 532 533/* 534 * Given a register and a count, return a value to program into 535 * REG_CP_PROTECT_REG(n) - this will block both reads and writes for _len 536 * registers starting at _reg. 537 * 538 * The register base needs to be a multiple of the length. If it is not, the 539 * hardware will quietly mask off the bits for you and shift the size. For 540 * example, if you intend the protection to start at 0x07 for a length of 4 541 * (0x07-0x0A) the hardware will actually protect (0x04-0x07) which might 542 * expose registers you intended to protect! 543 */ 544#define ADRENO_PROTECT_RW(_reg, _len) \ 545 ((1 << 30) | (1 << 29) | \ 546 ((ilog2((_len)) & 0x1F) << 24) | (((_reg) << 2) & 0xFFFFF)) 547 548/* 549 * Same as above, but allow reads over the range. For areas of mixed use (such 550 * as performance counters) this allows us to protect a much larger range with a 551 * single register 552 */ 553#define ADRENO_PROTECT_RDONLY(_reg, _len) \ 554 ((1 << 29) \ 555 ((ilog2((_len)) & 0x1F) << 24) | (((_reg) << 2) & 0xFFFFF)) 556 557 558#define gpu_poll_timeout(gpu, addr, val, cond, interval, timeout) \ 559 readl_poll_timeout((gpu)->mmio + ((addr) << 2), val, cond, \ 560 interval, timeout) 561 562#endif /* __ADRENO_GPU_H__ */ 563