1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (C) 2013 Red Hat 4 * Author: Rob Clark <robdclark@gmail.com> 5 * 6 * Copyright (c) 2014 The Linux Foundation. All rights reserved. 7 */ 8 9#include <linux/ascii85.h> 10#include <linux/interconnect.h> 11#include <linux/firmware/qcom/qcom_scm.h> 12#include <linux/kernel.h> 13#include <linux/of_address.h> 14#include <linux/pm_opp.h> 15#include <linux/slab.h> 16#include <linux/soc/qcom/mdt_loader.h> 17#include <linux/nvmem-consumer.h> 18#include <soc/qcom/ocmem.h> 19#include "adreno_gpu.h" 20#include "a6xx_gpu.h" 21#include "msm_gem.h" 22#include "msm_mmu.h" 23 24static u64 address_space_size = 0; 25MODULE_PARM_DESC(address_space_size, "Override for size of processes private GPU address space"); 26module_param(address_space_size, ullong, 0600); 27 28static bool zap_available = true; 29 30static int zap_shader_load_mdt(struct msm_gpu *gpu, const char *fwname, 31 u32 pasid) 32{ 33 struct device *dev = &gpu->pdev->dev; 34 const struct firmware *fw; 35 const char *signed_fwname = NULL; 36 struct device_node *np, *mem_np; 37 struct resource r; 38 phys_addr_t mem_phys; 39 ssize_t mem_size; 40 void *mem_region = NULL; 41 int ret; 42 43 if (!IS_ENABLED(CONFIG_ARCH_QCOM)) { 44 zap_available = false; 45 return -EINVAL; 46 } 47 48 np = of_get_child_by_name(dev->of_node, "zap-shader"); 49 if (!np) { 50 zap_available = false; 51 return -ENODEV; 52 } 53 54 mem_np = of_parse_phandle(np, "memory-region", 0); 55 of_node_put(np); 56 if (!mem_np) { 57 zap_available = false; 58 return -EINVAL; 59 } 60 61 ret = of_address_to_resource(mem_np, 0, &r); 62 of_node_put(mem_np); 63 if (ret) 64 return ret; 65 66 mem_phys = r.start; 67 68 /* 69 * Check for a firmware-name property. This is the new scheme 70 * to handle firmware that may be signed with device specific 71 * keys, allowing us to have a different zap fw path for different 72 * devices. 73 * 74 * If the firmware-name property is found, we bypass the 75 * adreno_request_fw() mechanism, because we don't need to handle 76 * the /lib/firmware/qcom/... vs /lib/firmware/... case. 77 * 78 * If the firmware-name property is not found, for backwards 79 * compatibility we fall back to the fwname from the gpulist 80 * table. 81 */ 82 of_property_read_string_index(np, "firmware-name", 0, &signed_fwname); 83 if (signed_fwname) { 84 fwname = signed_fwname; 85 ret = request_firmware_direct(&fw, fwname, gpu->dev->dev); 86 if (ret) 87 fw = ERR_PTR(ret); 88 } else if (fwname) { 89 /* Request the MDT file from the default location: */ 90 fw = adreno_request_fw(to_adreno_gpu(gpu), fwname); 91 } else { 92 /* 93 * For new targets, we require the firmware-name property, 94 * if a zap-shader is required, rather than falling back 95 * to a firmware name specified in gpulist. 96 * 97 * Because the firmware is signed with a (potentially) 98 * device specific key, having the name come from gpulist 99 * was a bad idea, and is only provided for backwards 100 * compatibility for older targets. 101 */ 102 return -ENODEV; 103 } 104 105 if (IS_ERR(fw)) { 106 DRM_DEV_ERROR(dev, "Unable to load %s\n", fwname); 107 return PTR_ERR(fw); 108 } 109 110 /* Figure out how much memory we need */ 111 mem_size = qcom_mdt_get_size(fw); 112 if (mem_size < 0) { 113 ret = mem_size; 114 goto out; 115 } 116 117 if (mem_size > resource_size(&r)) { 118 DRM_DEV_ERROR(dev, 119 "memory region is too small to load the MDT\n"); 120 ret = -E2BIG; 121 goto out; 122 } 123 124 /* Allocate memory for the firmware image */ 125 mem_region = memremap(mem_phys, mem_size, MEMREMAP_WC); 126 if (!mem_region) { 127 ret = -ENOMEM; 128 goto out; 129 } 130 131 /* 132 * Load the rest of the MDT 133 * 134 * Note that we could be dealing with two different paths, since 135 * with upstream linux-firmware it would be in a qcom/ subdir.. 136 * adreno_request_fw() handles this, but qcom_mdt_load() does 137 * not. But since we've already gotten through adreno_request_fw() 138 * we know which of the two cases it is: 139 */ 140 if (signed_fwname || (to_adreno_gpu(gpu)->fwloc == FW_LOCATION_LEGACY)) { 141 ret = qcom_mdt_load(dev, fw, fwname, pasid, 142 mem_region, mem_phys, mem_size, NULL); 143 } else { 144 char *newname; 145 146 newname = kasprintf(GFP_KERNEL, "qcom/%s", fwname); 147 148 ret = qcom_mdt_load(dev, fw, newname, pasid, 149 mem_region, mem_phys, mem_size, NULL); 150 kfree(newname); 151 } 152 if (ret) 153 goto out; 154 155 /* Send the image to the secure world */ 156 ret = qcom_scm_pas_auth_and_reset(pasid); 157 158 /* 159 * If the scm call returns -EOPNOTSUPP we assume that this target 160 * doesn't need/support the zap shader so quietly fail 161 */ 162 if (ret == -EOPNOTSUPP) 163 zap_available = false; 164 else if (ret) 165 DRM_DEV_ERROR(dev, "Unable to authorize the image\n"); 166 167out: 168 if (mem_region) 169 memunmap(mem_region); 170 171 release_firmware(fw); 172 173 return ret; 174} 175 176int adreno_zap_shader_load(struct msm_gpu *gpu, u32 pasid) 177{ 178 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 179 struct platform_device *pdev = gpu->pdev; 180 181 /* Short cut if we determine the zap shader isn't available/needed */ 182 if (!zap_available) 183 return -ENODEV; 184 185 /* We need SCM to be able to load the firmware */ 186 if (!qcom_scm_is_available()) { 187 DRM_DEV_ERROR(&pdev->dev, "SCM is not available\n"); 188 return -EPROBE_DEFER; 189 } 190 191 return zap_shader_load_mdt(gpu, adreno_gpu->info->zapfw, pasid); 192} 193 194struct msm_gem_address_space * 195adreno_create_address_space(struct msm_gpu *gpu, 196 struct platform_device *pdev) 197{ 198 return adreno_iommu_create_address_space(gpu, pdev, 0); 199} 200 201struct msm_gem_address_space * 202adreno_iommu_create_address_space(struct msm_gpu *gpu, 203 struct platform_device *pdev, 204 unsigned long quirks) 205{ 206 struct iommu_domain_geometry *geometry; 207 struct msm_mmu *mmu; 208 struct msm_gem_address_space *aspace; 209 u64 start, size; 210 211 mmu = msm_iommu_gpu_new(&pdev->dev, gpu, quirks); 212 if (IS_ERR_OR_NULL(mmu)) 213 return ERR_CAST(mmu); 214 215 geometry = msm_iommu_get_geometry(mmu); 216 if (IS_ERR(geometry)) 217 return ERR_CAST(geometry); 218 219 /* 220 * Use the aperture start or SZ_16M, whichever is greater. This will 221 * ensure that we align with the allocated pagetable range while still 222 * allowing room in the lower 32 bits for GMEM and whatnot 223 */ 224 start = max_t(u64, SZ_16M, geometry->aperture_start); 225 size = geometry->aperture_end - start + 1; 226 227 aspace = msm_gem_address_space_create(mmu, "gpu", 228 start & GENMASK_ULL(48, 0), size); 229 230 if (IS_ERR(aspace) && !IS_ERR(mmu)) 231 mmu->funcs->destroy(mmu); 232 233 return aspace; 234} 235 236u64 adreno_private_address_space_size(struct msm_gpu *gpu) 237{ 238 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 239 240 if (address_space_size) 241 return address_space_size; 242 243 if (adreno_gpu->info->address_space_size) 244 return adreno_gpu->info->address_space_size; 245 246 return SZ_4G; 247} 248 249#define ARM_SMMU_FSR_TF BIT(1) 250#define ARM_SMMU_FSR_PF BIT(3) 251#define ARM_SMMU_FSR_EF BIT(4) 252 253int adreno_fault_handler(struct msm_gpu *gpu, unsigned long iova, int flags, 254 struct adreno_smmu_fault_info *info, const char *block, 255 u32 scratch[4]) 256{ 257 const char *type = "UNKNOWN"; 258 bool do_devcoredump = info && !READ_ONCE(gpu->crashstate); 259 260 /* 261 * If we aren't going to be resuming later from fault_worker, then do 262 * it now. 263 */ 264 if (!do_devcoredump) { 265 gpu->aspace->mmu->funcs->resume_translation(gpu->aspace->mmu); 266 } 267 268 /* 269 * Print a default message if we couldn't get the data from the 270 * adreno-smmu-priv 271 */ 272 if (!info) { 273 pr_warn_ratelimited("*** gpu fault: iova=%.16lx flags=%d (%u,%u,%u,%u)\n", 274 iova, flags, 275 scratch[0], scratch[1], scratch[2], scratch[3]); 276 277 return 0; 278 } 279 280 if (info->fsr & ARM_SMMU_FSR_TF) 281 type = "TRANSLATION"; 282 else if (info->fsr & ARM_SMMU_FSR_PF) 283 type = "PERMISSION"; 284 else if (info->fsr & ARM_SMMU_FSR_EF) 285 type = "EXTERNAL"; 286 287 pr_warn_ratelimited("*** gpu fault: ttbr0=%.16llx iova=%.16lx dir=%s type=%s source=%s (%u,%u,%u,%u)\n", 288 info->ttbr0, iova, 289 flags & IOMMU_FAULT_WRITE ? "WRITE" : "READ", 290 type, block, 291 scratch[0], scratch[1], scratch[2], scratch[3]); 292 293 if (do_devcoredump) { 294 /* Turn off the hangcheck timer to keep it from bothering us */ 295 del_timer(&gpu->hangcheck_timer); 296 297 gpu->fault_info.ttbr0 = info->ttbr0; 298 gpu->fault_info.iova = iova; 299 gpu->fault_info.flags = flags; 300 gpu->fault_info.type = type; 301 gpu->fault_info.block = block; 302 303 kthread_queue_work(gpu->worker, &gpu->fault_work); 304 } 305 306 return 0; 307} 308 309int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx, 310 uint32_t param, uint64_t *value, uint32_t *len) 311{ 312 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 313 314 /* No pointer params yet */ 315 if (*len != 0) 316 return -EINVAL; 317 318 switch (param) { 319 case MSM_PARAM_GPU_ID: 320 *value = adreno_gpu->info->revn; 321 return 0; 322 case MSM_PARAM_GMEM_SIZE: 323 *value = adreno_gpu->info->gmem; 324 return 0; 325 case MSM_PARAM_GMEM_BASE: 326 *value = !adreno_is_a650_family(adreno_gpu) ? 0x100000 : 0; 327 return 0; 328 case MSM_PARAM_CHIP_ID: 329 *value = adreno_gpu->chip_id; 330 if (!adreno_gpu->info->revn) 331 *value |= ((uint64_t) adreno_gpu->speedbin) << 32; 332 return 0; 333 case MSM_PARAM_MAX_FREQ: 334 *value = adreno_gpu->base.fast_rate; 335 return 0; 336 case MSM_PARAM_TIMESTAMP: 337 if (adreno_gpu->funcs->get_timestamp) { 338 int ret; 339 340 pm_runtime_get_sync(&gpu->pdev->dev); 341 ret = adreno_gpu->funcs->get_timestamp(gpu, value); 342 pm_runtime_put_autosuspend(&gpu->pdev->dev); 343 344 return ret; 345 } 346 return -EINVAL; 347 case MSM_PARAM_PRIORITIES: 348 *value = gpu->nr_rings * NR_SCHED_PRIORITIES; 349 return 0; 350 case MSM_PARAM_PP_PGTABLE: 351 *value = 0; 352 return 0; 353 case MSM_PARAM_FAULTS: 354 if (ctx->aspace) 355 *value = gpu->global_faults + ctx->aspace->faults; 356 else 357 *value = gpu->global_faults; 358 return 0; 359 case MSM_PARAM_SUSPENDS: 360 *value = gpu->suspend_count; 361 return 0; 362 case MSM_PARAM_VA_START: 363 if (ctx->aspace == gpu->aspace) 364 return -EINVAL; 365 *value = ctx->aspace->va_start; 366 return 0; 367 case MSM_PARAM_VA_SIZE: 368 if (ctx->aspace == gpu->aspace) 369 return -EINVAL; 370 *value = ctx->aspace->va_size; 371 return 0; 372 default: 373 DBG("%s: invalid param: %u", gpu->name, param); 374 return -EINVAL; 375 } 376} 377 378int adreno_set_param(struct msm_gpu *gpu, struct msm_file_private *ctx, 379 uint32_t param, uint64_t value, uint32_t len) 380{ 381 switch (param) { 382 case MSM_PARAM_COMM: 383 case MSM_PARAM_CMDLINE: 384 /* kstrdup_quotable_cmdline() limits to PAGE_SIZE, so 385 * that should be a reasonable upper bound 386 */ 387 if (len > PAGE_SIZE) 388 return -EINVAL; 389 break; 390 default: 391 if (len != 0) 392 return -EINVAL; 393 } 394 395 switch (param) { 396 case MSM_PARAM_COMM: 397 case MSM_PARAM_CMDLINE: { 398 char *str, **paramp; 399 400 str = memdup_user_nul(u64_to_user_ptr(value), len); 401 if (IS_ERR(str)) 402 return PTR_ERR(str); 403 404 mutex_lock(&gpu->lock); 405 406 if (param == MSM_PARAM_COMM) { 407 paramp = &ctx->comm; 408 } else { 409 paramp = &ctx->cmdline; 410 } 411 412 kfree(*paramp); 413 *paramp = str; 414 415 mutex_unlock(&gpu->lock); 416 417 return 0; 418 } 419 case MSM_PARAM_SYSPROF: 420 if (!capable(CAP_SYS_ADMIN)) 421 return -EPERM; 422 return msm_file_private_set_sysprof(ctx, gpu, value); 423 default: 424 DBG("%s: invalid param: %u", gpu->name, param); 425 return -EINVAL; 426 } 427} 428 429const struct firmware * 430adreno_request_fw(struct adreno_gpu *adreno_gpu, const char *fwname) 431{ 432 struct drm_device *drm = adreno_gpu->base.dev; 433 const struct firmware *fw = NULL; 434 char *newname; 435 int ret; 436 437 newname = kasprintf(GFP_KERNEL, "qcom/%s", fwname); 438 if (!newname) 439 return ERR_PTR(-ENOMEM); 440 441 /* 442 * Try first to load from qcom/$fwfile using a direct load (to avoid 443 * a potential timeout waiting for usermode helper) 444 */ 445 if ((adreno_gpu->fwloc == FW_LOCATION_UNKNOWN) || 446 (adreno_gpu->fwloc == FW_LOCATION_NEW)) { 447 448 ret = request_firmware_direct(&fw, newname, drm->dev); 449 if (!ret) { 450 DRM_DEV_INFO(drm->dev, "loaded %s from new location\n", 451 newname); 452 adreno_gpu->fwloc = FW_LOCATION_NEW; 453 goto out; 454 } else if (adreno_gpu->fwloc != FW_LOCATION_UNKNOWN) { 455 DRM_DEV_ERROR(drm->dev, "failed to load %s: %d\n", 456 newname, ret); 457 fw = ERR_PTR(ret); 458 goto out; 459 } 460 } 461 462 /* 463 * Then try the legacy location without qcom/ prefix 464 */ 465 if ((adreno_gpu->fwloc == FW_LOCATION_UNKNOWN) || 466 (adreno_gpu->fwloc == FW_LOCATION_LEGACY)) { 467 468 ret = request_firmware_direct(&fw, fwname, drm->dev); 469 if (!ret) { 470 DRM_DEV_INFO(drm->dev, "loaded %s from legacy location\n", 471 newname); 472 adreno_gpu->fwloc = FW_LOCATION_LEGACY; 473 goto out; 474 } else if (adreno_gpu->fwloc != FW_LOCATION_UNKNOWN) { 475 DRM_DEV_ERROR(drm->dev, "failed to load %s: %d\n", 476 fwname, ret); 477 fw = ERR_PTR(ret); 478 goto out; 479 } 480 } 481 482 /* 483 * Finally fall back to request_firmware() for cases where the 484 * usermode helper is needed (I think mainly android) 485 */ 486 if ((adreno_gpu->fwloc == FW_LOCATION_UNKNOWN) || 487 (adreno_gpu->fwloc == FW_LOCATION_HELPER)) { 488 489 ret = request_firmware(&fw, newname, drm->dev); 490 if (!ret) { 491 DRM_DEV_INFO(drm->dev, "loaded %s with helper\n", 492 newname); 493 adreno_gpu->fwloc = FW_LOCATION_HELPER; 494 goto out; 495 } else if (adreno_gpu->fwloc != FW_LOCATION_UNKNOWN) { 496 DRM_DEV_ERROR(drm->dev, "failed to load %s: %d\n", 497 newname, ret); 498 fw = ERR_PTR(ret); 499 goto out; 500 } 501 } 502 503 DRM_DEV_ERROR(drm->dev, "failed to load %s\n", fwname); 504 fw = ERR_PTR(-ENOENT); 505out: 506 kfree(newname); 507 return fw; 508} 509 510int adreno_load_fw(struct adreno_gpu *adreno_gpu) 511{ 512 int i; 513 514 for (i = 0; i < ARRAY_SIZE(adreno_gpu->info->fw); i++) { 515 const struct firmware *fw; 516 517 if (!adreno_gpu->info->fw[i]) 518 continue; 519 520 /* Skip loading GMU firwmare with GMU Wrapper */ 521 if (adreno_has_gmu_wrapper(adreno_gpu) && i == ADRENO_FW_GMU) 522 continue; 523 524 /* Skip if the firmware has already been loaded */ 525 if (adreno_gpu->fw[i]) 526 continue; 527 528 fw = adreno_request_fw(adreno_gpu, adreno_gpu->info->fw[i]); 529 if (IS_ERR(fw)) 530 return PTR_ERR(fw); 531 532 adreno_gpu->fw[i] = fw; 533 } 534 535 return 0; 536} 537 538struct drm_gem_object *adreno_fw_create_bo(struct msm_gpu *gpu, 539 const struct firmware *fw, u64 *iova) 540{ 541 struct drm_gem_object *bo; 542 void *ptr; 543 544 ptr = msm_gem_kernel_new(gpu->dev, fw->size - 4, 545 MSM_BO_WC | MSM_BO_GPU_READONLY, gpu->aspace, &bo, iova); 546 547 if (IS_ERR(ptr)) 548 return ERR_CAST(ptr); 549 550 memcpy(ptr, &fw->data[4], fw->size - 4); 551 552 msm_gem_put_vaddr(bo); 553 554 return bo; 555} 556 557int adreno_hw_init(struct msm_gpu *gpu) 558{ 559 VERB("%s", gpu->name); 560 561 for (int i = 0; i < gpu->nr_rings; i++) { 562 struct msm_ringbuffer *ring = gpu->rb[i]; 563 564 if (!ring) 565 continue; 566 567 ring->cur = ring->start; 568 ring->next = ring->start; 569 ring->memptrs->rptr = 0; 570 571 /* Detect and clean up an impossible fence, ie. if GPU managed 572 * to scribble something invalid, we don't want that to confuse 573 * us into mistakingly believing that submits have completed. 574 */ 575 if (fence_before(ring->fctx->last_fence, ring->memptrs->fence)) { 576 ring->memptrs->fence = ring->fctx->last_fence; 577 } 578 } 579 580 return 0; 581} 582 583/* Use this helper to read rptr, since a430 doesn't update rptr in memory */ 584static uint32_t get_rptr(struct adreno_gpu *adreno_gpu, 585 struct msm_ringbuffer *ring) 586{ 587 struct msm_gpu *gpu = &adreno_gpu->base; 588 589 return gpu->funcs->get_rptr(gpu, ring); 590} 591 592struct msm_ringbuffer *adreno_active_ring(struct msm_gpu *gpu) 593{ 594 return gpu->rb[0]; 595} 596 597void adreno_recover(struct msm_gpu *gpu) 598{ 599 struct drm_device *dev = gpu->dev; 600 int ret; 601 602 // XXX pm-runtime?? we *need* the device to be off after this 603 // so maybe continuing to call ->pm_suspend/resume() is better? 604 605 gpu->funcs->pm_suspend(gpu); 606 gpu->funcs->pm_resume(gpu); 607 608 ret = msm_gpu_hw_init(gpu); 609 if (ret) { 610 DRM_DEV_ERROR(dev->dev, "gpu hw init failed: %d\n", ret); 611 /* hmm, oh well? */ 612 } 613} 614 615void adreno_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring, u32 reg) 616{ 617 uint32_t wptr; 618 619 /* Copy the shadow to the actual register */ 620 ring->cur = ring->next; 621 622 /* 623 * Mask wptr value that we calculate to fit in the HW range. This is 624 * to account for the possibility that the last command fit exactly into 625 * the ringbuffer and rb->next hasn't wrapped to zero yet 626 */ 627 wptr = get_wptr(ring); 628 629 /* ensure writes to ringbuffer have hit system memory: */ 630 mb(); 631 632 gpu_write(gpu, reg, wptr); 633} 634 635bool adreno_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring) 636{ 637 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 638 uint32_t wptr = get_wptr(ring); 639 640 /* wait for CP to drain ringbuffer: */ 641 if (!spin_until(get_rptr(adreno_gpu, ring) == wptr)) 642 return true; 643 644 /* TODO maybe we need to reset GPU here to recover from hang? */ 645 DRM_ERROR("%s: timeout waiting to drain ringbuffer %d rptr/wptr = %X/%X\n", 646 gpu->name, ring->id, get_rptr(adreno_gpu, ring), wptr); 647 648 return false; 649} 650 651int adreno_gpu_state_get(struct msm_gpu *gpu, struct msm_gpu_state *state) 652{ 653 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 654 int i, count = 0; 655 656 WARN_ON(!mutex_is_locked(&gpu->lock)); 657 658 kref_init(&state->ref); 659 660 ktime_get_real_ts64(&state->time); 661 662 for (i = 0; i < gpu->nr_rings; i++) { 663 int size = 0, j; 664 665 state->ring[i].fence = gpu->rb[i]->memptrs->fence; 666 state->ring[i].iova = gpu->rb[i]->iova; 667 state->ring[i].seqno = gpu->rb[i]->fctx->last_fence; 668 state->ring[i].rptr = get_rptr(adreno_gpu, gpu->rb[i]); 669 state->ring[i].wptr = get_wptr(gpu->rb[i]); 670 671 /* Copy at least 'wptr' dwords of the data */ 672 size = state->ring[i].wptr; 673 674 /* After wptr find the last non zero dword to save space */ 675 for (j = state->ring[i].wptr; j < MSM_GPU_RINGBUFFER_SZ >> 2; j++) 676 if (gpu->rb[i]->start[j]) 677 size = j + 1; 678 679 if (size) { 680 state->ring[i].data = kvmalloc(size << 2, GFP_KERNEL); 681 if (state->ring[i].data) { 682 memcpy(state->ring[i].data, gpu->rb[i]->start, size << 2); 683 state->ring[i].data_size = size << 2; 684 } 685 } 686 } 687 688 /* Some targets prefer to collect their own registers */ 689 if (!adreno_gpu->registers) 690 return 0; 691 692 /* Count the number of registers */ 693 for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) 694 count += adreno_gpu->registers[i + 1] - 695 adreno_gpu->registers[i] + 1; 696 697 state->registers = kcalloc(count * 2, sizeof(u32), GFP_KERNEL); 698 if (state->registers) { 699 int pos = 0; 700 701 for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) { 702 u32 start = adreno_gpu->registers[i]; 703 u32 end = adreno_gpu->registers[i + 1]; 704 u32 addr; 705 706 for (addr = start; addr <= end; addr++) { 707 state->registers[pos++] = addr; 708 state->registers[pos++] = gpu_read(gpu, addr); 709 } 710 } 711 712 state->nr_registers = count; 713 } 714 715 return 0; 716} 717 718void adreno_gpu_state_destroy(struct msm_gpu_state *state) 719{ 720 int i; 721 722 for (i = 0; i < ARRAY_SIZE(state->ring); i++) 723 kvfree(state->ring[i].data); 724 725 for (i = 0; state->bos && i < state->nr_bos; i++) 726 kvfree(state->bos[i].data); 727 728 kfree(state->bos); 729 kfree(state->comm); 730 kfree(state->cmd); 731 kfree(state->registers); 732} 733 734static void adreno_gpu_state_kref_destroy(struct kref *kref) 735{ 736 struct msm_gpu_state *state = container_of(kref, 737 struct msm_gpu_state, ref); 738 739 adreno_gpu_state_destroy(state); 740 kfree(state); 741} 742 743int adreno_gpu_state_put(struct msm_gpu_state *state) 744{ 745 if (IS_ERR_OR_NULL(state)) 746 return 1; 747 748 return kref_put(&state->ref, adreno_gpu_state_kref_destroy); 749} 750 751#if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP) 752 753static char *adreno_gpu_ascii85_encode(u32 *src, size_t len) 754{ 755 void *buf; 756 size_t buf_itr = 0, buffer_size; 757 char out[ASCII85_BUFSZ]; 758 long l; 759 int i; 760 761 if (!src || !len) 762 return NULL; 763 764 l = ascii85_encode_len(len); 765 766 /* 767 * Ascii85 outputs either a 5 byte string or a 1 byte string. So we 768 * account for the worst case of 5 bytes per dword plus the 1 for '\0' 769 */ 770 buffer_size = (l * 5) + 1; 771 772 buf = kvmalloc(buffer_size, GFP_KERNEL); 773 if (!buf) 774 return NULL; 775 776 for (i = 0; i < l; i++) 777 buf_itr += scnprintf(buf + buf_itr, buffer_size - buf_itr, "%s", 778 ascii85_encode(src[i], out)); 779 780 return buf; 781} 782 783/* len is expected to be in bytes 784 * 785 * WARNING: *ptr should be allocated with kvmalloc or friends. It can be free'd 786 * with kvfree() and replaced with a newly kvmalloc'd buffer on the first call 787 * when the unencoded raw data is encoded 788 */ 789void adreno_show_object(struct drm_printer *p, void **ptr, int len, 790 bool *encoded) 791{ 792 if (!*ptr || !len) 793 return; 794 795 if (!*encoded) { 796 long datalen, i; 797 u32 *buf = *ptr; 798 799 /* 800 * Only dump the non-zero part of the buffer - rarely will 801 * any data completely fill the entire allocated size of 802 * the buffer. 803 */ 804 for (datalen = 0, i = 0; i < len >> 2; i++) 805 if (buf[i]) 806 datalen = ((i + 1) << 2); 807 808 /* 809 * If we reach here, then the originally captured binary buffer 810 * will be replaced with the ascii85 encoded string 811 */ 812 *ptr = adreno_gpu_ascii85_encode(buf, datalen); 813 814 kvfree(buf); 815 816 *encoded = true; 817 } 818 819 if (!*ptr) 820 return; 821 822 drm_puts(p, " data: !!ascii85 |\n"); 823 drm_puts(p, " "); 824 825 drm_puts(p, *ptr); 826 827 drm_puts(p, "\n"); 828} 829 830void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state, 831 struct drm_printer *p) 832{ 833 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 834 int i; 835 836 if (IS_ERR_OR_NULL(state)) 837 return; 838 839 drm_printf(p, "revision: %u (%"ADRENO_CHIPID_FMT")\n", 840 adreno_gpu->info->revn, 841 ADRENO_CHIPID_ARGS(adreno_gpu->chip_id)); 842 /* 843 * If this is state collected due to iova fault, so fault related info 844 * 845 * TTBR0 would not be zero, so this is a good way to distinguish 846 */ 847 if (state->fault_info.ttbr0) { 848 const struct msm_gpu_fault_info *info = &state->fault_info; 849 850 drm_puts(p, "fault-info:\n"); 851 drm_printf(p, " - ttbr0=%.16llx\n", info->ttbr0); 852 drm_printf(p, " - iova=%.16lx\n", info->iova); 853 drm_printf(p, " - dir=%s\n", info->flags & IOMMU_FAULT_WRITE ? "WRITE" : "READ"); 854 drm_printf(p, " - type=%s\n", info->type); 855 drm_printf(p, " - source=%s\n", info->block); 856 } 857 858 drm_printf(p, "rbbm-status: 0x%08x\n", state->rbbm_status); 859 860 drm_puts(p, "ringbuffer:\n"); 861 862 for (i = 0; i < gpu->nr_rings; i++) { 863 drm_printf(p, " - id: %d\n", i); 864 drm_printf(p, " iova: 0x%016llx\n", state->ring[i].iova); 865 drm_printf(p, " last-fence: %u\n", state->ring[i].seqno); 866 drm_printf(p, " retired-fence: %u\n", state->ring[i].fence); 867 drm_printf(p, " rptr: %u\n", state->ring[i].rptr); 868 drm_printf(p, " wptr: %u\n", state->ring[i].wptr); 869 drm_printf(p, " size: %u\n", MSM_GPU_RINGBUFFER_SZ); 870 871 adreno_show_object(p, &state->ring[i].data, 872 state->ring[i].data_size, &state->ring[i].encoded); 873 } 874 875 if (state->bos) { 876 drm_puts(p, "bos:\n"); 877 878 for (i = 0; i < state->nr_bos; i++) { 879 drm_printf(p, " - iova: 0x%016llx\n", 880 state->bos[i].iova); 881 drm_printf(p, " size: %zd\n", state->bos[i].size); 882 drm_printf(p, " name: %-32s\n", state->bos[i].name); 883 884 adreno_show_object(p, &state->bos[i].data, 885 state->bos[i].size, &state->bos[i].encoded); 886 } 887 } 888 889 if (state->nr_registers) { 890 drm_puts(p, "registers:\n"); 891 892 for (i = 0; i < state->nr_registers; i++) { 893 drm_printf(p, " - { offset: 0x%04x, value: 0x%08x }\n", 894 state->registers[i * 2] << 2, 895 state->registers[(i * 2) + 1]); 896 } 897 } 898} 899#endif 900 901/* Dump common gpu status and scratch registers on any hang, to make 902 * the hangcheck logs more useful. The scratch registers seem always 903 * safe to read when GPU has hung (unlike some other regs, depending 904 * on how the GPU hung), and they are useful to match up to cmdstream 905 * dumps when debugging hangs: 906 */ 907void adreno_dump_info(struct msm_gpu *gpu) 908{ 909 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 910 int i; 911 912 printk("revision: %u (%"ADRENO_CHIPID_FMT")\n", 913 adreno_gpu->info->revn, 914 ADRENO_CHIPID_ARGS(adreno_gpu->chip_id)); 915 916 for (i = 0; i < gpu->nr_rings; i++) { 917 struct msm_ringbuffer *ring = gpu->rb[i]; 918 919 printk("rb %d: fence: %d/%d\n", i, 920 ring->memptrs->fence, 921 ring->fctx->last_fence); 922 923 printk("rptr: %d\n", get_rptr(adreno_gpu, ring)); 924 printk("rb wptr: %d\n", get_wptr(ring)); 925 } 926} 927 928/* would be nice to not have to duplicate the _show() stuff with printk(): */ 929void adreno_dump(struct msm_gpu *gpu) 930{ 931 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 932 int i; 933 934 if (!adreno_gpu->registers) 935 return; 936 937 /* dump these out in a form that can be parsed by demsm: */ 938 printk("IO:region %s 00000000 00020000\n", gpu->name); 939 for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) { 940 uint32_t start = adreno_gpu->registers[i]; 941 uint32_t end = adreno_gpu->registers[i+1]; 942 uint32_t addr; 943 944 for (addr = start; addr <= end; addr++) { 945 uint32_t val = gpu_read(gpu, addr); 946 printk("IO:R %08x %08x\n", addr<<2, val); 947 } 948 } 949} 950 951static uint32_t ring_freewords(struct msm_ringbuffer *ring) 952{ 953 struct adreno_gpu *adreno_gpu = to_adreno_gpu(ring->gpu); 954 uint32_t size = MSM_GPU_RINGBUFFER_SZ >> 2; 955 /* Use ring->next to calculate free size */ 956 uint32_t wptr = ring->next - ring->start; 957 uint32_t rptr = get_rptr(adreno_gpu, ring); 958 return (rptr + (size - 1) - wptr) % size; 959} 960 961void adreno_wait_ring(struct msm_ringbuffer *ring, uint32_t ndwords) 962{ 963 if (spin_until(ring_freewords(ring) >= ndwords)) 964 DRM_DEV_ERROR(ring->gpu->dev->dev, 965 "timeout waiting for space in ringbuffer %d\n", 966 ring->id); 967} 968 969static int adreno_get_pwrlevels(struct device *dev, 970 struct msm_gpu *gpu) 971{ 972 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 973 unsigned long freq = ULONG_MAX; 974 struct dev_pm_opp *opp; 975 int ret; 976 977 gpu->fast_rate = 0; 978 979 /* devm_pm_opp_of_add_table may error out but will still create an OPP table */ 980 ret = devm_pm_opp_of_add_table(dev); 981 if (ret == -ENODEV) { 982 /* Special cases for ancient hw with ancient DT bindings */ 983 if (adreno_is_a2xx(adreno_gpu)) { 984 dev_warn(dev, "Unable to find the OPP table. Falling back to 200 MHz.\n"); 985 dev_pm_opp_add(dev, 200000000, 0); 986 } else if (adreno_is_a320(adreno_gpu)) { 987 dev_warn(dev, "Unable to find the OPP table. Falling back to 450 MHz.\n"); 988 dev_pm_opp_add(dev, 450000000, 0); 989 } else { 990 DRM_DEV_ERROR(dev, "Unable to find the OPP table\n"); 991 return -ENODEV; 992 } 993 } else if (ret) { 994 DRM_DEV_ERROR(dev, "Unable to set the OPP table\n"); 995 return ret; 996 } 997 998 /* Find the fastest defined rate */ 999 opp = dev_pm_opp_find_freq_floor(dev, &freq); 1000 if (IS_ERR(opp)) 1001 return PTR_ERR(opp); 1002 1003 gpu->fast_rate = freq; 1004 dev_pm_opp_put(opp); 1005 1006 DBG("fast_rate=%u, slow_rate=27000000", gpu->fast_rate); 1007 1008 return 0; 1009} 1010 1011int adreno_gpu_ocmem_init(struct device *dev, struct adreno_gpu *adreno_gpu, 1012 struct adreno_ocmem *adreno_ocmem) 1013{ 1014 struct ocmem_buf *ocmem_hdl; 1015 struct ocmem *ocmem; 1016 1017 ocmem = of_get_ocmem(dev); 1018 if (IS_ERR(ocmem)) { 1019 if (PTR_ERR(ocmem) == -ENODEV) { 1020 /* 1021 * Return success since either the ocmem property was 1022 * not specified in device tree, or ocmem support is 1023 * not compiled into the kernel. 1024 */ 1025 return 0; 1026 } 1027 1028 return PTR_ERR(ocmem); 1029 } 1030 1031 ocmem_hdl = ocmem_allocate(ocmem, OCMEM_GRAPHICS, adreno_gpu->info->gmem); 1032 if (IS_ERR(ocmem_hdl)) 1033 return PTR_ERR(ocmem_hdl); 1034 1035 adreno_ocmem->ocmem = ocmem; 1036 adreno_ocmem->base = ocmem_hdl->addr; 1037 adreno_ocmem->hdl = ocmem_hdl; 1038 1039 if (WARN_ON(ocmem_hdl->len != adreno_gpu->info->gmem)) 1040 return -ENOMEM; 1041 1042 return 0; 1043} 1044 1045void adreno_gpu_ocmem_cleanup(struct adreno_ocmem *adreno_ocmem) 1046{ 1047 if (adreno_ocmem && adreno_ocmem->base) 1048 ocmem_free(adreno_ocmem->ocmem, OCMEM_GRAPHICS, 1049 adreno_ocmem->hdl); 1050} 1051 1052int adreno_read_speedbin(struct device *dev, u32 *speedbin) 1053{ 1054 return nvmem_cell_read_variable_le_u32(dev, "speed_bin", speedbin); 1055} 1056 1057int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, 1058 struct adreno_gpu *adreno_gpu, 1059 const struct adreno_gpu_funcs *funcs, int nr_rings) 1060{ 1061 struct device *dev = &pdev->dev; 1062 struct adreno_platform_config *config = dev->platform_data; 1063 struct msm_gpu_config adreno_gpu_config = { 0 }; 1064 struct msm_gpu *gpu = &adreno_gpu->base; 1065 const char *gpu_name; 1066 u32 speedbin; 1067 int ret; 1068 1069 adreno_gpu->funcs = funcs; 1070 adreno_gpu->info = config->info; 1071 adreno_gpu->chip_id = config->chip_id; 1072 1073 gpu->allow_relocs = config->info->family < ADRENO_6XX_GEN1; 1074 1075 /* Only handle the core clock when GMU is not in use (or is absent). */ 1076 if (adreno_has_gmu_wrapper(adreno_gpu) || 1077 adreno_gpu->info->family < ADRENO_6XX_GEN1) { 1078 /* 1079 * This can only be done before devm_pm_opp_of_add_table(), or 1080 * dev_pm_opp_set_config() will WARN_ON() 1081 */ 1082 if (IS_ERR(devm_clk_get(dev, "core"))) { 1083 /* 1084 * If "core" is absent, go for the legacy clock name. 1085 * If we got this far in probing, it's a given one of 1086 * them exists. 1087 */ 1088 devm_pm_opp_set_clkname(dev, "core_clk"); 1089 } else 1090 devm_pm_opp_set_clkname(dev, "core"); 1091 } 1092 1093 if (adreno_read_speedbin(dev, &speedbin) || !speedbin) 1094 speedbin = 0xffff; 1095 adreno_gpu->speedbin = (uint16_t) (0xffff & speedbin); 1096 1097 gpu_name = devm_kasprintf(dev, GFP_KERNEL, "%"ADRENO_CHIPID_FMT, 1098 ADRENO_CHIPID_ARGS(config->chip_id)); 1099 if (!gpu_name) 1100 return -ENOMEM; 1101 1102 adreno_gpu_config.ioname = "kgsl_3d0_reg_memory"; 1103 1104 adreno_gpu_config.nr_rings = nr_rings; 1105 1106 ret = adreno_get_pwrlevels(dev, gpu); 1107 if (ret) 1108 return ret; 1109 1110 pm_runtime_set_autosuspend_delay(dev, 1111 adreno_gpu->info->inactive_period); 1112 pm_runtime_use_autosuspend(dev); 1113 1114 return msm_gpu_init(drm, pdev, &adreno_gpu->base, &funcs->base, 1115 gpu_name, &adreno_gpu_config); 1116} 1117 1118void adreno_gpu_cleanup(struct adreno_gpu *adreno_gpu) 1119{ 1120 struct msm_gpu *gpu = &adreno_gpu->base; 1121 struct msm_drm_private *priv = gpu->dev ? gpu->dev->dev_private : NULL; 1122 unsigned int i; 1123 1124 for (i = 0; i < ARRAY_SIZE(adreno_gpu->info->fw); i++) 1125 release_firmware(adreno_gpu->fw[i]); 1126 1127 if (priv && pm_runtime_enabled(&priv->gpu_pdev->dev)) 1128 pm_runtime_disable(&priv->gpu_pdev->dev); 1129 1130 msm_gpu_cleanup(&adreno_gpu->base); 1131} 1132