1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright (c) 2017 The Linux Foundation. All rights reserved. */
3
4#ifndef _A6XX_HFI_H_
5#define _A6XX_HFI_H_
6
7struct a6xx_hfi_queue_table_header {
8	u32 version;
9	u32 size;		/* Size of the queue table in dwords */
10	u32 qhdr0_offset;	/* Offset of the first queue header */
11	u32 qhdr_size;		/* Size of the queue headers */
12	u32 num_queues;		/* Number of total queues */
13	u32 active_queues;	/* Number of active queues */
14};
15
16struct a6xx_hfi_queue_header {
17	u32 status;
18	u32 iova;
19	u32 type;
20	u32 size;
21	u32 msg_size;
22	u32 dropped;
23	u32 rx_watermark;
24	u32 tx_watermark;
25	u32 rx_request;
26	u32 tx_request;
27	u32 read_index;
28	u32 write_index;
29};
30
31struct a6xx_hfi_queue {
32	struct a6xx_hfi_queue_header *header;
33	spinlock_t lock;
34	u32 *data;
35	atomic_t seqnum;
36
37	/*
38	 * Tracking for the start index of the last N messages in the
39	 * queue, for the benefit of devcore dump / crashdec (since
40	 * parsing in the reverse direction to decode the last N
41	 * messages is difficult to do and would rely on heuristics
42	 * which are not guaranteed to be correct)
43	 */
44#define HFI_HISTORY_SZ 8
45	s32 history[HFI_HISTORY_SZ];
46	u8  history_idx;
47};
48
49/* This is the outgoing queue to the GMU */
50#define HFI_COMMAND_QUEUE 0
51
52/* THis is the incoming response queue from the GMU */
53#define HFI_RESPONSE_QUEUE 1
54
55#define HFI_HEADER_ID(msg) ((msg) & 0xff)
56#define HFI_HEADER_SIZE(msg) (((msg) >> 8) & 0xff)
57#define HFI_HEADER_SEQNUM(msg) (((msg) >> 20) & 0xfff)
58
59/* FIXME: Do we need this or can we use ARRAY_SIZE? */
60#define HFI_RESPONSE_PAYLOAD_SIZE 16
61
62/* HFI message types */
63
64#define HFI_MSG_CMD 0
65#define HFI_MSG_ACK 1
66#define HFI_MSG_ACK_V1 2
67
68#define HFI_F2H_MSG_ACK 126
69
70struct a6xx_hfi_msg_response {
71	u32 header;
72	u32 ret_header;
73	u32 error;
74	u32 payload[HFI_RESPONSE_PAYLOAD_SIZE];
75};
76
77#define HFI_F2H_MSG_ERROR 100
78
79struct a6xx_hfi_msg_error {
80	u32 header;
81	u32 code;
82	u32 payload[2];
83};
84
85#define HFI_H2F_MSG_INIT 0
86
87struct a6xx_hfi_msg_gmu_init_cmd {
88	u32 header;
89	u32 seg_id;
90	u32 dbg_buffer_addr;
91	u32 dbg_buffer_size;
92	u32 boot_state;
93};
94
95#define HFI_H2F_MSG_FW_VERSION 1
96
97struct a6xx_hfi_msg_fw_version {
98	u32 header;
99	u32 supported_version;
100};
101
102#define HFI_H2F_MSG_PERF_TABLE 4
103
104struct perf_level {
105	u32 vote;
106	u32 freq;
107};
108
109struct perf_gx_level {
110	u32 vote;
111	u32 acd;
112	u32 freq;
113};
114
115struct a6xx_hfi_msg_perf_table_v1 {
116	u32 header;
117	u32 num_gpu_levels;
118	u32 num_gmu_levels;
119
120	struct perf_level gx_votes[16];
121	struct perf_level cx_votes[4];
122};
123
124struct a6xx_hfi_msg_perf_table {
125	u32 header;
126	u32 num_gpu_levels;
127	u32 num_gmu_levels;
128
129	struct perf_gx_level gx_votes[16];
130	struct perf_level cx_votes[4];
131};
132
133#define HFI_H2F_MSG_BW_TABLE 3
134
135struct a6xx_hfi_msg_bw_table {
136	u32 header;
137	u32 bw_level_num;
138	u32 cnoc_cmds_num;
139	u32 ddr_cmds_num;
140	u32 cnoc_wait_bitmask;
141	u32 ddr_wait_bitmask;
142	u32 cnoc_cmds_addrs[6];
143	u32 cnoc_cmds_data[2][6];
144	u32 ddr_cmds_addrs[8];
145	u32 ddr_cmds_data[16][8];
146};
147
148#define HFI_H2F_MSG_TEST 5
149
150struct a6xx_hfi_msg_test {
151	u32 header;
152};
153
154#define HFI_H2F_MSG_START 10
155
156struct a6xx_hfi_msg_start {
157	u32 header;
158};
159
160#define HFI_H2F_MSG_CORE_FW_START 14
161
162struct a6xx_hfi_msg_core_fw_start {
163	u32 header;
164	u32 handle;
165};
166
167#define HFI_H2F_MSG_GX_BW_PERF_VOTE 30
168
169struct a6xx_hfi_gx_bw_perf_vote_cmd {
170	u32 header;
171	u32 ack_type;
172	u32 freq;
173	u32 bw;
174};
175
176#define HFI_H2F_MSG_PREPARE_SLUMBER 33
177
178struct a6xx_hfi_prep_slumber_cmd {
179	u32 header;
180	u32 bw;
181	u32 freq;
182};
183
184#endif
185