1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2015 MediaTek Inc. 4 * Author: YT SHEN <yt.shen@mediatek.com> 5 */ 6 7#include <linux/component.h> 8#include <linux/iommu.h> 9#include <linux/module.h> 10#include <linux/of.h> 11#include <linux/of_platform.h> 12#include <linux/platform_device.h> 13#include <linux/pm_runtime.h> 14#include <linux/dma-mapping.h> 15 16#include <drm/drm_atomic.h> 17#include <drm/drm_atomic_helper.h> 18#include <drm/drm_drv.h> 19#include <drm/drm_fbdev_generic.h> 20#include <drm/drm_fourcc.h> 21#include <drm/drm_gem.h> 22#include <drm/drm_gem_framebuffer_helper.h> 23#include <drm/drm_ioctl.h> 24#include <drm/drm_of.h> 25#include <drm/drm_probe_helper.h> 26#include <drm/drm_vblank.h> 27 28#include "mtk_drm_crtc.h" 29#include "mtk_drm_ddp_comp.h" 30#include "mtk_drm_drv.h" 31#include "mtk_drm_gem.h" 32 33#define DRIVER_NAME "mediatek" 34#define DRIVER_DESC "Mediatek SoC DRM" 35#define DRIVER_DATE "20150513" 36#define DRIVER_MAJOR 1 37#define DRIVER_MINOR 0 38 39static const struct drm_mode_config_helper_funcs mtk_drm_mode_config_helpers = { 40 .atomic_commit_tail = drm_atomic_helper_commit_tail_rpm, 41}; 42 43static struct drm_framebuffer * 44mtk_drm_mode_fb_create(struct drm_device *dev, 45 struct drm_file *file, 46 const struct drm_mode_fb_cmd2 *cmd) 47{ 48 const struct drm_format_info *info = drm_get_format_info(dev, cmd); 49 50 if (info->num_planes != 1) 51 return ERR_PTR(-EINVAL); 52 53 return drm_gem_fb_create(dev, file, cmd); 54} 55 56static const struct drm_mode_config_funcs mtk_drm_mode_config_funcs = { 57 .fb_create = mtk_drm_mode_fb_create, 58 .atomic_check = drm_atomic_helper_check, 59 .atomic_commit = drm_atomic_helper_commit, 60}; 61 62static const unsigned int mt2701_mtk_ddp_main[] = { 63 DDP_COMPONENT_OVL0, 64 DDP_COMPONENT_RDMA0, 65 DDP_COMPONENT_COLOR0, 66 DDP_COMPONENT_BLS, 67 DDP_COMPONENT_DSI0, 68}; 69 70static const unsigned int mt2701_mtk_ddp_ext[] = { 71 DDP_COMPONENT_RDMA1, 72 DDP_COMPONENT_DPI0, 73}; 74 75static const unsigned int mt7623_mtk_ddp_main[] = { 76 DDP_COMPONENT_OVL0, 77 DDP_COMPONENT_RDMA0, 78 DDP_COMPONENT_COLOR0, 79 DDP_COMPONENT_BLS, 80 DDP_COMPONENT_DPI0, 81}; 82 83static const unsigned int mt7623_mtk_ddp_ext[] = { 84 DDP_COMPONENT_RDMA1, 85 DDP_COMPONENT_DSI0, 86}; 87 88static const unsigned int mt2712_mtk_ddp_main[] = { 89 DDP_COMPONENT_OVL0, 90 DDP_COMPONENT_COLOR0, 91 DDP_COMPONENT_AAL0, 92 DDP_COMPONENT_OD0, 93 DDP_COMPONENT_RDMA0, 94 DDP_COMPONENT_DPI0, 95 DDP_COMPONENT_PWM0, 96}; 97 98static const unsigned int mt2712_mtk_ddp_ext[] = { 99 DDP_COMPONENT_OVL1, 100 DDP_COMPONENT_COLOR1, 101 DDP_COMPONENT_AAL1, 102 DDP_COMPONENT_OD1, 103 DDP_COMPONENT_RDMA1, 104 DDP_COMPONENT_DPI1, 105 DDP_COMPONENT_PWM1, 106}; 107 108static const unsigned int mt2712_mtk_ddp_third[] = { 109 DDP_COMPONENT_RDMA2, 110 DDP_COMPONENT_DSI3, 111 DDP_COMPONENT_PWM2, 112}; 113 114static unsigned int mt8167_mtk_ddp_main[] = { 115 DDP_COMPONENT_OVL0, 116 DDP_COMPONENT_COLOR0, 117 DDP_COMPONENT_CCORR, 118 DDP_COMPONENT_AAL0, 119 DDP_COMPONENT_GAMMA, 120 DDP_COMPONENT_DITHER0, 121 DDP_COMPONENT_RDMA0, 122 DDP_COMPONENT_DSI0, 123}; 124 125static const unsigned int mt8173_mtk_ddp_main[] = { 126 DDP_COMPONENT_OVL0, 127 DDP_COMPONENT_COLOR0, 128 DDP_COMPONENT_AAL0, 129 DDP_COMPONENT_OD0, 130 DDP_COMPONENT_RDMA0, 131 DDP_COMPONENT_UFOE, 132 DDP_COMPONENT_DSI0, 133 DDP_COMPONENT_PWM0, 134}; 135 136static const unsigned int mt8173_mtk_ddp_ext[] = { 137 DDP_COMPONENT_OVL1, 138 DDP_COMPONENT_COLOR1, 139 DDP_COMPONENT_GAMMA, 140 DDP_COMPONENT_RDMA1, 141 DDP_COMPONENT_DPI0, 142}; 143 144static const unsigned int mt8183_mtk_ddp_main[] = { 145 DDP_COMPONENT_OVL0, 146 DDP_COMPONENT_OVL_2L0, 147 DDP_COMPONENT_RDMA0, 148 DDP_COMPONENT_COLOR0, 149 DDP_COMPONENT_CCORR, 150 DDP_COMPONENT_AAL0, 151 DDP_COMPONENT_GAMMA, 152 DDP_COMPONENT_DITHER0, 153 DDP_COMPONENT_DSI0, 154}; 155 156static const unsigned int mt8183_mtk_ddp_ext[] = { 157 DDP_COMPONENT_OVL_2L1, 158 DDP_COMPONENT_RDMA1, 159 DDP_COMPONENT_DPI0, 160}; 161 162static const unsigned int mt8186_mtk_ddp_main[] = { 163 DDP_COMPONENT_OVL0, 164 DDP_COMPONENT_RDMA0, 165 DDP_COMPONENT_COLOR0, 166 DDP_COMPONENT_CCORR, 167 DDP_COMPONENT_AAL0, 168 DDP_COMPONENT_GAMMA, 169 DDP_COMPONENT_POSTMASK0, 170 DDP_COMPONENT_DITHER0, 171 DDP_COMPONENT_DSI0, 172}; 173 174static const unsigned int mt8186_mtk_ddp_ext[] = { 175 DDP_COMPONENT_OVL_2L0, 176 DDP_COMPONENT_RDMA1, 177 DDP_COMPONENT_DPI0, 178}; 179 180static const unsigned int mt8188_mtk_ddp_main[] = { 181 DDP_COMPONENT_OVL0, 182 DDP_COMPONENT_RDMA0, 183 DDP_COMPONENT_COLOR0, 184 DDP_COMPONENT_CCORR, 185 DDP_COMPONENT_AAL0, 186 DDP_COMPONENT_GAMMA, 187 DDP_COMPONENT_POSTMASK0, 188 DDP_COMPONENT_DITHER0, 189 DDP_COMPONENT_DP_INTF0, 190}; 191 192static const unsigned int mt8192_mtk_ddp_main[] = { 193 DDP_COMPONENT_OVL0, 194 DDP_COMPONENT_OVL_2L0, 195 DDP_COMPONENT_RDMA0, 196 DDP_COMPONENT_COLOR0, 197 DDP_COMPONENT_CCORR, 198 DDP_COMPONENT_AAL0, 199 DDP_COMPONENT_GAMMA, 200 DDP_COMPONENT_POSTMASK0, 201 DDP_COMPONENT_DITHER0, 202 DDP_COMPONENT_DSI0, 203}; 204 205static const unsigned int mt8192_mtk_ddp_ext[] = { 206 DDP_COMPONENT_OVL_2L2, 207 DDP_COMPONENT_RDMA4, 208 DDP_COMPONENT_DPI0, 209}; 210 211static const unsigned int mt8195_mtk_ddp_main[] = { 212 DDP_COMPONENT_OVL0, 213 DDP_COMPONENT_RDMA0, 214 DDP_COMPONENT_COLOR0, 215 DDP_COMPONENT_CCORR, 216 DDP_COMPONENT_AAL0, 217 DDP_COMPONENT_GAMMA, 218 DDP_COMPONENT_DITHER0, 219 DDP_COMPONENT_DSC0, 220 DDP_COMPONENT_MERGE0, 221 DDP_COMPONENT_DP_INTF0, 222}; 223 224static const unsigned int mt8195_mtk_ddp_ext[] = { 225 DDP_COMPONENT_DRM_OVL_ADAPTOR, 226 DDP_COMPONENT_MERGE5, 227 DDP_COMPONENT_DP_INTF1, 228}; 229 230static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { 231 .main_path = mt2701_mtk_ddp_main, 232 .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main), 233 .ext_path = mt2701_mtk_ddp_ext, 234 .ext_len = ARRAY_SIZE(mt2701_mtk_ddp_ext), 235 .shadow_register = true, 236 .mmsys_dev_num = 1, 237}; 238 239static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = { 240 .main_path = mt7623_mtk_ddp_main, 241 .main_len = ARRAY_SIZE(mt7623_mtk_ddp_main), 242 .ext_path = mt7623_mtk_ddp_ext, 243 .ext_len = ARRAY_SIZE(mt7623_mtk_ddp_ext), 244 .shadow_register = true, 245 .mmsys_dev_num = 1, 246}; 247 248static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = { 249 .main_path = mt2712_mtk_ddp_main, 250 .main_len = ARRAY_SIZE(mt2712_mtk_ddp_main), 251 .ext_path = mt2712_mtk_ddp_ext, 252 .ext_len = ARRAY_SIZE(mt2712_mtk_ddp_ext), 253 .third_path = mt2712_mtk_ddp_third, 254 .third_len = ARRAY_SIZE(mt2712_mtk_ddp_third), 255 .mmsys_dev_num = 1, 256}; 257 258static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = { 259 .main_path = mt8167_mtk_ddp_main, 260 .main_len = ARRAY_SIZE(mt8167_mtk_ddp_main), 261 .mmsys_dev_num = 1, 262}; 263 264static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { 265 .main_path = mt8173_mtk_ddp_main, 266 .main_len = ARRAY_SIZE(mt8173_mtk_ddp_main), 267 .ext_path = mt8173_mtk_ddp_ext, 268 .ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext), 269 .mmsys_dev_num = 1, 270}; 271 272static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { 273 .main_path = mt8183_mtk_ddp_main, 274 .main_len = ARRAY_SIZE(mt8183_mtk_ddp_main), 275 .ext_path = mt8183_mtk_ddp_ext, 276 .ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext), 277 .mmsys_dev_num = 1, 278}; 279 280static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = { 281 .main_path = mt8186_mtk_ddp_main, 282 .main_len = ARRAY_SIZE(mt8186_mtk_ddp_main), 283 .ext_path = mt8186_mtk_ddp_ext, 284 .ext_len = ARRAY_SIZE(mt8186_mtk_ddp_ext), 285 .mmsys_dev_num = 1, 286}; 287 288static const struct mtk_mmsys_driver_data mt8188_vdosys0_driver_data = { 289 .main_path = mt8188_mtk_ddp_main, 290 .main_len = ARRAY_SIZE(mt8188_mtk_ddp_main), 291 .mmsys_dev_num = 1, 292}; 293 294static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = { 295 .main_path = mt8192_mtk_ddp_main, 296 .main_len = ARRAY_SIZE(mt8192_mtk_ddp_main), 297 .ext_path = mt8192_mtk_ddp_ext, 298 .ext_len = ARRAY_SIZE(mt8192_mtk_ddp_ext), 299 .mmsys_dev_num = 1, 300}; 301 302static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = { 303 .main_path = mt8195_mtk_ddp_main, 304 .main_len = ARRAY_SIZE(mt8195_mtk_ddp_main), 305 .mmsys_dev_num = 2, 306}; 307 308static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = { 309 .ext_path = mt8195_mtk_ddp_ext, 310 .ext_len = ARRAY_SIZE(mt8195_mtk_ddp_ext), 311 .mmsys_id = 1, 312 .mmsys_dev_num = 2, 313}; 314 315static const struct of_device_id mtk_drm_of_ids[] = { 316 { .compatible = "mediatek,mt2701-mmsys", 317 .data = &mt2701_mmsys_driver_data}, 318 { .compatible = "mediatek,mt7623-mmsys", 319 .data = &mt7623_mmsys_driver_data}, 320 { .compatible = "mediatek,mt2712-mmsys", 321 .data = &mt2712_mmsys_driver_data}, 322 { .compatible = "mediatek,mt8167-mmsys", 323 .data = &mt8167_mmsys_driver_data}, 324 { .compatible = "mediatek,mt8173-mmsys", 325 .data = &mt8173_mmsys_driver_data}, 326 { .compatible = "mediatek,mt8183-mmsys", 327 .data = &mt8183_mmsys_driver_data}, 328 { .compatible = "mediatek,mt8186-mmsys", 329 .data = &mt8186_mmsys_driver_data}, 330 { .compatible = "mediatek,mt8188-vdosys0", 331 .data = &mt8188_vdosys0_driver_data}, 332 { .compatible = "mediatek,mt8192-mmsys", 333 .data = &mt8192_mmsys_driver_data}, 334 { .compatible = "mediatek,mt8195-mmsys", 335 .data = &mt8195_vdosys0_driver_data}, 336 { .compatible = "mediatek,mt8195-vdosys0", 337 .data = &mt8195_vdosys0_driver_data}, 338 { .compatible = "mediatek,mt8195-vdosys1", 339 .data = &mt8195_vdosys1_driver_data}, 340 { } 341}; 342MODULE_DEVICE_TABLE(of, mtk_drm_of_ids); 343 344static int mtk_drm_match(struct device *dev, void *data) 345{ 346 if (!strncmp(dev_name(dev), "mediatek-drm", sizeof("mediatek-drm") - 1)) 347 return true; 348 return false; 349} 350 351static bool mtk_drm_get_all_drm_priv(struct device *dev) 352{ 353 struct mtk_drm_private *drm_priv = dev_get_drvdata(dev); 354 struct mtk_drm_private *all_drm_priv[MAX_CRTC]; 355 struct device_node *phandle = dev->parent->of_node; 356 const struct of_device_id *of_id; 357 struct device_node *node; 358 struct device *drm_dev; 359 unsigned int cnt = 0; 360 int i, j; 361 362 for_each_child_of_node(phandle->parent, node) { 363 struct platform_device *pdev; 364 365 of_id = of_match_node(mtk_drm_of_ids, node); 366 if (!of_id) 367 continue; 368 369 pdev = of_find_device_by_node(node); 370 if (!pdev) 371 continue; 372 373 drm_dev = device_find_child(&pdev->dev, NULL, mtk_drm_match); 374 if (!drm_dev || !dev_get_drvdata(drm_dev)) 375 continue; 376 377 all_drm_priv[cnt] = dev_get_drvdata(drm_dev); 378 if (all_drm_priv[cnt] && all_drm_priv[cnt]->mtk_drm_bound) 379 cnt++; 380 381 if (cnt == MAX_CRTC) 382 break; 383 } 384 385 if (drm_priv->data->mmsys_dev_num == cnt) { 386 for (i = 0; i < cnt; i++) 387 for (j = 0; j < cnt; j++) 388 all_drm_priv[j]->all_drm_private[i] = all_drm_priv[i]; 389 390 return true; 391 } 392 393 return false; 394} 395 396static bool mtk_drm_find_mmsys_comp(struct mtk_drm_private *private, int comp_id) 397{ 398 const struct mtk_mmsys_driver_data *drv_data = private->data; 399 int i; 400 401 if (drv_data->main_path) 402 for (i = 0; i < drv_data->main_len; i++) 403 if (drv_data->main_path[i] == comp_id) 404 return true; 405 406 if (drv_data->ext_path) 407 for (i = 0; i < drv_data->ext_len; i++) 408 if (drv_data->ext_path[i] == comp_id) 409 return true; 410 411 if (drv_data->third_path) 412 for (i = 0; i < drv_data->third_len; i++) 413 if (drv_data->third_path[i] == comp_id) 414 return true; 415 416 return false; 417} 418 419static int mtk_drm_kms_init(struct drm_device *drm) 420{ 421 struct mtk_drm_private *private = drm->dev_private; 422 struct mtk_drm_private *priv_n; 423 struct device *dma_dev = NULL; 424 struct drm_crtc *crtc; 425 int ret, i, j; 426 427 if (drm_firmware_drivers_only()) 428 return -ENODEV; 429 430 ret = drmm_mode_config_init(drm); 431 if (ret) 432 goto put_mutex_dev; 433 434 drm->mode_config.min_width = 64; 435 drm->mode_config.min_height = 64; 436 437 /* 438 * set max width and height as default value(4096x4096). 439 * this value would be used to check framebuffer size limitation 440 * at drm_mode_addfb(). 441 */ 442 drm->mode_config.max_width = 4096; 443 drm->mode_config.max_height = 4096; 444 drm->mode_config.funcs = &mtk_drm_mode_config_funcs; 445 drm->mode_config.helper_private = &mtk_drm_mode_config_helpers; 446 447 for (i = 0; i < private->data->mmsys_dev_num; i++) { 448 drm->dev_private = private->all_drm_private[i]; 449 ret = component_bind_all(private->all_drm_private[i]->dev, drm); 450 if (ret) 451 goto put_mutex_dev; 452 } 453 454 /* 455 * Ensure internal panels are at the top of the connector list before 456 * crtc creation. 457 */ 458 drm_helper_move_panel_connectors_to_head(drm); 459 460 /* 461 * 1. We currently support two fixed data streams, each optional, 462 * and each statically assigned to a crtc: 463 * OVL0 -> COLOR0 -> AAL -> OD -> RDMA0 -> UFOE -> DSI0 ... 464 * 2. For multi mmsys architecture, crtc path data are located in 465 * different drm private data structures. Loop through crtc index to 466 * create crtc from the main path and then ext_path and finally the 467 * third path. 468 */ 469 for (i = 0; i < MAX_CRTC; i++) { 470 for (j = 0; j < private->data->mmsys_dev_num; j++) { 471 priv_n = private->all_drm_private[j]; 472 473 if (i == 0 && priv_n->data->main_len) { 474 ret = mtk_drm_crtc_create(drm, priv_n->data->main_path, 475 priv_n->data->main_len, j); 476 if (ret) 477 goto err_component_unbind; 478 479 continue; 480 } else if (i == 1 && priv_n->data->ext_len) { 481 ret = mtk_drm_crtc_create(drm, priv_n->data->ext_path, 482 priv_n->data->ext_len, j); 483 if (ret) 484 goto err_component_unbind; 485 486 continue; 487 } else if (i == 2 && priv_n->data->third_len) { 488 ret = mtk_drm_crtc_create(drm, priv_n->data->third_path, 489 priv_n->data->third_len, j); 490 if (ret) 491 goto err_component_unbind; 492 493 continue; 494 } 495 } 496 } 497 498 /* Use OVL device for all DMA memory allocations */ 499 crtc = drm_crtc_from_index(drm, 0); 500 if (crtc) 501 dma_dev = mtk_drm_crtc_dma_dev_get(crtc); 502 if (!dma_dev) { 503 ret = -ENODEV; 504 dev_err(drm->dev, "Need at least one OVL device\n"); 505 goto err_component_unbind; 506 } 507 508 for (i = 0; i < private->data->mmsys_dev_num; i++) 509 private->all_drm_private[i]->dma_dev = dma_dev; 510 511 /* 512 * Configure the DMA segment size to make sure we get contiguous IOVA 513 * when importing PRIME buffers. 514 */ 515 ret = dma_set_max_seg_size(dma_dev, UINT_MAX); 516 if (ret) { 517 dev_err(dma_dev, "Failed to set DMA segment size\n"); 518 goto err_component_unbind; 519 } 520 521 ret = drm_vblank_init(drm, MAX_CRTC); 522 if (ret < 0) 523 goto err_component_unbind; 524 525 drm_kms_helper_poll_init(drm); 526 drm_mode_config_reset(drm); 527 528 return 0; 529 530err_component_unbind: 531 for (i = 0; i < private->data->mmsys_dev_num; i++) 532 component_unbind_all(private->all_drm_private[i]->dev, drm); 533put_mutex_dev: 534 for (i = 0; i < private->data->mmsys_dev_num; i++) 535 put_device(private->all_drm_private[i]->mutex_dev); 536 537 return ret; 538} 539 540static void mtk_drm_kms_deinit(struct drm_device *drm) 541{ 542 drm_kms_helper_poll_fini(drm); 543 drm_atomic_helper_shutdown(drm); 544 545 component_unbind_all(drm->dev, drm); 546} 547 548DEFINE_DRM_GEM_FOPS(mtk_drm_fops); 549 550/* 551 * We need to override this because the device used to import the memory is 552 * not dev->dev, as drm_gem_prime_import() expects. 553 */ 554static struct drm_gem_object *mtk_drm_gem_prime_import(struct drm_device *dev, 555 struct dma_buf *dma_buf) 556{ 557 struct mtk_drm_private *private = dev->dev_private; 558 559 return drm_gem_prime_import_dev(dev, dma_buf, private->dma_dev); 560} 561 562static const struct drm_driver mtk_drm_driver = { 563 .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC, 564 565 .dumb_create = mtk_drm_gem_dumb_create, 566 567 .gem_prime_import = mtk_drm_gem_prime_import, 568 .gem_prime_import_sg_table = mtk_gem_prime_import_sg_table, 569 .fops = &mtk_drm_fops, 570 571 .name = DRIVER_NAME, 572 .desc = DRIVER_DESC, 573 .date = DRIVER_DATE, 574 .major = DRIVER_MAJOR, 575 .minor = DRIVER_MINOR, 576}; 577 578static int compare_dev(struct device *dev, void *data) 579{ 580 return dev == (struct device *)data; 581} 582 583static int mtk_drm_bind(struct device *dev) 584{ 585 struct mtk_drm_private *private = dev_get_drvdata(dev); 586 struct platform_device *pdev; 587 struct drm_device *drm; 588 int ret, i; 589 590 if (!iommu_present(&platform_bus_type)) 591 return -EPROBE_DEFER; 592 593 pdev = of_find_device_by_node(private->mutex_node); 594 if (!pdev) { 595 dev_err(dev, "Waiting for disp-mutex device %pOF\n", 596 private->mutex_node); 597 of_node_put(private->mutex_node); 598 return -EPROBE_DEFER; 599 } 600 601 private->mutex_dev = &pdev->dev; 602 private->mtk_drm_bound = true; 603 private->dev = dev; 604 605 if (!mtk_drm_get_all_drm_priv(dev)) 606 return 0; 607 608 drm = drm_dev_alloc(&mtk_drm_driver, dev); 609 if (IS_ERR(drm)) 610 return PTR_ERR(drm); 611 612 private->drm_master = true; 613 drm->dev_private = private; 614 for (i = 0; i < private->data->mmsys_dev_num; i++) 615 private->all_drm_private[i]->drm = drm; 616 617 ret = mtk_drm_kms_init(drm); 618 if (ret < 0) 619 goto err_free; 620 621 ret = drm_dev_register(drm, 0); 622 if (ret < 0) 623 goto err_deinit; 624 625 drm_fbdev_generic_setup(drm, 32); 626 627 return 0; 628 629err_deinit: 630 mtk_drm_kms_deinit(drm); 631err_free: 632 private->drm = NULL; 633 drm_dev_put(drm); 634 return ret; 635} 636 637static void mtk_drm_unbind(struct device *dev) 638{ 639 struct mtk_drm_private *private = dev_get_drvdata(dev); 640 641 /* for multi mmsys dev, unregister drm dev in mmsys master */ 642 if (private->drm_master) { 643 drm_dev_unregister(private->drm); 644 mtk_drm_kms_deinit(private->drm); 645 drm_dev_put(private->drm); 646 } 647 private->mtk_drm_bound = false; 648 private->drm_master = false; 649 private->drm = NULL; 650} 651 652static const struct component_master_ops mtk_drm_ops = { 653 .bind = mtk_drm_bind, 654 .unbind = mtk_drm_unbind, 655}; 656 657static const struct of_device_id mtk_ddp_comp_dt_ids[] = { 658 { .compatible = "mediatek,mt8167-disp-aal", 659 .data = (void *)MTK_DISP_AAL}, 660 { .compatible = "mediatek,mt8173-disp-aal", 661 .data = (void *)MTK_DISP_AAL}, 662 { .compatible = "mediatek,mt8183-disp-aal", 663 .data = (void *)MTK_DISP_AAL}, 664 { .compatible = "mediatek,mt8192-disp-aal", 665 .data = (void *)MTK_DISP_AAL}, 666 { .compatible = "mediatek,mt8167-disp-ccorr", 667 .data = (void *)MTK_DISP_CCORR }, 668 { .compatible = "mediatek,mt8183-disp-ccorr", 669 .data = (void *)MTK_DISP_CCORR }, 670 { .compatible = "mediatek,mt8192-disp-ccorr", 671 .data = (void *)MTK_DISP_CCORR }, 672 { .compatible = "mediatek,mt2701-disp-color", 673 .data = (void *)MTK_DISP_COLOR }, 674 { .compatible = "mediatek,mt8167-disp-color", 675 .data = (void *)MTK_DISP_COLOR }, 676 { .compatible = "mediatek,mt8173-disp-color", 677 .data = (void *)MTK_DISP_COLOR }, 678 { .compatible = "mediatek,mt8167-disp-dither", 679 .data = (void *)MTK_DISP_DITHER }, 680 { .compatible = "mediatek,mt8183-disp-dither", 681 .data = (void *)MTK_DISP_DITHER }, 682 { .compatible = "mediatek,mt8195-disp-dsc", 683 .data = (void *)MTK_DISP_DSC }, 684 { .compatible = "mediatek,mt8167-disp-gamma", 685 .data = (void *)MTK_DISP_GAMMA, }, 686 { .compatible = "mediatek,mt8173-disp-gamma", 687 .data = (void *)MTK_DISP_GAMMA, }, 688 { .compatible = "mediatek,mt8183-disp-gamma", 689 .data = (void *)MTK_DISP_GAMMA, }, 690 { .compatible = "mediatek,mt8195-disp-merge", 691 .data = (void *)MTK_DISP_MERGE }, 692 { .compatible = "mediatek,mt2701-disp-mutex", 693 .data = (void *)MTK_DISP_MUTEX }, 694 { .compatible = "mediatek,mt2712-disp-mutex", 695 .data = (void *)MTK_DISP_MUTEX }, 696 { .compatible = "mediatek,mt8167-disp-mutex", 697 .data = (void *)MTK_DISP_MUTEX }, 698 { .compatible = "mediatek,mt8173-disp-mutex", 699 .data = (void *)MTK_DISP_MUTEX }, 700 { .compatible = "mediatek,mt8183-disp-mutex", 701 .data = (void *)MTK_DISP_MUTEX }, 702 { .compatible = "mediatek,mt8186-disp-mutex", 703 .data = (void *)MTK_DISP_MUTEX }, 704 { .compatible = "mediatek,mt8188-disp-mutex", 705 .data = (void *)MTK_DISP_MUTEX }, 706 { .compatible = "mediatek,mt8192-disp-mutex", 707 .data = (void *)MTK_DISP_MUTEX }, 708 { .compatible = "mediatek,mt8195-disp-mutex", 709 .data = (void *)MTK_DISP_MUTEX }, 710 { .compatible = "mediatek,mt8173-disp-od", 711 .data = (void *)MTK_DISP_OD }, 712 { .compatible = "mediatek,mt2701-disp-ovl", 713 .data = (void *)MTK_DISP_OVL }, 714 { .compatible = "mediatek,mt8167-disp-ovl", 715 .data = (void *)MTK_DISP_OVL }, 716 { .compatible = "mediatek,mt8173-disp-ovl", 717 .data = (void *)MTK_DISP_OVL }, 718 { .compatible = "mediatek,mt8183-disp-ovl", 719 .data = (void *)MTK_DISP_OVL }, 720 { .compatible = "mediatek,mt8192-disp-ovl", 721 .data = (void *)MTK_DISP_OVL }, 722 { .compatible = "mediatek,mt8183-disp-ovl-2l", 723 .data = (void *)MTK_DISP_OVL_2L }, 724 { .compatible = "mediatek,mt8192-disp-ovl-2l", 725 .data = (void *)MTK_DISP_OVL_2L }, 726 { .compatible = "mediatek,mt8192-disp-postmask", 727 .data = (void *)MTK_DISP_POSTMASK }, 728 { .compatible = "mediatek,mt2701-disp-pwm", 729 .data = (void *)MTK_DISP_BLS }, 730 { .compatible = "mediatek,mt8167-disp-pwm", 731 .data = (void *)MTK_DISP_PWM }, 732 { .compatible = "mediatek,mt8173-disp-pwm", 733 .data = (void *)MTK_DISP_PWM }, 734 { .compatible = "mediatek,mt2701-disp-rdma", 735 .data = (void *)MTK_DISP_RDMA }, 736 { .compatible = "mediatek,mt8167-disp-rdma", 737 .data = (void *)MTK_DISP_RDMA }, 738 { .compatible = "mediatek,mt8173-disp-rdma", 739 .data = (void *)MTK_DISP_RDMA }, 740 { .compatible = "mediatek,mt8183-disp-rdma", 741 .data = (void *)MTK_DISP_RDMA }, 742 { .compatible = "mediatek,mt8195-disp-rdma", 743 .data = (void *)MTK_DISP_RDMA }, 744 { .compatible = "mediatek,mt8173-disp-ufoe", 745 .data = (void *)MTK_DISP_UFOE }, 746 { .compatible = "mediatek,mt8173-disp-wdma", 747 .data = (void *)MTK_DISP_WDMA }, 748 { .compatible = "mediatek,mt2701-dpi", 749 .data = (void *)MTK_DPI }, 750 { .compatible = "mediatek,mt8167-dsi", 751 .data = (void *)MTK_DSI }, 752 { .compatible = "mediatek,mt8173-dpi", 753 .data = (void *)MTK_DPI }, 754 { .compatible = "mediatek,mt8183-dpi", 755 .data = (void *)MTK_DPI }, 756 { .compatible = "mediatek,mt8186-dpi", 757 .data = (void *)MTK_DPI }, 758 { .compatible = "mediatek,mt8188-dp-intf", 759 .data = (void *)MTK_DP_INTF }, 760 { .compatible = "mediatek,mt8192-dpi", 761 .data = (void *)MTK_DPI }, 762 { .compatible = "mediatek,mt8195-dp-intf", 763 .data = (void *)MTK_DP_INTF }, 764 { .compatible = "mediatek,mt2701-dsi", 765 .data = (void *)MTK_DSI }, 766 { .compatible = "mediatek,mt8173-dsi", 767 .data = (void *)MTK_DSI }, 768 { .compatible = "mediatek,mt8183-dsi", 769 .data = (void *)MTK_DSI }, 770 { .compatible = "mediatek,mt8186-dsi", 771 .data = (void *)MTK_DSI }, 772 { } 773}; 774 775static int mtk_drm_probe(struct platform_device *pdev) 776{ 777 struct device *dev = &pdev->dev; 778 struct device_node *phandle = dev->parent->of_node; 779 const struct of_device_id *of_id; 780 struct mtk_drm_private *private; 781 struct device_node *node; 782 struct component_match *match = NULL; 783 struct platform_device *ovl_adaptor; 784 int ret; 785 int i; 786 787 private = devm_kzalloc(dev, sizeof(*private), GFP_KERNEL); 788 if (!private) 789 return -ENOMEM; 790 791 private->mmsys_dev = dev->parent; 792 if (!private->mmsys_dev) { 793 dev_err(dev, "Failed to get MMSYS device\n"); 794 return -ENODEV; 795 } 796 797 of_id = of_match_node(mtk_drm_of_ids, phandle); 798 if (!of_id) 799 return -ENODEV; 800 801 private->data = of_id->data; 802 803 private->all_drm_private = devm_kmalloc_array(dev, private->data->mmsys_dev_num, 804 sizeof(*private->all_drm_private), 805 GFP_KERNEL); 806 if (!private->all_drm_private) 807 return -ENOMEM; 808 809 /* Bringup ovl_adaptor */ 810 if (mtk_drm_find_mmsys_comp(private, DDP_COMPONENT_DRM_OVL_ADAPTOR)) { 811 ovl_adaptor = platform_device_register_data(dev, "mediatek-disp-ovl-adaptor", 812 PLATFORM_DEVID_AUTO, 813 (void *)private->mmsys_dev, 814 sizeof(*private->mmsys_dev)); 815 private->ddp_comp[DDP_COMPONENT_DRM_OVL_ADAPTOR].dev = &ovl_adaptor->dev; 816 mtk_ddp_comp_init(NULL, &private->ddp_comp[DDP_COMPONENT_DRM_OVL_ADAPTOR], 817 DDP_COMPONENT_DRM_OVL_ADAPTOR); 818 component_match_add(dev, &match, compare_dev, &ovl_adaptor->dev); 819 } 820 821 /* Iterate over sibling DISP function blocks */ 822 for_each_child_of_node(phandle->parent, node) { 823 const struct of_device_id *of_id; 824 enum mtk_ddp_comp_type comp_type; 825 int comp_id; 826 827 of_id = of_match_node(mtk_ddp_comp_dt_ids, node); 828 if (!of_id) 829 continue; 830 831 if (!of_device_is_available(node)) { 832 dev_dbg(dev, "Skipping disabled component %pOF\n", 833 node); 834 continue; 835 } 836 837 comp_type = (enum mtk_ddp_comp_type)(uintptr_t)of_id->data; 838 839 if (comp_type == MTK_DISP_MUTEX) { 840 int id; 841 842 id = of_alias_get_id(node, "mutex"); 843 if (id < 0 || id == private->data->mmsys_id) { 844 private->mutex_node = of_node_get(node); 845 dev_dbg(dev, "get mutex for mmsys %d", private->data->mmsys_id); 846 } 847 continue; 848 } 849 850 comp_id = mtk_ddp_comp_get_id(node, comp_type); 851 if (comp_id < 0) { 852 dev_warn(dev, "Skipping unknown component %pOF\n", 853 node); 854 continue; 855 } 856 857 if (!mtk_drm_find_mmsys_comp(private, comp_id)) 858 continue; 859 860 private->comp_node[comp_id] = of_node_get(node); 861 862 /* 863 * Currently only the AAL, CCORR, COLOR, GAMMA, MERGE, OVL, RDMA, DSI, and DPI 864 * blocks have separate component platform drivers and initialize their own 865 * DDP component structure. The others are initialized here. 866 */ 867 if (comp_type == MTK_DISP_AAL || 868 comp_type == MTK_DISP_CCORR || 869 comp_type == MTK_DISP_COLOR || 870 comp_type == MTK_DISP_GAMMA || 871 comp_type == MTK_DISP_MERGE || 872 comp_type == MTK_DISP_OVL || 873 comp_type == MTK_DISP_OVL_2L || 874 comp_type == MTK_DISP_OVL_ADAPTOR || 875 comp_type == MTK_DISP_RDMA || 876 comp_type == MTK_DP_INTF || 877 comp_type == MTK_DPI || 878 comp_type == MTK_DSI) { 879 dev_info(dev, "Adding component match for %pOF\n", 880 node); 881 drm_of_component_match_add(dev, &match, component_compare_of, 882 node); 883 } 884 885 ret = mtk_ddp_comp_init(node, &private->ddp_comp[comp_id], comp_id); 886 if (ret) { 887 of_node_put(node); 888 goto err_node; 889 } 890 } 891 892 if (!private->mutex_node) { 893 dev_err(dev, "Failed to find disp-mutex node\n"); 894 ret = -ENODEV; 895 goto err_node; 896 } 897 898 pm_runtime_enable(dev); 899 900 platform_set_drvdata(pdev, private); 901 902 ret = component_master_add_with_match(dev, &mtk_drm_ops, match); 903 if (ret) 904 goto err_pm; 905 906 return 0; 907 908err_pm: 909 pm_runtime_disable(dev); 910err_node: 911 of_node_put(private->mutex_node); 912 for (i = 0; i < DDP_COMPONENT_DRM_ID_MAX; i++) 913 of_node_put(private->comp_node[i]); 914 return ret; 915} 916 917static void mtk_drm_remove(struct platform_device *pdev) 918{ 919 struct mtk_drm_private *private = platform_get_drvdata(pdev); 920 int i; 921 922 component_master_del(&pdev->dev, &mtk_drm_ops); 923 pm_runtime_disable(&pdev->dev); 924 of_node_put(private->mutex_node); 925 for (i = 0; i < DDP_COMPONENT_DRM_ID_MAX; i++) 926 of_node_put(private->comp_node[i]); 927} 928 929static int mtk_drm_sys_prepare(struct device *dev) 930{ 931 struct mtk_drm_private *private = dev_get_drvdata(dev); 932 struct drm_device *drm = private->drm; 933 934 if (private->drm_master) 935 return drm_mode_config_helper_suspend(drm); 936 else 937 return 0; 938} 939 940static void mtk_drm_sys_complete(struct device *dev) 941{ 942 struct mtk_drm_private *private = dev_get_drvdata(dev); 943 struct drm_device *drm = private->drm; 944 int ret = 0; 945 946 if (private->drm_master) 947 ret = drm_mode_config_helper_resume(drm); 948 if (ret) 949 dev_err(dev, "Failed to resume\n"); 950} 951 952static const struct dev_pm_ops mtk_drm_pm_ops = { 953 .prepare = mtk_drm_sys_prepare, 954 .complete = mtk_drm_sys_complete, 955}; 956 957static struct platform_driver mtk_drm_platform_driver = { 958 .probe = mtk_drm_probe, 959 .remove_new = mtk_drm_remove, 960 .driver = { 961 .name = "mediatek-drm", 962 .pm = &mtk_drm_pm_ops, 963 }, 964}; 965 966static struct platform_driver * const mtk_drm_drivers[] = { 967 &mtk_disp_aal_driver, 968 &mtk_disp_ccorr_driver, 969 &mtk_disp_color_driver, 970 &mtk_disp_gamma_driver, 971 &mtk_disp_merge_driver, 972 &mtk_disp_ovl_adaptor_driver, 973 &mtk_disp_ovl_driver, 974 &mtk_disp_rdma_driver, 975 &mtk_dpi_driver, 976 &mtk_drm_platform_driver, 977 &mtk_dsi_driver, 978 &mtk_ethdr_driver, 979 &mtk_mdp_rdma_driver, 980}; 981 982static int __init mtk_drm_init(void) 983{ 984 return platform_register_drivers(mtk_drm_drivers, 985 ARRAY_SIZE(mtk_drm_drivers)); 986} 987 988static void __exit mtk_drm_exit(void) 989{ 990 platform_unregister_drivers(mtk_drm_drivers, 991 ARRAY_SIZE(mtk_drm_drivers)); 992} 993 994module_init(mtk_drm_init); 995module_exit(mtk_drm_exit); 996 997MODULE_AUTHOR("YT SHEN <yt.shen@mediatek.com>"); 998MODULE_DESCRIPTION("Mediatek SoC DRM driver"); 999MODULE_LICENSE("GPL v2"); 1000