1/*
2 * Copyright © 2014-2017 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 */
24
25#ifndef _INTEL_DEVICE_INFO_H_
26#define _INTEL_DEVICE_INFO_H_
27
28#include <uapi/drm/i915_drm.h>
29
30#include "intel_step.h"
31
32#include "gt/intel_engine_types.h"
33#include "gt/intel_context_types.h"
34#include "gt/intel_sseu.h"
35
36#include "gem/i915_gem_object_types.h"
37
38struct drm_printer;
39struct drm_i915_private;
40struct intel_gt_definition;
41
42/* Keep in gen based order, and chronological order within a gen */
43enum intel_platform {
44	INTEL_PLATFORM_UNINITIALIZED = 0,
45	/* gen2 */
46	INTEL_I830,
47	INTEL_I845G,
48	INTEL_I85X,
49	INTEL_I865G,
50	/* gen3 */
51	INTEL_I915G,
52	INTEL_I915GM,
53	INTEL_I945G,
54	INTEL_I945GM,
55	INTEL_G33,
56	INTEL_PINEVIEW,
57	/* gen4 */
58	INTEL_I965G,
59	INTEL_I965GM,
60	INTEL_G45,
61	INTEL_GM45,
62	/* gen5 */
63	INTEL_IRONLAKE,
64	/* gen6 */
65	INTEL_SANDYBRIDGE,
66	/* gen7 */
67	INTEL_IVYBRIDGE,
68	INTEL_VALLEYVIEW,
69	INTEL_HASWELL,
70	/* gen8 */
71	INTEL_BROADWELL,
72	INTEL_CHERRYVIEW,
73	/* gen9 */
74	INTEL_SKYLAKE,
75	INTEL_BROXTON,
76	INTEL_KABYLAKE,
77	INTEL_GEMINILAKE,
78	INTEL_COFFEELAKE,
79	INTEL_COMETLAKE,
80	/* gen11 */
81	INTEL_ICELAKE,
82	INTEL_ELKHARTLAKE,
83	INTEL_JASPERLAKE,
84	/* gen12 */
85	INTEL_TIGERLAKE,
86	INTEL_ROCKETLAKE,
87	INTEL_DG1,
88	INTEL_ALDERLAKE_S,
89	INTEL_ALDERLAKE_P,
90	INTEL_XEHPSDV,
91	INTEL_DG2,
92	INTEL_PONTEVECCHIO,
93	INTEL_METEORLAKE,
94	INTEL_MAX_PLATFORMS
95};
96
97/*
98 * Subplatform bits share the same namespace per parent platform. In other words
99 * it is fine for the same bit to be used on multiple parent platforms.
100 */
101
102#define INTEL_SUBPLATFORM_BITS (3)
103#define INTEL_SUBPLATFORM_MASK (BIT(INTEL_SUBPLATFORM_BITS) - 1)
104
105/* HSW/BDW/SKL/KBL/CFL */
106#define INTEL_SUBPLATFORM_ULT	(0)
107#define INTEL_SUBPLATFORM_ULX	(1)
108
109/* ICL */
110#define INTEL_SUBPLATFORM_PORTF	(0)
111
112/* TGL */
113#define INTEL_SUBPLATFORM_UY	(0)
114
115/* DG2 */
116#define INTEL_SUBPLATFORM_G10	0
117#define INTEL_SUBPLATFORM_G11	1
118#define INTEL_SUBPLATFORM_G12	2
119
120/* ADL */
121#define INTEL_SUBPLATFORM_RPL	0
122
123/* ADL-P */
124/*
125 * As #define INTEL_SUBPLATFORM_RPL 0 will apply
126 * here too, SUBPLATFORM_N will have different
127 * bit set
128 */
129#define INTEL_SUBPLATFORM_N    1
130#define INTEL_SUBPLATFORM_RPLU  2
131
132/* MTL */
133#define INTEL_SUBPLATFORM_M	0
134#define INTEL_SUBPLATFORM_P	1
135
136enum intel_ppgtt_type {
137	INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,
138	INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING,
139	INTEL_PPGTT_FULL = I915_GEM_PPGTT_FULL,
140};
141
142#define DEV_INFO_FOR_EACH_FLAG(func) \
143	func(is_mobile); \
144	func(is_lp); \
145	func(require_force_probe); \
146	func(is_dgfx); \
147	/* Keep has_* in alphabetical order */ \
148	func(has_64bit_reloc); \
149	func(has_64k_pages); \
150	func(gpu_reset_clobbers_display); \
151	func(has_reset_engine); \
152	func(has_3d_pipeline); \
153	func(has_4tile); \
154	func(has_flat_ccs); \
155	func(has_global_mocs); \
156	func(has_gmd_id); \
157	func(has_gt_uc); \
158	func(has_heci_pxp); \
159	func(has_heci_gscfi); \
160	func(has_guc_deprivilege); \
161	func(has_l3_ccs_read); \
162	func(has_l3_dpf); \
163	func(has_llc); \
164	func(has_logical_ring_contexts); \
165	func(has_logical_ring_elsq); \
166	func(has_media_ratio_mode); \
167	func(has_mslice_steering); \
168	func(has_oa_bpc_reporting); \
169	func(has_oa_slice_contrib_limits); \
170	func(has_oam); \
171	func(has_one_eu_per_fuse_bit); \
172	func(has_pxp); \
173	func(has_rc6); \
174	func(has_rc6p); \
175	func(has_rps); \
176	func(has_runtime_pm); \
177	func(has_snoop); \
178	func(has_coherent_ggtt); \
179	func(tuning_thread_rr_after_dep); \
180	func(unfenced_needs_alignment); \
181	func(hws_needs_physical);
182
183struct intel_ip_version {
184	u8 ver;
185	u8 rel;
186	u8 step;
187};
188
189struct intel_runtime_info {
190	/*
191	 * Single "graphics" IP version that represents
192	 * render, compute and copy behavior.
193	 */
194	struct {
195		struct intel_ip_version ip;
196	} graphics;
197	struct {
198		struct intel_ip_version ip;
199	} media;
200
201	/*
202	 * Platform mask is used for optimizing or-ed IS_PLATFORM calls into
203	 * single runtime conditionals, and also to provide groundwork for
204	 * future per platform, or per SKU build optimizations.
205	 *
206	 * Array can be extended when necessary if the corresponding
207	 * BUILD_BUG_ON is hit.
208	 */
209	u32 platform_mask[2];
210
211	u16 device_id;
212
213	u32 rawclk_freq;
214
215	struct intel_step_info step;
216
217	unsigned int page_sizes; /* page sizes supported by the HW */
218
219	enum intel_ppgtt_type ppgtt_type;
220	unsigned int ppgtt_size; /* log2, e.g. 31/32/48 bits */
221
222	bool has_pooled_eu;
223};
224
225struct intel_device_info {
226	enum intel_platform platform;
227
228	unsigned int dma_mask_size; /* available DMA address bits */
229
230	const struct intel_gt_definition *extra_gt_list;
231
232	u8 gt; /* GT number, 0 if undefined */
233
234	intel_engine_mask_t platform_engine_mask; /* Engines supported by the HW */
235	u32 memory_regions; /* regions supported by the HW */
236
237#define DEFINE_FLAG(name) u8 name:1
238	DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
239#undef DEFINE_FLAG
240
241	/*
242	 * Initial runtime info. Do not access outside of i915_driver_create().
243	 */
244	const struct intel_runtime_info __runtime;
245
246	u32 cachelevel_to_pat[I915_MAX_CACHE_LEVEL];
247	u32 max_pat_index;
248};
249
250struct intel_driver_caps {
251	unsigned int scheduler;
252	bool has_logical_contexts:1;
253};
254
255const char *intel_platform_name(enum intel_platform platform);
256
257void intel_device_info_driver_create(struct drm_i915_private *i915, u16 device_id,
258				     const struct intel_device_info *match_info);
259void intel_device_info_runtime_init_early(struct drm_i915_private *dev_priv);
260void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
261
262void intel_device_info_print(const struct intel_device_info *info,
263			     const struct intel_runtime_info *runtime,
264			     struct drm_printer *p);
265
266void intel_driver_caps_print(const struct intel_driver_caps *caps,
267			     struct drm_printer *p);
268
269#endif
270