1// SPDX-License-Identifier: MIT 2/* 3 * Copyright © 2020 Intel Corporation 4 */ 5 6#include <linux/slab.h> /* fault-inject.h is not standalone! */ 7 8#include <linux/fault-inject.h> 9#include <linux/sched/mm.h> 10 11#include <drm/drm_cache.h> 12 13#include "gem/i915_gem_internal.h" 14#include "gem/i915_gem_lmem.h" 15#include "i915_reg.h" 16#include "i915_trace.h" 17#include "i915_utils.h" 18#include "intel_gt.h" 19#include "intel_gt_mcr.h" 20#include "intel_gt_print.h" 21#include "intel_gt_regs.h" 22#include "intel_gtt.h" 23 24 25static bool intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *i915) 26{ 27 return IS_BROXTON(i915) && i915_vtd_active(i915); 28} 29 30bool intel_vm_no_concurrent_access_wa(struct drm_i915_private *i915) 31{ 32 return IS_CHERRYVIEW(i915) || intel_ggtt_update_needs_vtd_wa(i915); 33} 34 35struct drm_i915_gem_object *alloc_pt_lmem(struct i915_address_space *vm, int sz) 36{ 37 struct drm_i915_gem_object *obj; 38 39 /* 40 * To avoid severe over-allocation when dealing with min_page_size 41 * restrictions, we override that behaviour here by allowing an object 42 * size and page layout which can be smaller. In practice this should be 43 * totally fine, since GTT paging structures are not typically inserted 44 * into the GTT. 45 * 46 * Note that we also hit this path for the scratch page, and for this 47 * case it might need to be 64K, but that should work fine here since we 48 * used the passed in size for the page size, which should ensure it 49 * also has the same alignment. 50 */ 51 obj = __i915_gem_object_create_lmem_with_ps(vm->i915, sz, sz, 52 vm->lmem_pt_obj_flags); 53 /* 54 * Ensure all paging structures for this vm share the same dma-resv 55 * object underneath, with the idea that one object_lock() will lock 56 * them all at once. 57 */ 58 if (!IS_ERR(obj)) { 59 obj->base.resv = i915_vm_resv_get(vm); 60 obj->shares_resv_from = vm; 61 } 62 63 return obj; 64} 65 66struct drm_i915_gem_object *alloc_pt_dma(struct i915_address_space *vm, int sz) 67{ 68 struct drm_i915_gem_object *obj; 69 70 if (I915_SELFTEST_ONLY(should_fail(&vm->fault_attr, 1))) 71 i915_gem_shrink_all(vm->i915); 72 73 obj = i915_gem_object_create_internal(vm->i915, sz); 74 /* 75 * Ensure all paging structures for this vm share the same dma-resv 76 * object underneath, with the idea that one object_lock() will lock 77 * them all at once. 78 */ 79 if (!IS_ERR(obj)) { 80 obj->base.resv = i915_vm_resv_get(vm); 81 obj->shares_resv_from = vm; 82 } 83 84 return obj; 85} 86 87int map_pt_dma(struct i915_address_space *vm, struct drm_i915_gem_object *obj) 88{ 89 enum i915_map_type type; 90 void *vaddr; 91 92 type = intel_gt_coherent_map_type(vm->gt, obj, true); 93 vaddr = i915_gem_object_pin_map_unlocked(obj, type); 94 if (IS_ERR(vaddr)) 95 return PTR_ERR(vaddr); 96 97 i915_gem_object_make_unshrinkable(obj); 98 return 0; 99} 100 101int map_pt_dma_locked(struct i915_address_space *vm, struct drm_i915_gem_object *obj) 102{ 103 enum i915_map_type type; 104 void *vaddr; 105 106 type = intel_gt_coherent_map_type(vm->gt, obj, true); 107 vaddr = i915_gem_object_pin_map(obj, type); 108 if (IS_ERR(vaddr)) 109 return PTR_ERR(vaddr); 110 111 i915_gem_object_make_unshrinkable(obj); 112 return 0; 113} 114 115static void clear_vm_list(struct list_head *list) 116{ 117 struct i915_vma *vma, *vn; 118 119 list_for_each_entry_safe(vma, vn, list, vm_link) { 120 struct drm_i915_gem_object *obj = vma->obj; 121 122 if (!i915_gem_object_get_rcu(obj)) { 123 /* 124 * Object is dying, but has not yet cleared its 125 * vma list. 126 * Unbind the dying vma to ensure our list 127 * is completely drained. We leave the destruction to 128 * the object destructor to avoid the vma 129 * disappearing under it. 130 */ 131 atomic_and(~I915_VMA_PIN_MASK, &vma->flags); 132 WARN_ON(__i915_vma_unbind(vma)); 133 134 /* Remove from the unbound list */ 135 list_del_init(&vma->vm_link); 136 137 /* 138 * Delay the vm and vm mutex freeing until the 139 * object is done with destruction. 140 */ 141 i915_vm_resv_get(vma->vm); 142 vma->vm_ddestroy = true; 143 } else { 144 i915_vma_destroy_locked(vma); 145 i915_gem_object_put(obj); 146 } 147 148 } 149} 150 151static void __i915_vm_close(struct i915_address_space *vm) 152{ 153 mutex_lock(&vm->mutex); 154 155 clear_vm_list(&vm->bound_list); 156 clear_vm_list(&vm->unbound_list); 157 158 /* Check for must-fix unanticipated side-effects */ 159 GEM_BUG_ON(!list_empty(&vm->bound_list)); 160 GEM_BUG_ON(!list_empty(&vm->unbound_list)); 161 162 mutex_unlock(&vm->mutex); 163} 164 165/* lock the vm into the current ww, if we lock one, we lock all */ 166int i915_vm_lock_objects(struct i915_address_space *vm, 167 struct i915_gem_ww_ctx *ww) 168{ 169 if (vm->scratch[0]->base.resv == &vm->_resv) { 170 return i915_gem_object_lock(vm->scratch[0], ww); 171 } else { 172 struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); 173 174 /* We borrowed the scratch page from ggtt, take the top level object */ 175 return i915_gem_object_lock(ppgtt->pd->pt.base, ww); 176 } 177} 178 179void i915_address_space_fini(struct i915_address_space *vm) 180{ 181 drm_mm_takedown(&vm->mm); 182} 183 184/** 185 * i915_vm_resv_release - Final struct i915_address_space destructor 186 * @kref: Pointer to the &i915_address_space.resv_ref member. 187 * 188 * This function is called when the last lock sharer no longer shares the 189 * &i915_address_space._resv lock, and also if we raced when 190 * destroying a vma by the vma destruction 191 */ 192void i915_vm_resv_release(struct kref *kref) 193{ 194 struct i915_address_space *vm = 195 container_of(kref, typeof(*vm), resv_ref); 196 197 dma_resv_fini(&vm->_resv); 198 mutex_destroy(&vm->mutex); 199 200 kfree(vm); 201} 202 203static void __i915_vm_release(struct work_struct *work) 204{ 205 struct i915_address_space *vm = 206 container_of(work, struct i915_address_space, release_work); 207 208 __i915_vm_close(vm); 209 210 /* Synchronize async unbinds. */ 211 i915_vma_resource_bind_dep_sync_all(vm); 212 213 vm->cleanup(vm); 214 i915_address_space_fini(vm); 215 216 i915_vm_resv_put(vm); 217} 218 219void i915_vm_release(struct kref *kref) 220{ 221 struct i915_address_space *vm = 222 container_of(kref, struct i915_address_space, ref); 223 224 GEM_BUG_ON(i915_is_ggtt(vm)); 225 trace_i915_ppgtt_release(vm); 226 227 queue_work(vm->i915->wq, &vm->release_work); 228} 229 230void i915_address_space_init(struct i915_address_space *vm, int subclass) 231{ 232 kref_init(&vm->ref); 233 234 /* 235 * Special case for GGTT that has already done an early 236 * kref_init here. 237 */ 238 if (!kref_read(&vm->resv_ref)) 239 kref_init(&vm->resv_ref); 240 241 vm->pending_unbind = RB_ROOT_CACHED; 242 INIT_WORK(&vm->release_work, __i915_vm_release); 243 244 /* 245 * The vm->mutex must be reclaim safe (for use in the shrinker). 246 * Do a dummy acquire now under fs_reclaim so that any allocation 247 * attempt holding the lock is immediately reported by lockdep. 248 */ 249 mutex_init(&vm->mutex); 250 lockdep_set_subclass(&vm->mutex, subclass); 251 252 if (!intel_vm_no_concurrent_access_wa(vm->i915)) { 253 i915_gem_shrinker_taints_mutex(vm->i915, &vm->mutex); 254 } else { 255 /* 256 * CHV + BXT VTD workaround use stop_machine(), 257 * which is allowed to allocate memory. This means &vm->mutex 258 * is the outer lock, and in theory we can allocate memory inside 259 * it through stop_machine(). 260 * 261 * Add the annotation for this, we use trylock in shrinker. 262 */ 263 mutex_acquire(&vm->mutex.dep_map, 0, 0, _THIS_IP_); 264 might_alloc(GFP_KERNEL); 265 mutex_release(&vm->mutex.dep_map, _THIS_IP_); 266 } 267 dma_resv_init(&vm->_resv); 268 269 GEM_BUG_ON(!vm->total); 270 drm_mm_init(&vm->mm, 0, vm->total); 271 272 memset64(vm->min_alignment, I915_GTT_MIN_ALIGNMENT, 273 ARRAY_SIZE(vm->min_alignment)); 274 275 if (HAS_64K_PAGES(vm->i915)) { 276 vm->min_alignment[INTEL_MEMORY_LOCAL] = I915_GTT_PAGE_SIZE_64K; 277 vm->min_alignment[INTEL_MEMORY_STOLEN_LOCAL] = I915_GTT_PAGE_SIZE_64K; 278 } 279 280 vm->mm.head_node.color = I915_COLOR_UNEVICTABLE; 281 282 INIT_LIST_HEAD(&vm->bound_list); 283 INIT_LIST_HEAD(&vm->unbound_list); 284} 285 286void *__px_vaddr(struct drm_i915_gem_object *p) 287{ 288 enum i915_map_type type; 289 290 GEM_BUG_ON(!i915_gem_object_has_pages(p)); 291 return page_unpack_bits(p->mm.mapping, &type); 292} 293 294dma_addr_t __px_dma(struct drm_i915_gem_object *p) 295{ 296 GEM_BUG_ON(!i915_gem_object_has_pages(p)); 297 return sg_dma_address(p->mm.pages->sgl); 298} 299 300struct page *__px_page(struct drm_i915_gem_object *p) 301{ 302 GEM_BUG_ON(!i915_gem_object_has_pages(p)); 303 return sg_page(p->mm.pages->sgl); 304} 305 306void 307fill_page_dma(struct drm_i915_gem_object *p, const u64 val, unsigned int count) 308{ 309 void *vaddr = __px_vaddr(p); 310 311 memset64(vaddr, val, count); 312 drm_clflush_virt_range(vaddr, PAGE_SIZE); 313} 314 315static void poison_scratch_page(struct drm_i915_gem_object *scratch) 316{ 317 void *vaddr = __px_vaddr(scratch); 318 u8 val; 319 320 val = 0; 321 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) 322 val = POISON_FREE; 323 324 memset(vaddr, val, scratch->base.size); 325 drm_clflush_virt_range(vaddr, scratch->base.size); 326} 327 328int setup_scratch_page(struct i915_address_space *vm) 329{ 330 unsigned long size; 331 332 /* 333 * In order to utilize 64K pages for an object with a size < 2M, we will 334 * need to support a 64K scratch page, given that every 16th entry for a 335 * page-table operating in 64K mode must point to a properly aligned 64K 336 * region, including any PTEs which happen to point to scratch. 337 * 338 * This is only relevant for the 48b PPGTT where we support 339 * huge-gtt-pages, see also i915_vma_insert(). However, as we share the 340 * scratch (read-only) between all vm, we create one 64k scratch page 341 * for all. 342 */ 343 size = I915_GTT_PAGE_SIZE_4K; 344 if (i915_vm_is_4lvl(vm) && 345 HAS_PAGE_SIZES(vm->i915, I915_GTT_PAGE_SIZE_64K) && 346 !HAS_64K_PAGES(vm->i915)) 347 size = I915_GTT_PAGE_SIZE_64K; 348 349 do { 350 struct drm_i915_gem_object *obj; 351 352 obj = vm->alloc_scratch_dma(vm, size); 353 if (IS_ERR(obj)) 354 goto skip; 355 356 if (map_pt_dma(vm, obj)) 357 goto skip_obj; 358 359 /* We need a single contiguous page for our scratch */ 360 if (obj->mm.page_sizes.sg < size) 361 goto skip_obj; 362 363 /* And it needs to be correspondingly aligned */ 364 if (__px_dma(obj) & (size - 1)) 365 goto skip_obj; 366 367 /* 368 * Use a non-zero scratch page for debugging. 369 * 370 * We want a value that should be reasonably obvious 371 * to spot in the error state, while also causing a GPU hang 372 * if executed. We prefer using a clear page in production, so 373 * should it ever be accidentally used, the effect should be 374 * fairly benign. 375 */ 376 poison_scratch_page(obj); 377 378 vm->scratch[0] = obj; 379 vm->scratch_order = get_order(size); 380 return 0; 381 382skip_obj: 383 i915_gem_object_put(obj); 384skip: 385 if (size == I915_GTT_PAGE_SIZE_4K) 386 return -ENOMEM; 387 388 size = I915_GTT_PAGE_SIZE_4K; 389 } while (1); 390} 391 392void free_scratch(struct i915_address_space *vm) 393{ 394 int i; 395 396 if (!vm->scratch[0]) 397 return; 398 399 for (i = 0; i <= vm->top; i++) 400 i915_gem_object_put(vm->scratch[i]); 401} 402 403void gtt_write_workarounds(struct intel_gt *gt) 404{ 405 struct drm_i915_private *i915 = gt->i915; 406 struct intel_uncore *uncore = gt->uncore; 407 408 /* 409 * This function is for gtt related workarounds. This function is 410 * called on driver load and after a GPU reset, so you can place 411 * workarounds here even if they get overwritten by GPU reset. 412 */ 413 /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl,icl */ 414 if (IS_BROADWELL(i915)) 415 intel_uncore_write(uncore, 416 GEN8_L3_LRA_1_GPGPU, 417 GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW); 418 else if (IS_CHERRYVIEW(i915)) 419 intel_uncore_write(uncore, 420 GEN8_L3_LRA_1_GPGPU, 421 GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV); 422 else if (IS_GEN9_LP(i915)) 423 intel_uncore_write(uncore, 424 GEN8_L3_LRA_1_GPGPU, 425 GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT); 426 else if (GRAPHICS_VER(i915) >= 9 && GRAPHICS_VER(i915) <= 11) 427 intel_uncore_write(uncore, 428 GEN8_L3_LRA_1_GPGPU, 429 GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL); 430 431 /* 432 * To support 64K PTEs we need to first enable the use of the 433 * Intermediate-Page-Size(IPS) bit of the PDE field via some magical 434 * mmio, otherwise the page-walker will simply ignore the IPS bit. This 435 * shouldn't be needed after GEN10. 436 * 437 * 64K pages were first introduced from BDW+, although technically they 438 * only *work* from gen9+. For pre-BDW we instead have the option for 439 * 32K pages, but we don't currently have any support for it in our 440 * driver. 441 */ 442 if (HAS_PAGE_SIZES(i915, I915_GTT_PAGE_SIZE_64K) && 443 GRAPHICS_VER(i915) <= 10) 444 intel_uncore_rmw(uncore, 445 GEN8_GAMW_ECO_DEV_RW_IA, 446 0, 447 GAMW_ECO_ENABLE_64K_IPS_FIELD); 448 449 if (IS_GRAPHICS_VER(i915, 8, 11)) { 450 bool can_use_gtt_cache = true; 451 452 /* 453 * According to the BSpec if we use 2M/1G pages then we also 454 * need to disable the GTT cache. At least on BDW we can see 455 * visual corruption when using 2M pages, and not disabling the 456 * GTT cache. 457 */ 458 if (HAS_PAGE_SIZES(i915, I915_GTT_PAGE_SIZE_2M)) 459 can_use_gtt_cache = false; 460 461 /* WaGttCachingOffByDefault */ 462 intel_uncore_write(uncore, 463 HSW_GTT_CACHE_EN, 464 can_use_gtt_cache ? GTT_CACHE_EN_ALL : 0); 465 gt_WARN_ON_ONCE(gt, can_use_gtt_cache && 466 intel_uncore_read(uncore, 467 HSW_GTT_CACHE_EN) == 0); 468 } 469} 470 471static void xelpmp_setup_private_ppat(struct intel_uncore *uncore) 472{ 473 intel_uncore_write(uncore, XELPMP_PAT_INDEX(0), 474 MTL_PPAT_L4_0_WB); 475 intel_uncore_write(uncore, XELPMP_PAT_INDEX(1), 476 MTL_PPAT_L4_1_WT); 477 intel_uncore_write(uncore, XELPMP_PAT_INDEX(2), 478 MTL_PPAT_L4_3_UC); 479 intel_uncore_write(uncore, XELPMP_PAT_INDEX(3), 480 MTL_PPAT_L4_0_WB | MTL_2_COH_1W); 481 intel_uncore_write(uncore, XELPMP_PAT_INDEX(4), 482 MTL_PPAT_L4_0_WB | MTL_3_COH_2W); 483 484 /* 485 * Remaining PAT entries are left at the hardware-default 486 * fully-cached setting 487 */ 488} 489 490static void xelpg_setup_private_ppat(struct intel_gt *gt) 491{ 492 intel_gt_mcr_multicast_write(gt, XEHP_PAT_INDEX(0), 493 MTL_PPAT_L4_0_WB); 494 intel_gt_mcr_multicast_write(gt, XEHP_PAT_INDEX(1), 495 MTL_PPAT_L4_1_WT); 496 intel_gt_mcr_multicast_write(gt, XEHP_PAT_INDEX(2), 497 MTL_PPAT_L4_3_UC); 498 intel_gt_mcr_multicast_write(gt, XEHP_PAT_INDEX(3), 499 MTL_PPAT_L4_0_WB | MTL_2_COH_1W); 500 intel_gt_mcr_multicast_write(gt, XEHP_PAT_INDEX(4), 501 MTL_PPAT_L4_0_WB | MTL_3_COH_2W); 502 503 /* 504 * Remaining PAT entries are left at the hardware-default 505 * fully-cached setting 506 */ 507} 508 509static void tgl_setup_private_ppat(struct intel_uncore *uncore) 510{ 511 /* TGL doesn't support LLC or AGE settings */ 512 intel_uncore_write(uncore, GEN12_PAT_INDEX(0), GEN8_PPAT_WB); 513 intel_uncore_write(uncore, GEN12_PAT_INDEX(1), GEN8_PPAT_WC); 514 intel_uncore_write(uncore, GEN12_PAT_INDEX(2), GEN8_PPAT_WT); 515 intel_uncore_write(uncore, GEN12_PAT_INDEX(3), GEN8_PPAT_UC); 516 intel_uncore_write(uncore, GEN12_PAT_INDEX(4), GEN8_PPAT_WB); 517 intel_uncore_write(uncore, GEN12_PAT_INDEX(5), GEN8_PPAT_WB); 518 intel_uncore_write(uncore, GEN12_PAT_INDEX(6), GEN8_PPAT_WB); 519 intel_uncore_write(uncore, GEN12_PAT_INDEX(7), GEN8_PPAT_WB); 520} 521 522static void xehp_setup_private_ppat(struct intel_gt *gt) 523{ 524 enum forcewake_domains fw; 525 unsigned long flags; 526 527 fw = intel_uncore_forcewake_for_reg(gt->uncore, _MMIO(XEHP_PAT_INDEX(0).reg), 528 FW_REG_WRITE); 529 intel_uncore_forcewake_get(gt->uncore, fw); 530 531 intel_gt_mcr_lock(gt, &flags); 532 intel_gt_mcr_multicast_write_fw(gt, XEHP_PAT_INDEX(0), GEN8_PPAT_WB); 533 intel_gt_mcr_multicast_write_fw(gt, XEHP_PAT_INDEX(1), GEN8_PPAT_WC); 534 intel_gt_mcr_multicast_write_fw(gt, XEHP_PAT_INDEX(2), GEN8_PPAT_WT); 535 intel_gt_mcr_multicast_write_fw(gt, XEHP_PAT_INDEX(3), GEN8_PPAT_UC); 536 intel_gt_mcr_multicast_write_fw(gt, XEHP_PAT_INDEX(4), GEN8_PPAT_WB); 537 intel_gt_mcr_multicast_write_fw(gt, XEHP_PAT_INDEX(5), GEN8_PPAT_WB); 538 intel_gt_mcr_multicast_write_fw(gt, XEHP_PAT_INDEX(6), GEN8_PPAT_WB); 539 intel_gt_mcr_multicast_write_fw(gt, XEHP_PAT_INDEX(7), GEN8_PPAT_WB); 540 intel_gt_mcr_unlock(gt, flags); 541 542 intel_uncore_forcewake_put(gt->uncore, fw); 543} 544 545static void icl_setup_private_ppat(struct intel_uncore *uncore) 546{ 547 intel_uncore_write(uncore, 548 GEN10_PAT_INDEX(0), 549 GEN8_PPAT_WB | GEN8_PPAT_LLC); 550 intel_uncore_write(uncore, 551 GEN10_PAT_INDEX(1), 552 GEN8_PPAT_WC | GEN8_PPAT_LLCELLC); 553 intel_uncore_write(uncore, 554 GEN10_PAT_INDEX(2), 555 GEN8_PPAT_WB | GEN8_PPAT_ELLC_OVERRIDE); 556 intel_uncore_write(uncore, 557 GEN10_PAT_INDEX(3), 558 GEN8_PPAT_UC); 559 intel_uncore_write(uncore, 560 GEN10_PAT_INDEX(4), 561 GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)); 562 intel_uncore_write(uncore, 563 GEN10_PAT_INDEX(5), 564 GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)); 565 intel_uncore_write(uncore, 566 GEN10_PAT_INDEX(6), 567 GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)); 568 intel_uncore_write(uncore, 569 GEN10_PAT_INDEX(7), 570 GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3)); 571} 572 573/* 574 * The GGTT and PPGTT need a private PPAT setup in order to handle cacheability 575 * bits. When using advanced contexts each context stores its own PAT, but 576 * writing this data shouldn't be harmful even in those cases. 577 */ 578static void bdw_setup_private_ppat(struct intel_uncore *uncore) 579{ 580 struct drm_i915_private *i915 = uncore->i915; 581 u64 pat; 582 583 pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */ 584 GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */ 585 GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */ 586 GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) | 587 GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) | 588 GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) | 589 GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3)); 590 591 /* for scanout with eLLC */ 592 if (GRAPHICS_VER(i915) >= 9) 593 pat |= GEN8_PPAT(2, GEN8_PPAT_WB | GEN8_PPAT_ELLC_OVERRIDE); 594 else 595 pat |= GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC); 596 597 intel_uncore_write(uncore, GEN8_PRIVATE_PAT_LO, lower_32_bits(pat)); 598 intel_uncore_write(uncore, GEN8_PRIVATE_PAT_HI, upper_32_bits(pat)); 599} 600 601static void chv_setup_private_ppat(struct intel_uncore *uncore) 602{ 603 u64 pat; 604 605 /* 606 * Map WB on BDW to snooped on CHV. 607 * 608 * Only the snoop bit has meaning for CHV, the rest is 609 * ignored. 610 * 611 * The hardware will never snoop for certain types of accesses: 612 * - CPU GTT (GMADR->GGTT->no snoop->memory) 613 * - PPGTT page tables 614 * - some other special cycles 615 * 616 * As with BDW, we also need to consider the following for GT accesses: 617 * "For GGTT, there is NO pat_sel[2:0] from the entry, 618 * so RTL will always use the value corresponding to 619 * pat_sel = 000". 620 * Which means we must set the snoop bit in PAT entry 0 621 * in order to keep the global status page working. 622 */ 623 624 pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) | 625 GEN8_PPAT(1, 0) | 626 GEN8_PPAT(2, 0) | 627 GEN8_PPAT(3, 0) | 628 GEN8_PPAT(4, CHV_PPAT_SNOOP) | 629 GEN8_PPAT(5, CHV_PPAT_SNOOP) | 630 GEN8_PPAT(6, CHV_PPAT_SNOOP) | 631 GEN8_PPAT(7, CHV_PPAT_SNOOP); 632 633 intel_uncore_write(uncore, GEN8_PRIVATE_PAT_LO, lower_32_bits(pat)); 634 intel_uncore_write(uncore, GEN8_PRIVATE_PAT_HI, upper_32_bits(pat)); 635} 636 637void setup_private_pat(struct intel_gt *gt) 638{ 639 struct intel_uncore *uncore = gt->uncore; 640 struct drm_i915_private *i915 = gt->i915; 641 642 GEM_BUG_ON(GRAPHICS_VER(i915) < 8); 643 644 if (gt->type == GT_MEDIA) { 645 xelpmp_setup_private_ppat(gt->uncore); 646 return; 647 } 648 649 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) 650 xelpg_setup_private_ppat(gt); 651 else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) 652 xehp_setup_private_ppat(gt); 653 else if (GRAPHICS_VER(i915) >= 12) 654 tgl_setup_private_ppat(uncore); 655 else if (GRAPHICS_VER(i915) >= 11) 656 icl_setup_private_ppat(uncore); 657 else if (IS_CHERRYVIEW(i915) || IS_GEN9_LP(i915)) 658 chv_setup_private_ppat(uncore); 659 else 660 bdw_setup_private_ppat(uncore); 661} 662 663struct i915_vma * 664__vm_create_scratch_for_read(struct i915_address_space *vm, unsigned long size) 665{ 666 struct drm_i915_gem_object *obj; 667 struct i915_vma *vma; 668 669 obj = i915_gem_object_create_internal(vm->i915, PAGE_ALIGN(size)); 670 if (IS_ERR(obj)) 671 return ERR_CAST(obj); 672 673 i915_gem_object_set_cache_coherency(obj, I915_CACHE_LLC); 674 675 vma = i915_vma_instance(obj, vm, NULL); 676 if (IS_ERR(vma)) { 677 i915_gem_object_put(obj); 678 return vma; 679 } 680 681 return vma; 682} 683 684struct i915_vma * 685__vm_create_scratch_for_read_pinned(struct i915_address_space *vm, unsigned long size) 686{ 687 struct i915_vma *vma; 688 int err; 689 690 vma = __vm_create_scratch_for_read(vm, size); 691 if (IS_ERR(vma)) 692 return vma; 693 694 err = i915_vma_pin(vma, 0, 0, 695 i915_vma_is_ggtt(vma) ? PIN_GLOBAL : PIN_USER); 696 if (err) { 697 i915_vma_put(vma); 698 return ERR_PTR(err); 699 } 700 701 return vma; 702} 703 704#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) 705#include "selftests/mock_gtt.c" 706#endif 707