1/* SPDX-License-Identifier: MIT */
2/*
3 * Copyright(c) 2019-2022, Intel Corporation. All rights reserved.
4 */
5#ifndef __INTEL_GSC_DEV_H__
6#define __INTEL_GSC_DEV_H__
7
8#include <linux/types.h>
9
10struct drm_i915_private;
11struct intel_gt;
12struct mei_aux_device;
13
14#define INTEL_GSC_NUM_INTERFACES 2
15/*
16 * The HECI1 bit corresponds to bit15 and HECI2 to bit14.
17 * The reason for this is to allow growth for more interfaces in the future.
18 */
19#define GSC_IRQ_INTF(_x)  BIT(15 - (_x))
20
21/**
22 * struct intel_gsc - graphics security controller
23 *
24 * @gem_obj: scratch memory GSC operations
25 * @intf : gsc interface
26 */
27struct intel_gsc {
28	struct intel_gsc_intf {
29		struct mei_aux_device *adev;
30		struct drm_i915_gem_object *gem_obj;
31		int irq;
32		unsigned int id;
33	} intf[INTEL_GSC_NUM_INTERFACES];
34};
35
36void intel_gsc_init(struct intel_gsc *gsc, struct drm_i915_private *i915);
37void intel_gsc_fini(struct intel_gsc *gsc);
38void intel_gsc_irq_handler(struct intel_gt *gt, u32 iir);
39
40#endif /* __INTEL_GSC_DEV_H__ */
41