1// SPDX-License-Identifier: MIT 2/* 3 * Copyright © 2020 Intel Corporation 4 * 5 */ 6 7#include "i915_drv.h" 8#include "i915_reg.h" 9#include "intel_de.h" 10#include "intel_display_types.h" 11#include "intel_vrr.h" 12 13bool intel_vrr_is_capable(struct intel_connector *connector) 14{ 15 const struct drm_display_info *info = &connector->base.display_info; 16 struct drm_i915_private *i915 = to_i915(connector->base.dev); 17 struct intel_dp *intel_dp; 18 19 /* 20 * DP Sink is capable of VRR video timings if 21 * Ignore MSA bit is set in DPCD. 22 * EDID monitor range also should be atleast 10 for reasonable 23 * Adaptive Sync or Variable Refresh Rate end user experience. 24 */ 25 switch (connector->base.connector_type) { 26 case DRM_MODE_CONNECTOR_eDP: 27 if (!connector->panel.vbt.vrr) 28 return false; 29 fallthrough; 30 case DRM_MODE_CONNECTOR_DisplayPort: 31 intel_dp = intel_attached_dp(connector); 32 33 if (!drm_dp_sink_can_do_video_without_timing_msa(intel_dp->dpcd)) 34 return false; 35 36 break; 37 default: 38 return false; 39 } 40 41 return HAS_VRR(i915) && 42 info->monitor_range.max_vfreq - info->monitor_range.min_vfreq > 10; 43} 44 45void 46intel_vrr_check_modeset(struct intel_atomic_state *state) 47{ 48 int i; 49 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 50 struct intel_crtc *crtc; 51 52 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 53 new_crtc_state, i) { 54 if (new_crtc_state->uapi.vrr_enabled != 55 old_crtc_state->uapi.vrr_enabled) 56 new_crtc_state->uapi.mode_changed = true; 57 } 58} 59 60/* 61 * Without VRR registers get latched at: 62 * vblank_start 63 * 64 * With VRR the earliest registers can get latched is: 65 * intel_vrr_vmin_vblank_start(), which if we want to maintain 66 * the correct min vtotal is >=vblank_start+1 67 * 68 * The latest point registers can get latched is the vmax decision boundary: 69 * intel_vrr_vmax_vblank_start() 70 * 71 * Between those two points the vblank exit starts (and hence registers get 72 * latched) ASAP after a push is sent. 73 * 74 * framestart_delay is programmable 1-4. 75 */ 76static int intel_vrr_vblank_exit_length(const struct intel_crtc_state *crtc_state) 77{ 78 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 79 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 80 81 if (DISPLAY_VER(i915) >= 13) 82 return crtc_state->vrr.guardband; 83 else 84 /* The hw imposes the extra scanline before frame start */ 85 return crtc_state->vrr.pipeline_full + crtc_state->framestart_delay + 1; 86} 87 88int intel_vrr_vmin_vblank_start(const struct intel_crtc_state *crtc_state) 89{ 90 /* Min vblank actually determined by flipline that is always >=vmin+1 */ 91 return crtc_state->vrr.vmin + 1 - intel_vrr_vblank_exit_length(crtc_state); 92} 93 94int intel_vrr_vmax_vblank_start(const struct intel_crtc_state *crtc_state) 95{ 96 return crtc_state->vrr.vmax - intel_vrr_vblank_exit_length(crtc_state); 97} 98 99void 100intel_vrr_compute_config(struct intel_crtc_state *crtc_state, 101 struct drm_connector_state *conn_state) 102{ 103 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 104 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 105 struct intel_connector *connector = 106 to_intel_connector(conn_state->connector); 107 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 108 const struct drm_display_info *info = &connector->base.display_info; 109 int vmin, vmax; 110 111 if (!intel_vrr_is_capable(connector)) 112 return; 113 114 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) 115 return; 116 117 vmin = DIV_ROUND_UP(adjusted_mode->crtc_clock * 1000, 118 adjusted_mode->crtc_htotal * info->monitor_range.max_vfreq); 119 vmax = adjusted_mode->crtc_clock * 1000 / 120 (adjusted_mode->crtc_htotal * info->monitor_range.min_vfreq); 121 122 vmin = max_t(int, vmin, adjusted_mode->crtc_vtotal); 123 vmax = max_t(int, vmax, adjusted_mode->crtc_vtotal); 124 125 if (vmin >= vmax) 126 return; 127 128 /* 129 * flipline determines the min vblank length the hardware will 130 * generate, and flipline>=vmin+1, hence we reduce vmin by one 131 * to make sure we can get the actual min vblank length. 132 */ 133 crtc_state->vrr.vmin = vmin - 1; 134 crtc_state->vrr.vmax = vmax; 135 136 crtc_state->vrr.flipline = crtc_state->vrr.vmin + 1; 137 138 /* 139 * For XE_LPD+, we use guardband and pipeline override 140 * is deprecated. 141 */ 142 if (DISPLAY_VER(i915) >= 13) { 143 crtc_state->vrr.guardband = 144 crtc_state->vrr.vmin + 1 - adjusted_mode->crtc_vblank_start; 145 } else { 146 crtc_state->vrr.pipeline_full = 147 min(255, crtc_state->vrr.vmin - adjusted_mode->crtc_vblank_start - 148 crtc_state->framestart_delay - 1); 149 } 150 151 if (crtc_state->uapi.vrr_enabled) { 152 crtc_state->vrr.enable = true; 153 crtc_state->mode_flags |= I915_MODE_FLAG_VRR; 154 } 155} 156 157static u32 trans_vrr_ctl(const struct intel_crtc_state *crtc_state) 158{ 159 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 160 161 if (DISPLAY_VER(i915) >= 13) 162 return VRR_CTL_IGN_MAX_SHIFT | VRR_CTL_FLIP_LINE_EN | 163 XELPD_VRR_CTL_VRR_GUARDBAND(crtc_state->vrr.guardband); 164 else 165 return VRR_CTL_IGN_MAX_SHIFT | VRR_CTL_FLIP_LINE_EN | 166 VRR_CTL_PIPELINE_FULL(crtc_state->vrr.pipeline_full) | 167 VRR_CTL_PIPELINE_FULL_OVERRIDE; 168} 169 170void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state) 171{ 172 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 173 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 174 175 /* 176 * TRANS_SET_CONTEXT_LATENCY with VRR enabled 177 * requires this chicken bit on ADL/DG2. 178 */ 179 if (DISPLAY_VER(dev_priv) == 13) 180 intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 181 0, PIPE_VBLANK_WITH_DELAY); 182 183 if (!crtc_state->vrr.flipline) { 184 intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), 0); 185 return; 186 } 187 188 intel_de_write(dev_priv, TRANS_VRR_VMIN(cpu_transcoder), crtc_state->vrr.vmin - 1); 189 intel_de_write(dev_priv, TRANS_VRR_VMAX(cpu_transcoder), crtc_state->vrr.vmax - 1); 190 intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), trans_vrr_ctl(crtc_state)); 191 intel_de_write(dev_priv, TRANS_VRR_FLIPLINE(cpu_transcoder), crtc_state->vrr.flipline - 1); 192} 193 194void intel_vrr_send_push(const struct intel_crtc_state *crtc_state) 195{ 196 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 197 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 198 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 199 200 if (!crtc_state->vrr.enable) 201 return; 202 203 intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder), 204 TRANS_PUSH_EN | TRANS_PUSH_SEND); 205} 206 207bool intel_vrr_is_push_sent(const struct intel_crtc_state *crtc_state) 208{ 209 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 210 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 211 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 212 213 if (!crtc_state->vrr.enable) 214 return false; 215 216 return intel_de_read(dev_priv, TRANS_PUSH(cpu_transcoder)) & TRANS_PUSH_SEND; 217} 218 219void intel_vrr_enable(const struct intel_crtc_state *crtc_state) 220{ 221 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 222 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 223 224 if (!crtc_state->vrr.enable) 225 return; 226 227 intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder), TRANS_PUSH_EN); 228 intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), 229 VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state)); 230} 231 232void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state) 233{ 234 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 235 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 236 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 237 238 if (!old_crtc_state->vrr.enable) 239 return; 240 241 intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), 242 trans_vrr_ctl(old_crtc_state)); 243 intel_de_wait_for_clear(dev_priv, TRANS_VRR_STATUS(cpu_transcoder), 244 VRR_STATUS_VRR_EN_LIVE, 1000); 245 intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder), 0); 246} 247 248void intel_vrr_get_config(struct intel_crtc_state *crtc_state) 249{ 250 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 251 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 252 u32 trans_vrr_ctl; 253 254 trans_vrr_ctl = intel_de_read(dev_priv, TRANS_VRR_CTL(cpu_transcoder)); 255 256 crtc_state->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE; 257 258 if (DISPLAY_VER(dev_priv) >= 13) 259 crtc_state->vrr.guardband = 260 REG_FIELD_GET(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, trans_vrr_ctl); 261 else 262 if (trans_vrr_ctl & VRR_CTL_PIPELINE_FULL_OVERRIDE) 263 crtc_state->vrr.pipeline_full = 264 REG_FIELD_GET(VRR_CTL_PIPELINE_FULL_MASK, trans_vrr_ctl); 265 266 if (trans_vrr_ctl & VRR_CTL_FLIP_LINE_EN) { 267 crtc_state->vrr.flipline = intel_de_read(dev_priv, TRANS_VRR_FLIPLINE(cpu_transcoder)) + 1; 268 crtc_state->vrr.vmax = intel_de_read(dev_priv, TRANS_VRR_VMAX(cpu_transcoder)) + 1; 269 crtc_state->vrr.vmin = intel_de_read(dev_priv, TRANS_VRR_VMIN(cpu_transcoder)) + 1; 270 } 271 272 if (crtc_state->vrr.enable) 273 crtc_state->mode_flags |= I915_MODE_FLAG_VRR; 274} 275