1/* 2 * Copyright 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2007 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 * DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: 26 * Eric Anholt <eric@anholt.net> 27 */ 28 29#include <linux/delay.h> 30#include <linux/export.h> 31#include <linux/i2c.h> 32#include <linux/slab.h> 33 34#include <drm/display/drm_hdmi_helper.h> 35#include <drm/drm_atomic_helper.h> 36#include <drm/drm_crtc.h> 37#include <drm/drm_edid.h> 38 39#include "i915_drv.h" 40#include "i915_reg.h" 41#include "intel_atomic.h" 42#include "intel_audio.h" 43#include "intel_connector.h" 44#include "intel_crtc.h" 45#include "intel_de.h" 46#include "intel_display_types.h" 47#include "intel_fifo_underrun.h" 48#include "intel_gmbus.h" 49#include "intel_hdmi.h" 50#include "intel_hotplug.h" 51#include "intel_panel.h" 52#include "intel_sdvo.h" 53#include "intel_sdvo_regs.h" 54 55#define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1) 56#define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1) 57#define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1) 58#define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_YPRPB0) 59 60#define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\ 61 SDVO_TV_MASK) 62 63#define IS_TV(c) (c->output_flag & SDVO_TV_MASK) 64#define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK) 65#define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK) 66#define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK)) 67#define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK)) 68 69 70static const char * const tv_format_names[] = { 71 "NTSC_M" , "NTSC_J" , "NTSC_443", 72 "PAL_B" , "PAL_D" , "PAL_G" , 73 "PAL_H" , "PAL_I" , "PAL_M" , 74 "PAL_N" , "PAL_NC" , "PAL_60" , 75 "SECAM_B" , "SECAM_D" , "SECAM_G" , 76 "SECAM_K" , "SECAM_K1", "SECAM_L" , 77 "SECAM_60" 78}; 79 80#define TV_FORMAT_NUM ARRAY_SIZE(tv_format_names) 81 82struct intel_sdvo { 83 struct intel_encoder base; 84 85 struct i2c_adapter *i2c; 86 u8 slave_addr; 87 88 struct i2c_adapter ddc; 89 90 /* Register for the SDVO device: SDVOB or SDVOC */ 91 i915_reg_t sdvo_reg; 92 93 /* Active outputs controlled by this SDVO output */ 94 u16 controlled_output; 95 96 /* 97 * Capabilities of the SDVO device returned by 98 * intel_sdvo_get_capabilities() 99 */ 100 struct intel_sdvo_caps caps; 101 102 u8 colorimetry_cap; 103 104 /* Pixel clock limitations reported by the SDVO device, in kHz */ 105 int pixel_clock_min, pixel_clock_max; 106 107 /* 108 * For multiple function SDVO device, 109 * this is for current attached outputs. 110 */ 111 u16 attached_output; 112 113 /* 114 * Hotplug activation bits for this device 115 */ 116 u16 hotplug_active; 117 118 enum port port; 119 120 /* DDC bus used by this SDVO encoder */ 121 u8 ddc_bus; 122 123 /* 124 * the sdvo flag gets lost in round trip: dtd->adjusted_mode->dtd 125 */ 126 u8 dtd_sdvo_flags; 127}; 128 129struct intel_sdvo_connector { 130 struct intel_connector base; 131 132 /* Mark the type of connector */ 133 u16 output_flag; 134 135 /* This contains all current supported TV format */ 136 u8 tv_format_supported[TV_FORMAT_NUM]; 137 int format_supported_num; 138 struct drm_property *tv_format; 139 140 /* add the property for the SDVO-TV */ 141 struct drm_property *left; 142 struct drm_property *right; 143 struct drm_property *top; 144 struct drm_property *bottom; 145 struct drm_property *hpos; 146 struct drm_property *vpos; 147 struct drm_property *contrast; 148 struct drm_property *saturation; 149 struct drm_property *hue; 150 struct drm_property *sharpness; 151 struct drm_property *flicker_filter; 152 struct drm_property *flicker_filter_adaptive; 153 struct drm_property *flicker_filter_2d; 154 struct drm_property *tv_chroma_filter; 155 struct drm_property *tv_luma_filter; 156 struct drm_property *dot_crawl; 157 158 /* add the property for the SDVO-TV/LVDS */ 159 struct drm_property *brightness; 160 161 /* this is to get the range of margin.*/ 162 u32 max_hscan, max_vscan; 163 164 /** 165 * This is set if we treat the device as HDMI, instead of DVI. 166 */ 167 bool is_hdmi; 168}; 169 170struct intel_sdvo_connector_state { 171 /* base.base: tv.saturation/contrast/hue/brightness */ 172 struct intel_digital_connector_state base; 173 174 struct { 175 unsigned overscan_h, overscan_v, hpos, vpos, sharpness; 176 unsigned flicker_filter, flicker_filter_2d, flicker_filter_adaptive; 177 unsigned chroma_filter, luma_filter, dot_crawl; 178 } tv; 179}; 180 181static struct intel_sdvo *to_sdvo(struct intel_encoder *encoder) 182{ 183 return container_of(encoder, struct intel_sdvo, base); 184} 185 186static struct intel_sdvo *intel_attached_sdvo(struct intel_connector *connector) 187{ 188 return to_sdvo(intel_attached_encoder(connector)); 189} 190 191static struct intel_sdvo_connector * 192to_intel_sdvo_connector(struct drm_connector *connector) 193{ 194 return container_of(connector, struct intel_sdvo_connector, base.base); 195} 196 197#define to_intel_sdvo_connector_state(conn_state) \ 198 container_of((conn_state), struct intel_sdvo_connector_state, base.base) 199 200static bool 201intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo); 202static bool 203intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, 204 struct intel_sdvo_connector *intel_sdvo_connector, 205 int type); 206static bool 207intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo, 208 struct intel_sdvo_connector *intel_sdvo_connector); 209 210/* 211 * Writes the SDVOB or SDVOC with the given value, but always writes both 212 * SDVOB and SDVOC to work around apparent hardware issues (according to 213 * comments in the BIOS). 214 */ 215static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val) 216{ 217 struct drm_device *dev = intel_sdvo->base.base.dev; 218 struct drm_i915_private *dev_priv = to_i915(dev); 219 u32 bval = val, cval = val; 220 int i; 221 222 if (HAS_PCH_SPLIT(dev_priv)) { 223 intel_de_write(dev_priv, intel_sdvo->sdvo_reg, val); 224 intel_de_posting_read(dev_priv, intel_sdvo->sdvo_reg); 225 /* 226 * HW workaround, need to write this twice for issue 227 * that may result in first write getting masked. 228 */ 229 if (HAS_PCH_IBX(dev_priv)) { 230 intel_de_write(dev_priv, intel_sdvo->sdvo_reg, val); 231 intel_de_posting_read(dev_priv, intel_sdvo->sdvo_reg); 232 } 233 return; 234 } 235 236 if (intel_sdvo->port == PORT_B) 237 cval = intel_de_read(dev_priv, GEN3_SDVOC); 238 else 239 bval = intel_de_read(dev_priv, GEN3_SDVOB); 240 241 /* 242 * Write the registers twice for luck. Sometimes, 243 * writing them only once doesn't appear to 'stick'. 244 * The BIOS does this too. Yay, magic 245 */ 246 for (i = 0; i < 2; i++) { 247 intel_de_write(dev_priv, GEN3_SDVOB, bval); 248 intel_de_posting_read(dev_priv, GEN3_SDVOB); 249 250 intel_de_write(dev_priv, GEN3_SDVOC, cval); 251 intel_de_posting_read(dev_priv, GEN3_SDVOC); 252 } 253} 254 255static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch) 256{ 257 struct i2c_msg msgs[] = { 258 { 259 .addr = intel_sdvo->slave_addr, 260 .flags = 0, 261 .len = 1, 262 .buf = &addr, 263 }, 264 { 265 .addr = intel_sdvo->slave_addr, 266 .flags = I2C_M_RD, 267 .len = 1, 268 .buf = ch, 269 } 270 }; 271 int ret; 272 273 if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2) 274 return true; 275 276 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret); 277 return false; 278} 279 280#define SDVO_CMD_NAME_ENTRY(cmd_) { .cmd = SDVO_CMD_ ## cmd_, .name = #cmd_ } 281 282/** Mapping of command numbers to names, for debug output */ 283static const struct { 284 u8 cmd; 285 const char *name; 286} __packed sdvo_cmd_names[] = { 287 SDVO_CMD_NAME_ENTRY(RESET), 288 SDVO_CMD_NAME_ENTRY(GET_DEVICE_CAPS), 289 SDVO_CMD_NAME_ENTRY(GET_FIRMWARE_REV), 290 SDVO_CMD_NAME_ENTRY(GET_TRAINED_INPUTS), 291 SDVO_CMD_NAME_ENTRY(GET_ACTIVE_OUTPUTS), 292 SDVO_CMD_NAME_ENTRY(SET_ACTIVE_OUTPUTS), 293 SDVO_CMD_NAME_ENTRY(GET_IN_OUT_MAP), 294 SDVO_CMD_NAME_ENTRY(SET_IN_OUT_MAP), 295 SDVO_CMD_NAME_ENTRY(GET_ATTACHED_DISPLAYS), 296 SDVO_CMD_NAME_ENTRY(GET_HOT_PLUG_SUPPORT), 297 SDVO_CMD_NAME_ENTRY(SET_ACTIVE_HOT_PLUG), 298 SDVO_CMD_NAME_ENTRY(GET_ACTIVE_HOT_PLUG), 299 SDVO_CMD_NAME_ENTRY(GET_INTERRUPT_EVENT_SOURCE), 300 SDVO_CMD_NAME_ENTRY(SET_TARGET_INPUT), 301 SDVO_CMD_NAME_ENTRY(SET_TARGET_OUTPUT), 302 SDVO_CMD_NAME_ENTRY(GET_INPUT_TIMINGS_PART1), 303 SDVO_CMD_NAME_ENTRY(GET_INPUT_TIMINGS_PART2), 304 SDVO_CMD_NAME_ENTRY(SET_INPUT_TIMINGS_PART1), 305 SDVO_CMD_NAME_ENTRY(SET_INPUT_TIMINGS_PART2), 306 SDVO_CMD_NAME_ENTRY(SET_OUTPUT_TIMINGS_PART1), 307 SDVO_CMD_NAME_ENTRY(SET_OUTPUT_TIMINGS_PART2), 308 SDVO_CMD_NAME_ENTRY(GET_OUTPUT_TIMINGS_PART1), 309 SDVO_CMD_NAME_ENTRY(GET_OUTPUT_TIMINGS_PART2), 310 SDVO_CMD_NAME_ENTRY(CREATE_PREFERRED_INPUT_TIMING), 311 SDVO_CMD_NAME_ENTRY(GET_PREFERRED_INPUT_TIMING_PART1), 312 SDVO_CMD_NAME_ENTRY(GET_PREFERRED_INPUT_TIMING_PART2), 313 SDVO_CMD_NAME_ENTRY(GET_INPUT_PIXEL_CLOCK_RANGE), 314 SDVO_CMD_NAME_ENTRY(GET_OUTPUT_PIXEL_CLOCK_RANGE), 315 SDVO_CMD_NAME_ENTRY(GET_SUPPORTED_CLOCK_RATE_MULTS), 316 SDVO_CMD_NAME_ENTRY(GET_CLOCK_RATE_MULT), 317 SDVO_CMD_NAME_ENTRY(SET_CLOCK_RATE_MULT), 318 SDVO_CMD_NAME_ENTRY(GET_SUPPORTED_TV_FORMATS), 319 SDVO_CMD_NAME_ENTRY(GET_TV_FORMAT), 320 SDVO_CMD_NAME_ENTRY(SET_TV_FORMAT), 321 SDVO_CMD_NAME_ENTRY(GET_SUPPORTED_POWER_STATES), 322 SDVO_CMD_NAME_ENTRY(GET_POWER_STATE), 323 SDVO_CMD_NAME_ENTRY(SET_ENCODER_POWER_STATE), 324 SDVO_CMD_NAME_ENTRY(SET_DISPLAY_POWER_STATE), 325 SDVO_CMD_NAME_ENTRY(SET_CONTROL_BUS_SWITCH), 326 SDVO_CMD_NAME_ENTRY(GET_SDTV_RESOLUTION_SUPPORT), 327 SDVO_CMD_NAME_ENTRY(GET_SCALED_HDTV_RESOLUTION_SUPPORT), 328 SDVO_CMD_NAME_ENTRY(GET_SUPPORTED_ENHANCEMENTS), 329 330 /* Add the op code for SDVO enhancements */ 331 SDVO_CMD_NAME_ENTRY(GET_MAX_HPOS), 332 SDVO_CMD_NAME_ENTRY(GET_HPOS), 333 SDVO_CMD_NAME_ENTRY(SET_HPOS), 334 SDVO_CMD_NAME_ENTRY(GET_MAX_VPOS), 335 SDVO_CMD_NAME_ENTRY(GET_VPOS), 336 SDVO_CMD_NAME_ENTRY(SET_VPOS), 337 SDVO_CMD_NAME_ENTRY(GET_MAX_SATURATION), 338 SDVO_CMD_NAME_ENTRY(GET_SATURATION), 339 SDVO_CMD_NAME_ENTRY(SET_SATURATION), 340 SDVO_CMD_NAME_ENTRY(GET_MAX_HUE), 341 SDVO_CMD_NAME_ENTRY(GET_HUE), 342 SDVO_CMD_NAME_ENTRY(SET_HUE), 343 SDVO_CMD_NAME_ENTRY(GET_MAX_CONTRAST), 344 SDVO_CMD_NAME_ENTRY(GET_CONTRAST), 345 SDVO_CMD_NAME_ENTRY(SET_CONTRAST), 346 SDVO_CMD_NAME_ENTRY(GET_MAX_BRIGHTNESS), 347 SDVO_CMD_NAME_ENTRY(GET_BRIGHTNESS), 348 SDVO_CMD_NAME_ENTRY(SET_BRIGHTNESS), 349 SDVO_CMD_NAME_ENTRY(GET_MAX_OVERSCAN_H), 350 SDVO_CMD_NAME_ENTRY(GET_OVERSCAN_H), 351 SDVO_CMD_NAME_ENTRY(SET_OVERSCAN_H), 352 SDVO_CMD_NAME_ENTRY(GET_MAX_OVERSCAN_V), 353 SDVO_CMD_NAME_ENTRY(GET_OVERSCAN_V), 354 SDVO_CMD_NAME_ENTRY(SET_OVERSCAN_V), 355 SDVO_CMD_NAME_ENTRY(GET_MAX_FLICKER_FILTER), 356 SDVO_CMD_NAME_ENTRY(GET_FLICKER_FILTER), 357 SDVO_CMD_NAME_ENTRY(SET_FLICKER_FILTER), 358 SDVO_CMD_NAME_ENTRY(GET_MAX_FLICKER_FILTER_ADAPTIVE), 359 SDVO_CMD_NAME_ENTRY(GET_FLICKER_FILTER_ADAPTIVE), 360 SDVO_CMD_NAME_ENTRY(SET_FLICKER_FILTER_ADAPTIVE), 361 SDVO_CMD_NAME_ENTRY(GET_MAX_FLICKER_FILTER_2D), 362 SDVO_CMD_NAME_ENTRY(GET_FLICKER_FILTER_2D), 363 SDVO_CMD_NAME_ENTRY(SET_FLICKER_FILTER_2D), 364 SDVO_CMD_NAME_ENTRY(GET_MAX_SHARPNESS), 365 SDVO_CMD_NAME_ENTRY(GET_SHARPNESS), 366 SDVO_CMD_NAME_ENTRY(SET_SHARPNESS), 367 SDVO_CMD_NAME_ENTRY(GET_DOT_CRAWL), 368 SDVO_CMD_NAME_ENTRY(SET_DOT_CRAWL), 369 SDVO_CMD_NAME_ENTRY(GET_MAX_TV_CHROMA_FILTER), 370 SDVO_CMD_NAME_ENTRY(GET_TV_CHROMA_FILTER), 371 SDVO_CMD_NAME_ENTRY(SET_TV_CHROMA_FILTER), 372 SDVO_CMD_NAME_ENTRY(GET_MAX_TV_LUMA_FILTER), 373 SDVO_CMD_NAME_ENTRY(GET_TV_LUMA_FILTER), 374 SDVO_CMD_NAME_ENTRY(SET_TV_LUMA_FILTER), 375 376 /* HDMI op code */ 377 SDVO_CMD_NAME_ENTRY(GET_SUPP_ENCODE), 378 SDVO_CMD_NAME_ENTRY(GET_ENCODE), 379 SDVO_CMD_NAME_ENTRY(SET_ENCODE), 380 SDVO_CMD_NAME_ENTRY(SET_PIXEL_REPLI), 381 SDVO_CMD_NAME_ENTRY(GET_PIXEL_REPLI), 382 SDVO_CMD_NAME_ENTRY(GET_COLORIMETRY_CAP), 383 SDVO_CMD_NAME_ENTRY(SET_COLORIMETRY), 384 SDVO_CMD_NAME_ENTRY(GET_COLORIMETRY), 385 SDVO_CMD_NAME_ENTRY(GET_AUDIO_ENCRYPT_PREFER), 386 SDVO_CMD_NAME_ENTRY(SET_AUDIO_STAT), 387 SDVO_CMD_NAME_ENTRY(GET_AUDIO_STAT), 388 SDVO_CMD_NAME_ENTRY(GET_HBUF_INDEX), 389 SDVO_CMD_NAME_ENTRY(SET_HBUF_INDEX), 390 SDVO_CMD_NAME_ENTRY(GET_HBUF_INFO), 391 SDVO_CMD_NAME_ENTRY(GET_HBUF_AV_SPLIT), 392 SDVO_CMD_NAME_ENTRY(SET_HBUF_AV_SPLIT), 393 SDVO_CMD_NAME_ENTRY(GET_HBUF_TXRATE), 394 SDVO_CMD_NAME_ENTRY(SET_HBUF_TXRATE), 395 SDVO_CMD_NAME_ENTRY(SET_HBUF_DATA), 396 SDVO_CMD_NAME_ENTRY(GET_HBUF_DATA), 397}; 398 399#undef SDVO_CMD_NAME_ENTRY 400 401static const char *sdvo_cmd_name(u8 cmd) 402{ 403 int i; 404 405 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) { 406 if (cmd == sdvo_cmd_names[i].cmd) 407 return sdvo_cmd_names[i].name; 408 } 409 410 return NULL; 411} 412 413#define SDVO_NAME(svdo) ((svdo)->port == PORT_B ? "SDVOB" : "SDVOC") 414 415static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd, 416 const void *args, int args_len) 417{ 418 struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev); 419 const char *cmd_name; 420 int i, pos = 0; 421 char buffer[64]; 422 423#define BUF_PRINT(args...) \ 424 pos += snprintf(buffer + pos, max_t(int, sizeof(buffer) - pos, 0), args) 425 426 for (i = 0; i < args_len; i++) { 427 BUF_PRINT("%02X ", ((u8 *)args)[i]); 428 } 429 for (; i < 8; i++) { 430 BUF_PRINT(" "); 431 } 432 433 cmd_name = sdvo_cmd_name(cmd); 434 if (cmd_name) 435 BUF_PRINT("(%s)", cmd_name); 436 else 437 BUF_PRINT("(%02X)", cmd); 438 439 drm_WARN_ON(&dev_priv->drm, pos >= sizeof(buffer) - 1); 440#undef BUF_PRINT 441 442 DRM_DEBUG_KMS("%s: W: %02X %s\n", SDVO_NAME(intel_sdvo), cmd, buffer); 443} 444 445static const char * const cmd_status_names[] = { 446 [SDVO_CMD_STATUS_POWER_ON] = "Power on", 447 [SDVO_CMD_STATUS_SUCCESS] = "Success", 448 [SDVO_CMD_STATUS_NOTSUPP] = "Not supported", 449 [SDVO_CMD_STATUS_INVALID_ARG] = "Invalid arg", 450 [SDVO_CMD_STATUS_PENDING] = "Pending", 451 [SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED] = "Target not specified", 452 [SDVO_CMD_STATUS_SCALING_NOT_SUPP] = "Scaling not supported", 453}; 454 455static const char *sdvo_cmd_status(u8 status) 456{ 457 if (status < ARRAY_SIZE(cmd_status_names)) 458 return cmd_status_names[status]; 459 else 460 return NULL; 461} 462 463static bool __intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd, 464 const void *args, int args_len, 465 bool unlocked) 466{ 467 u8 *buf, status; 468 struct i2c_msg *msgs; 469 int i, ret = true; 470 471 /* Would be simpler to allocate both in one go ? */ 472 buf = kzalloc(args_len * 2 + 2, GFP_KERNEL); 473 if (!buf) 474 return false; 475 476 msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL); 477 if (!msgs) { 478 kfree(buf); 479 return false; 480 } 481 482 intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len); 483 484 for (i = 0; i < args_len; i++) { 485 msgs[i].addr = intel_sdvo->slave_addr; 486 msgs[i].flags = 0; 487 msgs[i].len = 2; 488 msgs[i].buf = buf + 2 *i; 489 buf[2*i + 0] = SDVO_I2C_ARG_0 - i; 490 buf[2*i + 1] = ((u8*)args)[i]; 491 } 492 msgs[i].addr = intel_sdvo->slave_addr; 493 msgs[i].flags = 0; 494 msgs[i].len = 2; 495 msgs[i].buf = buf + 2*i; 496 buf[2*i + 0] = SDVO_I2C_OPCODE; 497 buf[2*i + 1] = cmd; 498 499 /* the following two are to read the response */ 500 status = SDVO_I2C_CMD_STATUS; 501 msgs[i+1].addr = intel_sdvo->slave_addr; 502 msgs[i+1].flags = 0; 503 msgs[i+1].len = 1; 504 msgs[i+1].buf = &status; 505 506 msgs[i+2].addr = intel_sdvo->slave_addr; 507 msgs[i+2].flags = I2C_M_RD; 508 msgs[i+2].len = 1; 509 msgs[i+2].buf = &status; 510 511 if (unlocked) 512 ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3); 513 else 514 ret = __i2c_transfer(intel_sdvo->i2c, msgs, i+3); 515 if (ret < 0) { 516 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret); 517 ret = false; 518 goto out; 519 } 520 if (ret != i+3) { 521 /* failure in I2C transfer */ 522 DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3); 523 ret = false; 524 } 525 526out: 527 kfree(msgs); 528 kfree(buf); 529 return ret; 530} 531 532static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd, 533 const void *args, int args_len) 534{ 535 return __intel_sdvo_write_cmd(intel_sdvo, cmd, args, args_len, true); 536} 537 538static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo, 539 void *response, int response_len) 540{ 541 struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev); 542 const char *cmd_status; 543 u8 retry = 15; /* 5 quick checks, followed by 10 long checks */ 544 u8 status; 545 int i, pos = 0; 546 char buffer[64]; 547 548 buffer[0] = '\0'; 549 550 /* 551 * The documentation states that all commands will be 552 * processed within 15µs, and that we need only poll 553 * the status byte a maximum of 3 times in order for the 554 * command to be complete. 555 * 556 * Check 5 times in case the hardware failed to read the docs. 557 * 558 * Also beware that the first response by many devices is to 559 * reply PENDING and stall for time. TVs are notorious for 560 * requiring longer than specified to complete their replies. 561 * Originally (in the DDX long ago), the delay was only ever 15ms 562 * with an additional delay of 30ms applied for TVs added later after 563 * many experiments. To accommodate both sets of delays, we do a 564 * sequence of slow checks if the device is falling behind and fails 565 * to reply within 5*15µs. 566 */ 567 if (!intel_sdvo_read_byte(intel_sdvo, 568 SDVO_I2C_CMD_STATUS, 569 &status)) 570 goto log_fail; 571 572 while ((status == SDVO_CMD_STATUS_PENDING || 573 status == SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED) && --retry) { 574 if (retry < 10) 575 msleep(15); 576 else 577 udelay(15); 578 579 if (!intel_sdvo_read_byte(intel_sdvo, 580 SDVO_I2C_CMD_STATUS, 581 &status)) 582 goto log_fail; 583 } 584 585#define BUF_PRINT(args...) \ 586 pos += snprintf(buffer + pos, max_t(int, sizeof(buffer) - pos, 0), args) 587 588 cmd_status = sdvo_cmd_status(status); 589 if (cmd_status) 590 BUF_PRINT("(%s)", cmd_status); 591 else 592 BUF_PRINT("(??? %d)", status); 593 594 if (status != SDVO_CMD_STATUS_SUCCESS) 595 goto log_fail; 596 597 /* Read the command response */ 598 for (i = 0; i < response_len; i++) { 599 if (!intel_sdvo_read_byte(intel_sdvo, 600 SDVO_I2C_RETURN_0 + i, 601 &((u8 *)response)[i])) 602 goto log_fail; 603 BUF_PRINT(" %02X", ((u8 *)response)[i]); 604 } 605 606 drm_WARN_ON(&dev_priv->drm, pos >= sizeof(buffer) - 1); 607#undef BUF_PRINT 608 609 DRM_DEBUG_KMS("%s: R: %s\n", SDVO_NAME(intel_sdvo), buffer); 610 return true; 611 612log_fail: 613 DRM_DEBUG_KMS("%s: R: ... failed %s\n", 614 SDVO_NAME(intel_sdvo), buffer); 615 return false; 616} 617 618static int intel_sdvo_get_pixel_multiplier(const struct drm_display_mode *adjusted_mode) 619{ 620 if (adjusted_mode->crtc_clock >= 100000) 621 return 1; 622 else if (adjusted_mode->crtc_clock >= 50000) 623 return 2; 624 else 625 return 4; 626} 627 628static bool __intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo, 629 u8 ddc_bus) 630{ 631 /* This must be the immediately preceding write before the i2c xfer */ 632 return __intel_sdvo_write_cmd(intel_sdvo, 633 SDVO_CMD_SET_CONTROL_BUS_SWITCH, 634 &ddc_bus, 1, false); 635} 636 637static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len) 638{ 639 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len)) 640 return false; 641 642 return intel_sdvo_read_response(intel_sdvo, NULL, 0); 643} 644 645static bool 646intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len) 647{ 648 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0)) 649 return false; 650 651 return intel_sdvo_read_response(intel_sdvo, value, len); 652} 653 654static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo) 655{ 656 struct intel_sdvo_set_target_input_args targets = {0}; 657 return intel_sdvo_set_value(intel_sdvo, 658 SDVO_CMD_SET_TARGET_INPUT, 659 &targets, sizeof(targets)); 660} 661 662/* 663 * Return whether each input is trained. 664 * 665 * This function is making an assumption about the layout of the response, 666 * which should be checked against the docs. 667 */ 668static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2) 669{ 670 struct intel_sdvo_get_trained_inputs_response response; 671 672 BUILD_BUG_ON(sizeof(response) != 1); 673 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS, 674 &response, sizeof(response))) 675 return false; 676 677 *input_1 = response.input0_trained; 678 *input_2 = response.input1_trained; 679 return true; 680} 681 682static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo, 683 u16 outputs) 684{ 685 return intel_sdvo_set_value(intel_sdvo, 686 SDVO_CMD_SET_ACTIVE_OUTPUTS, 687 &outputs, sizeof(outputs)); 688} 689 690static bool intel_sdvo_get_active_outputs(struct intel_sdvo *intel_sdvo, 691 u16 *outputs) 692{ 693 return intel_sdvo_get_value(intel_sdvo, 694 SDVO_CMD_GET_ACTIVE_OUTPUTS, 695 outputs, sizeof(*outputs)); 696} 697 698static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo, 699 int mode) 700{ 701 u8 state = SDVO_ENCODER_STATE_ON; 702 703 switch (mode) { 704 case DRM_MODE_DPMS_ON: 705 state = SDVO_ENCODER_STATE_ON; 706 break; 707 case DRM_MODE_DPMS_STANDBY: 708 state = SDVO_ENCODER_STATE_STANDBY; 709 break; 710 case DRM_MODE_DPMS_SUSPEND: 711 state = SDVO_ENCODER_STATE_SUSPEND; 712 break; 713 case DRM_MODE_DPMS_OFF: 714 state = SDVO_ENCODER_STATE_OFF; 715 break; 716 } 717 718 return intel_sdvo_set_value(intel_sdvo, 719 SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state)); 720} 721 722static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo, 723 int *clock_min, 724 int *clock_max) 725{ 726 struct intel_sdvo_pixel_clock_range clocks; 727 728 BUILD_BUG_ON(sizeof(clocks) != 4); 729 if (!intel_sdvo_get_value(intel_sdvo, 730 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE, 731 &clocks, sizeof(clocks))) 732 return false; 733 734 /* Convert the values from units of 10 kHz to kHz. */ 735 *clock_min = clocks.min * 10; 736 *clock_max = clocks.max * 10; 737 return true; 738} 739 740static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo, 741 u16 outputs) 742{ 743 return intel_sdvo_set_value(intel_sdvo, 744 SDVO_CMD_SET_TARGET_OUTPUT, 745 &outputs, sizeof(outputs)); 746} 747 748static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd, 749 struct intel_sdvo_dtd *dtd) 750{ 751 return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) && 752 intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2)); 753} 754 755static bool intel_sdvo_get_timing(struct intel_sdvo *intel_sdvo, u8 cmd, 756 struct intel_sdvo_dtd *dtd) 757{ 758 return intel_sdvo_get_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) && 759 intel_sdvo_get_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2)); 760} 761 762static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo, 763 struct intel_sdvo_dtd *dtd) 764{ 765 return intel_sdvo_set_timing(intel_sdvo, 766 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd); 767} 768 769static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo, 770 struct intel_sdvo_dtd *dtd) 771{ 772 return intel_sdvo_set_timing(intel_sdvo, 773 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd); 774} 775 776static bool intel_sdvo_get_input_timing(struct intel_sdvo *intel_sdvo, 777 struct intel_sdvo_dtd *dtd) 778{ 779 return intel_sdvo_get_timing(intel_sdvo, 780 SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd); 781} 782 783static bool 784intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo, 785 struct intel_sdvo_connector *intel_sdvo_connector, 786 const struct drm_display_mode *mode) 787{ 788 struct intel_sdvo_preferred_input_timing_args args; 789 790 memset(&args, 0, sizeof(args)); 791 args.clock = mode->clock / 10; 792 args.width = mode->hdisplay; 793 args.height = mode->vdisplay; 794 args.interlace = 0; 795 796 if (IS_LVDS(intel_sdvo_connector)) { 797 const struct drm_display_mode *fixed_mode = 798 intel_panel_fixed_mode(&intel_sdvo_connector->base, mode); 799 800 if (fixed_mode->hdisplay != args.width || 801 fixed_mode->vdisplay != args.height) 802 args.scaled = 1; 803 } 804 805 return intel_sdvo_set_value(intel_sdvo, 806 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING, 807 &args, sizeof(args)); 808} 809 810static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo, 811 struct intel_sdvo_dtd *dtd) 812{ 813 BUILD_BUG_ON(sizeof(dtd->part1) != 8); 814 BUILD_BUG_ON(sizeof(dtd->part2) != 8); 815 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1, 816 &dtd->part1, sizeof(dtd->part1)) && 817 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2, 818 &dtd->part2, sizeof(dtd->part2)); 819} 820 821static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val) 822{ 823 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1); 824} 825 826static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd, 827 const struct drm_display_mode *mode) 828{ 829 u16 width, height; 830 u16 h_blank_len, h_sync_len, v_blank_len, v_sync_len; 831 u16 h_sync_offset, v_sync_offset; 832 int mode_clock; 833 834 memset(dtd, 0, sizeof(*dtd)); 835 836 width = mode->hdisplay; 837 height = mode->vdisplay; 838 839 /* do some mode translations */ 840 h_blank_len = mode->htotal - mode->hdisplay; 841 h_sync_len = mode->hsync_end - mode->hsync_start; 842 843 v_blank_len = mode->vtotal - mode->vdisplay; 844 v_sync_len = mode->vsync_end - mode->vsync_start; 845 846 h_sync_offset = mode->hsync_start - mode->hdisplay; 847 v_sync_offset = mode->vsync_start - mode->vdisplay; 848 849 mode_clock = mode->clock; 850 mode_clock /= 10; 851 dtd->part1.clock = mode_clock; 852 853 dtd->part1.h_active = width & 0xff; 854 dtd->part1.h_blank = h_blank_len & 0xff; 855 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) | 856 ((h_blank_len >> 8) & 0xf); 857 dtd->part1.v_active = height & 0xff; 858 dtd->part1.v_blank = v_blank_len & 0xff; 859 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) | 860 ((v_blank_len >> 8) & 0xf); 861 862 dtd->part2.h_sync_off = h_sync_offset & 0xff; 863 dtd->part2.h_sync_width = h_sync_len & 0xff; 864 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 | 865 (v_sync_len & 0xf); 866 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) | 867 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) | 868 ((v_sync_len & 0x30) >> 4); 869 870 dtd->part2.dtd_flags = 0x18; 871 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 872 dtd->part2.dtd_flags |= DTD_FLAG_INTERLACE; 873 if (mode->flags & DRM_MODE_FLAG_PHSYNC) 874 dtd->part2.dtd_flags |= DTD_FLAG_HSYNC_POSITIVE; 875 if (mode->flags & DRM_MODE_FLAG_PVSYNC) 876 dtd->part2.dtd_flags |= DTD_FLAG_VSYNC_POSITIVE; 877 878 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0; 879} 880 881static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode *pmode, 882 const struct intel_sdvo_dtd *dtd) 883{ 884 struct drm_display_mode mode = {}; 885 886 mode.hdisplay = dtd->part1.h_active; 887 mode.hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8; 888 mode.hsync_start = mode.hdisplay + dtd->part2.h_sync_off; 889 mode.hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2; 890 mode.hsync_end = mode.hsync_start + dtd->part2.h_sync_width; 891 mode.hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4; 892 mode.htotal = mode.hdisplay + dtd->part1.h_blank; 893 mode.htotal += (dtd->part1.h_high & 0xf) << 8; 894 895 mode.vdisplay = dtd->part1.v_active; 896 mode.vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8; 897 mode.vsync_start = mode.vdisplay; 898 mode.vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf; 899 mode.vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2; 900 mode.vsync_start += dtd->part2.v_sync_off_high & 0xc0; 901 mode.vsync_end = mode.vsync_start + 902 (dtd->part2.v_sync_off_width & 0xf); 903 mode.vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4; 904 mode.vtotal = mode.vdisplay + dtd->part1.v_blank; 905 mode.vtotal += (dtd->part1.v_high & 0xf) << 8; 906 907 mode.clock = dtd->part1.clock * 10; 908 909 if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE) 910 mode.flags |= DRM_MODE_FLAG_INTERLACE; 911 if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE) 912 mode.flags |= DRM_MODE_FLAG_PHSYNC; 913 else 914 mode.flags |= DRM_MODE_FLAG_NHSYNC; 915 if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE) 916 mode.flags |= DRM_MODE_FLAG_PVSYNC; 917 else 918 mode.flags |= DRM_MODE_FLAG_NVSYNC; 919 920 drm_mode_set_crtcinfo(&mode, 0); 921 922 drm_mode_copy(pmode, &mode); 923} 924 925static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo) 926{ 927 struct intel_sdvo_encode encode; 928 929 BUILD_BUG_ON(sizeof(encode) != 2); 930 return intel_sdvo_get_value(intel_sdvo, 931 SDVO_CMD_GET_SUPP_ENCODE, 932 &encode, sizeof(encode)); 933} 934 935static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo, 936 u8 mode) 937{ 938 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1); 939} 940 941static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo, 942 u8 mode) 943{ 944 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1); 945} 946 947static bool intel_sdvo_set_pixel_replication(struct intel_sdvo *intel_sdvo, 948 u8 pixel_repeat) 949{ 950 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_PIXEL_REPLI, 951 &pixel_repeat, 1); 952} 953 954static bool intel_sdvo_set_audio_state(struct intel_sdvo *intel_sdvo, 955 u8 audio_state) 956{ 957 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_AUDIO_STAT, 958 &audio_state, 1); 959} 960 961static bool intel_sdvo_get_hbuf_size(struct intel_sdvo *intel_sdvo, 962 u8 *hbuf_size) 963{ 964 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO, 965 hbuf_size, 1)) 966 return false; 967 968 /* Buffer size is 0 based, hooray! However zero means zero. */ 969 if (*hbuf_size) 970 (*hbuf_size)++; 971 972 return true; 973} 974 975#if 0 976static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo) 977{ 978 int i, j; 979 u8 set_buf_index[2]; 980 u8 av_split; 981 u8 buf_size; 982 u8 buf[48]; 983 u8 *pos; 984 985 intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1); 986 987 for (i = 0; i <= av_split; i++) { 988 set_buf_index[0] = i; set_buf_index[1] = 0; 989 intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX, 990 set_buf_index, 2); 991 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0); 992 intel_sdvo_read_response(encoder, &buf_size, 1); 993 994 pos = buf; 995 for (j = 0; j <= buf_size; j += 8) { 996 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA, 997 NULL, 0); 998 intel_sdvo_read_response(encoder, pos, 8); 999 pos += 8; 1000 } 1001 } 1002} 1003#endif 1004 1005static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo, 1006 unsigned int if_index, u8 tx_rate, 1007 const u8 *data, unsigned int length) 1008{ 1009 u8 set_buf_index[2] = { if_index, 0 }; 1010 u8 hbuf_size, tmp[8]; 1011 int i; 1012 1013 if (!intel_sdvo_set_value(intel_sdvo, 1014 SDVO_CMD_SET_HBUF_INDEX, 1015 set_buf_index, 2)) 1016 return false; 1017 1018 if (!intel_sdvo_get_hbuf_size(intel_sdvo, &hbuf_size)) 1019 return false; 1020 1021 DRM_DEBUG_KMS("writing sdvo hbuf: %i, length %u, hbuf_size: %i\n", 1022 if_index, length, hbuf_size); 1023 1024 if (hbuf_size < length) 1025 return false; 1026 1027 for (i = 0; i < hbuf_size; i += 8) { 1028 memset(tmp, 0, 8); 1029 if (i < length) 1030 memcpy(tmp, data + i, min_t(unsigned, 8, length - i)); 1031 1032 if (!intel_sdvo_set_value(intel_sdvo, 1033 SDVO_CMD_SET_HBUF_DATA, 1034 tmp, 8)) 1035 return false; 1036 } 1037 1038 return intel_sdvo_set_value(intel_sdvo, 1039 SDVO_CMD_SET_HBUF_TXRATE, 1040 &tx_rate, 1); 1041} 1042 1043static ssize_t intel_sdvo_read_infoframe(struct intel_sdvo *intel_sdvo, 1044 unsigned int if_index, 1045 u8 *data, unsigned int length) 1046{ 1047 u8 set_buf_index[2] = { if_index, 0 }; 1048 u8 hbuf_size, tx_rate, av_split; 1049 int i; 1050 1051 if (!intel_sdvo_get_value(intel_sdvo, 1052 SDVO_CMD_GET_HBUF_AV_SPLIT, 1053 &av_split, 1)) 1054 return -ENXIO; 1055 1056 if (av_split < if_index) 1057 return 0; 1058 1059 if (!intel_sdvo_set_value(intel_sdvo, 1060 SDVO_CMD_SET_HBUF_INDEX, 1061 set_buf_index, 2)) 1062 return -ENXIO; 1063 1064 if (!intel_sdvo_get_value(intel_sdvo, 1065 SDVO_CMD_GET_HBUF_TXRATE, 1066 &tx_rate, 1)) 1067 return -ENXIO; 1068 1069 /* TX_DISABLED doesn't mean disabled for ELD */ 1070 if (if_index != SDVO_HBUF_INDEX_ELD && tx_rate == SDVO_HBUF_TX_DISABLED) 1071 return 0; 1072 1073 if (!intel_sdvo_get_hbuf_size(intel_sdvo, &hbuf_size)) 1074 return false; 1075 1076 DRM_DEBUG_KMS("reading sdvo hbuf: %i, length %u, hbuf_size: %i\n", 1077 if_index, length, hbuf_size); 1078 1079 hbuf_size = min_t(unsigned int, length, hbuf_size); 1080 1081 for (i = 0; i < hbuf_size; i += 8) { 1082 if (!intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_HBUF_DATA, NULL, 0)) 1083 return -ENXIO; 1084 if (!intel_sdvo_read_response(intel_sdvo, &data[i], 1085 min_t(unsigned int, 8, hbuf_size - i))) 1086 return -ENXIO; 1087 } 1088 1089 return hbuf_size; 1090} 1091 1092static bool intel_sdvo_compute_avi_infoframe(struct intel_sdvo *intel_sdvo, 1093 struct intel_crtc_state *crtc_state, 1094 struct drm_connector_state *conn_state) 1095{ 1096 struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev); 1097 struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi; 1098 const struct drm_display_mode *adjusted_mode = 1099 &crtc_state->hw.adjusted_mode; 1100 int ret; 1101 1102 if (!crtc_state->has_hdmi_sink) 1103 return true; 1104 1105 crtc_state->infoframes.enable |= 1106 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI); 1107 1108 ret = drm_hdmi_avi_infoframe_from_display_mode(frame, 1109 conn_state->connector, 1110 adjusted_mode); 1111 if (ret) 1112 return false; 1113 1114 drm_hdmi_avi_infoframe_quant_range(frame, 1115 conn_state->connector, 1116 adjusted_mode, 1117 crtc_state->limited_color_range ? 1118 HDMI_QUANTIZATION_RANGE_LIMITED : 1119 HDMI_QUANTIZATION_RANGE_FULL); 1120 1121 ret = hdmi_avi_infoframe_check(frame); 1122 if (drm_WARN_ON(&dev_priv->drm, ret)) 1123 return false; 1124 1125 return true; 1126} 1127 1128static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo, 1129 const struct intel_crtc_state *crtc_state) 1130{ 1131 struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev); 1132 u8 sdvo_data[HDMI_INFOFRAME_SIZE(AVI)]; 1133 const union hdmi_infoframe *frame = &crtc_state->infoframes.avi; 1134 ssize_t len; 1135 1136 if ((crtc_state->infoframes.enable & 1137 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI)) == 0) 1138 return true; 1139 1140 if (drm_WARN_ON(&dev_priv->drm, 1141 frame->any.type != HDMI_INFOFRAME_TYPE_AVI)) 1142 return false; 1143 1144 len = hdmi_infoframe_pack_only(frame, sdvo_data, sizeof(sdvo_data)); 1145 if (drm_WARN_ON(&dev_priv->drm, len < 0)) 1146 return false; 1147 1148 return intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF, 1149 SDVO_HBUF_TX_VSYNC, 1150 sdvo_data, len); 1151} 1152 1153static void intel_sdvo_get_avi_infoframe(struct intel_sdvo *intel_sdvo, 1154 struct intel_crtc_state *crtc_state) 1155{ 1156 u8 sdvo_data[HDMI_INFOFRAME_SIZE(AVI)]; 1157 union hdmi_infoframe *frame = &crtc_state->infoframes.avi; 1158 ssize_t len; 1159 int ret; 1160 1161 if (!crtc_state->has_hdmi_sink) 1162 return; 1163 1164 len = intel_sdvo_read_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF, 1165 sdvo_data, sizeof(sdvo_data)); 1166 if (len < 0) { 1167 DRM_DEBUG_KMS("failed to read AVI infoframe\n"); 1168 return; 1169 } else if (len == 0) { 1170 return; 1171 } 1172 1173 crtc_state->infoframes.enable |= 1174 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI); 1175 1176 ret = hdmi_infoframe_unpack(frame, sdvo_data, len); 1177 if (ret) { 1178 DRM_DEBUG_KMS("Failed to unpack AVI infoframe\n"); 1179 return; 1180 } 1181 1182 if (frame->any.type != HDMI_INFOFRAME_TYPE_AVI) 1183 DRM_DEBUG_KMS("Found the wrong infoframe type 0x%x (expected 0x%02x)\n", 1184 frame->any.type, HDMI_INFOFRAME_TYPE_AVI); 1185} 1186 1187static void intel_sdvo_get_eld(struct intel_sdvo *intel_sdvo, 1188 struct intel_crtc_state *crtc_state) 1189{ 1190 struct drm_i915_private *i915 = to_i915(intel_sdvo->base.base.dev); 1191 ssize_t len; 1192 u8 val; 1193 1194 if (!crtc_state->has_audio) 1195 return; 1196 1197 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_AUDIO_STAT, &val, 1)) 1198 return; 1199 1200 if ((val & SDVO_AUDIO_ELD_VALID) == 0) 1201 return; 1202 1203 len = intel_sdvo_read_infoframe(intel_sdvo, SDVO_HBUF_INDEX_ELD, 1204 crtc_state->eld, sizeof(crtc_state->eld)); 1205 if (len < 0) 1206 drm_dbg_kms(&i915->drm, "failed to read ELD\n"); 1207} 1208 1209static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo, 1210 const struct drm_connector_state *conn_state) 1211{ 1212 struct intel_sdvo_tv_format format; 1213 u32 format_map; 1214 1215 format_map = 1 << conn_state->tv.legacy_mode; 1216 memset(&format, 0, sizeof(format)); 1217 memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map))); 1218 1219 BUILD_BUG_ON(sizeof(format) != 6); 1220 return intel_sdvo_set_value(intel_sdvo, 1221 SDVO_CMD_SET_TV_FORMAT, 1222 &format, sizeof(format)); 1223} 1224 1225static bool 1226intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo, 1227 const struct drm_display_mode *mode) 1228{ 1229 struct intel_sdvo_dtd output_dtd; 1230 1231 if (!intel_sdvo_set_target_output(intel_sdvo, 1232 intel_sdvo->attached_output)) 1233 return false; 1234 1235 intel_sdvo_get_dtd_from_mode(&output_dtd, mode); 1236 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd)) 1237 return false; 1238 1239 return true; 1240} 1241 1242/* 1243 * Asks the sdvo controller for the preferred input mode given the output mode. 1244 * Unfortunately we have to set up the full output mode to do that. 1245 */ 1246static bool 1247intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo, 1248 struct intel_sdvo_connector *intel_sdvo_connector, 1249 const struct drm_display_mode *mode, 1250 struct drm_display_mode *adjusted_mode) 1251{ 1252 struct intel_sdvo_dtd input_dtd; 1253 1254 /* Reset the input timing to the screen. Assume always input 0. */ 1255 if (!intel_sdvo_set_target_input(intel_sdvo)) 1256 return false; 1257 1258 if (!intel_sdvo_create_preferred_input_timing(intel_sdvo, 1259 intel_sdvo_connector, 1260 mode)) 1261 return false; 1262 1263 if (!intel_sdvo_get_preferred_input_timing(intel_sdvo, 1264 &input_dtd)) 1265 return false; 1266 1267 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd); 1268 intel_sdvo->dtd_sdvo_flags = input_dtd.part2.sdvo_flags; 1269 1270 return true; 1271} 1272 1273static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_state *pipe_config) 1274{ 1275 struct drm_i915_private *dev_priv = to_i915(pipe_config->uapi.crtc->dev); 1276 unsigned dotclock = pipe_config->port_clock; 1277 struct dpll *clock = &pipe_config->dpll; 1278 1279 /* 1280 * SDVO TV has fixed PLL values depend on its clock range, 1281 * this mirrors vbios setting. 1282 */ 1283 if (dotclock >= 100000 && dotclock < 140500) { 1284 clock->p1 = 2; 1285 clock->p2 = 10; 1286 clock->n = 3; 1287 clock->m1 = 16; 1288 clock->m2 = 8; 1289 } else if (dotclock >= 140500 && dotclock <= 200000) { 1290 clock->p1 = 1; 1291 clock->p2 = 10; 1292 clock->n = 6; 1293 clock->m1 = 12; 1294 clock->m2 = 8; 1295 } else { 1296 drm_WARN(&dev_priv->drm, 1, 1297 "SDVO TV clock out of range: %i\n", dotclock); 1298 } 1299 1300 pipe_config->clock_set = true; 1301} 1302 1303static bool intel_has_hdmi_sink(struct intel_sdvo_connector *intel_sdvo_connector, 1304 const struct drm_connector_state *conn_state) 1305{ 1306 struct drm_connector *connector = conn_state->connector; 1307 1308 return intel_sdvo_connector->is_hdmi && 1309 connector->display_info.is_hdmi && 1310 READ_ONCE(to_intel_digital_connector_state(conn_state)->force_audio) != HDMI_AUDIO_OFF_DVI; 1311} 1312 1313static bool intel_sdvo_limited_color_range(struct intel_encoder *encoder, 1314 const struct intel_crtc_state *crtc_state, 1315 const struct drm_connector_state *conn_state) 1316{ 1317 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1318 1319 if ((intel_sdvo->colorimetry_cap & SDVO_COLORIMETRY_RGB220) == 0) 1320 return false; 1321 1322 return intel_hdmi_limited_color_range(crtc_state, conn_state); 1323} 1324 1325static bool intel_sdvo_has_audio(struct intel_encoder *encoder, 1326 const struct intel_crtc_state *crtc_state, 1327 const struct drm_connector_state *conn_state) 1328{ 1329 struct drm_connector *connector = conn_state->connector; 1330 struct intel_sdvo_connector *intel_sdvo_connector = 1331 to_intel_sdvo_connector(connector); 1332 const struct intel_digital_connector_state *intel_conn_state = 1333 to_intel_digital_connector_state(conn_state); 1334 1335 if (!crtc_state->has_hdmi_sink) 1336 return false; 1337 1338 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO) 1339 return intel_sdvo_connector->is_hdmi && 1340 connector->display_info.has_audio; 1341 else 1342 return intel_conn_state->force_audio == HDMI_AUDIO_ON; 1343} 1344 1345static int intel_sdvo_compute_config(struct intel_encoder *encoder, 1346 struct intel_crtc_state *pipe_config, 1347 struct drm_connector_state *conn_state) 1348{ 1349 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1350 struct intel_sdvo_connector *intel_sdvo_connector = 1351 to_intel_sdvo_connector(conn_state->connector); 1352 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 1353 struct drm_display_mode *mode = &pipe_config->hw.mode; 1354 1355 DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n"); 1356 pipe_config->pipe_bpp = 8*3; 1357 pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB; 1358 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 1359 1360 if (HAS_PCH_SPLIT(to_i915(encoder->base.dev))) 1361 pipe_config->has_pch_encoder = true; 1362 1363 /* 1364 * We need to construct preferred input timings based on our 1365 * output timings. To do that, we have to set the output 1366 * timings, even though this isn't really the right place in 1367 * the sequence to do it. Oh well. 1368 */ 1369 if (IS_TV(intel_sdvo_connector)) { 1370 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode)) 1371 return -EINVAL; 1372 1373 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo, 1374 intel_sdvo_connector, 1375 mode, 1376 adjusted_mode); 1377 pipe_config->sdvo_tv_clock = true; 1378 } else if (IS_LVDS(intel_sdvo_connector)) { 1379 const struct drm_display_mode *fixed_mode = 1380 intel_panel_fixed_mode(&intel_sdvo_connector->base, mode); 1381 int ret; 1382 1383 ret = intel_panel_compute_config(&intel_sdvo_connector->base, 1384 adjusted_mode); 1385 if (ret) 1386 return ret; 1387 1388 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, fixed_mode)) 1389 return -EINVAL; 1390 1391 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo, 1392 intel_sdvo_connector, 1393 mode, 1394 adjusted_mode); 1395 } 1396 1397 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 1398 return -EINVAL; 1399 1400 /* 1401 * Make the CRTC code factor in the SDVO pixel multiplier. The 1402 * SDVO device will factor out the multiplier during mode_set. 1403 */ 1404 pipe_config->pixel_multiplier = 1405 intel_sdvo_get_pixel_multiplier(adjusted_mode); 1406 1407 pipe_config->has_hdmi_sink = intel_has_hdmi_sink(intel_sdvo_connector, conn_state); 1408 1409 pipe_config->has_audio = 1410 intel_sdvo_has_audio(encoder, pipe_config, conn_state) && 1411 intel_audio_compute_config(encoder, pipe_config, conn_state); 1412 1413 pipe_config->limited_color_range = 1414 intel_sdvo_limited_color_range(encoder, pipe_config, 1415 conn_state); 1416 1417 /* Clock computation needs to happen after pixel multiplier. */ 1418 if (IS_TV(intel_sdvo_connector)) 1419 i9xx_adjust_sdvo_tv_clock(pipe_config); 1420 1421 if (conn_state->picture_aspect_ratio) 1422 adjusted_mode->picture_aspect_ratio = 1423 conn_state->picture_aspect_ratio; 1424 1425 if (!intel_sdvo_compute_avi_infoframe(intel_sdvo, 1426 pipe_config, conn_state)) { 1427 DRM_DEBUG_KMS("bad AVI infoframe\n"); 1428 return -EINVAL; 1429 } 1430 1431 return 0; 1432} 1433 1434#define UPDATE_PROPERTY(input, NAME) \ 1435 do { \ 1436 val = input; \ 1437 intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_##NAME, &val, sizeof(val)); \ 1438 } while (0) 1439 1440static void intel_sdvo_update_props(struct intel_sdvo *intel_sdvo, 1441 const struct intel_sdvo_connector_state *sdvo_state) 1442{ 1443 const struct drm_connector_state *conn_state = &sdvo_state->base.base; 1444 struct intel_sdvo_connector *intel_sdvo_conn = 1445 to_intel_sdvo_connector(conn_state->connector); 1446 u16 val; 1447 1448 if (intel_sdvo_conn->left) 1449 UPDATE_PROPERTY(sdvo_state->tv.overscan_h, OVERSCAN_H); 1450 1451 if (intel_sdvo_conn->top) 1452 UPDATE_PROPERTY(sdvo_state->tv.overscan_v, OVERSCAN_V); 1453 1454 if (intel_sdvo_conn->hpos) 1455 UPDATE_PROPERTY(sdvo_state->tv.hpos, HPOS); 1456 1457 if (intel_sdvo_conn->vpos) 1458 UPDATE_PROPERTY(sdvo_state->tv.vpos, VPOS); 1459 1460 if (intel_sdvo_conn->saturation) 1461 UPDATE_PROPERTY(conn_state->tv.saturation, SATURATION); 1462 1463 if (intel_sdvo_conn->contrast) 1464 UPDATE_PROPERTY(conn_state->tv.contrast, CONTRAST); 1465 1466 if (intel_sdvo_conn->hue) 1467 UPDATE_PROPERTY(conn_state->tv.hue, HUE); 1468 1469 if (intel_sdvo_conn->brightness) 1470 UPDATE_PROPERTY(conn_state->tv.brightness, BRIGHTNESS); 1471 1472 if (intel_sdvo_conn->sharpness) 1473 UPDATE_PROPERTY(sdvo_state->tv.sharpness, SHARPNESS); 1474 1475 if (intel_sdvo_conn->flicker_filter) 1476 UPDATE_PROPERTY(sdvo_state->tv.flicker_filter, FLICKER_FILTER); 1477 1478 if (intel_sdvo_conn->flicker_filter_2d) 1479 UPDATE_PROPERTY(sdvo_state->tv.flicker_filter_2d, FLICKER_FILTER_2D); 1480 1481 if (intel_sdvo_conn->flicker_filter_adaptive) 1482 UPDATE_PROPERTY(sdvo_state->tv.flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE); 1483 1484 if (intel_sdvo_conn->tv_chroma_filter) 1485 UPDATE_PROPERTY(sdvo_state->tv.chroma_filter, TV_CHROMA_FILTER); 1486 1487 if (intel_sdvo_conn->tv_luma_filter) 1488 UPDATE_PROPERTY(sdvo_state->tv.luma_filter, TV_LUMA_FILTER); 1489 1490 if (intel_sdvo_conn->dot_crawl) 1491 UPDATE_PROPERTY(sdvo_state->tv.dot_crawl, DOT_CRAWL); 1492 1493#undef UPDATE_PROPERTY 1494} 1495 1496static void intel_sdvo_pre_enable(struct intel_atomic_state *state, 1497 struct intel_encoder *intel_encoder, 1498 const struct intel_crtc_state *crtc_state, 1499 const struct drm_connector_state *conn_state) 1500{ 1501 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); 1502 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1503 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 1504 const struct intel_sdvo_connector_state *sdvo_state = 1505 to_intel_sdvo_connector_state(conn_state); 1506 struct intel_sdvo_connector *intel_sdvo_connector = 1507 to_intel_sdvo_connector(conn_state->connector); 1508 const struct drm_display_mode *mode = &crtc_state->hw.mode; 1509 struct intel_sdvo *intel_sdvo = to_sdvo(intel_encoder); 1510 u32 sdvox; 1511 struct intel_sdvo_in_out_map in_out; 1512 struct intel_sdvo_dtd input_dtd, output_dtd; 1513 int rate; 1514 1515 intel_sdvo_update_props(intel_sdvo, sdvo_state); 1516 1517 /* 1518 * First, set the input mapping for the first input to our controlled 1519 * output. This is only correct if we're a single-input device, in 1520 * which case the first input is the output from the appropriate SDVO 1521 * channel on the motherboard. In a two-input device, the first input 1522 * will be SDVOB and the second SDVOC. 1523 */ 1524 in_out.in0 = intel_sdvo->attached_output; 1525 in_out.in1 = 0; 1526 1527 intel_sdvo_set_value(intel_sdvo, 1528 SDVO_CMD_SET_IN_OUT_MAP, 1529 &in_out, sizeof(in_out)); 1530 1531 /* Set the output timings to the screen */ 1532 if (!intel_sdvo_set_target_output(intel_sdvo, 1533 intel_sdvo->attached_output)) 1534 return; 1535 1536 /* lvds has a special fixed output timing. */ 1537 if (IS_LVDS(intel_sdvo_connector)) { 1538 const struct drm_display_mode *fixed_mode = 1539 intel_panel_fixed_mode(&intel_sdvo_connector->base, mode); 1540 1541 intel_sdvo_get_dtd_from_mode(&output_dtd, fixed_mode); 1542 } else { 1543 intel_sdvo_get_dtd_from_mode(&output_dtd, mode); 1544 } 1545 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd)) 1546 drm_info(&dev_priv->drm, 1547 "Setting output timings on %s failed\n", 1548 SDVO_NAME(intel_sdvo)); 1549 1550 /* Set the input timing to the screen. Assume always input 0. */ 1551 if (!intel_sdvo_set_target_input(intel_sdvo)) 1552 return; 1553 1554 if (crtc_state->has_hdmi_sink) { 1555 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI); 1556 intel_sdvo_set_colorimetry(intel_sdvo, 1557 crtc_state->limited_color_range ? 1558 SDVO_COLORIMETRY_RGB220 : 1559 SDVO_COLORIMETRY_RGB256); 1560 intel_sdvo_set_avi_infoframe(intel_sdvo, crtc_state); 1561 intel_sdvo_set_pixel_replication(intel_sdvo, 1562 !!(adjusted_mode->flags & 1563 DRM_MODE_FLAG_DBLCLK)); 1564 } else 1565 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI); 1566 1567 if (IS_TV(intel_sdvo_connector) && 1568 !intel_sdvo_set_tv_format(intel_sdvo, conn_state)) 1569 return; 1570 1571 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode); 1572 1573 if (IS_TV(intel_sdvo_connector) || IS_LVDS(intel_sdvo_connector)) 1574 input_dtd.part2.sdvo_flags = intel_sdvo->dtd_sdvo_flags; 1575 if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd)) 1576 drm_info(&dev_priv->drm, 1577 "Setting input timings on %s failed\n", 1578 SDVO_NAME(intel_sdvo)); 1579 1580 switch (crtc_state->pixel_multiplier) { 1581 default: 1582 drm_WARN(&dev_priv->drm, 1, 1583 "unknown pixel multiplier specified\n"); 1584 fallthrough; 1585 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break; 1586 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break; 1587 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break; 1588 } 1589 if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate)) 1590 return; 1591 1592 /* Set the SDVO control regs. */ 1593 if (DISPLAY_VER(dev_priv) >= 4) { 1594 /* The real mode polarity is set by the SDVO commands, using 1595 * struct intel_sdvo_dtd. */ 1596 sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH; 1597 if (DISPLAY_VER(dev_priv) < 5) 1598 sdvox |= SDVO_BORDER_ENABLE; 1599 } else { 1600 sdvox = intel_de_read(dev_priv, intel_sdvo->sdvo_reg); 1601 if (intel_sdvo->port == PORT_B) 1602 sdvox &= SDVOB_PRESERVE_MASK; 1603 else 1604 sdvox &= SDVOC_PRESERVE_MASK; 1605 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE; 1606 } 1607 1608 if (HAS_PCH_CPT(dev_priv)) 1609 sdvox |= SDVO_PIPE_SEL_CPT(crtc->pipe); 1610 else 1611 sdvox |= SDVO_PIPE_SEL(crtc->pipe); 1612 1613 if (DISPLAY_VER(dev_priv) >= 4) { 1614 /* done in crtc_mode_set as the dpll_md reg must be written early */ 1615 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || 1616 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) { 1617 /* done in crtc_mode_set as it lives inside the dpll register */ 1618 } else { 1619 sdvox |= (crtc_state->pixel_multiplier - 1) 1620 << SDVO_PORT_MULTIPLY_SHIFT; 1621 } 1622 1623 if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL && 1624 DISPLAY_VER(dev_priv) < 5) 1625 sdvox |= SDVO_STALL_SELECT; 1626 intel_sdvo_write_sdvox(intel_sdvo, sdvox); 1627} 1628 1629static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector) 1630{ 1631 struct intel_sdvo_connector *intel_sdvo_connector = 1632 to_intel_sdvo_connector(&connector->base); 1633 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 1634 u16 active_outputs = 0; 1635 1636 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs); 1637 1638 return active_outputs & intel_sdvo_connector->output_flag; 1639} 1640 1641bool intel_sdvo_port_enabled(struct drm_i915_private *dev_priv, 1642 i915_reg_t sdvo_reg, enum pipe *pipe) 1643{ 1644 u32 val; 1645 1646 val = intel_de_read(dev_priv, sdvo_reg); 1647 1648 /* asserts want to know the pipe even if the port is disabled */ 1649 if (HAS_PCH_CPT(dev_priv)) 1650 *pipe = (val & SDVO_PIPE_SEL_MASK_CPT) >> SDVO_PIPE_SEL_SHIFT_CPT; 1651 else if (IS_CHERRYVIEW(dev_priv)) 1652 *pipe = (val & SDVO_PIPE_SEL_MASK_CHV) >> SDVO_PIPE_SEL_SHIFT_CHV; 1653 else 1654 *pipe = (val & SDVO_PIPE_SEL_MASK) >> SDVO_PIPE_SEL_SHIFT; 1655 1656 return val & SDVO_ENABLE; 1657} 1658 1659static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder, 1660 enum pipe *pipe) 1661{ 1662 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1663 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1664 u16 active_outputs = 0; 1665 bool ret; 1666 1667 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs); 1668 1669 ret = intel_sdvo_port_enabled(dev_priv, intel_sdvo->sdvo_reg, pipe); 1670 1671 return ret || active_outputs; 1672} 1673 1674static void intel_sdvo_get_config(struct intel_encoder *encoder, 1675 struct intel_crtc_state *pipe_config) 1676{ 1677 struct drm_device *dev = encoder->base.dev; 1678 struct drm_i915_private *dev_priv = to_i915(dev); 1679 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1680 struct intel_sdvo_dtd dtd; 1681 int encoder_pixel_multiplier = 0; 1682 int dotclock; 1683 u32 flags = 0, sdvox; 1684 u8 val; 1685 bool ret; 1686 1687 pipe_config->output_types |= BIT(INTEL_OUTPUT_SDVO); 1688 1689 sdvox = intel_de_read(dev_priv, intel_sdvo->sdvo_reg); 1690 1691 ret = intel_sdvo_get_input_timing(intel_sdvo, &dtd); 1692 if (!ret) { 1693 /* 1694 * Some sdvo encoders are not spec compliant and don't 1695 * implement the mandatory get_timings function. 1696 */ 1697 drm_dbg(&dev_priv->drm, "failed to retrieve SDVO DTD\n"); 1698 pipe_config->quirks |= PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS; 1699 } else { 1700 if (dtd.part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE) 1701 flags |= DRM_MODE_FLAG_PHSYNC; 1702 else 1703 flags |= DRM_MODE_FLAG_NHSYNC; 1704 1705 if (dtd.part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE) 1706 flags |= DRM_MODE_FLAG_PVSYNC; 1707 else 1708 flags |= DRM_MODE_FLAG_NVSYNC; 1709 } 1710 1711 pipe_config->hw.adjusted_mode.flags |= flags; 1712 1713 /* 1714 * pixel multiplier readout is tricky: Only on i915g/gm it is stored in 1715 * the sdvo port register, on all other platforms it is part of the dpll 1716 * state. Since the general pipe state readout happens before the 1717 * encoder->get_config we so already have a valid pixel multplier on all 1718 * other platfroms. 1719 */ 1720 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) { 1721 pipe_config->pixel_multiplier = 1722 ((sdvox & SDVO_PORT_MULTIPLY_MASK) 1723 >> SDVO_PORT_MULTIPLY_SHIFT) + 1; 1724 } 1725 1726 dotclock = pipe_config->port_clock; 1727 1728 if (pipe_config->pixel_multiplier) 1729 dotclock /= pipe_config->pixel_multiplier; 1730 1731 pipe_config->hw.adjusted_mode.crtc_clock = dotclock; 1732 1733 /* Cross check the port pixel multiplier with the sdvo encoder state. */ 1734 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT, 1735 &val, 1)) { 1736 switch (val) { 1737 case SDVO_CLOCK_RATE_MULT_1X: 1738 encoder_pixel_multiplier = 1; 1739 break; 1740 case SDVO_CLOCK_RATE_MULT_2X: 1741 encoder_pixel_multiplier = 2; 1742 break; 1743 case SDVO_CLOCK_RATE_MULT_4X: 1744 encoder_pixel_multiplier = 4; 1745 break; 1746 } 1747 } 1748 1749 drm_WARN(dev, 1750 encoder_pixel_multiplier != pipe_config->pixel_multiplier, 1751 "SDVO pixel multiplier mismatch, port: %i, encoder: %i\n", 1752 pipe_config->pixel_multiplier, encoder_pixel_multiplier); 1753 1754 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_COLORIMETRY, 1755 &val, 1)) { 1756 if (val == SDVO_COLORIMETRY_RGB220) 1757 pipe_config->limited_color_range = true; 1758 } 1759 1760 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_AUDIO_STAT, 1761 &val, 1)) { 1762 if (val & SDVO_AUDIO_PRESENCE_DETECT) 1763 pipe_config->has_audio = true; 1764 } 1765 1766 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ENCODE, 1767 &val, 1)) { 1768 if (val == SDVO_ENCODE_HDMI) 1769 pipe_config->has_hdmi_sink = true; 1770 } 1771 1772 intel_sdvo_get_avi_infoframe(intel_sdvo, pipe_config); 1773 1774 intel_sdvo_get_eld(intel_sdvo, pipe_config); 1775} 1776 1777static void intel_sdvo_disable_audio(struct intel_sdvo *intel_sdvo) 1778{ 1779 intel_sdvo_set_audio_state(intel_sdvo, 0); 1780} 1781 1782static void intel_sdvo_enable_audio(struct intel_sdvo *intel_sdvo, 1783 const struct intel_crtc_state *crtc_state, 1784 const struct drm_connector_state *conn_state) 1785{ 1786 const u8 *eld = crtc_state->eld; 1787 1788 intel_sdvo_set_audio_state(intel_sdvo, 0); 1789 1790 intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_ELD, 1791 SDVO_HBUF_TX_DISABLED, 1792 eld, drm_eld_size(eld)); 1793 1794 intel_sdvo_set_audio_state(intel_sdvo, SDVO_AUDIO_ELD_VALID | 1795 SDVO_AUDIO_PRESENCE_DETECT); 1796} 1797 1798static void intel_disable_sdvo(struct intel_atomic_state *state, 1799 struct intel_encoder *encoder, 1800 const struct intel_crtc_state *old_crtc_state, 1801 const struct drm_connector_state *conn_state) 1802{ 1803 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1804 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1805 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 1806 u32 temp; 1807 1808 if (old_crtc_state->has_audio) 1809 intel_sdvo_disable_audio(intel_sdvo); 1810 1811 intel_sdvo_set_active_outputs(intel_sdvo, 0); 1812 if (0) 1813 intel_sdvo_set_encoder_power_state(intel_sdvo, 1814 DRM_MODE_DPMS_OFF); 1815 1816 temp = intel_de_read(dev_priv, intel_sdvo->sdvo_reg); 1817 1818 temp &= ~SDVO_ENABLE; 1819 intel_sdvo_write_sdvox(intel_sdvo, temp); 1820 1821 /* 1822 * HW workaround for IBX, we need to move the port 1823 * to transcoder A after disabling it to allow the 1824 * matching DP port to be enabled on transcoder A. 1825 */ 1826 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) { 1827 /* 1828 * We get CPU/PCH FIFO underruns on the other pipe when 1829 * doing the workaround. Sweep them under the rug. 1830 */ 1831 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); 1832 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); 1833 1834 temp &= ~SDVO_PIPE_SEL_MASK; 1835 temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A); 1836 intel_sdvo_write_sdvox(intel_sdvo, temp); 1837 1838 temp &= ~SDVO_ENABLE; 1839 intel_sdvo_write_sdvox(intel_sdvo, temp); 1840 1841 intel_wait_for_vblank_if_active(dev_priv, PIPE_A); 1842 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); 1843 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); 1844 } 1845} 1846 1847static void pch_disable_sdvo(struct intel_atomic_state *state, 1848 struct intel_encoder *encoder, 1849 const struct intel_crtc_state *old_crtc_state, 1850 const struct drm_connector_state *old_conn_state) 1851{ 1852} 1853 1854static void pch_post_disable_sdvo(struct intel_atomic_state *state, 1855 struct intel_encoder *encoder, 1856 const struct intel_crtc_state *old_crtc_state, 1857 const struct drm_connector_state *old_conn_state) 1858{ 1859 intel_disable_sdvo(state, encoder, old_crtc_state, old_conn_state); 1860} 1861 1862static void intel_enable_sdvo(struct intel_atomic_state *state, 1863 struct intel_encoder *encoder, 1864 const struct intel_crtc_state *pipe_config, 1865 const struct drm_connector_state *conn_state) 1866{ 1867 struct drm_device *dev = encoder->base.dev; 1868 struct drm_i915_private *dev_priv = to_i915(dev); 1869 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1870 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 1871 u32 temp; 1872 bool input1, input2; 1873 int i; 1874 bool success; 1875 1876 temp = intel_de_read(dev_priv, intel_sdvo->sdvo_reg); 1877 temp |= SDVO_ENABLE; 1878 intel_sdvo_write_sdvox(intel_sdvo, temp); 1879 1880 for (i = 0; i < 2; i++) 1881 intel_crtc_wait_for_next_vblank(crtc); 1882 1883 success = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2); 1884 /* 1885 * Warn if the device reported failure to sync. 1886 * 1887 * A lot of SDVO devices fail to notify of sync, but it's 1888 * a given it the status is a success, we succeeded. 1889 */ 1890 if (success && !input1) { 1891 drm_dbg_kms(&dev_priv->drm, 1892 "First %s output reported failure to " 1893 "sync\n", SDVO_NAME(intel_sdvo)); 1894 } 1895 1896 if (0) 1897 intel_sdvo_set_encoder_power_state(intel_sdvo, 1898 DRM_MODE_DPMS_ON); 1899 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output); 1900 1901 if (pipe_config->has_audio) 1902 intel_sdvo_enable_audio(intel_sdvo, pipe_config, conn_state); 1903} 1904 1905static enum drm_mode_status 1906intel_sdvo_mode_valid(struct drm_connector *connector, 1907 struct drm_display_mode *mode) 1908{ 1909 struct drm_i915_private *i915 = to_i915(connector->dev); 1910 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(to_intel_connector(connector)); 1911 struct intel_sdvo_connector *intel_sdvo_connector = 1912 to_intel_sdvo_connector(connector); 1913 bool has_hdmi_sink = intel_has_hdmi_sink(intel_sdvo_connector, connector->state); 1914 int max_dotclk = i915->max_dotclk_freq; 1915 enum drm_mode_status status; 1916 int clock = mode->clock; 1917 1918 status = intel_cpu_transcoder_mode_valid(i915, mode); 1919 if (status != MODE_OK) 1920 return status; 1921 1922 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 1923 return MODE_NO_DBLESCAN; 1924 1925 if (clock > max_dotclk) 1926 return MODE_CLOCK_HIGH; 1927 1928 if (mode->flags & DRM_MODE_FLAG_DBLCLK) { 1929 if (!has_hdmi_sink) 1930 return MODE_CLOCK_LOW; 1931 clock *= 2; 1932 } 1933 1934 if (intel_sdvo->pixel_clock_min > clock) 1935 return MODE_CLOCK_LOW; 1936 1937 if (intel_sdvo->pixel_clock_max < clock) 1938 return MODE_CLOCK_HIGH; 1939 1940 if (IS_LVDS(intel_sdvo_connector)) { 1941 enum drm_mode_status status; 1942 1943 status = intel_panel_mode_valid(&intel_sdvo_connector->base, mode); 1944 if (status != MODE_OK) 1945 return status; 1946 } 1947 1948 return MODE_OK; 1949} 1950 1951static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps) 1952{ 1953 BUILD_BUG_ON(sizeof(*caps) != 8); 1954 if (!intel_sdvo_get_value(intel_sdvo, 1955 SDVO_CMD_GET_DEVICE_CAPS, 1956 caps, sizeof(*caps))) 1957 return false; 1958 1959 DRM_DEBUG_KMS("SDVO capabilities:\n" 1960 " vendor_id: %d\n" 1961 " device_id: %d\n" 1962 " device_rev_id: %d\n" 1963 " sdvo_version_major: %d\n" 1964 " sdvo_version_minor: %d\n" 1965 " sdvo_inputs_mask: %d\n" 1966 " smooth_scaling: %d\n" 1967 " sharp_scaling: %d\n" 1968 " up_scaling: %d\n" 1969 " down_scaling: %d\n" 1970 " stall_support: %d\n" 1971 " output_flags: %d\n", 1972 caps->vendor_id, 1973 caps->device_id, 1974 caps->device_rev_id, 1975 caps->sdvo_version_major, 1976 caps->sdvo_version_minor, 1977 caps->sdvo_inputs_mask, 1978 caps->smooth_scaling, 1979 caps->sharp_scaling, 1980 caps->up_scaling, 1981 caps->down_scaling, 1982 caps->stall_support, 1983 caps->output_flags); 1984 1985 return true; 1986} 1987 1988static u8 intel_sdvo_get_colorimetry_cap(struct intel_sdvo *intel_sdvo) 1989{ 1990 u8 cap; 1991 1992 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_COLORIMETRY_CAP, 1993 &cap, sizeof(cap))) 1994 return SDVO_COLORIMETRY_RGB256; 1995 1996 return cap; 1997} 1998 1999static u16 intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo) 2000{ 2001 struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev); 2002 u16 hotplug; 2003 2004 if (!I915_HAS_HOTPLUG(dev_priv)) 2005 return 0; 2006 2007 /* 2008 * HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise 2009 * on the line. 2010 */ 2011 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) 2012 return 0; 2013 2014 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT, 2015 &hotplug, sizeof(hotplug))) 2016 return 0; 2017 2018 return hotplug; 2019} 2020 2021static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder) 2022{ 2023 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 2024 2025 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, 2026 &intel_sdvo->hotplug_active, 2); 2027} 2028 2029static enum intel_hotplug_state 2030intel_sdvo_hotplug(struct intel_encoder *encoder, 2031 struct intel_connector *connector) 2032{ 2033 intel_sdvo_enable_hotplug(encoder); 2034 2035 return intel_encoder_hotplug(encoder, connector); 2036} 2037 2038static bool 2039intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo) 2040{ 2041 /* Is there more than one type of output? */ 2042 return hweight16(intel_sdvo->caps.output_flags) > 1; 2043} 2044 2045static const struct drm_edid * 2046intel_sdvo_get_edid(struct drm_connector *connector) 2047{ 2048 struct intel_sdvo *sdvo = intel_attached_sdvo(to_intel_connector(connector)); 2049 return drm_edid_read_ddc(connector, &sdvo->ddc); 2050} 2051 2052/* Mac mini hack -- use the same DDC as the analog connector */ 2053static const struct drm_edid * 2054intel_sdvo_get_analog_edid(struct drm_connector *connector) 2055{ 2056 struct drm_i915_private *i915 = to_i915(connector->dev); 2057 struct i2c_adapter *i2c; 2058 2059 i2c = intel_gmbus_get_adapter(i915, i915->display.vbt.crt_ddc_pin); 2060 2061 return drm_edid_read_ddc(connector, i2c); 2062} 2063 2064static enum drm_connector_status 2065intel_sdvo_tmds_sink_detect(struct drm_connector *connector) 2066{ 2067 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(to_intel_connector(connector)); 2068 enum drm_connector_status status; 2069 const struct drm_edid *drm_edid; 2070 2071 drm_edid = intel_sdvo_get_edid(connector); 2072 2073 if (!drm_edid && intel_sdvo_multifunc_encoder(intel_sdvo)) { 2074 u8 ddc, saved_ddc = intel_sdvo->ddc_bus; 2075 2076 /* 2077 * Don't use the 1 as the argument of DDC bus switch to get 2078 * the EDID. It is used for SDVO SPD ROM. 2079 */ 2080 for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) { 2081 intel_sdvo->ddc_bus = ddc; 2082 drm_edid = intel_sdvo_get_edid(connector); 2083 if (drm_edid) 2084 break; 2085 } 2086 /* 2087 * If we found the EDID on the other bus, 2088 * assume that is the correct DDC bus. 2089 */ 2090 if (!drm_edid) 2091 intel_sdvo->ddc_bus = saved_ddc; 2092 } 2093 2094 /* 2095 * When there is no edid and no monitor is connected with VGA 2096 * port, try to use the CRT ddc to read the EDID for DVI-connector. 2097 */ 2098 if (!drm_edid) 2099 drm_edid = intel_sdvo_get_analog_edid(connector); 2100 2101 status = connector_status_unknown; 2102 if (drm_edid) { 2103 const struct edid *edid = drm_edid_raw(drm_edid); 2104 2105 /* DDC bus is shared, match EDID to connector type */ 2106 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) 2107 status = connector_status_connected; 2108 else 2109 status = connector_status_disconnected; 2110 drm_edid_free(drm_edid); 2111 } 2112 2113 return status; 2114} 2115 2116static bool 2117intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo, 2118 const struct drm_edid *drm_edid) 2119{ 2120 const struct edid *edid = drm_edid_raw(drm_edid); 2121 bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL); 2122 bool connector_is_digital = !!IS_DIGITAL(sdvo); 2123 2124 DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n", 2125 connector_is_digital, monitor_is_digital); 2126 return connector_is_digital == monitor_is_digital; 2127} 2128 2129static enum drm_connector_status 2130intel_sdvo_detect(struct drm_connector *connector, bool force) 2131{ 2132 struct drm_i915_private *i915 = to_i915(connector->dev); 2133 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(to_intel_connector(connector)); 2134 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 2135 enum drm_connector_status ret; 2136 u16 response; 2137 2138 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 2139 connector->base.id, connector->name); 2140 2141 if (!INTEL_DISPLAY_ENABLED(i915)) 2142 return connector_status_disconnected; 2143 2144 if (!intel_sdvo_get_value(intel_sdvo, 2145 SDVO_CMD_GET_ATTACHED_DISPLAYS, 2146 &response, 2)) 2147 return connector_status_unknown; 2148 2149 DRM_DEBUG_KMS("SDVO response %d %d [%x]\n", 2150 response & 0xff, response >> 8, 2151 intel_sdvo_connector->output_flag); 2152 2153 if (response == 0) 2154 return connector_status_disconnected; 2155 2156 intel_sdvo->attached_output = response; 2157 2158 if ((intel_sdvo_connector->output_flag & response) == 0) 2159 ret = connector_status_disconnected; 2160 else if (IS_TMDS(intel_sdvo_connector)) 2161 ret = intel_sdvo_tmds_sink_detect(connector); 2162 else { 2163 const struct drm_edid *drm_edid; 2164 2165 /* if we have an edid check it matches the connection */ 2166 drm_edid = intel_sdvo_get_edid(connector); 2167 if (!drm_edid) 2168 drm_edid = intel_sdvo_get_analog_edid(connector); 2169 if (drm_edid) { 2170 if (intel_sdvo_connector_matches_edid(intel_sdvo_connector, 2171 drm_edid)) 2172 ret = connector_status_connected; 2173 else 2174 ret = connector_status_disconnected; 2175 2176 drm_edid_free(drm_edid); 2177 } else { 2178 ret = connector_status_connected; 2179 } 2180 } 2181 2182 return ret; 2183} 2184 2185static int intel_sdvo_get_ddc_modes(struct drm_connector *connector) 2186{ 2187 int num_modes = 0; 2188 const struct drm_edid *drm_edid; 2189 2190 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 2191 connector->base.id, connector->name); 2192 2193 /* set the bus switch and get the modes */ 2194 drm_edid = intel_sdvo_get_edid(connector); 2195 2196 /* 2197 * Mac mini hack. On this device, the DVI-I connector shares one DDC 2198 * link between analog and digital outputs. So, if the regular SDVO 2199 * DDC fails, check to see if the analog output is disconnected, in 2200 * which case we'll look there for the digital DDC data. 2201 */ 2202 if (!drm_edid) 2203 drm_edid = intel_sdvo_get_analog_edid(connector); 2204 2205 if (!drm_edid) 2206 return 0; 2207 2208 if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector), 2209 drm_edid)) 2210 num_modes += intel_connector_update_modes(connector, drm_edid); 2211 2212 drm_edid_free(drm_edid); 2213 2214 return num_modes; 2215} 2216 2217/* 2218 * Set of SDVO TV modes. 2219 * Note! This is in reply order (see loop in get_tv_modes). 2220 * XXX: all 60Hz refresh? 2221 */ 2222static const struct drm_display_mode sdvo_tv_modes[] = { 2223 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384, 2224 416, 0, 200, 201, 232, 233, 0, 2225 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2226 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384, 2227 416, 0, 240, 241, 272, 273, 0, 2228 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2229 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464, 2230 496, 0, 300, 301, 332, 333, 0, 2231 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2232 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704, 2233 736, 0, 350, 351, 382, 383, 0, 2234 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2235 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704, 2236 736, 0, 400, 401, 432, 433, 0, 2237 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2238 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704, 2239 736, 0, 480, 481, 512, 513, 0, 2240 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2241 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768, 2242 800, 0, 480, 481, 512, 513, 0, 2243 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2244 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768, 2245 800, 0, 576, 577, 608, 609, 0, 2246 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2247 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784, 2248 816, 0, 350, 351, 382, 383, 0, 2249 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2250 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784, 2251 816, 0, 400, 401, 432, 433, 0, 2252 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2253 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784, 2254 816, 0, 480, 481, 512, 513, 0, 2255 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2256 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784, 2257 816, 0, 540, 541, 572, 573, 0, 2258 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2259 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784, 2260 816, 0, 576, 577, 608, 609, 0, 2261 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2262 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832, 2263 864, 0, 576, 577, 608, 609, 0, 2264 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2265 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864, 2266 896, 0, 600, 601, 632, 633, 0, 2267 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2268 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896, 2269 928, 0, 624, 625, 656, 657, 0, 2270 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2271 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984, 2272 1016, 0, 766, 767, 798, 799, 0, 2273 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2274 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088, 2275 1120, 0, 768, 769, 800, 801, 0, 2276 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2277 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344, 2278 1376, 0, 1024, 1025, 1056, 1057, 0, 2279 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2280}; 2281 2282static int intel_sdvo_get_tv_modes(struct drm_connector *connector) 2283{ 2284 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(to_intel_connector(connector)); 2285 const struct drm_connector_state *conn_state = connector->state; 2286 struct intel_sdvo_sdtv_resolution_request tv_res; 2287 u32 reply = 0, format_map = 0; 2288 int num_modes = 0; 2289 int i; 2290 2291 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 2292 connector->base.id, connector->name); 2293 2294 /* 2295 * Read the list of supported input resolutions for the selected TV 2296 * format. 2297 */ 2298 format_map = 1 << conn_state->tv.legacy_mode; 2299 memcpy(&tv_res, &format_map, 2300 min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request))); 2301 2302 if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output)) 2303 return 0; 2304 2305 BUILD_BUG_ON(sizeof(tv_res) != 3); 2306 if (!intel_sdvo_write_cmd(intel_sdvo, 2307 SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT, 2308 &tv_res, sizeof(tv_res))) 2309 return 0; 2310 if (!intel_sdvo_read_response(intel_sdvo, &reply, 3)) 2311 return 0; 2312 2313 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++) { 2314 if (reply & (1 << i)) { 2315 struct drm_display_mode *nmode; 2316 nmode = drm_mode_duplicate(connector->dev, 2317 &sdvo_tv_modes[i]); 2318 if (nmode) { 2319 drm_mode_probed_add(connector, nmode); 2320 num_modes++; 2321 } 2322 } 2323 } 2324 2325 return num_modes; 2326} 2327 2328static int intel_sdvo_get_lvds_modes(struct drm_connector *connector) 2329{ 2330 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2331 2332 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n", 2333 connector->base.id, connector->name); 2334 2335 return intel_panel_get_modes(to_intel_connector(connector)); 2336} 2337 2338static int intel_sdvo_get_modes(struct drm_connector *connector) 2339{ 2340 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 2341 2342 if (IS_TV(intel_sdvo_connector)) 2343 return intel_sdvo_get_tv_modes(connector); 2344 else if (IS_LVDS(intel_sdvo_connector)) 2345 return intel_sdvo_get_lvds_modes(connector); 2346 else 2347 return intel_sdvo_get_ddc_modes(connector); 2348} 2349 2350static int 2351intel_sdvo_connector_atomic_get_property(struct drm_connector *connector, 2352 const struct drm_connector_state *state, 2353 struct drm_property *property, 2354 u64 *val) 2355{ 2356 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 2357 const struct intel_sdvo_connector_state *sdvo_state = to_intel_sdvo_connector_state((void *)state); 2358 2359 if (property == intel_sdvo_connector->tv_format) { 2360 int i; 2361 2362 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++) 2363 if (state->tv.legacy_mode == intel_sdvo_connector->tv_format_supported[i]) { 2364 *val = i; 2365 2366 return 0; 2367 } 2368 2369 drm_WARN_ON(connector->dev, 1); 2370 *val = 0; 2371 } else if (property == intel_sdvo_connector->top || 2372 property == intel_sdvo_connector->bottom) 2373 *val = intel_sdvo_connector->max_vscan - sdvo_state->tv.overscan_v; 2374 else if (property == intel_sdvo_connector->left || 2375 property == intel_sdvo_connector->right) 2376 *val = intel_sdvo_connector->max_hscan - sdvo_state->tv.overscan_h; 2377 else if (property == intel_sdvo_connector->hpos) 2378 *val = sdvo_state->tv.hpos; 2379 else if (property == intel_sdvo_connector->vpos) 2380 *val = sdvo_state->tv.vpos; 2381 else if (property == intel_sdvo_connector->saturation) 2382 *val = state->tv.saturation; 2383 else if (property == intel_sdvo_connector->contrast) 2384 *val = state->tv.contrast; 2385 else if (property == intel_sdvo_connector->hue) 2386 *val = state->tv.hue; 2387 else if (property == intel_sdvo_connector->brightness) 2388 *val = state->tv.brightness; 2389 else if (property == intel_sdvo_connector->sharpness) 2390 *val = sdvo_state->tv.sharpness; 2391 else if (property == intel_sdvo_connector->flicker_filter) 2392 *val = sdvo_state->tv.flicker_filter; 2393 else if (property == intel_sdvo_connector->flicker_filter_2d) 2394 *val = sdvo_state->tv.flicker_filter_2d; 2395 else if (property == intel_sdvo_connector->flicker_filter_adaptive) 2396 *val = sdvo_state->tv.flicker_filter_adaptive; 2397 else if (property == intel_sdvo_connector->tv_chroma_filter) 2398 *val = sdvo_state->tv.chroma_filter; 2399 else if (property == intel_sdvo_connector->tv_luma_filter) 2400 *val = sdvo_state->tv.luma_filter; 2401 else if (property == intel_sdvo_connector->dot_crawl) 2402 *val = sdvo_state->tv.dot_crawl; 2403 else 2404 return intel_digital_connector_atomic_get_property(connector, state, property, val); 2405 2406 return 0; 2407} 2408 2409static int 2410intel_sdvo_connector_atomic_set_property(struct drm_connector *connector, 2411 struct drm_connector_state *state, 2412 struct drm_property *property, 2413 u64 val) 2414{ 2415 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 2416 struct intel_sdvo_connector_state *sdvo_state = to_intel_sdvo_connector_state(state); 2417 2418 if (property == intel_sdvo_connector->tv_format) { 2419 state->tv.legacy_mode = intel_sdvo_connector->tv_format_supported[val]; 2420 2421 if (state->crtc) { 2422 struct drm_crtc_state *crtc_state = 2423 drm_atomic_get_new_crtc_state(state->state, state->crtc); 2424 2425 crtc_state->connectors_changed = true; 2426 } 2427 } else if (property == intel_sdvo_connector->top || 2428 property == intel_sdvo_connector->bottom) 2429 /* Cannot set these independent from each other */ 2430 sdvo_state->tv.overscan_v = intel_sdvo_connector->max_vscan - val; 2431 else if (property == intel_sdvo_connector->left || 2432 property == intel_sdvo_connector->right) 2433 /* Cannot set these independent from each other */ 2434 sdvo_state->tv.overscan_h = intel_sdvo_connector->max_hscan - val; 2435 else if (property == intel_sdvo_connector->hpos) 2436 sdvo_state->tv.hpos = val; 2437 else if (property == intel_sdvo_connector->vpos) 2438 sdvo_state->tv.vpos = val; 2439 else if (property == intel_sdvo_connector->saturation) 2440 state->tv.saturation = val; 2441 else if (property == intel_sdvo_connector->contrast) 2442 state->tv.contrast = val; 2443 else if (property == intel_sdvo_connector->hue) 2444 state->tv.hue = val; 2445 else if (property == intel_sdvo_connector->brightness) 2446 state->tv.brightness = val; 2447 else if (property == intel_sdvo_connector->sharpness) 2448 sdvo_state->tv.sharpness = val; 2449 else if (property == intel_sdvo_connector->flicker_filter) 2450 sdvo_state->tv.flicker_filter = val; 2451 else if (property == intel_sdvo_connector->flicker_filter_2d) 2452 sdvo_state->tv.flicker_filter_2d = val; 2453 else if (property == intel_sdvo_connector->flicker_filter_adaptive) 2454 sdvo_state->tv.flicker_filter_adaptive = val; 2455 else if (property == intel_sdvo_connector->tv_chroma_filter) 2456 sdvo_state->tv.chroma_filter = val; 2457 else if (property == intel_sdvo_connector->tv_luma_filter) 2458 sdvo_state->tv.luma_filter = val; 2459 else if (property == intel_sdvo_connector->dot_crawl) 2460 sdvo_state->tv.dot_crawl = val; 2461 else 2462 return intel_digital_connector_atomic_set_property(connector, state, property, val); 2463 2464 return 0; 2465} 2466 2467static int 2468intel_sdvo_connector_register(struct drm_connector *connector) 2469{ 2470 struct intel_sdvo *sdvo = intel_attached_sdvo(to_intel_connector(connector)); 2471 int ret; 2472 2473 ret = intel_connector_register(connector); 2474 if (ret) 2475 return ret; 2476 2477 return sysfs_create_link(&connector->kdev->kobj, 2478 &sdvo->ddc.dev.kobj, 2479 sdvo->ddc.dev.kobj.name); 2480} 2481 2482static void 2483intel_sdvo_connector_unregister(struct drm_connector *connector) 2484{ 2485 struct intel_sdvo *sdvo = intel_attached_sdvo(to_intel_connector(connector)); 2486 2487 sysfs_remove_link(&connector->kdev->kobj, 2488 sdvo->ddc.dev.kobj.name); 2489 intel_connector_unregister(connector); 2490} 2491 2492static struct drm_connector_state * 2493intel_sdvo_connector_duplicate_state(struct drm_connector *connector) 2494{ 2495 struct intel_sdvo_connector_state *state; 2496 2497 state = kmemdup(connector->state, sizeof(*state), GFP_KERNEL); 2498 if (!state) 2499 return NULL; 2500 2501 __drm_atomic_helper_connector_duplicate_state(connector, &state->base.base); 2502 return &state->base.base; 2503} 2504 2505static const struct drm_connector_funcs intel_sdvo_connector_funcs = { 2506 .detect = intel_sdvo_detect, 2507 .fill_modes = drm_helper_probe_single_connector_modes, 2508 .atomic_get_property = intel_sdvo_connector_atomic_get_property, 2509 .atomic_set_property = intel_sdvo_connector_atomic_set_property, 2510 .late_register = intel_sdvo_connector_register, 2511 .early_unregister = intel_sdvo_connector_unregister, 2512 .destroy = intel_connector_destroy, 2513 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 2514 .atomic_duplicate_state = intel_sdvo_connector_duplicate_state, 2515}; 2516 2517static int intel_sdvo_atomic_check(struct drm_connector *conn, 2518 struct drm_atomic_state *state) 2519{ 2520 struct drm_connector_state *new_conn_state = 2521 drm_atomic_get_new_connector_state(state, conn); 2522 struct drm_connector_state *old_conn_state = 2523 drm_atomic_get_old_connector_state(state, conn); 2524 struct intel_sdvo_connector_state *old_state = 2525 to_intel_sdvo_connector_state(old_conn_state); 2526 struct intel_sdvo_connector_state *new_state = 2527 to_intel_sdvo_connector_state(new_conn_state); 2528 2529 if (new_conn_state->crtc && 2530 (memcmp(&old_state->tv, &new_state->tv, sizeof(old_state->tv)) || 2531 memcmp(&old_conn_state->tv, &new_conn_state->tv, sizeof(old_conn_state->tv)))) { 2532 struct drm_crtc_state *crtc_state = 2533 drm_atomic_get_new_crtc_state(state, 2534 new_conn_state->crtc); 2535 2536 crtc_state->connectors_changed = true; 2537 } 2538 2539 return intel_digital_connector_atomic_check(conn, state); 2540} 2541 2542static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = { 2543 .get_modes = intel_sdvo_get_modes, 2544 .mode_valid = intel_sdvo_mode_valid, 2545 .atomic_check = intel_sdvo_atomic_check, 2546}; 2547 2548static void intel_sdvo_enc_destroy(struct drm_encoder *encoder) 2549{ 2550 struct intel_sdvo *intel_sdvo = to_sdvo(to_intel_encoder(encoder)); 2551 2552 i2c_del_adapter(&intel_sdvo->ddc); 2553 intel_encoder_destroy(encoder); 2554} 2555 2556static const struct drm_encoder_funcs intel_sdvo_enc_funcs = { 2557 .destroy = intel_sdvo_enc_destroy, 2558}; 2559 2560static void 2561intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo) 2562{ 2563 u16 mask = 0; 2564 unsigned int num_bits; 2565 2566 /* 2567 * Make a mask of outputs less than or equal to our own priority in the 2568 * list. 2569 */ 2570 switch (sdvo->controlled_output) { 2571 case SDVO_OUTPUT_LVDS1: 2572 mask |= SDVO_OUTPUT_LVDS1; 2573 fallthrough; 2574 case SDVO_OUTPUT_LVDS0: 2575 mask |= SDVO_OUTPUT_LVDS0; 2576 fallthrough; 2577 case SDVO_OUTPUT_TMDS1: 2578 mask |= SDVO_OUTPUT_TMDS1; 2579 fallthrough; 2580 case SDVO_OUTPUT_TMDS0: 2581 mask |= SDVO_OUTPUT_TMDS0; 2582 fallthrough; 2583 case SDVO_OUTPUT_RGB1: 2584 mask |= SDVO_OUTPUT_RGB1; 2585 fallthrough; 2586 case SDVO_OUTPUT_RGB0: 2587 mask |= SDVO_OUTPUT_RGB0; 2588 break; 2589 } 2590 2591 /* Count bits to find what number we are in the priority list. */ 2592 mask &= sdvo->caps.output_flags; 2593 num_bits = hweight16(mask); 2594 /* If more than 3 outputs, default to DDC bus 3 for now. */ 2595 if (num_bits > 3) 2596 num_bits = 3; 2597 2598 /* Corresponds to SDVO_CONTROL_BUS_DDCx */ 2599 sdvo->ddc_bus = 1 << num_bits; 2600} 2601 2602/* 2603 * Choose the appropriate DDC bus for control bus switch command for this 2604 * SDVO output based on the controlled output. 2605 * 2606 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS 2607 * outputs, then LVDS outputs. 2608 */ 2609static void 2610intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv, 2611 struct intel_sdvo *sdvo) 2612{ 2613 struct sdvo_device_mapping *mapping; 2614 2615 if (sdvo->port == PORT_B) 2616 mapping = &dev_priv->display.vbt.sdvo_mappings[0]; 2617 else 2618 mapping = &dev_priv->display.vbt.sdvo_mappings[1]; 2619 2620 if (mapping->initialized) 2621 sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4); 2622 else 2623 intel_sdvo_guess_ddc_bus(sdvo); 2624} 2625 2626static void 2627intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv, 2628 struct intel_sdvo *sdvo) 2629{ 2630 struct sdvo_device_mapping *mapping; 2631 u8 pin; 2632 2633 if (sdvo->port == PORT_B) 2634 mapping = &dev_priv->display.vbt.sdvo_mappings[0]; 2635 else 2636 mapping = &dev_priv->display.vbt.sdvo_mappings[1]; 2637 2638 if (mapping->initialized && 2639 intel_gmbus_is_valid_pin(dev_priv, mapping->i2c_pin)) 2640 pin = mapping->i2c_pin; 2641 else 2642 pin = GMBUS_PIN_DPB; 2643 2644 sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin); 2645 2646 /* 2647 * With gmbus we should be able to drive sdvo i2c at 2MHz, but somehow 2648 * our code totally fails once we start using gmbus. Hence fall back to 2649 * bit banging for now. 2650 */ 2651 intel_gmbus_force_bit(sdvo->i2c, true); 2652} 2653 2654/* undo any changes intel_sdvo_select_i2c_bus() did to sdvo->i2c */ 2655static void 2656intel_sdvo_unselect_i2c_bus(struct intel_sdvo *sdvo) 2657{ 2658 intel_gmbus_force_bit(sdvo->i2c, false); 2659} 2660 2661static bool 2662intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo) 2663{ 2664 return intel_sdvo_check_supp_encode(intel_sdvo); 2665} 2666 2667static u8 2668intel_sdvo_get_slave_addr(struct drm_i915_private *dev_priv, 2669 struct intel_sdvo *sdvo) 2670{ 2671 struct sdvo_device_mapping *my_mapping, *other_mapping; 2672 2673 if (sdvo->port == PORT_B) { 2674 my_mapping = &dev_priv->display.vbt.sdvo_mappings[0]; 2675 other_mapping = &dev_priv->display.vbt.sdvo_mappings[1]; 2676 } else { 2677 my_mapping = &dev_priv->display.vbt.sdvo_mappings[1]; 2678 other_mapping = &dev_priv->display.vbt.sdvo_mappings[0]; 2679 } 2680 2681 /* If the BIOS described our SDVO device, take advantage of it. */ 2682 if (my_mapping->slave_addr) 2683 return my_mapping->slave_addr; 2684 2685 /* 2686 * If the BIOS only described a different SDVO device, use the 2687 * address that it isn't using. 2688 */ 2689 if (other_mapping->slave_addr) { 2690 if (other_mapping->slave_addr == 0x70) 2691 return 0x72; 2692 else 2693 return 0x70; 2694 } 2695 2696 /* 2697 * No SDVO device info is found for another DVO port, 2698 * so use mapping assumption we had before BIOS parsing. 2699 */ 2700 if (sdvo->port == PORT_B) 2701 return 0x70; 2702 else 2703 return 0x72; 2704} 2705 2706static int 2707intel_sdvo_connector_init(struct intel_sdvo_connector *connector, 2708 struct intel_sdvo *encoder) 2709{ 2710 struct drm_connector *drm_connector; 2711 int ret; 2712 2713 drm_connector = &connector->base.base; 2714 ret = drm_connector_init(encoder->base.base.dev, 2715 drm_connector, 2716 &intel_sdvo_connector_funcs, 2717 connector->base.base.connector_type); 2718 if (ret < 0) 2719 return ret; 2720 2721 drm_connector_helper_add(drm_connector, 2722 &intel_sdvo_connector_helper_funcs); 2723 2724 connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB; 2725 connector->base.base.interlace_allowed = true; 2726 connector->base.get_hw_state = intel_sdvo_connector_get_hw_state; 2727 2728 intel_connector_attach_encoder(&connector->base, &encoder->base); 2729 2730 return 0; 2731} 2732 2733static void 2734intel_sdvo_add_hdmi_properties(struct intel_sdvo *intel_sdvo, 2735 struct intel_sdvo_connector *connector) 2736{ 2737 intel_attach_force_audio_property(&connector->base.base); 2738 if (intel_sdvo->colorimetry_cap & SDVO_COLORIMETRY_RGB220) 2739 intel_attach_broadcast_rgb_property(&connector->base.base); 2740 intel_attach_aspect_ratio_property(&connector->base.base); 2741} 2742 2743static struct intel_sdvo_connector *intel_sdvo_connector_alloc(void) 2744{ 2745 struct intel_sdvo_connector *sdvo_connector; 2746 struct intel_sdvo_connector_state *conn_state; 2747 2748 sdvo_connector = kzalloc(sizeof(*sdvo_connector), GFP_KERNEL); 2749 if (!sdvo_connector) 2750 return NULL; 2751 2752 conn_state = kzalloc(sizeof(*conn_state), GFP_KERNEL); 2753 if (!conn_state) { 2754 kfree(sdvo_connector); 2755 return NULL; 2756 } 2757 2758 __drm_atomic_helper_connector_reset(&sdvo_connector->base.base, 2759 &conn_state->base.base); 2760 2761 intel_panel_init_alloc(&sdvo_connector->base); 2762 2763 return sdvo_connector; 2764} 2765 2766static bool 2767intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, u16 type) 2768{ 2769 struct drm_encoder *encoder = &intel_sdvo->base.base; 2770 struct drm_connector *connector; 2771 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 2772 struct intel_connector *intel_connector; 2773 struct intel_sdvo_connector *intel_sdvo_connector; 2774 2775 DRM_DEBUG_KMS("initialising DVI type 0x%x\n", type); 2776 2777 intel_sdvo_connector = intel_sdvo_connector_alloc(); 2778 if (!intel_sdvo_connector) 2779 return false; 2780 2781 intel_sdvo_connector->output_flag = type; 2782 2783 intel_connector = &intel_sdvo_connector->base; 2784 connector = &intel_connector->base; 2785 if (intel_sdvo_get_hotplug_support(intel_sdvo) & 2786 intel_sdvo_connector->output_flag) { 2787 intel_sdvo->hotplug_active |= intel_sdvo_connector->output_flag; 2788 /* 2789 * Some SDVO devices have one-shot hotplug interrupts. 2790 * Ensure that they get re-enabled when an interrupt happens. 2791 */ 2792 intel_connector->polled = DRM_CONNECTOR_POLL_HPD; 2793 intel_encoder->hotplug = intel_sdvo_hotplug; 2794 intel_sdvo_enable_hotplug(intel_encoder); 2795 } else { 2796 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT; 2797 } 2798 encoder->encoder_type = DRM_MODE_ENCODER_TMDS; 2799 connector->connector_type = DRM_MODE_CONNECTOR_DVID; 2800 2801 if (intel_sdvo_is_hdmi_connector(intel_sdvo)) { 2802 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA; 2803 intel_sdvo_connector->is_hdmi = true; 2804 } 2805 2806 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { 2807 kfree(intel_sdvo_connector); 2808 return false; 2809 } 2810 2811 if (intel_sdvo_connector->is_hdmi) 2812 intel_sdvo_add_hdmi_properties(intel_sdvo, intel_sdvo_connector); 2813 2814 return true; 2815} 2816 2817static bool 2818intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, u16 type) 2819{ 2820 struct drm_encoder *encoder = &intel_sdvo->base.base; 2821 struct drm_connector *connector; 2822 struct intel_connector *intel_connector; 2823 struct intel_sdvo_connector *intel_sdvo_connector; 2824 2825 DRM_DEBUG_KMS("initialising TV type 0x%x\n", type); 2826 2827 intel_sdvo_connector = intel_sdvo_connector_alloc(); 2828 if (!intel_sdvo_connector) 2829 return false; 2830 2831 intel_connector = &intel_sdvo_connector->base; 2832 connector = &intel_connector->base; 2833 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC; 2834 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO; 2835 2836 intel_sdvo_connector->output_flag = type; 2837 2838 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { 2839 kfree(intel_sdvo_connector); 2840 return false; 2841 } 2842 2843 if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type)) 2844 goto err; 2845 2846 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector)) 2847 goto err; 2848 2849 return true; 2850 2851err: 2852 intel_connector_destroy(connector); 2853 return false; 2854} 2855 2856static bool 2857intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, u16 type) 2858{ 2859 struct drm_encoder *encoder = &intel_sdvo->base.base; 2860 struct drm_connector *connector; 2861 struct intel_connector *intel_connector; 2862 struct intel_sdvo_connector *intel_sdvo_connector; 2863 2864 DRM_DEBUG_KMS("initialising analog type 0x%x\n", type); 2865 2866 intel_sdvo_connector = intel_sdvo_connector_alloc(); 2867 if (!intel_sdvo_connector) 2868 return false; 2869 2870 intel_connector = &intel_sdvo_connector->base; 2871 connector = &intel_connector->base; 2872 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT; 2873 encoder->encoder_type = DRM_MODE_ENCODER_DAC; 2874 connector->connector_type = DRM_MODE_CONNECTOR_VGA; 2875 2876 intel_sdvo_connector->output_flag = type; 2877 2878 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { 2879 kfree(intel_sdvo_connector); 2880 return false; 2881 } 2882 2883 return true; 2884} 2885 2886static bool 2887intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, u16 type) 2888{ 2889 struct drm_encoder *encoder = &intel_sdvo->base.base; 2890 struct drm_i915_private *i915 = to_i915(encoder->dev); 2891 struct drm_connector *connector; 2892 struct intel_connector *intel_connector; 2893 struct intel_sdvo_connector *intel_sdvo_connector; 2894 2895 DRM_DEBUG_KMS("initialising LVDS type 0x%x\n", type); 2896 2897 intel_sdvo_connector = intel_sdvo_connector_alloc(); 2898 if (!intel_sdvo_connector) 2899 return false; 2900 2901 intel_connector = &intel_sdvo_connector->base; 2902 connector = &intel_connector->base; 2903 encoder->encoder_type = DRM_MODE_ENCODER_LVDS; 2904 connector->connector_type = DRM_MODE_CONNECTOR_LVDS; 2905 2906 intel_sdvo_connector->output_flag = type; 2907 2908 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { 2909 kfree(intel_sdvo_connector); 2910 return false; 2911 } 2912 2913 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector)) 2914 goto err; 2915 2916 intel_bios_init_panel_late(i915, &intel_connector->panel, NULL, NULL); 2917 2918 /* 2919 * Fetch modes from VBT. For SDVO prefer the VBT mode since some 2920 * SDVO->LVDS transcoders can't cope with the EDID mode. 2921 */ 2922 intel_panel_add_vbt_sdvo_fixed_mode(intel_connector); 2923 2924 if (!intel_panel_preferred_fixed_mode(intel_connector)) { 2925 mutex_lock(&i915->drm.mode_config.mutex); 2926 2927 intel_ddc_get_modes(connector, &intel_sdvo->ddc); 2928 intel_panel_add_edid_fixed_modes(intel_connector, false); 2929 2930 mutex_unlock(&i915->drm.mode_config.mutex); 2931 } 2932 2933 intel_panel_init(intel_connector, NULL); 2934 2935 if (!intel_panel_preferred_fixed_mode(intel_connector)) 2936 goto err; 2937 2938 return true; 2939 2940err: 2941 intel_connector_destroy(connector); 2942 return false; 2943} 2944 2945static u16 intel_sdvo_filter_output_flags(u16 flags) 2946{ 2947 flags &= SDVO_OUTPUT_MASK; 2948 2949 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/ 2950 if (!(flags & SDVO_OUTPUT_TMDS0)) 2951 flags &= ~SDVO_OUTPUT_TMDS1; 2952 2953 if (!(flags & SDVO_OUTPUT_RGB0)) 2954 flags &= ~SDVO_OUTPUT_RGB1; 2955 2956 if (!(flags & SDVO_OUTPUT_LVDS0)) 2957 flags &= ~SDVO_OUTPUT_LVDS1; 2958 2959 return flags; 2960} 2961 2962static bool intel_sdvo_output_init(struct intel_sdvo *sdvo, u16 type) 2963{ 2964 if (type & SDVO_TMDS_MASK) 2965 return intel_sdvo_dvi_init(sdvo, type); 2966 else if (type & SDVO_TV_MASK) 2967 return intel_sdvo_tv_init(sdvo, type); 2968 else if (type & SDVO_RGB_MASK) 2969 return intel_sdvo_analog_init(sdvo, type); 2970 else if (type & SDVO_LVDS_MASK) 2971 return intel_sdvo_lvds_init(sdvo, type); 2972 else 2973 return false; 2974} 2975 2976static bool 2977intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo) 2978{ 2979 static const u16 probe_order[] = { 2980 SDVO_OUTPUT_TMDS0, 2981 SDVO_OUTPUT_TMDS1, 2982 /* TV has no XXX1 function block */ 2983 SDVO_OUTPUT_SVID0, 2984 SDVO_OUTPUT_CVBS0, 2985 SDVO_OUTPUT_YPRPB0, 2986 SDVO_OUTPUT_RGB0, 2987 SDVO_OUTPUT_RGB1, 2988 SDVO_OUTPUT_LVDS0, 2989 SDVO_OUTPUT_LVDS1, 2990 }; 2991 struct drm_i915_private *i915 = to_i915(intel_sdvo->base.base.dev); 2992 u16 flags; 2993 int i; 2994 2995 flags = intel_sdvo_filter_output_flags(intel_sdvo->caps.output_flags); 2996 2997 if (flags == 0) { 2998 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%04x)\n", 2999 SDVO_NAME(intel_sdvo), intel_sdvo->caps.output_flags); 3000 return false; 3001 } 3002 3003 intel_sdvo->controlled_output = flags; 3004 3005 intel_sdvo_select_ddc_bus(i915, intel_sdvo); 3006 3007 for (i = 0; i < ARRAY_SIZE(probe_order); i++) { 3008 u16 type = flags & probe_order[i]; 3009 3010 if (!type) 3011 continue; 3012 3013 if (!intel_sdvo_output_init(intel_sdvo, type)) 3014 return false; 3015 } 3016 3017 intel_sdvo->base.pipe_mask = ~0; 3018 3019 return true; 3020} 3021 3022static void intel_sdvo_output_cleanup(struct intel_sdvo *intel_sdvo) 3023{ 3024 struct drm_device *dev = intel_sdvo->base.base.dev; 3025 struct drm_connector *connector, *tmp; 3026 3027 list_for_each_entry_safe(connector, tmp, 3028 &dev->mode_config.connector_list, head) { 3029 if (intel_attached_encoder(to_intel_connector(connector)) == &intel_sdvo->base) { 3030 drm_connector_unregister(connector); 3031 intel_connector_destroy(connector); 3032 } 3033 } 3034} 3035 3036static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, 3037 struct intel_sdvo_connector *intel_sdvo_connector, 3038 int type) 3039{ 3040 struct drm_device *dev = intel_sdvo->base.base.dev; 3041 struct intel_sdvo_tv_format format; 3042 u32 format_map, i; 3043 3044 if (!intel_sdvo_set_target_output(intel_sdvo, type)) 3045 return false; 3046 3047 BUILD_BUG_ON(sizeof(format) != 6); 3048 if (!intel_sdvo_get_value(intel_sdvo, 3049 SDVO_CMD_GET_SUPPORTED_TV_FORMATS, 3050 &format, sizeof(format))) 3051 return false; 3052 3053 memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format))); 3054 3055 if (format_map == 0) 3056 return false; 3057 3058 intel_sdvo_connector->format_supported_num = 0; 3059 for (i = 0 ; i < TV_FORMAT_NUM; i++) 3060 if (format_map & (1 << i)) 3061 intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i; 3062 3063 3064 intel_sdvo_connector->tv_format = 3065 drm_property_create(dev, DRM_MODE_PROP_ENUM, 3066 "mode", intel_sdvo_connector->format_supported_num); 3067 if (!intel_sdvo_connector->tv_format) 3068 return false; 3069 3070 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++) 3071 drm_property_add_enum(intel_sdvo_connector->tv_format, i, 3072 tv_format_names[intel_sdvo_connector->tv_format_supported[i]]); 3073 3074 intel_sdvo_connector->base.base.state->tv.legacy_mode = intel_sdvo_connector->tv_format_supported[0]; 3075 drm_object_attach_property(&intel_sdvo_connector->base.base.base, 3076 intel_sdvo_connector->tv_format, 0); 3077 return true; 3078 3079} 3080 3081#define _ENHANCEMENT(state_assignment, name, NAME) do { \ 3082 if (enhancements.name) { \ 3083 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \ 3084 !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \ 3085 return false; \ 3086 intel_sdvo_connector->name = \ 3087 drm_property_create_range(dev, 0, #name, 0, data_value[0]); \ 3088 if (!intel_sdvo_connector->name) return false; \ 3089 state_assignment = response; \ 3090 drm_object_attach_property(&connector->base, \ 3091 intel_sdvo_connector->name, 0); \ 3092 DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \ 3093 data_value[0], data_value[1], response); \ 3094 } \ 3095} while (0) 3096 3097#define ENHANCEMENT(state, name, NAME) _ENHANCEMENT((state)->name, name, NAME) 3098 3099static bool 3100intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo, 3101 struct intel_sdvo_connector *intel_sdvo_connector, 3102 struct intel_sdvo_enhancements_reply enhancements) 3103{ 3104 struct drm_device *dev = intel_sdvo->base.base.dev; 3105 struct drm_connector *connector = &intel_sdvo_connector->base.base; 3106 struct drm_connector_state *conn_state = connector->state; 3107 struct intel_sdvo_connector_state *sdvo_state = 3108 to_intel_sdvo_connector_state(conn_state); 3109 u16 response, data_value[2]; 3110 3111 /* when horizontal overscan is supported, Add the left/right property */ 3112 if (enhancements.overscan_h) { 3113 if (!intel_sdvo_get_value(intel_sdvo, 3114 SDVO_CMD_GET_MAX_OVERSCAN_H, 3115 &data_value, 4)) 3116 return false; 3117 3118 if (!intel_sdvo_get_value(intel_sdvo, 3119 SDVO_CMD_GET_OVERSCAN_H, 3120 &response, 2)) 3121 return false; 3122 3123 sdvo_state->tv.overscan_h = response; 3124 3125 intel_sdvo_connector->max_hscan = data_value[0]; 3126 intel_sdvo_connector->left = 3127 drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]); 3128 if (!intel_sdvo_connector->left) 3129 return false; 3130 3131 drm_object_attach_property(&connector->base, 3132 intel_sdvo_connector->left, 0); 3133 3134 intel_sdvo_connector->right = 3135 drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]); 3136 if (!intel_sdvo_connector->right) 3137 return false; 3138 3139 drm_object_attach_property(&connector->base, 3140 intel_sdvo_connector->right, 0); 3141 DRM_DEBUG_KMS("h_overscan: max %d, " 3142 "default %d, current %d\n", 3143 data_value[0], data_value[1], response); 3144 } 3145 3146 if (enhancements.overscan_v) { 3147 if (!intel_sdvo_get_value(intel_sdvo, 3148 SDVO_CMD_GET_MAX_OVERSCAN_V, 3149 &data_value, 4)) 3150 return false; 3151 3152 if (!intel_sdvo_get_value(intel_sdvo, 3153 SDVO_CMD_GET_OVERSCAN_V, 3154 &response, 2)) 3155 return false; 3156 3157 sdvo_state->tv.overscan_v = response; 3158 3159 intel_sdvo_connector->max_vscan = data_value[0]; 3160 intel_sdvo_connector->top = 3161 drm_property_create_range(dev, 0, 3162 "top_margin", 0, data_value[0]); 3163 if (!intel_sdvo_connector->top) 3164 return false; 3165 3166 drm_object_attach_property(&connector->base, 3167 intel_sdvo_connector->top, 0); 3168 3169 intel_sdvo_connector->bottom = 3170 drm_property_create_range(dev, 0, 3171 "bottom_margin", 0, data_value[0]); 3172 if (!intel_sdvo_connector->bottom) 3173 return false; 3174 3175 drm_object_attach_property(&connector->base, 3176 intel_sdvo_connector->bottom, 0); 3177 DRM_DEBUG_KMS("v_overscan: max %d, " 3178 "default %d, current %d\n", 3179 data_value[0], data_value[1], response); 3180 } 3181 3182 ENHANCEMENT(&sdvo_state->tv, hpos, HPOS); 3183 ENHANCEMENT(&sdvo_state->tv, vpos, VPOS); 3184 ENHANCEMENT(&conn_state->tv, saturation, SATURATION); 3185 ENHANCEMENT(&conn_state->tv, contrast, CONTRAST); 3186 ENHANCEMENT(&conn_state->tv, hue, HUE); 3187 ENHANCEMENT(&conn_state->tv, brightness, BRIGHTNESS); 3188 ENHANCEMENT(&sdvo_state->tv, sharpness, SHARPNESS); 3189 ENHANCEMENT(&sdvo_state->tv, flicker_filter, FLICKER_FILTER); 3190 ENHANCEMENT(&sdvo_state->tv, flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE); 3191 ENHANCEMENT(&sdvo_state->tv, flicker_filter_2d, FLICKER_FILTER_2D); 3192 _ENHANCEMENT(sdvo_state->tv.chroma_filter, tv_chroma_filter, TV_CHROMA_FILTER); 3193 _ENHANCEMENT(sdvo_state->tv.luma_filter, tv_luma_filter, TV_LUMA_FILTER); 3194 3195 if (enhancements.dot_crawl) { 3196 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2)) 3197 return false; 3198 3199 sdvo_state->tv.dot_crawl = response & 0x1; 3200 intel_sdvo_connector->dot_crawl = 3201 drm_property_create_range(dev, 0, "dot_crawl", 0, 1); 3202 if (!intel_sdvo_connector->dot_crawl) 3203 return false; 3204 3205 drm_object_attach_property(&connector->base, 3206 intel_sdvo_connector->dot_crawl, 0); 3207 DRM_DEBUG_KMS("dot crawl: current %d\n", response); 3208 } 3209 3210 return true; 3211} 3212 3213static bool 3214intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo, 3215 struct intel_sdvo_connector *intel_sdvo_connector, 3216 struct intel_sdvo_enhancements_reply enhancements) 3217{ 3218 struct drm_device *dev = intel_sdvo->base.base.dev; 3219 struct drm_connector *connector = &intel_sdvo_connector->base.base; 3220 u16 response, data_value[2]; 3221 3222 ENHANCEMENT(&connector->state->tv, brightness, BRIGHTNESS); 3223 3224 return true; 3225} 3226#undef ENHANCEMENT 3227#undef _ENHANCEMENT 3228 3229static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo, 3230 struct intel_sdvo_connector *intel_sdvo_connector) 3231{ 3232 union { 3233 struct intel_sdvo_enhancements_reply reply; 3234 u16 response; 3235 } enhancements; 3236 3237 BUILD_BUG_ON(sizeof(enhancements) != 2); 3238 3239 if (!intel_sdvo_get_value(intel_sdvo, 3240 SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS, 3241 &enhancements, sizeof(enhancements)) || 3242 enhancements.response == 0) { 3243 DRM_DEBUG_KMS("No enhancement is supported\n"); 3244 return true; 3245 } 3246 3247 if (IS_TV(intel_sdvo_connector)) 3248 return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply); 3249 else if (IS_LVDS(intel_sdvo_connector)) 3250 return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply); 3251 else 3252 return true; 3253} 3254 3255static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter, 3256 struct i2c_msg *msgs, 3257 int num) 3258{ 3259 struct intel_sdvo *sdvo = adapter->algo_data; 3260 3261 if (!__intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus)) 3262 return -EIO; 3263 3264 return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num); 3265} 3266 3267static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter) 3268{ 3269 struct intel_sdvo *sdvo = adapter->algo_data; 3270 return sdvo->i2c->algo->functionality(sdvo->i2c); 3271} 3272 3273static const struct i2c_algorithm intel_sdvo_ddc_proxy = { 3274 .master_xfer = intel_sdvo_ddc_proxy_xfer, 3275 .functionality = intel_sdvo_ddc_proxy_func 3276}; 3277 3278static void proxy_lock_bus(struct i2c_adapter *adapter, 3279 unsigned int flags) 3280{ 3281 struct intel_sdvo *sdvo = adapter->algo_data; 3282 sdvo->i2c->lock_ops->lock_bus(sdvo->i2c, flags); 3283} 3284 3285static int proxy_trylock_bus(struct i2c_adapter *adapter, 3286 unsigned int flags) 3287{ 3288 struct intel_sdvo *sdvo = adapter->algo_data; 3289 return sdvo->i2c->lock_ops->trylock_bus(sdvo->i2c, flags); 3290} 3291 3292static void proxy_unlock_bus(struct i2c_adapter *adapter, 3293 unsigned int flags) 3294{ 3295 struct intel_sdvo *sdvo = adapter->algo_data; 3296 sdvo->i2c->lock_ops->unlock_bus(sdvo->i2c, flags); 3297} 3298 3299static const struct i2c_lock_operations proxy_lock_ops = { 3300 .lock_bus = proxy_lock_bus, 3301 .trylock_bus = proxy_trylock_bus, 3302 .unlock_bus = proxy_unlock_bus, 3303}; 3304 3305static bool 3306intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo, 3307 struct drm_i915_private *dev_priv) 3308{ 3309 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 3310 3311 sdvo->ddc.owner = THIS_MODULE; 3312 sdvo->ddc.class = I2C_CLASS_DDC; 3313 snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy"); 3314 sdvo->ddc.dev.parent = &pdev->dev; 3315 sdvo->ddc.algo_data = sdvo; 3316 sdvo->ddc.algo = &intel_sdvo_ddc_proxy; 3317 sdvo->ddc.lock_ops = &proxy_lock_ops; 3318 3319 return i2c_add_adapter(&sdvo->ddc) == 0; 3320} 3321 3322static bool is_sdvo_port_valid(struct drm_i915_private *dev_priv, enum port port) 3323{ 3324 if (HAS_PCH_SPLIT(dev_priv)) 3325 return port == PORT_B; 3326 else 3327 return port == PORT_B || port == PORT_C; 3328} 3329 3330static bool assert_sdvo_port_valid(struct drm_i915_private *dev_priv, 3331 enum port port) 3332{ 3333 return !drm_WARN(&dev_priv->drm, !is_sdvo_port_valid(dev_priv, port), 3334 "Platform does not support SDVO %c\n", port_name(port)); 3335} 3336 3337bool intel_sdvo_init(struct drm_i915_private *dev_priv, 3338 i915_reg_t sdvo_reg, enum port port) 3339{ 3340 struct intel_encoder *intel_encoder; 3341 struct intel_sdvo *intel_sdvo; 3342 int i; 3343 3344 if (!assert_port_valid(dev_priv, port)) 3345 return false; 3346 3347 if (!assert_sdvo_port_valid(dev_priv, port)) 3348 return false; 3349 3350 intel_sdvo = kzalloc(sizeof(*intel_sdvo), GFP_KERNEL); 3351 if (!intel_sdvo) 3352 return false; 3353 3354 intel_sdvo->sdvo_reg = sdvo_reg; 3355 intel_sdvo->port = port; 3356 intel_sdvo->slave_addr = 3357 intel_sdvo_get_slave_addr(dev_priv, intel_sdvo) >> 1; 3358 intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo); 3359 if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev_priv)) 3360 goto err_i2c_bus; 3361 3362 /* encoder type will be decided later */ 3363 intel_encoder = &intel_sdvo->base; 3364 intel_encoder->type = INTEL_OUTPUT_SDVO; 3365 intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER; 3366 intel_encoder->port = port; 3367 drm_encoder_init(&dev_priv->drm, &intel_encoder->base, 3368 &intel_sdvo_enc_funcs, 0, 3369 "SDVO %c", port_name(port)); 3370 3371 /* Read the regs to test if we can talk to the device */ 3372 for (i = 0; i < 0x40; i++) { 3373 u8 byte; 3374 3375 if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) { 3376 drm_dbg_kms(&dev_priv->drm, 3377 "No SDVO device found on %s\n", 3378 SDVO_NAME(intel_sdvo)); 3379 goto err; 3380 } 3381 } 3382 3383 intel_encoder->compute_config = intel_sdvo_compute_config; 3384 if (HAS_PCH_SPLIT(dev_priv)) { 3385 intel_encoder->disable = pch_disable_sdvo; 3386 intel_encoder->post_disable = pch_post_disable_sdvo; 3387 } else { 3388 intel_encoder->disable = intel_disable_sdvo; 3389 } 3390 intel_encoder->pre_enable = intel_sdvo_pre_enable; 3391 intel_encoder->enable = intel_enable_sdvo; 3392 intel_encoder->get_hw_state = intel_sdvo_get_hw_state; 3393 intel_encoder->get_config = intel_sdvo_get_config; 3394 3395 /* In default case sdvo lvds is false */ 3396 if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps)) 3397 goto err; 3398 3399 intel_sdvo->colorimetry_cap = 3400 intel_sdvo_get_colorimetry_cap(intel_sdvo); 3401 3402 if (!intel_sdvo_output_setup(intel_sdvo)) { 3403 drm_dbg_kms(&dev_priv->drm, 3404 "SDVO output failed to setup on %s\n", 3405 SDVO_NAME(intel_sdvo)); 3406 /* Output_setup can leave behind connectors! */ 3407 goto err_output; 3408 } 3409 3410 /* 3411 * Only enable the hotplug irq if we need it, to work around noisy 3412 * hotplug lines. 3413 */ 3414 if (intel_sdvo->hotplug_active) { 3415 if (intel_sdvo->port == PORT_B) 3416 intel_encoder->hpd_pin = HPD_SDVO_B; 3417 else 3418 intel_encoder->hpd_pin = HPD_SDVO_C; 3419 } 3420 3421 /* 3422 * Cloning SDVO with anything is often impossible, since the SDVO 3423 * encoder can request a special input timing mode. And even if that's 3424 * not the case we have evidence that cloning a plain unscaled mode with 3425 * VGA doesn't really work. Furthermore the cloning flags are way too 3426 * simplistic anyway to express such constraints, so just give up on 3427 * cloning for SDVO encoders. 3428 */ 3429 intel_sdvo->base.cloneable = 0; 3430 3431 /* Set the input timing to the screen. Assume always input 0. */ 3432 if (!intel_sdvo_set_target_input(intel_sdvo)) 3433 goto err_output; 3434 3435 if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo, 3436 &intel_sdvo->pixel_clock_min, 3437 &intel_sdvo->pixel_clock_max)) 3438 goto err_output; 3439 3440 drm_dbg_kms(&dev_priv->drm, "%s device VID/DID: %02X:%02X.%02X, " 3441 "clock range %dMHz - %dMHz, " 3442 "input 1: %c, input 2: %c, " 3443 "output 1: %c, output 2: %c\n", 3444 SDVO_NAME(intel_sdvo), 3445 intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id, 3446 intel_sdvo->caps.device_rev_id, 3447 intel_sdvo->pixel_clock_min / 1000, 3448 intel_sdvo->pixel_clock_max / 1000, 3449 (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N', 3450 (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N', 3451 /* check currently supported outputs */ 3452 intel_sdvo->caps.output_flags & 3453 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0 | 3454 SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_SVID0 | 3455 SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_YPRPB0) ? 'Y' : 'N', 3456 intel_sdvo->caps.output_flags & 3457 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1 | 3458 SDVO_OUTPUT_LVDS1) ? 'Y' : 'N'); 3459 return true; 3460 3461err_output: 3462 intel_sdvo_output_cleanup(intel_sdvo); 3463 3464err: 3465 drm_encoder_cleanup(&intel_encoder->base); 3466 i2c_del_adapter(&intel_sdvo->ddc); 3467err_i2c_bus: 3468 intel_sdvo_unselect_i2c_bus(intel_sdvo); 3469 kfree(intel_sdvo); 3470 3471 return false; 3472} 3473