1/* 2 * Copyright © 2006-2007 Intel Corporation 3 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Eric Anholt <eric@anholt.net> 26 * Dave Airlie <airlied@linux.ie> 27 * Jesse Barnes <jesse.barnes@intel.com> 28 */ 29 30#include <acpi/button.h> 31#include <linux/acpi.h> 32#include <linux/dmi.h> 33#include <linux/i2c.h> 34#include <linux/slab.h> 35#include <linux/vga_switcheroo.h> 36 37#include <drm/drm_atomic_helper.h> 38#include <drm/drm_crtc.h> 39#include <drm/drm_edid.h> 40 41#include "i915_drv.h" 42#include "i915_reg.h" 43#include "intel_atomic.h" 44#include "intel_backlight.h" 45#include "intel_connector.h" 46#include "intel_de.h" 47#include "intel_display_types.h" 48#include "intel_dpll.h" 49#include "intel_fdi.h" 50#include "intel_gmbus.h" 51#include "intel_lvds.h" 52#include "intel_lvds_regs.h" 53#include "intel_panel.h" 54#include "intel_pps_regs.h" 55 56/* Private structure for the integrated LVDS support */ 57struct intel_lvds_pps { 58 /* 100us units */ 59 int t1_t2; 60 int t3; 61 int t4; 62 int t5; 63 int tx; 64 65 int divider; 66 67 int port; 68 bool powerdown_on_reset; 69}; 70 71struct intel_lvds_encoder { 72 struct intel_encoder base; 73 74 bool is_dual_link; 75 i915_reg_t reg; 76 u32 a3_power; 77 78 struct intel_lvds_pps init_pps; 79 u32 init_lvds_val; 80 81 struct intel_connector *attached_connector; 82}; 83 84static struct intel_lvds_encoder *to_lvds_encoder(struct intel_encoder *encoder) 85{ 86 return container_of(encoder, struct intel_lvds_encoder, base); 87} 88 89bool intel_lvds_port_enabled(struct drm_i915_private *i915, 90 i915_reg_t lvds_reg, enum pipe *pipe) 91{ 92 u32 val; 93 94 val = intel_de_read(i915, lvds_reg); 95 96 /* asserts want to know the pipe even if the port is disabled */ 97 if (HAS_PCH_CPT(i915)) 98 *pipe = REG_FIELD_GET(LVDS_PIPE_SEL_MASK_CPT, val); 99 else 100 *pipe = REG_FIELD_GET(LVDS_PIPE_SEL_MASK, val); 101 102 return val & LVDS_PORT_EN; 103} 104 105static bool intel_lvds_get_hw_state(struct intel_encoder *encoder, 106 enum pipe *pipe) 107{ 108 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 109 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder); 110 intel_wakeref_t wakeref; 111 bool ret; 112 113 wakeref = intel_display_power_get_if_enabled(i915, encoder->power_domain); 114 if (!wakeref) 115 return false; 116 117 ret = intel_lvds_port_enabled(i915, lvds_encoder->reg, pipe); 118 119 intel_display_power_put(i915, encoder->power_domain, wakeref); 120 121 return ret; 122} 123 124static void intel_lvds_get_config(struct intel_encoder *encoder, 125 struct intel_crtc_state *crtc_state) 126{ 127 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 128 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder); 129 u32 tmp, flags = 0; 130 131 crtc_state->output_types |= BIT(INTEL_OUTPUT_LVDS); 132 133 tmp = intel_de_read(dev_priv, lvds_encoder->reg); 134 if (tmp & LVDS_HSYNC_POLARITY) 135 flags |= DRM_MODE_FLAG_NHSYNC; 136 else 137 flags |= DRM_MODE_FLAG_PHSYNC; 138 if (tmp & LVDS_VSYNC_POLARITY) 139 flags |= DRM_MODE_FLAG_NVSYNC; 140 else 141 flags |= DRM_MODE_FLAG_PVSYNC; 142 143 crtc_state->hw.adjusted_mode.flags |= flags; 144 145 if (DISPLAY_VER(dev_priv) < 5) 146 crtc_state->gmch_pfit.lvds_border_bits = 147 tmp & LVDS_BORDER_ENABLE; 148 149 /* gen2/3 store dither state in pfit control, needs to match */ 150 if (DISPLAY_VER(dev_priv) < 4) { 151 tmp = intel_de_read(dev_priv, PFIT_CONTROL); 152 153 crtc_state->gmch_pfit.control |= tmp & PFIT_PANEL_8TO6_DITHER_ENABLE; 154 } 155 156 crtc_state->hw.adjusted_mode.crtc_clock = crtc_state->port_clock; 157} 158 159static void intel_lvds_pps_get_hw_state(struct drm_i915_private *dev_priv, 160 struct intel_lvds_pps *pps) 161{ 162 u32 val; 163 164 pps->powerdown_on_reset = intel_de_read(dev_priv, PP_CONTROL(0)) & PANEL_POWER_RESET; 165 166 val = intel_de_read(dev_priv, PP_ON_DELAYS(0)); 167 pps->port = REG_FIELD_GET(PANEL_PORT_SELECT_MASK, val); 168 pps->t1_t2 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, val); 169 pps->t5 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, val); 170 171 val = intel_de_read(dev_priv, PP_OFF_DELAYS(0)); 172 pps->t3 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, val); 173 pps->tx = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, val); 174 175 val = intel_de_read(dev_priv, PP_DIVISOR(0)); 176 pps->divider = REG_FIELD_GET(PP_REFERENCE_DIVIDER_MASK, val); 177 val = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, val); 178 /* 179 * Remove the BSpec specified +1 (100ms) offset that accounts for a 180 * too short power-cycle delay due to the asynchronous programming of 181 * the register. 182 */ 183 if (val) 184 val--; 185 /* Convert from 100ms to 100us units */ 186 pps->t4 = val * 1000; 187 188 if (DISPLAY_VER(dev_priv) <= 4 && 189 pps->t1_t2 == 0 && pps->t5 == 0 && pps->t3 == 0 && pps->tx == 0) { 190 drm_dbg_kms(&dev_priv->drm, 191 "Panel power timings uninitialized, " 192 "setting defaults\n"); 193 /* Set T2 to 40ms and T5 to 200ms in 100 usec units */ 194 pps->t1_t2 = 40 * 10; 195 pps->t5 = 200 * 10; 196 /* Set T3 to 35ms and Tx to 200ms in 100 usec units */ 197 pps->t3 = 35 * 10; 198 pps->tx = 200 * 10; 199 } 200 201 drm_dbg(&dev_priv->drm, "LVDS PPS:t1+t2 %d t3 %d t4 %d t5 %d tx %d " 202 "divider %d port %d powerdown_on_reset %d\n", 203 pps->t1_t2, pps->t3, pps->t4, pps->t5, pps->tx, 204 pps->divider, pps->port, pps->powerdown_on_reset); 205} 206 207static void intel_lvds_pps_init_hw(struct drm_i915_private *dev_priv, 208 struct intel_lvds_pps *pps) 209{ 210 u32 val; 211 212 val = intel_de_read(dev_priv, PP_CONTROL(0)); 213 drm_WARN_ON(&dev_priv->drm, 214 (val & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS); 215 if (pps->powerdown_on_reset) 216 val |= PANEL_POWER_RESET; 217 intel_de_write(dev_priv, PP_CONTROL(0), val); 218 219 intel_de_write(dev_priv, PP_ON_DELAYS(0), 220 REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, pps->port) | 221 REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, pps->t1_t2) | 222 REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, pps->t5)); 223 224 intel_de_write(dev_priv, PP_OFF_DELAYS(0), 225 REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, pps->t3) | 226 REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, pps->tx)); 227 228 intel_de_write(dev_priv, PP_DIVISOR(0), 229 REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, pps->divider) | 230 REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(pps->t4, 1000) + 1)); 231} 232 233static void intel_pre_enable_lvds(struct intel_atomic_state *state, 234 struct intel_encoder *encoder, 235 const struct intel_crtc_state *crtc_state, 236 const struct drm_connector_state *conn_state) 237{ 238 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder); 239 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 240 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 241 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 242 enum pipe pipe = crtc->pipe; 243 u32 temp; 244 245 if (HAS_PCH_SPLIT(i915)) { 246 assert_fdi_rx_pll_disabled(i915, pipe); 247 assert_shared_dpll_disabled(i915, crtc_state->shared_dpll); 248 } else { 249 assert_pll_disabled(i915, pipe); 250 } 251 252 intel_lvds_pps_init_hw(i915, &lvds_encoder->init_pps); 253 254 temp = lvds_encoder->init_lvds_val; 255 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; 256 257 if (HAS_PCH_CPT(i915)) { 258 temp &= ~LVDS_PIPE_SEL_MASK_CPT; 259 temp |= LVDS_PIPE_SEL_CPT(pipe); 260 } else { 261 temp &= ~LVDS_PIPE_SEL_MASK; 262 temp |= LVDS_PIPE_SEL(pipe); 263 } 264 265 /* set the corresponsding LVDS_BORDER bit */ 266 temp &= ~LVDS_BORDER_ENABLE; 267 temp |= crtc_state->gmch_pfit.lvds_border_bits; 268 269 /* 270 * Set the B0-B3 data pairs corresponding to whether we're going to 271 * set the DPLLs for dual-channel mode or not. 272 */ 273 if (lvds_encoder->is_dual_link) 274 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; 275 else 276 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); 277 278 /* 279 * It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) 280 * appropriately here, but we need to look more thoroughly into how 281 * panels behave in the two modes. For now, let's just maintain the 282 * value we got from the BIOS. 283 */ 284 temp &= ~LVDS_A3_POWER_MASK; 285 temp |= lvds_encoder->a3_power; 286 287 /* 288 * Set the dithering flag on LVDS as needed, note that there is no 289 * special lvds dither control bit on pch-split platforms, dithering is 290 * only controlled through the TRANSCONF reg. 291 */ 292 if (DISPLAY_VER(i915) == 4) { 293 /* 294 * Bspec wording suggests that LVDS port dithering only exists 295 * for 18bpp panels. 296 */ 297 if (crtc_state->dither && crtc_state->pipe_bpp == 18) 298 temp |= LVDS_ENABLE_DITHER; 299 else 300 temp &= ~LVDS_ENABLE_DITHER; 301 } 302 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY); 303 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) 304 temp |= LVDS_HSYNC_POLARITY; 305 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) 306 temp |= LVDS_VSYNC_POLARITY; 307 308 intel_de_write(i915, lvds_encoder->reg, temp); 309} 310 311/* 312 * Sets the power state for the panel. 313 */ 314static void intel_enable_lvds(struct intel_atomic_state *state, 315 struct intel_encoder *encoder, 316 const struct intel_crtc_state *crtc_state, 317 const struct drm_connector_state *conn_state) 318{ 319 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder); 320 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 321 322 intel_de_rmw(dev_priv, lvds_encoder->reg, 0, LVDS_PORT_EN); 323 324 intel_de_rmw(dev_priv, PP_CONTROL(0), 0, PANEL_POWER_ON); 325 intel_de_posting_read(dev_priv, lvds_encoder->reg); 326 327 if (intel_de_wait_for_set(dev_priv, PP_STATUS(0), PP_ON, 5000)) 328 drm_err(&dev_priv->drm, 329 "timed out waiting for panel to power on\n"); 330 331 intel_backlight_enable(crtc_state, conn_state); 332} 333 334static void intel_disable_lvds(struct intel_atomic_state *state, 335 struct intel_encoder *encoder, 336 const struct intel_crtc_state *old_crtc_state, 337 const struct drm_connector_state *old_conn_state) 338{ 339 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder); 340 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 341 342 intel_de_rmw(dev_priv, PP_CONTROL(0), PANEL_POWER_ON, 0); 343 if (intel_de_wait_for_clear(dev_priv, PP_STATUS(0), PP_ON, 1000)) 344 drm_err(&dev_priv->drm, 345 "timed out waiting for panel to power off\n"); 346 347 intel_de_rmw(dev_priv, lvds_encoder->reg, LVDS_PORT_EN, 0); 348 intel_de_posting_read(dev_priv, lvds_encoder->reg); 349} 350 351static void gmch_disable_lvds(struct intel_atomic_state *state, 352 struct intel_encoder *encoder, 353 const struct intel_crtc_state *old_crtc_state, 354 const struct drm_connector_state *old_conn_state) 355 356{ 357 intel_backlight_disable(old_conn_state); 358 359 intel_disable_lvds(state, encoder, old_crtc_state, old_conn_state); 360} 361 362static void pch_disable_lvds(struct intel_atomic_state *state, 363 struct intel_encoder *encoder, 364 const struct intel_crtc_state *old_crtc_state, 365 const struct drm_connector_state *old_conn_state) 366{ 367 intel_backlight_disable(old_conn_state); 368} 369 370static void pch_post_disable_lvds(struct intel_atomic_state *state, 371 struct intel_encoder *encoder, 372 const struct intel_crtc_state *old_crtc_state, 373 const struct drm_connector_state *old_conn_state) 374{ 375 intel_disable_lvds(state, encoder, old_crtc_state, old_conn_state); 376} 377 378static void intel_lvds_shutdown(struct intel_encoder *encoder) 379{ 380 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 381 382 if (intel_de_wait_for_clear(dev_priv, PP_STATUS(0), PP_CYCLE_DELAY_ACTIVE, 5000)) 383 drm_err(&dev_priv->drm, 384 "timed out waiting for panel power cycle delay\n"); 385} 386 387static enum drm_mode_status 388intel_lvds_mode_valid(struct drm_connector *_connector, 389 struct drm_display_mode *mode) 390{ 391 struct intel_connector *connector = to_intel_connector(_connector); 392 struct drm_i915_private *i915 = to_i915(connector->base.dev); 393 const struct drm_display_mode *fixed_mode = 394 intel_panel_fixed_mode(connector, mode); 395 int max_pixclk = to_i915(connector->base.dev)->max_dotclk_freq; 396 enum drm_mode_status status; 397 398 status = intel_cpu_transcoder_mode_valid(i915, mode); 399 if (status != MODE_OK) 400 return status; 401 402 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 403 return MODE_NO_DBLESCAN; 404 405 status = intel_panel_mode_valid(connector, mode); 406 if (status != MODE_OK) 407 return status; 408 409 if (fixed_mode->clock > max_pixclk) 410 return MODE_CLOCK_HIGH; 411 412 return MODE_OK; 413} 414 415static int intel_lvds_compute_config(struct intel_encoder *encoder, 416 struct intel_crtc_state *crtc_state, 417 struct drm_connector_state *conn_state) 418{ 419 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 420 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder); 421 struct intel_connector *connector = lvds_encoder->attached_connector; 422 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 423 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 424 unsigned int lvds_bpp; 425 int ret; 426 427 /* Should never happen!! */ 428 if (DISPLAY_VER(i915) < 4 && crtc->pipe == 0) { 429 drm_err(&i915->drm, "Can't support LVDS on pipe A\n"); 430 return -EINVAL; 431 } 432 433 if (lvds_encoder->a3_power == LVDS_A3_POWER_UP) 434 lvds_bpp = 8*3; 435 else 436 lvds_bpp = 6*3; 437 438 if (lvds_bpp != crtc_state->pipe_bpp && !crtc_state->bw_constrained) { 439 drm_dbg_kms(&i915->drm, 440 "forcing display bpp (was %d) to LVDS (%d)\n", 441 crtc_state->pipe_bpp, lvds_bpp); 442 crtc_state->pipe_bpp = lvds_bpp; 443 } 444 445 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB; 446 crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB; 447 448 /* 449 * We have timings from the BIOS for the panel, put them in 450 * to the adjusted mode. The CRTC will be set up for this mode, 451 * with the panel scaling set up to source from the H/VDisplay 452 * of the original mode. 453 */ 454 ret = intel_panel_compute_config(connector, adjusted_mode); 455 if (ret) 456 return ret; 457 458 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 459 return -EINVAL; 460 461 if (HAS_PCH_SPLIT(i915)) 462 crtc_state->has_pch_encoder = true; 463 464 ret = intel_panel_fitting(crtc_state, conn_state); 465 if (ret) 466 return ret; 467 468 /* 469 * XXX: It would be nice to support lower refresh rates on the 470 * panels to reduce power consumption, and perhaps match the 471 * user's requested refresh rate. 472 */ 473 474 return 0; 475} 476 477/* 478 * Return the list of DDC modes if available, or the BIOS fixed mode otherwise. 479 */ 480static int intel_lvds_get_modes(struct drm_connector *_connector) 481{ 482 struct intel_connector *connector = to_intel_connector(_connector); 483 const struct drm_edid *fixed_edid = connector->panel.fixed_edid; 484 485 /* Use panel fixed edid if we have one */ 486 if (!IS_ERR_OR_NULL(fixed_edid)) { 487 drm_edid_connector_update(&connector->base, fixed_edid); 488 489 return drm_edid_connector_add_modes(&connector->base); 490 } 491 492 return intel_panel_get_modes(connector); 493} 494 495static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = { 496 .get_modes = intel_lvds_get_modes, 497 .mode_valid = intel_lvds_mode_valid, 498 .atomic_check = intel_digital_connector_atomic_check, 499}; 500 501static const struct drm_connector_funcs intel_lvds_connector_funcs = { 502 .detect = intel_panel_detect, 503 .fill_modes = drm_helper_probe_single_connector_modes, 504 .atomic_get_property = intel_digital_connector_atomic_get_property, 505 .atomic_set_property = intel_digital_connector_atomic_set_property, 506 .late_register = intel_connector_register, 507 .early_unregister = intel_connector_unregister, 508 .destroy = intel_connector_destroy, 509 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 510 .atomic_duplicate_state = intel_digital_connector_duplicate_state, 511}; 512 513static const struct drm_encoder_funcs intel_lvds_enc_funcs = { 514 .destroy = intel_encoder_destroy, 515}; 516 517static int intel_no_lvds_dmi_callback(const struct dmi_system_id *id) 518{ 519 DRM_INFO("Skipping LVDS initialization for %s\n", id->ident); 520 return 1; 521} 522 523/* These systems claim to have LVDS, but really don't */ 524static const struct dmi_system_id intel_no_lvds[] = { 525 { 526 .callback = intel_no_lvds_dmi_callback, 527 .ident = "Apple Mac Mini (Core series)", 528 .matches = { 529 DMI_MATCH(DMI_SYS_VENDOR, "Apple"), 530 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"), 531 }, 532 }, 533 { 534 .callback = intel_no_lvds_dmi_callback, 535 .ident = "Apple Mac Mini (Core 2 series)", 536 .matches = { 537 DMI_MATCH(DMI_SYS_VENDOR, "Apple"), 538 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"), 539 }, 540 }, 541 { 542 .callback = intel_no_lvds_dmi_callback, 543 .ident = "MSI IM-945GSE-A", 544 .matches = { 545 DMI_MATCH(DMI_SYS_VENDOR, "MSI"), 546 DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"), 547 }, 548 }, 549 { 550 .callback = intel_no_lvds_dmi_callback, 551 .ident = "Dell Studio Hybrid", 552 .matches = { 553 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 554 DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"), 555 }, 556 }, 557 { 558 .callback = intel_no_lvds_dmi_callback, 559 .ident = "Dell OptiPlex FX170", 560 .matches = { 561 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 562 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"), 563 }, 564 }, 565 { 566 .callback = intel_no_lvds_dmi_callback, 567 .ident = "AOpen Mini PC", 568 .matches = { 569 DMI_MATCH(DMI_SYS_VENDOR, "AOpen"), 570 DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"), 571 }, 572 }, 573 { 574 .callback = intel_no_lvds_dmi_callback, 575 .ident = "AOpen Mini PC MP915", 576 .matches = { 577 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), 578 DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"), 579 }, 580 }, 581 { 582 .callback = intel_no_lvds_dmi_callback, 583 .ident = "AOpen i915GMm-HFS", 584 .matches = { 585 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), 586 DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"), 587 }, 588 }, 589 { 590 .callback = intel_no_lvds_dmi_callback, 591 .ident = "AOpen i45GMx-I", 592 .matches = { 593 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), 594 DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"), 595 }, 596 }, 597 { 598 .callback = intel_no_lvds_dmi_callback, 599 .ident = "Aopen i945GTt-VFA", 600 .matches = { 601 DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"), 602 }, 603 }, 604 { 605 .callback = intel_no_lvds_dmi_callback, 606 .ident = "Clientron U800", 607 .matches = { 608 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"), 609 DMI_MATCH(DMI_PRODUCT_NAME, "U800"), 610 }, 611 }, 612 { 613 .callback = intel_no_lvds_dmi_callback, 614 .ident = "Clientron E830", 615 .matches = { 616 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"), 617 DMI_MATCH(DMI_PRODUCT_NAME, "E830"), 618 }, 619 }, 620 { 621 .callback = intel_no_lvds_dmi_callback, 622 .ident = "Asus EeeBox PC EB1007", 623 .matches = { 624 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."), 625 DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"), 626 }, 627 }, 628 { 629 .callback = intel_no_lvds_dmi_callback, 630 .ident = "Asus AT5NM10T-I", 631 .matches = { 632 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 633 DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"), 634 }, 635 }, 636 { 637 .callback = intel_no_lvds_dmi_callback, 638 .ident = "Hewlett-Packard HP t5740", 639 .matches = { 640 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), 641 DMI_MATCH(DMI_PRODUCT_NAME, " t5740"), 642 }, 643 }, 644 { 645 .callback = intel_no_lvds_dmi_callback, 646 .ident = "Hewlett-Packard t5745", 647 .matches = { 648 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), 649 DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"), 650 }, 651 }, 652 { 653 .callback = intel_no_lvds_dmi_callback, 654 .ident = "Hewlett-Packard st5747", 655 .matches = { 656 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), 657 DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"), 658 }, 659 }, 660 { 661 .callback = intel_no_lvds_dmi_callback, 662 .ident = "MSI Wind Box DC500", 663 .matches = { 664 DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"), 665 DMI_MATCH(DMI_BOARD_NAME, "MS-7469"), 666 }, 667 }, 668 { 669 .callback = intel_no_lvds_dmi_callback, 670 .ident = "Gigabyte GA-D525TUD", 671 .matches = { 672 DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."), 673 DMI_MATCH(DMI_BOARD_NAME, "D525TUD"), 674 }, 675 }, 676 { 677 .callback = intel_no_lvds_dmi_callback, 678 .ident = "Supermicro X7SPA-H", 679 .matches = { 680 DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"), 681 DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"), 682 }, 683 }, 684 { 685 .callback = intel_no_lvds_dmi_callback, 686 .ident = "Fujitsu Esprimo Q900", 687 .matches = { 688 DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"), 689 DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO Q900"), 690 }, 691 }, 692 { 693 .callback = intel_no_lvds_dmi_callback, 694 .ident = "Intel D410PT", 695 .matches = { 696 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), 697 DMI_MATCH(DMI_BOARD_NAME, "D410PT"), 698 }, 699 }, 700 { 701 .callback = intel_no_lvds_dmi_callback, 702 .ident = "Intel D425KT", 703 .matches = { 704 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), 705 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D425KT"), 706 }, 707 }, 708 { 709 .callback = intel_no_lvds_dmi_callback, 710 .ident = "Intel D510MO", 711 .matches = { 712 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), 713 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D510MO"), 714 }, 715 }, 716 { 717 .callback = intel_no_lvds_dmi_callback, 718 .ident = "Intel D525MW", 719 .matches = { 720 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), 721 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D525MW"), 722 }, 723 }, 724 { 725 .callback = intel_no_lvds_dmi_callback, 726 .ident = "Radiant P845", 727 .matches = { 728 DMI_MATCH(DMI_SYS_VENDOR, "Radiant Systems Inc"), 729 DMI_MATCH(DMI_PRODUCT_NAME, "P845"), 730 }, 731 }, 732 733 { } /* terminating entry */ 734}; 735 736static int intel_dual_link_lvds_callback(const struct dmi_system_id *id) 737{ 738 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident); 739 return 1; 740} 741 742static const struct dmi_system_id intel_dual_link_lvds[] = { 743 { 744 .callback = intel_dual_link_lvds_callback, 745 .ident = "Apple MacBook Pro 15\" (2010)", 746 .matches = { 747 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), 748 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro6,2"), 749 }, 750 }, 751 { 752 .callback = intel_dual_link_lvds_callback, 753 .ident = "Apple MacBook Pro 15\" (2011)", 754 .matches = { 755 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), 756 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"), 757 }, 758 }, 759 { 760 .callback = intel_dual_link_lvds_callback, 761 .ident = "Apple MacBook Pro 15\" (2012)", 762 .matches = { 763 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), 764 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro9,1"), 765 }, 766 }, 767 { } /* terminating entry */ 768}; 769 770struct intel_encoder *intel_get_lvds_encoder(struct drm_i915_private *i915) 771{ 772 struct intel_encoder *encoder; 773 774 for_each_intel_encoder(&i915->drm, encoder) { 775 if (encoder->type == INTEL_OUTPUT_LVDS) 776 return encoder; 777 } 778 779 return NULL; 780} 781 782bool intel_is_dual_link_lvds(struct drm_i915_private *i915) 783{ 784 struct intel_encoder *encoder = intel_get_lvds_encoder(i915); 785 786 return encoder && to_lvds_encoder(encoder)->is_dual_link; 787} 788 789static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder) 790{ 791 struct drm_i915_private *i915 = to_i915(lvds_encoder->base.base.dev); 792 struct intel_connector *connector = lvds_encoder->attached_connector; 793 const struct drm_display_mode *fixed_mode = 794 intel_panel_preferred_fixed_mode(connector); 795 unsigned int val; 796 797 /* use the module option value if specified */ 798 if (i915->params.lvds_channel_mode > 0) 799 return i915->params.lvds_channel_mode == 2; 800 801 /* single channel LVDS is limited to 112 MHz */ 802 if (fixed_mode->clock > 112999) 803 return true; 804 805 if (dmi_check_system(intel_dual_link_lvds)) 806 return true; 807 808 /* 809 * BIOS should set the proper LVDS register value at boot, but 810 * in reality, it doesn't set the value when the lid is closed; 811 * we need to check "the value to be set" in VBT when LVDS 812 * register is uninitialized. 813 */ 814 val = intel_de_read(i915, lvds_encoder->reg); 815 if (HAS_PCH_CPT(i915)) 816 val &= ~(LVDS_DETECTED | LVDS_PIPE_SEL_MASK_CPT); 817 else 818 val &= ~(LVDS_DETECTED | LVDS_PIPE_SEL_MASK); 819 if (val == 0) 820 val = connector->panel.vbt.bios_lvds_val; 821 822 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP; 823} 824 825static void intel_lvds_add_properties(struct drm_connector *connector) 826{ 827 intel_attach_scaling_mode_property(connector); 828} 829 830/** 831 * intel_lvds_init - setup LVDS connectors on this device 832 * @i915: i915 device 833 * 834 * Create the connector, register the LVDS DDC bus, and try to figure out what 835 * modes we can display on the LVDS panel (if present). 836 */ 837void intel_lvds_init(struct drm_i915_private *i915) 838{ 839 struct intel_lvds_encoder *lvds_encoder; 840 struct intel_connector *connector; 841 const struct drm_edid *drm_edid; 842 struct intel_encoder *encoder; 843 i915_reg_t lvds_reg; 844 u32 lvds; 845 u8 pin; 846 847 /* Skip init on machines we know falsely report LVDS */ 848 if (dmi_check_system(intel_no_lvds)) { 849 drm_WARN(&i915->drm, !i915->display.vbt.int_lvds_support, 850 "Useless DMI match. Internal LVDS support disabled by VBT\n"); 851 return; 852 } 853 854 if (!i915->display.vbt.int_lvds_support) { 855 drm_dbg_kms(&i915->drm, 856 "Internal LVDS support disabled by VBT\n"); 857 return; 858 } 859 860 if (HAS_PCH_SPLIT(i915)) 861 lvds_reg = PCH_LVDS; 862 else 863 lvds_reg = LVDS; 864 865 lvds = intel_de_read(i915, lvds_reg); 866 867 if (HAS_PCH_SPLIT(i915)) { 868 if ((lvds & LVDS_DETECTED) == 0) 869 return; 870 } 871 872 pin = GMBUS_PIN_PANEL; 873 if (!intel_bios_is_lvds_present(i915, &pin)) { 874 if ((lvds & LVDS_PORT_EN) == 0) { 875 drm_dbg_kms(&i915->drm, 876 "LVDS is not present in VBT\n"); 877 return; 878 } 879 drm_dbg_kms(&i915->drm, 880 "LVDS is not present in VBT, but enabled anyway\n"); 881 } 882 883 lvds_encoder = kzalloc(sizeof(*lvds_encoder), GFP_KERNEL); 884 if (!lvds_encoder) 885 return; 886 887 connector = intel_connector_alloc(); 888 if (!connector) { 889 kfree(lvds_encoder); 890 return; 891 } 892 893 lvds_encoder->attached_connector = connector; 894 encoder = &lvds_encoder->base; 895 896 drm_connector_init(&i915->drm, &connector->base, &intel_lvds_connector_funcs, 897 DRM_MODE_CONNECTOR_LVDS); 898 899 drm_encoder_init(&i915->drm, &encoder->base, &intel_lvds_enc_funcs, 900 DRM_MODE_ENCODER_LVDS, "LVDS"); 901 902 encoder->enable = intel_enable_lvds; 903 encoder->pre_enable = intel_pre_enable_lvds; 904 encoder->compute_config = intel_lvds_compute_config; 905 if (HAS_PCH_SPLIT(i915)) { 906 encoder->disable = pch_disable_lvds; 907 encoder->post_disable = pch_post_disable_lvds; 908 } else { 909 encoder->disable = gmch_disable_lvds; 910 } 911 encoder->get_hw_state = intel_lvds_get_hw_state; 912 encoder->get_config = intel_lvds_get_config; 913 encoder->update_pipe = intel_backlight_update; 914 encoder->shutdown = intel_lvds_shutdown; 915 connector->get_hw_state = intel_connector_get_hw_state; 916 917 intel_connector_attach_encoder(connector, encoder); 918 919 encoder->type = INTEL_OUTPUT_LVDS; 920 encoder->power_domain = POWER_DOMAIN_PORT_OTHER; 921 encoder->port = PORT_NONE; 922 encoder->cloneable = 0; 923 if (DISPLAY_VER(i915) < 4) 924 encoder->pipe_mask = BIT(PIPE_B); 925 else 926 encoder->pipe_mask = ~0; 927 928 drm_connector_helper_add(&connector->base, &intel_lvds_connector_helper_funcs); 929 connector->base.display_info.subpixel_order = SubPixelHorizontalRGB; 930 931 lvds_encoder->reg = lvds_reg; 932 933 intel_lvds_add_properties(&connector->base); 934 935 intel_lvds_pps_get_hw_state(i915, &lvds_encoder->init_pps); 936 lvds_encoder->init_lvds_val = lvds; 937 938 /* 939 * LVDS discovery: 940 * 1) check for EDID on DDC 941 * 2) check for VBT data 942 * 3) check to see if LVDS is already on 943 * if none of the above, no panel 944 */ 945 946 /* 947 * Attempt to get the fixed panel mode from DDC. Assume that the 948 * preferred mode is the right one. 949 */ 950 mutex_lock(&i915->drm.mode_config.mutex); 951 if (vga_switcheroo_handler_flags() & VGA_SWITCHEROO_CAN_SWITCH_DDC) { 952 drm_edid = drm_edid_read_switcheroo(&connector->base, 953 intel_gmbus_get_adapter(i915, pin)); 954 } else { 955 drm_edid = drm_edid_read_ddc(&connector->base, 956 intel_gmbus_get_adapter(i915, pin)); 957 } 958 if (drm_edid) { 959 if (drm_edid_connector_update(&connector->base, drm_edid) || 960 !drm_edid_connector_add_modes(&connector->base)) { 961 drm_edid_connector_update(&connector->base, NULL); 962 drm_edid_free(drm_edid); 963 drm_edid = ERR_PTR(-EINVAL); 964 } 965 } else { 966 drm_edid = ERR_PTR(-ENOENT); 967 } 968 intel_bios_init_panel_late(i915, &connector->panel, NULL, 969 IS_ERR(drm_edid) ? NULL : drm_edid); 970 971 /* Try EDID first */ 972 intel_panel_add_edid_fixed_modes(connector, true); 973 974 /* Failed to get EDID, what about VBT? */ 975 if (!intel_panel_preferred_fixed_mode(connector)) 976 intel_panel_add_vbt_lfp_fixed_mode(connector); 977 978 /* 979 * If we didn't get a fixed mode from EDID or VBT, try checking 980 * if the panel is already turned on. If so, assume that 981 * whatever is currently programmed is the correct mode. 982 */ 983 if (!intel_panel_preferred_fixed_mode(connector)) 984 intel_panel_add_encoder_fixed_mode(connector, encoder); 985 986 mutex_unlock(&i915->drm.mode_config.mutex); 987 988 /* If we still don't have a mode after all that, give up. */ 989 if (!intel_panel_preferred_fixed_mode(connector)) 990 goto failed; 991 992 intel_panel_init(connector, drm_edid); 993 994 intel_backlight_setup(connector, INVALID_PIPE); 995 996 lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder); 997 drm_dbg_kms(&i915->drm, "detected %s-link lvds configuration\n", 998 lvds_encoder->is_dual_link ? "dual" : "single"); 999 1000 lvds_encoder->a3_power = lvds & LVDS_A3_POWER_MASK; 1001 1002 return; 1003 1004failed: 1005 drm_dbg_kms(&i915->drm, "No LVDS modes found, disabling.\n"); 1006 drm_connector_cleanup(&connector->base); 1007 drm_encoder_cleanup(&encoder->base); 1008 kfree(lvds_encoder); 1009 intel_connector_free(connector); 1010 return; 1011} 1012