1// SPDX-License-Identifier: MIT 2/* 3 * Copyright © 2021 Intel Corporation 4 */ 5 6#include <drm/drm_blend.h> 7#include <drm/drm_framebuffer.h> 8#include <drm/drm_modeset_helper.h> 9 10#include "i915_drv.h" 11#include "intel_display.h" 12#include "intel_display_types.h" 13#include "intel_dpt.h" 14#include "intel_fb.h" 15 16#define check_array_bounds(i915, a, i) drm_WARN_ON(&(i915)->drm, (i) >= ARRAY_SIZE(a)) 17 18/* 19 * From the Sky Lake PRM: 20 * "The Color Control Surface (CCS) contains the compression status of 21 * the cache-line pairs. The compression state of the cache-line pair 22 * is specified by 2 bits in the CCS. Each CCS cache-line represents 23 * an area on the main surface of 16 x16 sets of 128 byte Y-tiled 24 * cache-line-pairs. CCS is always Y tiled." 25 * 26 * Since cache line pairs refers to horizontally adjacent cache lines, 27 * each cache line in the CCS corresponds to an area of 32x16 cache 28 * lines on the main surface. Since each pixel is 4 bytes, this gives 29 * us a ratio of one byte in the CCS for each 8x16 pixels in the 30 * main surface. 31 */ 32static const struct drm_format_info skl_ccs_formats[] = { 33 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2, 34 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, }, 35 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2, 36 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, }, 37 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2, 38 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, }, 39 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2, 40 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, }, 41}; 42 43/* 44 * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the 45 * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles 46 * in the main surface. With 4 byte pixels and each Y-tile having dimensions of 47 * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2x32 pixels in 48 * the main surface. 49 */ 50static const struct drm_format_info gen12_ccs_formats[] = { 51 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2, 52 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, 53 .hsub = 1, .vsub = 1, }, 54 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2, 55 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, 56 .hsub = 1, .vsub = 1, }, 57 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2, 58 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, 59 .hsub = 1, .vsub = 1, .has_alpha = true }, 60 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2, 61 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, 62 .hsub = 1, .vsub = 1, .has_alpha = true }, 63 { .format = DRM_FORMAT_YUYV, .num_planes = 2, 64 .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, 65 .hsub = 2, .vsub = 1, .is_yuv = true }, 66 { .format = DRM_FORMAT_YVYU, .num_planes = 2, 67 .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, 68 .hsub = 2, .vsub = 1, .is_yuv = true }, 69 { .format = DRM_FORMAT_UYVY, .num_planes = 2, 70 .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, 71 .hsub = 2, .vsub = 1, .is_yuv = true }, 72 { .format = DRM_FORMAT_VYUY, .num_planes = 2, 73 .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, 74 .hsub = 2, .vsub = 1, .is_yuv = true }, 75 { .format = DRM_FORMAT_XYUV8888, .num_planes = 2, 76 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, 77 .hsub = 1, .vsub = 1, .is_yuv = true }, 78 { .format = DRM_FORMAT_NV12, .num_planes = 4, 79 .char_per_block = { 1, 2, 1, 1 }, .block_w = { 1, 1, 4, 4 }, .block_h = { 1, 1, 1, 1 }, 80 .hsub = 2, .vsub = 2, .is_yuv = true }, 81 { .format = DRM_FORMAT_P010, .num_planes = 4, 82 .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 }, 83 .hsub = 2, .vsub = 2, .is_yuv = true }, 84 { .format = DRM_FORMAT_P012, .num_planes = 4, 85 .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 }, 86 .hsub = 2, .vsub = 2, .is_yuv = true }, 87 { .format = DRM_FORMAT_P016, .num_planes = 4, 88 .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 }, 89 .hsub = 2, .vsub = 2, .is_yuv = true }, 90}; 91 92/* 93 * Same as gen12_ccs_formats[] above, but with additional surface used 94 * to pass Clear Color information in plane 2 with 64 bits of data. 95 */ 96static const struct drm_format_info gen12_ccs_cc_formats[] = { 97 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 3, 98 .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 }, 99 .hsub = 1, .vsub = 1, }, 100 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 3, 101 .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 }, 102 .hsub = 1, .vsub = 1, }, 103 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 3, 104 .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 }, 105 .hsub = 1, .vsub = 1, .has_alpha = true }, 106 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 3, 107 .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 }, 108 .hsub = 1, .vsub = 1, .has_alpha = true }, 109}; 110 111static const struct drm_format_info gen12_flat_ccs_cc_formats[] = { 112 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2, 113 .char_per_block = { 4, 0 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, 114 .hsub = 1, .vsub = 1, }, 115 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2, 116 .char_per_block = { 4, 0 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, 117 .hsub = 1, .vsub = 1, }, 118 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2, 119 .char_per_block = { 4, 0 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, 120 .hsub = 1, .vsub = 1, .has_alpha = true }, 121 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2, 122 .char_per_block = { 4, 0 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, 123 .hsub = 1, .vsub = 1, .has_alpha = true }, 124}; 125 126struct intel_modifier_desc { 127 u64 modifier; 128 struct { 129 u8 from; 130 u8 until; 131 } display_ver; 132#define DISPLAY_VER_ALL { 0, -1 } 133 134 const struct drm_format_info *formats; 135 int format_count; 136#define FORMAT_OVERRIDE(format_list) \ 137 .formats = format_list, \ 138 .format_count = ARRAY_SIZE(format_list) 139 140 u8 plane_caps; 141 142 struct { 143 u8 cc_planes:3; 144 u8 packed_aux_planes:4; 145 u8 planar_aux_planes:4; 146 } ccs; 147}; 148 149#define INTEL_PLANE_CAP_CCS_MASK (INTEL_PLANE_CAP_CCS_RC | \ 150 INTEL_PLANE_CAP_CCS_RC_CC | \ 151 INTEL_PLANE_CAP_CCS_MC) 152#define INTEL_PLANE_CAP_TILING_MASK (INTEL_PLANE_CAP_TILING_X | \ 153 INTEL_PLANE_CAP_TILING_Y | \ 154 INTEL_PLANE_CAP_TILING_Yf | \ 155 INTEL_PLANE_CAP_TILING_4) 156#define INTEL_PLANE_CAP_TILING_NONE 0 157 158static const struct intel_modifier_desc intel_modifiers[] = { 159 { 160 .modifier = I915_FORMAT_MOD_4_TILED_MTL_MC_CCS, 161 .display_ver = { 14, 14 }, 162 .plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_MC, 163 164 .ccs.packed_aux_planes = BIT(1), 165 .ccs.planar_aux_planes = BIT(2) | BIT(3), 166 167 FORMAT_OVERRIDE(gen12_ccs_formats), 168 }, { 169 .modifier = I915_FORMAT_MOD_4_TILED_MTL_RC_CCS, 170 .display_ver = { 14, 14 }, 171 .plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_RC, 172 173 .ccs.packed_aux_planes = BIT(1), 174 175 FORMAT_OVERRIDE(gen12_ccs_formats), 176 }, { 177 .modifier = I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC, 178 .display_ver = { 14, 14 }, 179 .plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_RC_CC, 180 181 .ccs.cc_planes = BIT(2), 182 .ccs.packed_aux_planes = BIT(1), 183 184 FORMAT_OVERRIDE(gen12_ccs_cc_formats), 185 }, { 186 .modifier = I915_FORMAT_MOD_4_TILED_DG2_MC_CCS, 187 .display_ver = { 13, 13 }, 188 .plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_MC, 189 }, { 190 .modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC, 191 .display_ver = { 13, 13 }, 192 .plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_RC_CC, 193 194 .ccs.cc_planes = BIT(1), 195 196 FORMAT_OVERRIDE(gen12_flat_ccs_cc_formats), 197 }, { 198 .modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS, 199 .display_ver = { 13, 13 }, 200 .plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_RC, 201 }, { 202 .modifier = I915_FORMAT_MOD_4_TILED, 203 .display_ver = { 13, -1 }, 204 .plane_caps = INTEL_PLANE_CAP_TILING_4, 205 }, { 206 .modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS, 207 .display_ver = { 12, 13 }, 208 .plane_caps = INTEL_PLANE_CAP_TILING_Y | INTEL_PLANE_CAP_CCS_MC, 209 210 .ccs.packed_aux_planes = BIT(1), 211 .ccs.planar_aux_planes = BIT(2) | BIT(3), 212 213 FORMAT_OVERRIDE(gen12_ccs_formats), 214 }, { 215 .modifier = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS, 216 .display_ver = { 12, 13 }, 217 .plane_caps = INTEL_PLANE_CAP_TILING_Y | INTEL_PLANE_CAP_CCS_RC, 218 219 .ccs.packed_aux_planes = BIT(1), 220 221 FORMAT_OVERRIDE(gen12_ccs_formats), 222 }, { 223 .modifier = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC, 224 .display_ver = { 12, 13 }, 225 .plane_caps = INTEL_PLANE_CAP_TILING_Y | INTEL_PLANE_CAP_CCS_RC_CC, 226 227 .ccs.cc_planes = BIT(2), 228 .ccs.packed_aux_planes = BIT(1), 229 230 FORMAT_OVERRIDE(gen12_ccs_cc_formats), 231 }, { 232 .modifier = I915_FORMAT_MOD_Yf_TILED_CCS, 233 .display_ver = { 9, 11 }, 234 .plane_caps = INTEL_PLANE_CAP_TILING_Yf | INTEL_PLANE_CAP_CCS_RC, 235 236 .ccs.packed_aux_planes = BIT(1), 237 238 FORMAT_OVERRIDE(skl_ccs_formats), 239 }, { 240 .modifier = I915_FORMAT_MOD_Y_TILED_CCS, 241 .display_ver = { 9, 11 }, 242 .plane_caps = INTEL_PLANE_CAP_TILING_Y | INTEL_PLANE_CAP_CCS_RC, 243 244 .ccs.packed_aux_planes = BIT(1), 245 246 FORMAT_OVERRIDE(skl_ccs_formats), 247 }, { 248 .modifier = I915_FORMAT_MOD_Yf_TILED, 249 .display_ver = { 9, 11 }, 250 .plane_caps = INTEL_PLANE_CAP_TILING_Yf, 251 }, { 252 .modifier = I915_FORMAT_MOD_Y_TILED, 253 .display_ver = { 9, 13 }, 254 .plane_caps = INTEL_PLANE_CAP_TILING_Y, 255 }, { 256 .modifier = I915_FORMAT_MOD_X_TILED, 257 .display_ver = DISPLAY_VER_ALL, 258 .plane_caps = INTEL_PLANE_CAP_TILING_X, 259 }, { 260 .modifier = DRM_FORMAT_MOD_LINEAR, 261 .display_ver = DISPLAY_VER_ALL, 262 }, 263}; 264 265static const struct intel_modifier_desc *lookup_modifier_or_null(u64 modifier) 266{ 267 int i; 268 269 for (i = 0; i < ARRAY_SIZE(intel_modifiers); i++) 270 if (intel_modifiers[i].modifier == modifier) 271 return &intel_modifiers[i]; 272 273 return NULL; 274} 275 276static const struct intel_modifier_desc *lookup_modifier(u64 modifier) 277{ 278 const struct intel_modifier_desc *md = lookup_modifier_or_null(modifier); 279 280 if (WARN_ON(!md)) 281 return &intel_modifiers[0]; 282 283 return md; 284} 285 286static const struct drm_format_info * 287lookup_format_info(const struct drm_format_info formats[], 288 int num_formats, u32 format) 289{ 290 int i; 291 292 for (i = 0; i < num_formats; i++) { 293 if (formats[i].format == format) 294 return &formats[i]; 295 } 296 297 return NULL; 298} 299 300/** 301 * intel_fb_get_format_info: Get a modifier specific format information 302 * @cmd: FB add command structure 303 * 304 * Returns: 305 * Returns the format information for @cmd->pixel_format specific to @cmd->modifier[0], 306 * or %NULL if the modifier doesn't override the format. 307 */ 308const struct drm_format_info * 309intel_fb_get_format_info(const struct drm_mode_fb_cmd2 *cmd) 310{ 311 const struct intel_modifier_desc *md = lookup_modifier_or_null(cmd->modifier[0]); 312 313 if (!md || !md->formats) 314 return NULL; 315 316 return lookup_format_info(md->formats, md->format_count, cmd->pixel_format); 317} 318 319static bool plane_caps_contain_any(u8 caps, u8 mask) 320{ 321 return caps & mask; 322} 323 324static bool plane_caps_contain_all(u8 caps, u8 mask) 325{ 326 return (caps & mask) == mask; 327} 328 329/** 330 * intel_fb_is_tiled_modifier: Check if a modifier is a tiled modifier type 331 * @modifier: Modifier to check 332 * 333 * Returns: 334 * Returns %true if @modifier is a tiled modifier. 335 */ 336bool intel_fb_is_tiled_modifier(u64 modifier) 337{ 338 return plane_caps_contain_any(lookup_modifier(modifier)->plane_caps, 339 INTEL_PLANE_CAP_TILING_MASK); 340} 341 342/** 343 * intel_fb_is_ccs_modifier: Check if a modifier is a CCS modifier type 344 * @modifier: Modifier to check 345 * 346 * Returns: 347 * Returns %true if @modifier is a render, render with color clear or 348 * media compression modifier. 349 */ 350bool intel_fb_is_ccs_modifier(u64 modifier) 351{ 352 return plane_caps_contain_any(lookup_modifier(modifier)->plane_caps, 353 INTEL_PLANE_CAP_CCS_MASK); 354} 355 356/** 357 * intel_fb_is_rc_ccs_cc_modifier: Check if a modifier is an RC CCS CC modifier type 358 * @modifier: Modifier to check 359 * 360 * Returns: 361 * Returns %true if @modifier is a render with color clear modifier. 362 */ 363bool intel_fb_is_rc_ccs_cc_modifier(u64 modifier) 364{ 365 return plane_caps_contain_any(lookup_modifier(modifier)->plane_caps, 366 INTEL_PLANE_CAP_CCS_RC_CC); 367} 368 369/** 370 * intel_fb_is_mc_ccs_modifier: Check if a modifier is an MC CCS modifier type 371 * @modifier: Modifier to check 372 * 373 * Returns: 374 * Returns %true if @modifier is a media compression modifier. 375 */ 376bool intel_fb_is_mc_ccs_modifier(u64 modifier) 377{ 378 return plane_caps_contain_any(lookup_modifier(modifier)->plane_caps, 379 INTEL_PLANE_CAP_CCS_MC); 380} 381 382static bool check_modifier_display_ver_range(const struct intel_modifier_desc *md, 383 u8 display_ver_from, u8 display_ver_until) 384{ 385 return md->display_ver.from <= display_ver_until && 386 display_ver_from <= md->display_ver.until; 387} 388 389static bool plane_has_modifier(struct drm_i915_private *i915, 390 u8 plane_caps, 391 const struct intel_modifier_desc *md) 392{ 393 if (!IS_DISPLAY_VER(i915, md->display_ver.from, md->display_ver.until)) 394 return false; 395 396 if (!plane_caps_contain_all(plane_caps, md->plane_caps)) 397 return false; 398 399 /* 400 * Separate AuxCCS and Flat CCS modifiers to be run only on platforms 401 * where supported. 402 */ 403 if (intel_fb_is_ccs_modifier(md->modifier) && 404 HAS_FLAT_CCS(i915) != !md->ccs.packed_aux_planes) 405 return false; 406 407 return true; 408} 409 410/** 411 * intel_fb_plane_get_modifiers: Get the modifiers for the given platform and plane capabilities 412 * @i915: i915 device instance 413 * @plane_caps: capabilities for the plane the modifiers are queried for 414 * 415 * Returns: 416 * Returns the list of modifiers allowed by the @i915 platform and @plane_caps. 417 * The caller must free the returned buffer. 418 */ 419u64 *intel_fb_plane_get_modifiers(struct drm_i915_private *i915, 420 u8 plane_caps) 421{ 422 u64 *list, *p; 423 int count = 1; /* +1 for invalid modifier terminator */ 424 int i; 425 426 for (i = 0; i < ARRAY_SIZE(intel_modifiers); i++) { 427 if (plane_has_modifier(i915, plane_caps, &intel_modifiers[i])) 428 count++; 429 } 430 431 list = kmalloc_array(count, sizeof(*list), GFP_KERNEL); 432 if (drm_WARN_ON(&i915->drm, !list)) 433 return NULL; 434 435 p = list; 436 for (i = 0; i < ARRAY_SIZE(intel_modifiers); i++) { 437 if (plane_has_modifier(i915, plane_caps, &intel_modifiers[i])) 438 *p++ = intel_modifiers[i].modifier; 439 } 440 *p++ = DRM_FORMAT_MOD_INVALID; 441 442 return list; 443} 444 445/** 446 * intel_fb_plane_supports_modifier: Determine if a modifier is supported by the given plane 447 * @plane: Plane to check the modifier support for 448 * @modifier: The modifier to check the support for 449 * 450 * Returns: 451 * %true if the @modifier is supported on @plane. 452 */ 453bool intel_fb_plane_supports_modifier(struct intel_plane *plane, u64 modifier) 454{ 455 int i; 456 457 for (i = 0; i < plane->base.modifier_count; i++) 458 if (plane->base.modifiers[i] == modifier) 459 return true; 460 461 return false; 462} 463 464static bool format_is_yuv_semiplanar(const struct intel_modifier_desc *md, 465 const struct drm_format_info *info) 466{ 467 if (!info->is_yuv) 468 return false; 469 470 if (hweight8(md->ccs.planar_aux_planes) == 2) 471 return info->num_planes == 4; 472 else 473 return info->num_planes == 2; 474} 475 476/** 477 * intel_format_info_is_yuv_semiplanar: Check if the given format is YUV semiplanar 478 * @info: format to check 479 * @modifier: modifier used with the format 480 * 481 * Returns: 482 * %true if @info / @modifier is YUV semiplanar. 483 */ 484bool intel_format_info_is_yuv_semiplanar(const struct drm_format_info *info, 485 u64 modifier) 486{ 487 return format_is_yuv_semiplanar(lookup_modifier(modifier), info); 488} 489 490static u8 ccs_aux_plane_mask(const struct intel_modifier_desc *md, 491 const struct drm_format_info *format) 492{ 493 if (format_is_yuv_semiplanar(md, format)) 494 return md->ccs.planar_aux_planes; 495 else 496 return md->ccs.packed_aux_planes; 497} 498 499/** 500 * intel_fb_is_ccs_aux_plane: Check if a framebuffer color plane is a CCS AUX plane 501 * @fb: Framebuffer 502 * @color_plane: color plane index to check 503 * 504 * Returns: 505 * Returns %true if @fb's color plane at index @color_plane is a CCS AUX plane. 506 */ 507bool intel_fb_is_ccs_aux_plane(const struct drm_framebuffer *fb, int color_plane) 508{ 509 const struct intel_modifier_desc *md = lookup_modifier(fb->modifier); 510 511 return ccs_aux_plane_mask(md, fb->format) & BIT(color_plane); 512} 513 514/** 515 * intel_fb_is_gen12_ccs_aux_plane: Check if a framebuffer color plane is a GEN12 CCS AUX plane 516 * @fb: Framebuffer 517 * @color_plane: color plane index to check 518 * 519 * Returns: 520 * Returns %true if @fb's color plane at index @color_plane is a GEN12 CCS AUX plane. 521 */ 522static bool intel_fb_is_gen12_ccs_aux_plane(const struct drm_framebuffer *fb, int color_plane) 523{ 524 const struct intel_modifier_desc *md = lookup_modifier(fb->modifier); 525 526 return check_modifier_display_ver_range(md, 12, 14) && 527 ccs_aux_plane_mask(md, fb->format) & BIT(color_plane); 528} 529 530/** 531 * intel_fb_rc_ccs_cc_plane: Get the CCS CC color plane index for a framebuffer 532 * @fb: Framebuffer 533 * 534 * Returns: 535 * Returns the index of the color clear plane for @fb, or -1 if @fb is not a 536 * framebuffer using a render compression/color clear modifier. 537 */ 538int intel_fb_rc_ccs_cc_plane(const struct drm_framebuffer *fb) 539{ 540 const struct intel_modifier_desc *md = lookup_modifier(fb->modifier); 541 542 if (!md->ccs.cc_planes) 543 return -1; 544 545 drm_WARN_ON_ONCE(fb->dev, hweight8(md->ccs.cc_planes) > 1); 546 547 return ilog2((int)md->ccs.cc_planes); 548} 549 550static bool is_gen12_ccs_cc_plane(const struct drm_framebuffer *fb, int color_plane) 551{ 552 return intel_fb_rc_ccs_cc_plane(fb) == color_plane; 553} 554 555static bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb, int color_plane) 556{ 557 return intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) && 558 color_plane == 1; 559} 560 561bool is_surface_linear(const struct drm_framebuffer *fb, int color_plane) 562{ 563 return fb->modifier == DRM_FORMAT_MOD_LINEAR || 564 intel_fb_is_gen12_ccs_aux_plane(fb, color_plane) || 565 is_gen12_ccs_cc_plane(fb, color_plane); 566} 567 568int main_to_ccs_plane(const struct drm_framebuffer *fb, int main_plane) 569{ 570 drm_WARN_ON(fb->dev, !intel_fb_is_ccs_modifier(fb->modifier) || 571 (main_plane && main_plane >= fb->format->num_planes / 2)); 572 573 return fb->format->num_planes / 2 + main_plane; 574} 575 576int skl_ccs_to_main_plane(const struct drm_framebuffer *fb, int ccs_plane) 577{ 578 drm_WARN_ON(fb->dev, !intel_fb_is_ccs_modifier(fb->modifier) || 579 ccs_plane < fb->format->num_planes / 2); 580 581 if (is_gen12_ccs_cc_plane(fb, ccs_plane)) 582 return 0; 583 584 return ccs_plane - fb->format->num_planes / 2; 585} 586 587static unsigned int gen12_ccs_aux_stride(struct intel_framebuffer *fb, int ccs_plane) 588{ 589 int main_plane = skl_ccs_to_main_plane(&fb->base, ccs_plane); 590 unsigned int main_stride = fb->base.pitches[main_plane]; 591 unsigned int main_tile_width = intel_tile_width_bytes(&fb->base, main_plane); 592 593 return DIV_ROUND_UP(main_stride, 4 * main_tile_width) * 64; 594} 595 596int skl_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane) 597{ 598 const struct intel_modifier_desc *md = lookup_modifier(fb->modifier); 599 struct drm_i915_private *i915 = to_i915(fb->dev); 600 601 if (md->ccs.packed_aux_planes | md->ccs.planar_aux_planes) 602 return main_to_ccs_plane(fb, main_plane); 603 else if (DISPLAY_VER(i915) < 11 && 604 format_is_yuv_semiplanar(md, fb->format)) 605 return 1; 606 else 607 return 0; 608} 609 610unsigned int intel_tile_size(const struct drm_i915_private *i915) 611{ 612 return DISPLAY_VER(i915) == 2 ? 2048 : 4096; 613} 614 615unsigned int 616intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane) 617{ 618 struct drm_i915_private *dev_priv = to_i915(fb->dev); 619 unsigned int cpp = fb->format->cpp[color_plane]; 620 621 switch (fb->modifier) { 622 case DRM_FORMAT_MOD_LINEAR: 623 return intel_tile_size(dev_priv); 624 case I915_FORMAT_MOD_X_TILED: 625 if (DISPLAY_VER(dev_priv) == 2) 626 return 128; 627 else 628 return 512; 629 case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS: 630 case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC: 631 case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS: 632 case I915_FORMAT_MOD_4_TILED: 633 /* 634 * Each 4K tile consists of 64B(8*8) subtiles, with 635 * same shape as Y Tile(i.e 4*16B OWords) 636 */ 637 return 128; 638 case I915_FORMAT_MOD_Y_TILED_CCS: 639 if (intel_fb_is_ccs_aux_plane(fb, color_plane)) 640 return 128; 641 fallthrough; 642 case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS: 643 case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC: 644 case I915_FORMAT_MOD_4_TILED_MTL_MC_CCS: 645 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: 646 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: 647 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: 648 if (intel_fb_is_ccs_aux_plane(fb, color_plane) || 649 is_gen12_ccs_cc_plane(fb, color_plane)) 650 return 64; 651 fallthrough; 652 case I915_FORMAT_MOD_Y_TILED: 653 if (DISPLAY_VER(dev_priv) == 2 || HAS_128_BYTE_Y_TILING(dev_priv)) 654 return 128; 655 else 656 return 512; 657 case I915_FORMAT_MOD_Yf_TILED_CCS: 658 if (intel_fb_is_ccs_aux_plane(fb, color_plane)) 659 return 128; 660 fallthrough; 661 case I915_FORMAT_MOD_Yf_TILED: 662 switch (cpp) { 663 case 1: 664 return 64; 665 case 2: 666 case 4: 667 return 128; 668 case 8: 669 case 16: 670 return 256; 671 default: 672 MISSING_CASE(cpp); 673 return cpp; 674 } 675 break; 676 default: 677 MISSING_CASE(fb->modifier); 678 return cpp; 679 } 680} 681 682unsigned int intel_tile_height(const struct drm_framebuffer *fb, int color_plane) 683{ 684 return intel_tile_size(to_i915(fb->dev)) / 685 intel_tile_width_bytes(fb, color_plane); 686} 687 688/* 689 * Return the tile dimensions in pixel units, based on the (2 or 4 kbyte) GTT 690 * page tile size. 691 */ 692static void intel_tile_dims(const struct drm_framebuffer *fb, int color_plane, 693 unsigned int *tile_width, 694 unsigned int *tile_height) 695{ 696 unsigned int tile_width_bytes = intel_tile_width_bytes(fb, color_plane); 697 unsigned int cpp = fb->format->cpp[color_plane]; 698 699 *tile_width = tile_width_bytes / cpp; 700 *tile_height = intel_tile_height(fb, color_plane); 701} 702 703/* 704 * Return the tile dimensions in pixel units, based on the tile block size. 705 * The block covers the full GTT page sized tile on all tiled surfaces and 706 * it's a 64 byte portion of the tile on TGL+ CCS surfaces. 707 */ 708static void intel_tile_block_dims(const struct drm_framebuffer *fb, int color_plane, 709 unsigned int *tile_width, 710 unsigned int *tile_height) 711{ 712 intel_tile_dims(fb, color_plane, tile_width, tile_height); 713 714 if (intel_fb_is_gen12_ccs_aux_plane(fb, color_plane)) 715 *tile_height = 1; 716} 717 718unsigned int intel_tile_row_size(const struct drm_framebuffer *fb, int color_plane) 719{ 720 unsigned int tile_width, tile_height; 721 722 intel_tile_dims(fb, color_plane, &tile_width, &tile_height); 723 724 return fb->pitches[color_plane] * tile_height; 725} 726 727unsigned int 728intel_fb_align_height(const struct drm_framebuffer *fb, 729 int color_plane, unsigned int height) 730{ 731 unsigned int tile_height = intel_tile_height(fb, color_plane); 732 733 return ALIGN(height, tile_height); 734} 735 736static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier) 737{ 738 u8 tiling_caps = lookup_modifier(fb_modifier)->plane_caps & 739 INTEL_PLANE_CAP_TILING_MASK; 740 741 switch (tiling_caps) { 742 case INTEL_PLANE_CAP_TILING_Y: 743 return I915_TILING_Y; 744 case INTEL_PLANE_CAP_TILING_X: 745 return I915_TILING_X; 746 case INTEL_PLANE_CAP_TILING_4: 747 case INTEL_PLANE_CAP_TILING_Yf: 748 case INTEL_PLANE_CAP_TILING_NONE: 749 return I915_TILING_NONE; 750 default: 751 MISSING_CASE(tiling_caps); 752 return I915_TILING_NONE; 753 } 754} 755 756bool intel_fb_modifier_uses_dpt(struct drm_i915_private *i915, u64 modifier) 757{ 758 return HAS_DPT(i915) && modifier != DRM_FORMAT_MOD_LINEAR; 759} 760 761bool intel_fb_uses_dpt(const struct drm_framebuffer *fb) 762{ 763 return fb && to_i915(fb->dev)->params.enable_dpt && 764 intel_fb_modifier_uses_dpt(to_i915(fb->dev), fb->modifier); 765} 766 767unsigned int intel_cursor_alignment(const struct drm_i915_private *i915) 768{ 769 if (IS_I830(i915)) 770 return 16 * 1024; 771 else if (IS_I85X(i915)) 772 return 256; 773 else if (IS_I845G(i915) || IS_I865G(i915)) 774 return 32; 775 else 776 return 4 * 1024; 777} 778 779static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv) 780{ 781 if (DISPLAY_VER(dev_priv) >= 9) 782 return 256 * 1024; 783 else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) || 784 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 785 return 128 * 1024; 786 else if (DISPLAY_VER(dev_priv) >= 4) 787 return 4 * 1024; 788 else 789 return 0; 790} 791 792unsigned int intel_surf_alignment(const struct drm_framebuffer *fb, 793 int color_plane) 794{ 795 struct drm_i915_private *dev_priv = to_i915(fb->dev); 796 797 if (intel_fb_uses_dpt(fb)) 798 return 512 * 4096; 799 800 /* AUX_DIST needs only 4K alignment */ 801 if (intel_fb_is_ccs_aux_plane(fb, color_plane)) 802 return 4096; 803 804 if (is_semiplanar_uv_plane(fb, color_plane)) { 805 /* 806 * TODO: cross-check wrt. the bspec stride in bytes * 64 bytes 807 * alignment for linear UV planes on all platforms. 808 */ 809 if (DISPLAY_VER(dev_priv) >= 12) { 810 if (fb->modifier == DRM_FORMAT_MOD_LINEAR) 811 return intel_linear_alignment(dev_priv); 812 813 return intel_tile_row_size(fb, color_plane); 814 } 815 816 return 4096; 817 } 818 819 drm_WARN_ON(&dev_priv->drm, color_plane != 0); 820 821 switch (fb->modifier) { 822 case DRM_FORMAT_MOD_LINEAR: 823 return intel_linear_alignment(dev_priv); 824 case I915_FORMAT_MOD_X_TILED: 825 if (HAS_ASYNC_FLIPS(dev_priv)) 826 return 256 * 1024; 827 return 0; 828 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: 829 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: 830 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: 831 case I915_FORMAT_MOD_4_TILED_MTL_MC_CCS: 832 case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS: 833 case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC: 834 return 16 * 1024; 835 case I915_FORMAT_MOD_Y_TILED_CCS: 836 case I915_FORMAT_MOD_Yf_TILED_CCS: 837 case I915_FORMAT_MOD_Y_TILED: 838 case I915_FORMAT_MOD_4_TILED: 839 case I915_FORMAT_MOD_Yf_TILED: 840 return 1 * 1024 * 1024; 841 case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS: 842 case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC: 843 case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS: 844 return 16 * 1024; 845 default: 846 MISSING_CASE(fb->modifier); 847 return 0; 848 } 849} 850 851void intel_fb_plane_get_subsampling(int *hsub, int *vsub, 852 const struct drm_framebuffer *fb, 853 int color_plane) 854{ 855 int main_plane; 856 857 if (color_plane == 0) { 858 *hsub = 1; 859 *vsub = 1; 860 861 return; 862 } 863 864 /* 865 * TODO: Deduct the subsampling from the char block for all CCS 866 * formats and planes. 867 */ 868 if (!intel_fb_is_gen12_ccs_aux_plane(fb, color_plane)) { 869 *hsub = fb->format->hsub; 870 *vsub = fb->format->vsub; 871 872 return; 873 } 874 875 main_plane = skl_ccs_to_main_plane(fb, color_plane); 876 *hsub = drm_format_info_block_width(fb->format, color_plane) / 877 drm_format_info_block_width(fb->format, main_plane); 878 879 /* 880 * The min stride check in the core framebuffer_check() function 881 * assumes that format->hsub applies to every plane except for the 882 * first plane. That's incorrect for the CCS AUX plane of the first 883 * plane, but for the above check to pass we must define the block 884 * width with that subsampling applied to it. Adjust the width here 885 * accordingly, so we can calculate the actual subsampling factor. 886 */ 887 if (main_plane == 0) 888 *hsub *= fb->format->hsub; 889 890 *vsub = 32; 891} 892 893static void intel_fb_plane_dims(const struct intel_framebuffer *fb, int color_plane, int *w, int *h) 894{ 895 int main_plane = intel_fb_is_ccs_aux_plane(&fb->base, color_plane) ? 896 skl_ccs_to_main_plane(&fb->base, color_plane) : 0; 897 unsigned int main_width = fb->base.width; 898 unsigned int main_height = fb->base.height; 899 int main_hsub, main_vsub; 900 int hsub, vsub; 901 902 intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, &fb->base, main_plane); 903 intel_fb_plane_get_subsampling(&hsub, &vsub, &fb->base, color_plane); 904 905 *w = DIV_ROUND_UP(main_width, main_hsub * hsub); 906 *h = DIV_ROUND_UP(main_height, main_vsub * vsub); 907} 908 909static u32 intel_adjust_tile_offset(int *x, int *y, 910 unsigned int tile_width, 911 unsigned int tile_height, 912 unsigned int tile_size, 913 unsigned int pitch_tiles, 914 u32 old_offset, 915 u32 new_offset) 916{ 917 unsigned int pitch_pixels = pitch_tiles * tile_width; 918 unsigned int tiles; 919 920 WARN_ON(old_offset & (tile_size - 1)); 921 WARN_ON(new_offset & (tile_size - 1)); 922 WARN_ON(new_offset > old_offset); 923 924 tiles = (old_offset - new_offset) / tile_size; 925 926 *y += tiles / pitch_tiles * tile_height; 927 *x += tiles % pitch_tiles * tile_width; 928 929 /* minimize x in case it got needlessly big */ 930 *y += *x / pitch_pixels * tile_height; 931 *x %= pitch_pixels; 932 933 return new_offset; 934} 935 936static u32 intel_adjust_linear_offset(int *x, int *y, 937 unsigned int cpp, 938 unsigned int pitch, 939 u32 old_offset, 940 u32 new_offset) 941{ 942 old_offset += *y * pitch + *x * cpp; 943 944 *y = (old_offset - new_offset) / pitch; 945 *x = ((old_offset - new_offset) - *y * pitch) / cpp; 946 947 return new_offset; 948} 949 950static u32 intel_adjust_aligned_offset(int *x, int *y, 951 const struct drm_framebuffer *fb, 952 int color_plane, 953 unsigned int rotation, 954 unsigned int pitch, 955 u32 old_offset, u32 new_offset) 956{ 957 struct drm_i915_private *i915 = to_i915(fb->dev); 958 unsigned int cpp = fb->format->cpp[color_plane]; 959 960 drm_WARN_ON(&i915->drm, new_offset > old_offset); 961 962 if (!is_surface_linear(fb, color_plane)) { 963 unsigned int tile_size, tile_width, tile_height; 964 unsigned int pitch_tiles; 965 966 tile_size = intel_tile_size(i915); 967 intel_tile_dims(fb, color_plane, &tile_width, &tile_height); 968 969 if (drm_rotation_90_or_270(rotation)) { 970 pitch_tiles = pitch / tile_height; 971 swap(tile_width, tile_height); 972 } else { 973 pitch_tiles = pitch / (tile_width * cpp); 974 } 975 976 intel_adjust_tile_offset(x, y, tile_width, tile_height, 977 tile_size, pitch_tiles, 978 old_offset, new_offset); 979 } else { 980 intel_adjust_linear_offset(x, y, cpp, pitch, 981 old_offset, new_offset); 982 } 983 984 return new_offset; 985} 986 987/* 988 * Adjust the tile offset by moving the difference into 989 * the x/y offsets. 990 */ 991u32 intel_plane_adjust_aligned_offset(int *x, int *y, 992 const struct intel_plane_state *state, 993 int color_plane, 994 u32 old_offset, u32 new_offset) 995{ 996 return intel_adjust_aligned_offset(x, y, state->hw.fb, color_plane, 997 state->hw.rotation, 998 state->view.color_plane[color_plane].mapping_stride, 999 old_offset, new_offset); 1000} 1001 1002/* 1003 * Computes the aligned offset to the base tile and adjusts 1004 * x, y. bytes per pixel is assumed to be a power-of-two. 1005 * 1006 * In the 90/270 rotated case, x and y are assumed 1007 * to be already rotated to match the rotated GTT view, and 1008 * pitch is the tile_height aligned framebuffer height. 1009 * 1010 * This function is used when computing the derived information 1011 * under intel_framebuffer, so using any of that information 1012 * here is not allowed. Anything under drm_framebuffer can be 1013 * used. This is why the user has to pass in the pitch since it 1014 * is specified in the rotated orientation. 1015 */ 1016static u32 intel_compute_aligned_offset(struct drm_i915_private *i915, 1017 int *x, int *y, 1018 const struct drm_framebuffer *fb, 1019 int color_plane, 1020 unsigned int pitch, 1021 unsigned int rotation, 1022 u32 alignment) 1023{ 1024 unsigned int cpp = fb->format->cpp[color_plane]; 1025 u32 offset, offset_aligned; 1026 1027 if (!is_surface_linear(fb, color_plane)) { 1028 unsigned int tile_size, tile_width, tile_height; 1029 unsigned int tile_rows, tiles, pitch_tiles; 1030 1031 tile_size = intel_tile_size(i915); 1032 intel_tile_dims(fb, color_plane, &tile_width, &tile_height); 1033 1034 if (drm_rotation_90_or_270(rotation)) { 1035 pitch_tiles = pitch / tile_height; 1036 swap(tile_width, tile_height); 1037 } else { 1038 pitch_tiles = pitch / (tile_width * cpp); 1039 } 1040 1041 tile_rows = *y / tile_height; 1042 *y %= tile_height; 1043 1044 tiles = *x / tile_width; 1045 *x %= tile_width; 1046 1047 offset = (tile_rows * pitch_tiles + tiles) * tile_size; 1048 1049 offset_aligned = offset; 1050 if (alignment) 1051 offset_aligned = rounddown(offset_aligned, alignment); 1052 1053 intel_adjust_tile_offset(x, y, tile_width, tile_height, 1054 tile_size, pitch_tiles, 1055 offset, offset_aligned); 1056 } else { 1057 offset = *y * pitch + *x * cpp; 1058 offset_aligned = offset; 1059 if (alignment) { 1060 offset_aligned = rounddown(offset_aligned, alignment); 1061 *y = (offset % alignment) / pitch; 1062 *x = ((offset % alignment) - *y * pitch) / cpp; 1063 } else { 1064 *y = *x = 0; 1065 } 1066 } 1067 1068 return offset_aligned; 1069} 1070 1071u32 intel_plane_compute_aligned_offset(int *x, int *y, 1072 const struct intel_plane_state *state, 1073 int color_plane) 1074{ 1075 struct intel_plane *intel_plane = to_intel_plane(state->uapi.plane); 1076 struct drm_i915_private *i915 = to_i915(intel_plane->base.dev); 1077 const struct drm_framebuffer *fb = state->hw.fb; 1078 unsigned int rotation = state->hw.rotation; 1079 int pitch = state->view.color_plane[color_plane].mapping_stride; 1080 u32 alignment; 1081 1082 if (intel_plane->id == PLANE_CURSOR) 1083 alignment = intel_cursor_alignment(i915); 1084 else 1085 alignment = intel_surf_alignment(fb, color_plane); 1086 1087 return intel_compute_aligned_offset(i915, x, y, fb, color_plane, 1088 pitch, rotation, alignment); 1089} 1090 1091/* Convert the fb->offset[] into x/y offsets */ 1092static int intel_fb_offset_to_xy(int *x, int *y, 1093 const struct drm_framebuffer *fb, 1094 int color_plane) 1095{ 1096 struct drm_i915_private *i915 = to_i915(fb->dev); 1097 unsigned int height; 1098 u32 alignment; 1099 1100 if (DISPLAY_VER(i915) >= 12 && 1101 !intel_fb_needs_pot_stride_remap(to_intel_framebuffer(fb)) && 1102 is_semiplanar_uv_plane(fb, color_plane)) 1103 alignment = intel_tile_row_size(fb, color_plane); 1104 else if (fb->modifier != DRM_FORMAT_MOD_LINEAR) 1105 alignment = intel_tile_size(i915); 1106 else 1107 alignment = 0; 1108 1109 if (alignment != 0 && fb->offsets[color_plane] % alignment) { 1110 drm_dbg_kms(&i915->drm, 1111 "Misaligned offset 0x%08x for color plane %d\n", 1112 fb->offsets[color_plane], color_plane); 1113 return -EINVAL; 1114 } 1115 1116 height = drm_framebuffer_plane_height(fb->height, fb, color_plane); 1117 height = ALIGN(height, intel_tile_height(fb, color_plane)); 1118 1119 /* Catch potential overflows early */ 1120 if (add_overflows_t(u32, mul_u32_u32(height, fb->pitches[color_plane]), 1121 fb->offsets[color_plane])) { 1122 drm_dbg_kms(&i915->drm, 1123 "Bad offset 0x%08x or pitch %d for color plane %d\n", 1124 fb->offsets[color_plane], fb->pitches[color_plane], 1125 color_plane); 1126 return -ERANGE; 1127 } 1128 1129 *x = 0; 1130 *y = 0; 1131 1132 intel_adjust_aligned_offset(x, y, 1133 fb, color_plane, DRM_MODE_ROTATE_0, 1134 fb->pitches[color_plane], 1135 fb->offsets[color_plane], 0); 1136 1137 return 0; 1138} 1139 1140static int intel_fb_check_ccs_xy(const struct drm_framebuffer *fb, int ccs_plane, int x, int y) 1141{ 1142 struct drm_i915_private *i915 = to_i915(fb->dev); 1143 const struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); 1144 int main_plane; 1145 int hsub, vsub; 1146 int tile_width, tile_height; 1147 int ccs_x, ccs_y; 1148 int main_x, main_y; 1149 1150 if (!intel_fb_is_ccs_aux_plane(fb, ccs_plane)) 1151 return 0; 1152 1153 /* 1154 * While all the tile dimensions are based on a 2k or 4k GTT page size 1155 * here the main and CCS coordinates must match only within a (64 byte 1156 * on TGL+) block inside the tile. 1157 */ 1158 intel_tile_block_dims(fb, ccs_plane, &tile_width, &tile_height); 1159 intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane); 1160 1161 tile_width *= hsub; 1162 tile_height *= vsub; 1163 1164 ccs_x = (x * hsub) % tile_width; 1165 ccs_y = (y * vsub) % tile_height; 1166 1167 main_plane = skl_ccs_to_main_plane(fb, ccs_plane); 1168 main_x = intel_fb->normal_view.color_plane[main_plane].x % tile_width; 1169 main_y = intel_fb->normal_view.color_plane[main_plane].y % tile_height; 1170 1171 /* 1172 * CCS doesn't have its own x/y offset register, so the intra CCS tile 1173 * x/y offsets must match between CCS and the main surface. 1174 */ 1175 if (main_x != ccs_x || main_y != ccs_y) { 1176 drm_dbg_kms(&i915->drm, 1177 "Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n", 1178 main_x, main_y, 1179 ccs_x, ccs_y, 1180 intel_fb->normal_view.color_plane[main_plane].x, 1181 intel_fb->normal_view.color_plane[main_plane].y, 1182 x, y); 1183 return -EINVAL; 1184 } 1185 1186 return 0; 1187} 1188 1189static bool intel_plane_can_remap(const struct intel_plane_state *plane_state) 1190{ 1191 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 1192 struct drm_i915_private *i915 = to_i915(plane->base.dev); 1193 const struct drm_framebuffer *fb = plane_state->hw.fb; 1194 int i; 1195 1196 /* We don't want to deal with remapping with cursors */ 1197 if (plane->id == PLANE_CURSOR) 1198 return false; 1199 1200 /* 1201 * The display engine limits already match/exceed the 1202 * render engine limits, so not much point in remapping. 1203 * Would also need to deal with the fence POT alignment 1204 * and gen2 2KiB GTT tile size. 1205 */ 1206 if (DISPLAY_VER(i915) < 4) 1207 return false; 1208 1209 /* 1210 * The new CCS hash mode isn't compatible with remapping as 1211 * the virtual address of the pages affects the compressed data. 1212 */ 1213 if (intel_fb_is_ccs_modifier(fb->modifier)) 1214 return false; 1215 1216 /* Linear needs a page aligned stride for remapping */ 1217 if (fb->modifier == DRM_FORMAT_MOD_LINEAR) { 1218 unsigned int alignment = intel_tile_size(i915) - 1; 1219 1220 for (i = 0; i < fb->format->num_planes; i++) { 1221 if (fb->pitches[i] & alignment) 1222 return false; 1223 } 1224 } 1225 1226 return true; 1227} 1228 1229bool intel_fb_needs_pot_stride_remap(const struct intel_framebuffer *fb) 1230{ 1231 struct drm_i915_private *i915 = to_i915(fb->base.dev); 1232 1233 return (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14) && 1234 intel_fb_uses_dpt(&fb->base); 1235} 1236 1237static int intel_fb_pitch(const struct intel_framebuffer *fb, int color_plane, unsigned int rotation) 1238{ 1239 if (drm_rotation_90_or_270(rotation)) 1240 return fb->rotated_view.color_plane[color_plane].mapping_stride; 1241 else if (intel_fb_needs_pot_stride_remap(fb)) 1242 return fb->remapped_view.color_plane[color_plane].mapping_stride; 1243 else 1244 return fb->normal_view.color_plane[color_plane].mapping_stride; 1245} 1246 1247static bool intel_plane_needs_remap(const struct intel_plane_state *plane_state) 1248{ 1249 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 1250 const struct intel_framebuffer *fb = to_intel_framebuffer(plane_state->hw.fb); 1251 unsigned int rotation = plane_state->hw.rotation; 1252 u32 stride, max_stride; 1253 1254 /* 1255 * No remapping for invisible planes since we don't have 1256 * an actual source viewport to remap. 1257 */ 1258 if (!plane_state->uapi.visible) 1259 return false; 1260 1261 if (!intel_plane_can_remap(plane_state)) 1262 return false; 1263 1264 /* 1265 * FIXME: aux plane limits on gen9+ are 1266 * unclear in Bspec, for now no checking. 1267 */ 1268 stride = intel_fb_pitch(fb, 0, rotation); 1269 max_stride = plane->max_stride(plane, fb->base.format->format, 1270 fb->base.modifier, rotation); 1271 1272 return stride > max_stride; 1273} 1274 1275static int convert_plane_offset_to_xy(const struct intel_framebuffer *fb, int color_plane, 1276 int plane_width, int *x, int *y) 1277{ 1278 struct drm_i915_gem_object *obj = intel_fb_obj(&fb->base); 1279 int ret; 1280 1281 ret = intel_fb_offset_to_xy(x, y, &fb->base, color_plane); 1282 if (ret) { 1283 drm_dbg_kms(fb->base.dev, 1284 "bad fb plane %d offset: 0x%x\n", 1285 color_plane, fb->base.offsets[color_plane]); 1286 return ret; 1287 } 1288 1289 ret = intel_fb_check_ccs_xy(&fb->base, color_plane, *x, *y); 1290 if (ret) 1291 return ret; 1292 1293 /* 1294 * The fence (if used) is aligned to the start of the object 1295 * so having the framebuffer wrap around across the edge of the 1296 * fenced region doesn't really work. We have no API to configure 1297 * the fence start offset within the object (nor could we probably 1298 * on gen2/3). So it's just easier if we just require that the 1299 * fb layout agrees with the fence layout. We already check that the 1300 * fb stride matches the fence stride elsewhere. 1301 */ 1302 if (color_plane == 0 && i915_gem_object_is_tiled(obj) && 1303 (*x + plane_width) * fb->base.format->cpp[color_plane] > fb->base.pitches[color_plane]) { 1304 drm_dbg_kms(fb->base.dev, 1305 "bad fb plane %d offset: 0x%x\n", 1306 color_plane, fb->base.offsets[color_plane]); 1307 return -EINVAL; 1308 } 1309 1310 return 0; 1311} 1312 1313static u32 calc_plane_aligned_offset(const struct intel_framebuffer *fb, int color_plane, int *x, int *y) 1314{ 1315 struct drm_i915_private *i915 = to_i915(fb->base.dev); 1316 unsigned int tile_size = intel_tile_size(i915); 1317 u32 offset; 1318 1319 offset = intel_compute_aligned_offset(i915, x, y, &fb->base, color_plane, 1320 fb->base.pitches[color_plane], 1321 DRM_MODE_ROTATE_0, 1322 tile_size); 1323 1324 return offset / tile_size; 1325} 1326 1327struct fb_plane_view_dims { 1328 unsigned int width, height; 1329 unsigned int tile_width, tile_height; 1330}; 1331 1332static void init_plane_view_dims(const struct intel_framebuffer *fb, int color_plane, 1333 unsigned int width, unsigned int height, 1334 struct fb_plane_view_dims *dims) 1335{ 1336 dims->width = width; 1337 dims->height = height; 1338 1339 intel_tile_dims(&fb->base, color_plane, &dims->tile_width, &dims->tile_height); 1340} 1341 1342static unsigned int 1343plane_view_src_stride_tiles(const struct intel_framebuffer *fb, int color_plane, 1344 const struct fb_plane_view_dims *dims) 1345{ 1346 return DIV_ROUND_UP(fb->base.pitches[color_plane], 1347 dims->tile_width * fb->base.format->cpp[color_plane]); 1348} 1349 1350static unsigned int 1351plane_view_dst_stride_tiles(const struct intel_framebuffer *fb, int color_plane, 1352 unsigned int pitch_tiles) 1353{ 1354 if (intel_fb_needs_pot_stride_remap(fb)) { 1355 /* 1356 * ADL_P, the only platform needing a POT stride has a minimum 1357 * of 8 main surface tiles. 1358 */ 1359 return roundup_pow_of_two(max(pitch_tiles, 8u)); 1360 } else { 1361 return pitch_tiles; 1362 } 1363} 1364 1365static unsigned int 1366plane_view_scanout_stride(const struct intel_framebuffer *fb, int color_plane, 1367 unsigned int tile_width, 1368 unsigned int src_stride_tiles, unsigned int dst_stride_tiles) 1369{ 1370 struct drm_i915_private *i915 = to_i915(fb->base.dev); 1371 unsigned int stride_tiles; 1372 1373 if ((IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14) && 1374 src_stride_tiles < dst_stride_tiles) 1375 stride_tiles = src_stride_tiles; 1376 else 1377 stride_tiles = dst_stride_tiles; 1378 1379 return stride_tiles * tile_width * fb->base.format->cpp[color_plane]; 1380} 1381 1382static unsigned int 1383plane_view_width_tiles(const struct intel_framebuffer *fb, int color_plane, 1384 const struct fb_plane_view_dims *dims, 1385 int x) 1386{ 1387 return DIV_ROUND_UP(x + dims->width, dims->tile_width); 1388} 1389 1390static unsigned int 1391plane_view_height_tiles(const struct intel_framebuffer *fb, int color_plane, 1392 const struct fb_plane_view_dims *dims, 1393 int y) 1394{ 1395 return DIV_ROUND_UP(y + dims->height, dims->tile_height); 1396} 1397 1398static unsigned int 1399plane_view_linear_tiles(const struct intel_framebuffer *fb, int color_plane, 1400 const struct fb_plane_view_dims *dims, 1401 int x, int y) 1402{ 1403 struct drm_i915_private *i915 = to_i915(fb->base.dev); 1404 unsigned int size; 1405 1406 size = (y + dims->height) * fb->base.pitches[color_plane] + 1407 x * fb->base.format->cpp[color_plane]; 1408 1409 return DIV_ROUND_UP(size, intel_tile_size(i915)); 1410} 1411 1412#define assign_chk_ovf(i915, var, val) ({ \ 1413 drm_WARN_ON(&(i915)->drm, overflows_type(val, var)); \ 1414 (var) = (val); \ 1415}) 1416 1417#define assign_bfld_chk_ovf(i915, var, val) ({ \ 1418 (var) = (val); \ 1419 drm_WARN_ON(&(i915)->drm, (var) != (val)); \ 1420 (var); \ 1421}) 1422 1423static u32 calc_plane_remap_info(const struct intel_framebuffer *fb, int color_plane, 1424 const struct fb_plane_view_dims *dims, 1425 u32 obj_offset, u32 gtt_offset, int x, int y, 1426 struct intel_fb_view *view) 1427{ 1428 struct drm_i915_private *i915 = to_i915(fb->base.dev); 1429 struct intel_remapped_plane_info *remap_info = &view->gtt.remapped.plane[color_plane]; 1430 struct i915_color_plane_view *color_plane_info = &view->color_plane[color_plane]; 1431 unsigned int tile_width = dims->tile_width; 1432 unsigned int tile_height = dims->tile_height; 1433 unsigned int tile_size = intel_tile_size(i915); 1434 struct drm_rect r; 1435 u32 size = 0; 1436 1437 assign_bfld_chk_ovf(i915, remap_info->offset, obj_offset); 1438 1439 if (intel_fb_is_gen12_ccs_aux_plane(&fb->base, color_plane)) { 1440 remap_info->linear = 1; 1441 1442 assign_chk_ovf(i915, remap_info->size, 1443 plane_view_linear_tiles(fb, color_plane, dims, x, y)); 1444 } else { 1445 remap_info->linear = 0; 1446 1447 assign_chk_ovf(i915, remap_info->src_stride, 1448 plane_view_src_stride_tiles(fb, color_plane, dims)); 1449 assign_chk_ovf(i915, remap_info->width, 1450 plane_view_width_tiles(fb, color_plane, dims, x)); 1451 assign_chk_ovf(i915, remap_info->height, 1452 plane_view_height_tiles(fb, color_plane, dims, y)); 1453 } 1454 1455 if (view->gtt.type == I915_GTT_VIEW_ROTATED) { 1456 drm_WARN_ON(&i915->drm, remap_info->linear); 1457 check_array_bounds(i915, view->gtt.rotated.plane, color_plane); 1458 1459 assign_chk_ovf(i915, remap_info->dst_stride, 1460 plane_view_dst_stride_tiles(fb, color_plane, remap_info->height)); 1461 1462 /* rotate the x/y offsets to match the GTT view */ 1463 drm_rect_init(&r, x, y, dims->width, dims->height); 1464 drm_rect_rotate(&r, 1465 remap_info->width * tile_width, 1466 remap_info->height * tile_height, 1467 DRM_MODE_ROTATE_270); 1468 1469 color_plane_info->x = r.x1; 1470 color_plane_info->y = r.y1; 1471 1472 color_plane_info->mapping_stride = remap_info->dst_stride * tile_height; 1473 color_plane_info->scanout_stride = color_plane_info->mapping_stride; 1474 1475 size += remap_info->dst_stride * remap_info->width; 1476 1477 /* rotate the tile dimensions to match the GTT view */ 1478 swap(tile_width, tile_height); 1479 } else { 1480 drm_WARN_ON(&i915->drm, view->gtt.type != I915_GTT_VIEW_REMAPPED); 1481 1482 check_array_bounds(i915, view->gtt.remapped.plane, color_plane); 1483 1484 if (view->gtt.remapped.plane_alignment) { 1485 unsigned int aligned_offset = ALIGN(gtt_offset, 1486 view->gtt.remapped.plane_alignment); 1487 1488 size += aligned_offset - gtt_offset; 1489 gtt_offset = aligned_offset; 1490 } 1491 1492 color_plane_info->x = x; 1493 color_plane_info->y = y; 1494 1495 if (remap_info->linear) { 1496 color_plane_info->mapping_stride = fb->base.pitches[color_plane]; 1497 color_plane_info->scanout_stride = color_plane_info->mapping_stride; 1498 1499 size += remap_info->size; 1500 } else { 1501 unsigned int dst_stride; 1502 1503 /* 1504 * The hardware automagically calculates the CCS AUX surface 1505 * stride from the main surface stride so can't really remap a 1506 * smaller subset (unless we'd remap in whole AUX page units). 1507 */ 1508 if (intel_fb_needs_pot_stride_remap(fb) && 1509 intel_fb_is_ccs_modifier(fb->base.modifier)) 1510 dst_stride = remap_info->src_stride; 1511 else 1512 dst_stride = remap_info->width; 1513 1514 dst_stride = plane_view_dst_stride_tiles(fb, color_plane, dst_stride); 1515 1516 assign_chk_ovf(i915, remap_info->dst_stride, dst_stride); 1517 color_plane_info->mapping_stride = dst_stride * 1518 tile_width * 1519 fb->base.format->cpp[color_plane]; 1520 color_plane_info->scanout_stride = 1521 plane_view_scanout_stride(fb, color_plane, tile_width, 1522 remap_info->src_stride, 1523 dst_stride); 1524 1525 size += dst_stride * remap_info->height; 1526 } 1527 } 1528 1529 /* 1530 * We only keep the x/y offsets, so push all of the gtt offset into 1531 * the x/y offsets. x,y will hold the first pixel of the framebuffer 1532 * plane from the start of the remapped/rotated gtt mapping. 1533 */ 1534 if (remap_info->linear) 1535 intel_adjust_linear_offset(&color_plane_info->x, &color_plane_info->y, 1536 fb->base.format->cpp[color_plane], 1537 color_plane_info->mapping_stride, 1538 gtt_offset * tile_size, 0); 1539 else 1540 intel_adjust_tile_offset(&color_plane_info->x, &color_plane_info->y, 1541 tile_width, tile_height, 1542 tile_size, remap_info->dst_stride, 1543 gtt_offset * tile_size, 0); 1544 1545 return size; 1546} 1547 1548#undef assign_chk_ovf 1549 1550/* Return number of tiles @color_plane needs. */ 1551static unsigned int 1552calc_plane_normal_size(const struct intel_framebuffer *fb, int color_plane, 1553 const struct fb_plane_view_dims *dims, 1554 int x, int y) 1555{ 1556 unsigned int tiles; 1557 1558 if (is_surface_linear(&fb->base, color_plane)) { 1559 tiles = plane_view_linear_tiles(fb, color_plane, dims, x, y); 1560 } else { 1561 tiles = plane_view_src_stride_tiles(fb, color_plane, dims) * 1562 plane_view_height_tiles(fb, color_plane, dims, y); 1563 /* 1564 * If the plane isn't horizontally tile aligned, 1565 * we need one more tile. 1566 */ 1567 if (x != 0) 1568 tiles++; 1569 } 1570 1571 return tiles; 1572} 1573 1574static void intel_fb_view_init(struct drm_i915_private *i915, struct intel_fb_view *view, 1575 enum i915_gtt_view_type view_type) 1576{ 1577 memset(view, 0, sizeof(*view)); 1578 view->gtt.type = view_type; 1579 1580 if (view_type == I915_GTT_VIEW_REMAPPED && 1581 (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14)) 1582 view->gtt.remapped.plane_alignment = SZ_2M / PAGE_SIZE; 1583} 1584 1585bool intel_fb_supports_90_270_rotation(const struct intel_framebuffer *fb) 1586{ 1587 if (DISPLAY_VER(to_i915(fb->base.dev)) >= 13) 1588 return false; 1589 1590 return fb->base.modifier == I915_FORMAT_MOD_Y_TILED || 1591 fb->base.modifier == I915_FORMAT_MOD_Yf_TILED; 1592} 1593 1594int intel_fill_fb_info(struct drm_i915_private *i915, struct intel_framebuffer *fb) 1595{ 1596 struct drm_i915_gem_object *obj = intel_fb_obj(&fb->base); 1597 u32 gtt_offset_rotated = 0; 1598 u32 gtt_offset_remapped = 0; 1599 unsigned int max_size = 0; 1600 int i, num_planes = fb->base.format->num_planes; 1601 unsigned int tile_size = intel_tile_size(i915); 1602 1603 intel_fb_view_init(i915, &fb->normal_view, I915_GTT_VIEW_NORMAL); 1604 1605 drm_WARN_ON(&i915->drm, 1606 intel_fb_supports_90_270_rotation(fb) && 1607 intel_fb_needs_pot_stride_remap(fb)); 1608 1609 if (intel_fb_supports_90_270_rotation(fb)) 1610 intel_fb_view_init(i915, &fb->rotated_view, I915_GTT_VIEW_ROTATED); 1611 if (intel_fb_needs_pot_stride_remap(fb)) 1612 intel_fb_view_init(i915, &fb->remapped_view, I915_GTT_VIEW_REMAPPED); 1613 1614 for (i = 0; i < num_planes; i++) { 1615 struct fb_plane_view_dims view_dims; 1616 unsigned int width, height; 1617 unsigned int size; 1618 u32 offset; 1619 int x, y; 1620 int ret; 1621 1622 /* 1623 * Plane 2 of Render Compression with Clear Color fb modifier 1624 * is consumed by the driver and not passed to DE. Skip the 1625 * arithmetic related to alignment and offset calculation. 1626 */ 1627 if (is_gen12_ccs_cc_plane(&fb->base, i)) { 1628 if (IS_ALIGNED(fb->base.offsets[i], PAGE_SIZE)) 1629 continue; 1630 else 1631 return -EINVAL; 1632 } 1633 1634 intel_fb_plane_dims(fb, i, &width, &height); 1635 1636 ret = convert_plane_offset_to_xy(fb, i, width, &x, &y); 1637 if (ret) 1638 return ret; 1639 1640 init_plane_view_dims(fb, i, width, height, &view_dims); 1641 1642 /* 1643 * First pixel of the framebuffer from 1644 * the start of the normal gtt mapping. 1645 */ 1646 fb->normal_view.color_plane[i].x = x; 1647 fb->normal_view.color_plane[i].y = y; 1648 fb->normal_view.color_plane[i].mapping_stride = fb->base.pitches[i]; 1649 fb->normal_view.color_plane[i].scanout_stride = 1650 fb->normal_view.color_plane[i].mapping_stride; 1651 1652 offset = calc_plane_aligned_offset(fb, i, &x, &y); 1653 1654 if (intel_fb_supports_90_270_rotation(fb)) 1655 gtt_offset_rotated += calc_plane_remap_info(fb, i, &view_dims, 1656 offset, gtt_offset_rotated, x, y, 1657 &fb->rotated_view); 1658 1659 if (intel_fb_needs_pot_stride_remap(fb)) 1660 gtt_offset_remapped += calc_plane_remap_info(fb, i, &view_dims, 1661 offset, gtt_offset_remapped, x, y, 1662 &fb->remapped_view); 1663 1664 size = calc_plane_normal_size(fb, i, &view_dims, x, y); 1665 /* how many tiles in total needed in the bo */ 1666 max_size = max(max_size, offset + size); 1667 } 1668 1669 if (mul_u32_u32(max_size, tile_size) > obj->base.size) { 1670 drm_dbg_kms(&i915->drm, 1671 "fb too big for bo (need %llu bytes, have %zu bytes)\n", 1672 mul_u32_u32(max_size, tile_size), obj->base.size); 1673 return -EINVAL; 1674 } 1675 1676 return 0; 1677} 1678 1679static void intel_plane_remap_gtt(struct intel_plane_state *plane_state) 1680{ 1681 struct drm_i915_private *i915 = 1682 to_i915(plane_state->uapi.plane->dev); 1683 struct drm_framebuffer *fb = plane_state->hw.fb; 1684 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); 1685 unsigned int rotation = plane_state->hw.rotation; 1686 int i, num_planes = fb->format->num_planes; 1687 unsigned int src_x, src_y; 1688 unsigned int src_w, src_h; 1689 u32 gtt_offset = 0; 1690 1691 intel_fb_view_init(i915, &plane_state->view, 1692 drm_rotation_90_or_270(rotation) ? I915_GTT_VIEW_ROTATED : 1693 I915_GTT_VIEW_REMAPPED); 1694 1695 src_x = plane_state->uapi.src.x1 >> 16; 1696 src_y = plane_state->uapi.src.y1 >> 16; 1697 src_w = drm_rect_width(&plane_state->uapi.src) >> 16; 1698 src_h = drm_rect_height(&plane_state->uapi.src) >> 16; 1699 1700 drm_WARN_ON(&i915->drm, intel_fb_is_ccs_modifier(fb->modifier)); 1701 1702 /* Make src coordinates relative to the viewport */ 1703 drm_rect_translate(&plane_state->uapi.src, 1704 -(src_x << 16), -(src_y << 16)); 1705 1706 /* Rotate src coordinates to match rotated GTT view */ 1707 if (drm_rotation_90_or_270(rotation)) 1708 drm_rect_rotate(&plane_state->uapi.src, 1709 src_w << 16, src_h << 16, 1710 DRM_MODE_ROTATE_270); 1711 1712 for (i = 0; i < num_planes; i++) { 1713 unsigned int hsub = i ? fb->format->hsub : 1; 1714 unsigned int vsub = i ? fb->format->vsub : 1; 1715 struct fb_plane_view_dims view_dims; 1716 unsigned int width, height; 1717 unsigned int x, y; 1718 u32 offset; 1719 1720 x = src_x / hsub; 1721 y = src_y / vsub; 1722 width = src_w / hsub; 1723 height = src_h / vsub; 1724 1725 init_plane_view_dims(intel_fb, i, width, height, &view_dims); 1726 1727 /* 1728 * First pixel of the src viewport from the 1729 * start of the normal gtt mapping. 1730 */ 1731 x += intel_fb->normal_view.color_plane[i].x; 1732 y += intel_fb->normal_view.color_plane[i].y; 1733 1734 offset = calc_plane_aligned_offset(intel_fb, i, &x, &y); 1735 1736 gtt_offset += calc_plane_remap_info(intel_fb, i, &view_dims, 1737 offset, gtt_offset, x, y, 1738 &plane_state->view); 1739 } 1740} 1741 1742void intel_fb_fill_view(const struct intel_framebuffer *fb, unsigned int rotation, 1743 struct intel_fb_view *view) 1744{ 1745 if (drm_rotation_90_or_270(rotation)) 1746 *view = fb->rotated_view; 1747 else if (intel_fb_needs_pot_stride_remap(fb)) 1748 *view = fb->remapped_view; 1749 else 1750 *view = fb->normal_view; 1751} 1752 1753static 1754u32 intel_fb_max_stride(struct drm_i915_private *dev_priv, 1755 u32 pixel_format, u64 modifier) 1756{ 1757 /* 1758 * Arbitrary limit for gen4+ chosen to match the 1759 * render engine max stride. 1760 * 1761 * The new CCS hash mode makes remapping impossible 1762 */ 1763 if (DISPLAY_VER(dev_priv) < 4 || intel_fb_is_ccs_modifier(modifier) || 1764 intel_fb_modifier_uses_dpt(dev_priv, modifier)) 1765 return intel_plane_fb_max_stride(dev_priv, pixel_format, modifier); 1766 else if (DISPLAY_VER(dev_priv) >= 7) 1767 return 256 * 1024; 1768 else 1769 return 128 * 1024; 1770} 1771 1772static u32 1773intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane) 1774{ 1775 struct drm_i915_private *dev_priv = to_i915(fb->dev); 1776 u32 tile_width; 1777 1778 if (is_surface_linear(fb, color_plane)) { 1779 u32 max_stride = intel_plane_fb_max_stride(dev_priv, 1780 fb->format->format, 1781 fb->modifier); 1782 1783 /* 1784 * To make remapping with linear generally feasible 1785 * we need the stride to be page aligned. 1786 */ 1787 if (fb->pitches[color_plane] > max_stride && 1788 !intel_fb_is_ccs_modifier(fb->modifier)) 1789 return intel_tile_size(dev_priv); 1790 else 1791 return 64; 1792 } 1793 1794 tile_width = intel_tile_width_bytes(fb, color_plane); 1795 if (intel_fb_is_ccs_modifier(fb->modifier)) { 1796 /* 1797 * On TGL the surface stride must be 4 tile aligned, mapped by 1798 * one 64 byte cacheline on the CCS AUX surface. 1799 */ 1800 if (DISPLAY_VER(dev_priv) >= 12) 1801 tile_width *= 4; 1802 /* 1803 * Display WA #0531: skl,bxt,kbl,glk 1804 * 1805 * Render decompression and plane width > 3840 1806 * combined with horizontal panning requires the 1807 * plane stride to be a multiple of 4. We'll just 1808 * require the entire fb to accommodate that to avoid 1809 * potential runtime errors at plane configuration time. 1810 */ 1811 else if ((DISPLAY_VER(dev_priv) == 9 || IS_GEMINILAKE(dev_priv)) && 1812 color_plane == 0 && fb->width > 3840) 1813 tile_width *= 4; 1814 } 1815 return tile_width; 1816} 1817 1818static int intel_plane_check_stride(const struct intel_plane_state *plane_state) 1819{ 1820 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 1821 const struct drm_framebuffer *fb = plane_state->hw.fb; 1822 unsigned int rotation = plane_state->hw.rotation; 1823 u32 stride, max_stride; 1824 1825 /* 1826 * We ignore stride for all invisible planes that 1827 * can be remapped. Otherwise we could end up 1828 * with a false positive when the remapping didn't 1829 * kick in due the plane being invisible. 1830 */ 1831 if (intel_plane_can_remap(plane_state) && 1832 !plane_state->uapi.visible) 1833 return 0; 1834 1835 /* FIXME other color planes? */ 1836 stride = plane_state->view.color_plane[0].mapping_stride; 1837 max_stride = plane->max_stride(plane, fb->format->format, 1838 fb->modifier, rotation); 1839 1840 if (stride > max_stride) { 1841 DRM_DEBUG_KMS("[FB:%d] stride (%d) exceeds [PLANE:%d:%s] max stride (%d)\n", 1842 fb->base.id, stride, 1843 plane->base.base.id, plane->base.name, max_stride); 1844 return -EINVAL; 1845 } 1846 1847 return 0; 1848} 1849 1850int intel_plane_compute_gtt(struct intel_plane_state *plane_state) 1851{ 1852 const struct intel_framebuffer *fb = 1853 to_intel_framebuffer(plane_state->hw.fb); 1854 unsigned int rotation = plane_state->hw.rotation; 1855 1856 if (!fb) 1857 return 0; 1858 1859 if (intel_plane_needs_remap(plane_state)) { 1860 intel_plane_remap_gtt(plane_state); 1861 1862 /* 1863 * Sometimes even remapping can't overcome 1864 * the stride limitations :( Can happen with 1865 * big plane sizes and suitably misaligned 1866 * offsets. 1867 */ 1868 return intel_plane_check_stride(plane_state); 1869 } 1870 1871 intel_fb_fill_view(fb, rotation, &plane_state->view); 1872 1873 /* Rotate src coordinates to match rotated GTT view */ 1874 if (drm_rotation_90_or_270(rotation)) 1875 drm_rect_rotate(&plane_state->uapi.src, 1876 fb->base.width << 16, fb->base.height << 16, 1877 DRM_MODE_ROTATE_270); 1878 1879 return intel_plane_check_stride(plane_state); 1880} 1881 1882static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) 1883{ 1884 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); 1885 1886 drm_framebuffer_cleanup(fb); 1887 1888 if (intel_fb_uses_dpt(fb)) 1889 intel_dpt_destroy(intel_fb->dpt_vm); 1890 1891 intel_frontbuffer_put(intel_fb->frontbuffer); 1892 1893 kfree(intel_fb); 1894} 1895 1896static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, 1897 struct drm_file *file, 1898 unsigned int *handle) 1899{ 1900 struct drm_i915_gem_object *obj = intel_fb_obj(fb); 1901 struct drm_i915_private *i915 = to_i915(obj->base.dev); 1902 1903 if (i915_gem_object_is_userptr(obj)) { 1904 drm_dbg(&i915->drm, 1905 "attempting to use a userptr for a framebuffer, denied\n"); 1906 return -EINVAL; 1907 } 1908 1909 return drm_gem_handle_create(file, &obj->base, handle); 1910} 1911 1912static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb, 1913 struct drm_file *file, 1914 unsigned int flags, unsigned int color, 1915 struct drm_clip_rect *clips, 1916 unsigned int num_clips) 1917{ 1918 struct drm_i915_gem_object *obj = intel_fb_obj(fb); 1919 1920 i915_gem_object_flush_if_display(obj); 1921 intel_frontbuffer_flush(to_intel_frontbuffer(fb), ORIGIN_DIRTYFB); 1922 1923 return 0; 1924} 1925 1926static const struct drm_framebuffer_funcs intel_fb_funcs = { 1927 .destroy = intel_user_framebuffer_destroy, 1928 .create_handle = intel_user_framebuffer_create_handle, 1929 .dirty = intel_user_framebuffer_dirty, 1930}; 1931 1932int intel_framebuffer_init(struct intel_framebuffer *intel_fb, 1933 struct drm_i915_gem_object *obj, 1934 struct drm_mode_fb_cmd2 *mode_cmd) 1935{ 1936 struct drm_i915_private *dev_priv = to_i915(obj->base.dev); 1937 struct drm_framebuffer *fb = &intel_fb->base; 1938 u32 max_stride; 1939 unsigned int tiling, stride; 1940 int ret = -EINVAL; 1941 int i; 1942 1943 intel_fb->frontbuffer = intel_frontbuffer_get(obj); 1944 if (!intel_fb->frontbuffer) 1945 return -ENOMEM; 1946 1947 i915_gem_object_lock(obj, NULL); 1948 tiling = i915_gem_object_get_tiling(obj); 1949 stride = i915_gem_object_get_stride(obj); 1950 i915_gem_object_unlock(obj); 1951 1952 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) { 1953 /* 1954 * If there's a fence, enforce that 1955 * the fb modifier and tiling mode match. 1956 */ 1957 if (tiling != I915_TILING_NONE && 1958 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) { 1959 drm_dbg_kms(&dev_priv->drm, 1960 "tiling_mode doesn't match fb modifier\n"); 1961 goto err; 1962 } 1963 } else { 1964 if (tiling == I915_TILING_X) { 1965 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED; 1966 } else if (tiling == I915_TILING_Y) { 1967 drm_dbg_kms(&dev_priv->drm, 1968 "No Y tiling for legacy addfb\n"); 1969 goto err; 1970 } 1971 } 1972 1973 if (!drm_any_plane_has_format(&dev_priv->drm, 1974 mode_cmd->pixel_format, 1975 mode_cmd->modifier[0])) { 1976 drm_dbg_kms(&dev_priv->drm, 1977 "unsupported pixel format %p4cc / modifier 0x%llx\n", 1978 &mode_cmd->pixel_format, mode_cmd->modifier[0]); 1979 goto err; 1980 } 1981 1982 /* 1983 * gen2/3 display engine uses the fence if present, 1984 * so the tiling mode must match the fb modifier exactly. 1985 */ 1986 if (DISPLAY_VER(dev_priv) < 4 && 1987 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) { 1988 drm_dbg_kms(&dev_priv->drm, 1989 "tiling_mode must match fb modifier exactly on gen2/3\n"); 1990 goto err; 1991 } 1992 1993 max_stride = intel_fb_max_stride(dev_priv, mode_cmd->pixel_format, 1994 mode_cmd->modifier[0]); 1995 if (mode_cmd->pitches[0] > max_stride) { 1996 drm_dbg_kms(&dev_priv->drm, 1997 "%s pitch (%u) must be at most %d\n", 1998 mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ? 1999 "tiled" : "linear", 2000 mode_cmd->pitches[0], max_stride); 2001 goto err; 2002 } 2003 2004 /* 2005 * If there's a fence, enforce that 2006 * the fb pitch and fence stride match. 2007 */ 2008 if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) { 2009 drm_dbg_kms(&dev_priv->drm, 2010 "pitch (%d) must match tiling stride (%d)\n", 2011 mode_cmd->pitches[0], stride); 2012 goto err; 2013 } 2014 2015 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ 2016 if (mode_cmd->offsets[0] != 0) { 2017 drm_dbg_kms(&dev_priv->drm, 2018 "plane 0 offset (0x%08x) must be 0\n", 2019 mode_cmd->offsets[0]); 2020 goto err; 2021 } 2022 2023 drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd); 2024 2025 for (i = 0; i < fb->format->num_planes; i++) { 2026 u32 stride_alignment; 2027 2028 if (mode_cmd->handles[i] != mode_cmd->handles[0]) { 2029 drm_dbg_kms(&dev_priv->drm, "bad plane %d handle\n", 2030 i); 2031 goto err; 2032 } 2033 2034 stride_alignment = intel_fb_stride_alignment(fb, i); 2035 if (fb->pitches[i] & (stride_alignment - 1)) { 2036 drm_dbg_kms(&dev_priv->drm, 2037 "plane %d pitch (%d) must be at least %u byte aligned\n", 2038 i, fb->pitches[i], stride_alignment); 2039 goto err; 2040 } 2041 2042 if (intel_fb_is_gen12_ccs_aux_plane(fb, i)) { 2043 int ccs_aux_stride = gen12_ccs_aux_stride(intel_fb, i); 2044 2045 if (fb->pitches[i] != ccs_aux_stride) { 2046 drm_dbg_kms(&dev_priv->drm, 2047 "ccs aux plane %d pitch (%d) must be %d\n", 2048 i, 2049 fb->pitches[i], ccs_aux_stride); 2050 goto err; 2051 } 2052 } 2053 2054 fb->obj[i] = &obj->base; 2055 } 2056 2057 ret = intel_fill_fb_info(dev_priv, intel_fb); 2058 if (ret) 2059 goto err; 2060 2061 if (intel_fb_uses_dpt(fb)) { 2062 struct i915_address_space *vm; 2063 2064 vm = intel_dpt_create(intel_fb); 2065 if (IS_ERR(vm)) { 2066 drm_dbg_kms(&dev_priv->drm, "failed to create DPT\n"); 2067 ret = PTR_ERR(vm); 2068 goto err; 2069 } 2070 2071 intel_fb->dpt_vm = vm; 2072 } 2073 2074 ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs); 2075 if (ret) { 2076 drm_err(&dev_priv->drm, "framebuffer init failed %d\n", ret); 2077 goto err_free_dpt; 2078 } 2079 2080 return 0; 2081 2082err_free_dpt: 2083 if (intel_fb_uses_dpt(fb)) 2084 intel_dpt_destroy(intel_fb->dpt_vm); 2085err: 2086 intel_frontbuffer_put(intel_fb->frontbuffer); 2087 return ret; 2088} 2089 2090struct drm_framebuffer * 2091intel_user_framebuffer_create(struct drm_device *dev, 2092 struct drm_file *filp, 2093 const struct drm_mode_fb_cmd2 *user_mode_cmd) 2094{ 2095 struct drm_framebuffer *fb; 2096 struct drm_i915_gem_object *obj; 2097 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd; 2098 struct drm_i915_private *i915; 2099 2100 obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]); 2101 if (!obj) 2102 return ERR_PTR(-ENOENT); 2103 2104 /* object is backed with LMEM for discrete */ 2105 i915 = to_i915(obj->base.dev); 2106 if (HAS_LMEM(i915) && !i915_gem_object_can_migrate(obj, INTEL_REGION_LMEM_0)) { 2107 /* object is "remote", not in local memory */ 2108 i915_gem_object_put(obj); 2109 drm_dbg_kms(&i915->drm, "framebuffer must reside in local memory\n"); 2110 return ERR_PTR(-EREMOTE); 2111 } 2112 2113 fb = intel_framebuffer_create(obj, &mode_cmd); 2114 i915_gem_object_put(obj); 2115 2116 return fb; 2117} 2118 2119struct drm_framebuffer * 2120intel_framebuffer_create(struct drm_i915_gem_object *obj, 2121 struct drm_mode_fb_cmd2 *mode_cmd) 2122{ 2123 struct intel_framebuffer *intel_fb; 2124 int ret; 2125 2126 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); 2127 if (!intel_fb) 2128 return ERR_PTR(-ENOMEM); 2129 2130 ret = intel_framebuffer_init(intel_fb, obj, mode_cmd); 2131 if (ret) 2132 goto err; 2133 2134 return &intel_fb->base; 2135 2136err: 2137 kfree(intel_fb); 2138 return ERR_PTR(ret); 2139} 2140