1/* 2 * Copyright © 2006-2007 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 */ 26 27#include <linux/dma-resv.h> 28#include <linux/i2c.h> 29#include <linux/input.h> 30#include <linux/kernel.h> 31#include <linux/module.h> 32#include <linux/slab.h> 33#include <linux/string_helpers.h> 34 35#include <drm/display/drm_dp_helper.h> 36#include <drm/drm_atomic.h> 37#include <drm/drm_atomic_helper.h> 38#include <drm/drm_atomic_uapi.h> 39#include <drm/drm_damage_helper.h> 40#include <drm/drm_edid.h> 41#include <drm/drm_fourcc.h> 42#include <drm/drm_probe_helper.h> 43#include <drm/drm_rect.h> 44 45#include "gem/i915_gem_lmem.h" 46#include "gem/i915_gem_object.h" 47 48#include "g4x_dp.h" 49#include "g4x_hdmi.h" 50#include "hsw_ips.h" 51#include "i915_drv.h" 52#include "i915_reg.h" 53#include "i915_utils.h" 54#include "i9xx_plane.h" 55#include "i9xx_wm.h" 56#include "intel_atomic.h" 57#include "intel_atomic_plane.h" 58#include "intel_audio.h" 59#include "intel_bw.h" 60#include "intel_cdclk.h" 61#include "intel_clock_gating.h" 62#include "intel_color.h" 63#include "intel_crt.h" 64#include "intel_crtc.h" 65#include "intel_crtc_state_dump.h" 66#include "intel_ddi.h" 67#include "intel_de.h" 68#include "intel_display_driver.h" 69#include "intel_display_power.h" 70#include "intel_display_types.h" 71#include "intel_dmc.h" 72#include "intel_dp.h" 73#include "intel_dp_link_training.h" 74#include "intel_dp_mst.h" 75#include "intel_dpio_phy.h" 76#include "intel_dpll.h" 77#include "intel_dpll_mgr.h" 78#include "intel_dpt.h" 79#include "intel_drrs.h" 80#include "intel_dsi.h" 81#include "intel_dvo.h" 82#include "intel_fb.h" 83#include "intel_fbc.h" 84#include "intel_fbdev.h" 85#include "intel_fdi.h" 86#include "intel_fifo_underrun.h" 87#include "intel_frontbuffer.h" 88#include "intel_hdmi.h" 89#include "intel_hotplug.h" 90#include "intel_lvds.h" 91#include "intel_lvds_regs.h" 92#include "intel_modeset_setup.h" 93#include "intel_modeset_verify.h" 94#include "intel_overlay.h" 95#include "intel_panel.h" 96#include "intel_pch_display.h" 97#include "intel_pch_refclk.h" 98#include "intel_pcode.h" 99#include "intel_pipe_crc.h" 100#include "intel_plane_initial.h" 101#include "intel_pmdemand.h" 102#include "intel_pps.h" 103#include "intel_psr.h" 104#include "intel_sdvo.h" 105#include "intel_snps_phy.h" 106#include "intel_tc.h" 107#include "intel_tv.h" 108#include "intel_vblank.h" 109#include "intel_vdsc.h" 110#include "intel_vdsc_regs.h" 111#include "intel_vga.h" 112#include "intel_vrr.h" 113#include "intel_wm.h" 114#include "skl_scaler.h" 115#include "skl_universal_plane.h" 116#include "skl_watermark.h" 117#include "vlv_dsi.h" 118#include "vlv_dsi_pll.h" 119#include "vlv_dsi_regs.h" 120#include "vlv_sideband.h" 121 122static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state); 123static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state); 124static void hsw_set_transconf(const struct intel_crtc_state *crtc_state); 125static void bdw_set_pipe_misc(const struct intel_crtc_state *crtc_state); 126 127/* returns HPLL frequency in kHz */ 128int vlv_get_hpll_vco(struct drm_i915_private *dev_priv) 129{ 130 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; 131 132 /* Obtain SKU information */ 133 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & 134 CCK_FUSE_HPLL_FREQ_MASK; 135 136 return vco_freq[hpll_freq] * 1000; 137} 138 139int vlv_get_cck_clock(struct drm_i915_private *dev_priv, 140 const char *name, u32 reg, int ref_freq) 141{ 142 u32 val; 143 int divider; 144 145 val = vlv_cck_read(dev_priv, reg); 146 divider = val & CCK_FREQUENCY_VALUES; 147 148 drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) != 149 (divider << CCK_FREQUENCY_STATUS_SHIFT), 150 "%s change in progress\n", name); 151 152 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1); 153} 154 155int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, 156 const char *name, u32 reg) 157{ 158 int hpll; 159 160 vlv_cck_get(dev_priv); 161 162 if (dev_priv->hpll_freq == 0) 163 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv); 164 165 hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq); 166 167 vlv_cck_put(dev_priv); 168 169 return hpll; 170} 171 172void intel_update_czclk(struct drm_i915_private *dev_priv) 173{ 174 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) 175 return; 176 177 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", 178 CCK_CZ_CLOCK_CONTROL); 179 180 drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n", 181 dev_priv->czclk_freq); 182} 183 184static bool is_hdr_mode(const struct intel_crtc_state *crtc_state) 185{ 186 return (crtc_state->active_planes & 187 ~(icl_hdr_plane_mask() | BIT(PLANE_CURSOR))) == 0; 188} 189 190/* WA Display #0827: Gen9:all */ 191static void 192skl_wa_827(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable) 193{ 194 if (enable) 195 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), 196 0, DUPS1_GATING_DIS | DUPS2_GATING_DIS); 197 else 198 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), 199 DUPS1_GATING_DIS | DUPS2_GATING_DIS, 0); 200} 201 202/* Wa_2006604312:icl,ehl */ 203static void 204icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe, 205 bool enable) 206{ 207 if (enable) 208 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), 0, DPFR_GATING_DIS); 209 else 210 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), DPFR_GATING_DIS, 0); 211} 212 213/* Wa_1604331009:icl,jsl,ehl */ 214static void 215icl_wa_cursorclkgating(struct drm_i915_private *dev_priv, enum pipe pipe, 216 bool enable) 217{ 218 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), CURSOR_GATING_DIS, 219 enable ? CURSOR_GATING_DIS : 0); 220} 221 222static bool 223is_trans_port_sync_slave(const struct intel_crtc_state *crtc_state) 224{ 225 return crtc_state->master_transcoder != INVALID_TRANSCODER; 226} 227 228bool 229is_trans_port_sync_master(const struct intel_crtc_state *crtc_state) 230{ 231 return crtc_state->sync_mode_slaves_mask != 0; 232} 233 234bool 235is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state) 236{ 237 return is_trans_port_sync_master(crtc_state) || 238 is_trans_port_sync_slave(crtc_state); 239} 240 241static enum pipe bigjoiner_master_pipe(const struct intel_crtc_state *crtc_state) 242{ 243 return ffs(crtc_state->bigjoiner_pipes) - 1; 244} 245 246u8 intel_crtc_bigjoiner_slave_pipes(const struct intel_crtc_state *crtc_state) 247{ 248 if (crtc_state->bigjoiner_pipes) 249 return crtc_state->bigjoiner_pipes & ~BIT(bigjoiner_master_pipe(crtc_state)); 250 else 251 return 0; 252} 253 254bool intel_crtc_is_bigjoiner_slave(const struct intel_crtc_state *crtc_state) 255{ 256 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 257 258 return crtc_state->bigjoiner_pipes && 259 crtc->pipe != bigjoiner_master_pipe(crtc_state); 260} 261 262bool intel_crtc_is_bigjoiner_master(const struct intel_crtc_state *crtc_state) 263{ 264 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 265 266 return crtc_state->bigjoiner_pipes && 267 crtc->pipe == bigjoiner_master_pipe(crtc_state); 268} 269 270static int intel_bigjoiner_num_pipes(const struct intel_crtc_state *crtc_state) 271{ 272 return hweight8(crtc_state->bigjoiner_pipes); 273} 274 275struct intel_crtc *intel_master_crtc(const struct intel_crtc_state *crtc_state) 276{ 277 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 278 279 if (intel_crtc_is_bigjoiner_slave(crtc_state)) 280 return intel_crtc_for_pipe(i915, bigjoiner_master_pipe(crtc_state)); 281 else 282 return to_intel_crtc(crtc_state->uapi.crtc); 283} 284 285static void 286intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state) 287{ 288 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 289 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 290 291 if (DISPLAY_VER(dev_priv) >= 4) { 292 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 293 294 /* Wait for the Pipe State to go off */ 295 if (intel_de_wait_for_clear(dev_priv, TRANSCONF(cpu_transcoder), 296 TRANSCONF_STATE_ENABLE, 100)) 297 drm_WARN(&dev_priv->drm, 1, "pipe_off wait timed out\n"); 298 } else { 299 intel_wait_for_pipe_scanline_stopped(crtc); 300 } 301} 302 303void assert_transcoder(struct drm_i915_private *dev_priv, 304 enum transcoder cpu_transcoder, bool state) 305{ 306 bool cur_state; 307 enum intel_display_power_domain power_domain; 308 intel_wakeref_t wakeref; 309 310 /* we keep both pipes enabled on 830 */ 311 if (IS_I830(dev_priv)) 312 state = true; 313 314 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 315 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 316 if (wakeref) { 317 u32 val = intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)); 318 cur_state = !!(val & TRANSCONF_ENABLE); 319 320 intel_display_power_put(dev_priv, power_domain, wakeref); 321 } else { 322 cur_state = false; 323 } 324 325 I915_STATE_WARN(dev_priv, cur_state != state, 326 "transcoder %s assertion failure (expected %s, current %s)\n", 327 transcoder_name(cpu_transcoder), str_on_off(state), 328 str_on_off(cur_state)); 329} 330 331static void assert_plane(struct intel_plane *plane, bool state) 332{ 333 struct drm_i915_private *i915 = to_i915(plane->base.dev); 334 enum pipe pipe; 335 bool cur_state; 336 337 cur_state = plane->get_hw_state(plane, &pipe); 338 339 I915_STATE_WARN(i915, cur_state != state, 340 "%s assertion failure (expected %s, current %s)\n", 341 plane->base.name, str_on_off(state), 342 str_on_off(cur_state)); 343} 344 345#define assert_plane_enabled(p) assert_plane(p, true) 346#define assert_plane_disabled(p) assert_plane(p, false) 347 348static void assert_planes_disabled(struct intel_crtc *crtc) 349{ 350 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 351 struct intel_plane *plane; 352 353 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) 354 assert_plane_disabled(plane); 355} 356 357void vlv_wait_port_ready(struct drm_i915_private *dev_priv, 358 struct intel_digital_port *dig_port, 359 unsigned int expected_mask) 360{ 361 u32 port_mask; 362 i915_reg_t dpll_reg; 363 364 switch (dig_port->base.port) { 365 default: 366 MISSING_CASE(dig_port->base.port); 367 fallthrough; 368 case PORT_B: 369 port_mask = DPLL_PORTB_READY_MASK; 370 dpll_reg = DPLL(0); 371 break; 372 case PORT_C: 373 port_mask = DPLL_PORTC_READY_MASK; 374 dpll_reg = DPLL(0); 375 expected_mask <<= 4; 376 break; 377 case PORT_D: 378 port_mask = DPLL_PORTD_READY_MASK; 379 dpll_reg = DPIO_PHY_STATUS; 380 break; 381 } 382 383 if (intel_de_wait_for_register(dev_priv, dpll_reg, 384 port_mask, expected_mask, 1000)) 385 drm_WARN(&dev_priv->drm, 1, 386 "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n", 387 dig_port->base.base.base.id, dig_port->base.base.name, 388 intel_de_read(dev_priv, dpll_reg) & port_mask, 389 expected_mask); 390} 391 392void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state) 393{ 394 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 395 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 396 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; 397 enum pipe pipe = crtc->pipe; 398 i915_reg_t reg; 399 u32 val; 400 401 drm_dbg_kms(&dev_priv->drm, "enabling pipe %c\n", pipe_name(pipe)); 402 403 assert_planes_disabled(crtc); 404 405 /* 406 * A pipe without a PLL won't actually be able to drive bits from 407 * a plane. On ILK+ the pipe PLLs are integrated, so we don't 408 * need the check. 409 */ 410 if (HAS_GMCH(dev_priv)) { 411 if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI)) 412 assert_dsi_pll_enabled(dev_priv); 413 else 414 assert_pll_enabled(dev_priv, pipe); 415 } else { 416 if (new_crtc_state->has_pch_encoder) { 417 /* if driving the PCH, we need FDI enabled */ 418 assert_fdi_rx_pll_enabled(dev_priv, 419 intel_crtc_pch_transcoder(crtc)); 420 assert_fdi_tx_pll_enabled(dev_priv, 421 (enum pipe) cpu_transcoder); 422 } 423 /* FIXME: assert CPU port conditions for SNB+ */ 424 } 425 426 /* Wa_22012358565:adl-p */ 427 if (DISPLAY_VER(dev_priv) == 13) 428 intel_de_rmw(dev_priv, PIPE_ARB_CTL(pipe), 429 0, PIPE_ARB_USE_PROG_SLOTS); 430 431 reg = TRANSCONF(cpu_transcoder); 432 val = intel_de_read(dev_priv, reg); 433 if (val & TRANSCONF_ENABLE) { 434 /* we keep both pipes enabled on 830 */ 435 drm_WARN_ON(&dev_priv->drm, !IS_I830(dev_priv)); 436 return; 437 } 438 439 intel_de_write(dev_priv, reg, val | TRANSCONF_ENABLE); 440 intel_de_posting_read(dev_priv, reg); 441 442 /* 443 * Until the pipe starts PIPEDSL reads will return a stale value, 444 * which causes an apparent vblank timestamp jump when PIPEDSL 445 * resets to its proper value. That also messes up the frame count 446 * when it's derived from the timestamps. So let's wait for the 447 * pipe to start properly before we call drm_crtc_vblank_on() 448 */ 449 if (intel_crtc_max_vblank_count(new_crtc_state) == 0) 450 intel_wait_for_pipe_scanline_moving(crtc); 451} 452 453void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state) 454{ 455 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 456 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 457 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 458 enum pipe pipe = crtc->pipe; 459 i915_reg_t reg; 460 u32 val; 461 462 drm_dbg_kms(&dev_priv->drm, "disabling pipe %c\n", pipe_name(pipe)); 463 464 /* 465 * Make sure planes won't keep trying to pump pixels to us, 466 * or we might hang the display. 467 */ 468 assert_planes_disabled(crtc); 469 470 reg = TRANSCONF(cpu_transcoder); 471 val = intel_de_read(dev_priv, reg); 472 if ((val & TRANSCONF_ENABLE) == 0) 473 return; 474 475 /* 476 * Double wide has implications for planes 477 * so best keep it disabled when not needed. 478 */ 479 if (old_crtc_state->double_wide) 480 val &= ~TRANSCONF_DOUBLE_WIDE; 481 482 /* Don't disable pipe or pipe PLLs if needed */ 483 if (!IS_I830(dev_priv)) 484 val &= ~TRANSCONF_ENABLE; 485 486 if (DISPLAY_VER(dev_priv) >= 14) 487 intel_de_rmw(dev_priv, MTL_CHICKEN_TRANS(cpu_transcoder), 488 FECSTALL_DIS_DPTSTREAM_DPTTG, 0); 489 else if (DISPLAY_VER(dev_priv) >= 12) 490 intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 491 FECSTALL_DIS_DPTSTREAM_DPTTG, 0); 492 493 intel_de_write(dev_priv, reg, val); 494 if ((val & TRANSCONF_ENABLE) == 0) 495 intel_wait_for_pipe_off(old_crtc_state); 496} 497 498unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info) 499{ 500 unsigned int size = 0; 501 int i; 502 503 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) 504 size += rot_info->plane[i].dst_stride * rot_info->plane[i].width; 505 506 return size; 507} 508 509unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info) 510{ 511 unsigned int size = 0; 512 int i; 513 514 for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++) { 515 unsigned int plane_size; 516 517 if (rem_info->plane[i].linear) 518 plane_size = rem_info->plane[i].size; 519 else 520 plane_size = rem_info->plane[i].dst_stride * rem_info->plane[i].height; 521 522 if (plane_size == 0) 523 continue; 524 525 if (rem_info->plane_alignment) 526 size = ALIGN(size, rem_info->plane_alignment); 527 528 size += plane_size; 529 } 530 531 return size; 532} 533 534bool intel_plane_uses_fence(const struct intel_plane_state *plane_state) 535{ 536 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 537 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 538 539 return DISPLAY_VER(dev_priv) < 4 || 540 (plane->fbc && 541 plane_state->view.gtt.type == I915_GTT_VIEW_NORMAL); 542} 543 544/* 545 * Convert the x/y offsets into a linear offset. 546 * Only valid with 0/180 degree rotation, which is fine since linear 547 * offset is only used with linear buffers on pre-hsw and tiled buffers 548 * with gen2/3, and 90/270 degree rotations isn't supported on any of them. 549 */ 550u32 intel_fb_xy_to_linear(int x, int y, 551 const struct intel_plane_state *state, 552 int color_plane) 553{ 554 const struct drm_framebuffer *fb = state->hw.fb; 555 unsigned int cpp = fb->format->cpp[color_plane]; 556 unsigned int pitch = state->view.color_plane[color_plane].mapping_stride; 557 558 return y * pitch + x * cpp; 559} 560 561/* 562 * Add the x/y offsets derived from fb->offsets[] to the user 563 * specified plane src x/y offsets. The resulting x/y offsets 564 * specify the start of scanout from the beginning of the gtt mapping. 565 */ 566void intel_add_fb_offsets(int *x, int *y, 567 const struct intel_plane_state *state, 568 int color_plane) 569 570{ 571 *x += state->view.color_plane[color_plane].x; 572 *y += state->view.color_plane[color_plane].y; 573} 574 575u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv, 576 u32 pixel_format, u64 modifier) 577{ 578 struct intel_crtc *crtc; 579 struct intel_plane *plane; 580 581 if (!HAS_DISPLAY(dev_priv)) 582 return 0; 583 584 /* 585 * We assume the primary plane for pipe A has 586 * the highest stride limits of them all, 587 * if in case pipe A is disabled, use the first pipe from pipe_mask. 588 */ 589 crtc = intel_first_crtc(dev_priv); 590 if (!crtc) 591 return 0; 592 593 plane = to_intel_plane(crtc->base.primary); 594 595 return plane->max_stride(plane, pixel_format, modifier, 596 DRM_MODE_ROTATE_0); 597} 598 599void intel_set_plane_visible(struct intel_crtc_state *crtc_state, 600 struct intel_plane_state *plane_state, 601 bool visible) 602{ 603 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 604 605 plane_state->uapi.visible = visible; 606 607 if (visible) 608 crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base); 609 else 610 crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base); 611} 612 613void intel_plane_fixup_bitmasks(struct intel_crtc_state *crtc_state) 614{ 615 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 616 struct drm_plane *plane; 617 618 /* 619 * Active_planes aliases if multiple "primary" or cursor planes 620 * have been used on the same (or wrong) pipe. plane_mask uses 621 * unique ids, hence we can use that to reconstruct active_planes. 622 */ 623 crtc_state->enabled_planes = 0; 624 crtc_state->active_planes = 0; 625 626 drm_for_each_plane_mask(plane, &dev_priv->drm, 627 crtc_state->uapi.plane_mask) { 628 crtc_state->enabled_planes |= BIT(to_intel_plane(plane)->id); 629 crtc_state->active_planes |= BIT(to_intel_plane(plane)->id); 630 } 631} 632 633void intel_plane_disable_noatomic(struct intel_crtc *crtc, 634 struct intel_plane *plane) 635{ 636 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 637 struct intel_crtc_state *crtc_state = 638 to_intel_crtc_state(crtc->base.state); 639 struct intel_plane_state *plane_state = 640 to_intel_plane_state(plane->base.state); 641 642 drm_dbg_kms(&dev_priv->drm, 643 "Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n", 644 plane->base.base.id, plane->base.name, 645 crtc->base.base.id, crtc->base.name); 646 647 intel_set_plane_visible(crtc_state, plane_state, false); 648 intel_plane_fixup_bitmasks(crtc_state); 649 crtc_state->data_rate[plane->id] = 0; 650 crtc_state->data_rate_y[plane->id] = 0; 651 crtc_state->rel_data_rate[plane->id] = 0; 652 crtc_state->rel_data_rate_y[plane->id] = 0; 653 crtc_state->min_cdclk[plane->id] = 0; 654 655 if ((crtc_state->active_planes & ~BIT(PLANE_CURSOR)) == 0 && 656 hsw_ips_disable(crtc_state)) { 657 crtc_state->ips_enabled = false; 658 intel_crtc_wait_for_next_vblank(crtc); 659 } 660 661 /* 662 * Vblank time updates from the shadow to live plane control register 663 * are blocked if the memory self-refresh mode is active at that 664 * moment. So to make sure the plane gets truly disabled, disable 665 * first the self-refresh mode. The self-refresh enable bit in turn 666 * will be checked/applied by the HW only at the next frame start 667 * event which is after the vblank start event, so we need to have a 668 * wait-for-vblank between disabling the plane and the pipe. 669 */ 670 if (HAS_GMCH(dev_priv) && 671 intel_set_memory_cxsr(dev_priv, false)) 672 intel_crtc_wait_for_next_vblank(crtc); 673 674 /* 675 * Gen2 reports pipe underruns whenever all planes are disabled. 676 * So disable underrun reporting before all the planes get disabled. 677 */ 678 if (DISPLAY_VER(dev_priv) == 2 && !crtc_state->active_planes) 679 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false); 680 681 intel_plane_disable_arm(plane, crtc_state); 682 intel_crtc_wait_for_next_vblank(crtc); 683} 684 685unsigned int 686intel_plane_fence_y_offset(const struct intel_plane_state *plane_state) 687{ 688 int x = 0, y = 0; 689 690 intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0, 691 plane_state->view.color_plane[0].offset, 0); 692 693 return y; 694} 695 696static void icl_set_pipe_chicken(const struct intel_crtc_state *crtc_state) 697{ 698 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 699 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 700 enum pipe pipe = crtc->pipe; 701 u32 tmp; 702 703 tmp = intel_de_read(dev_priv, PIPE_CHICKEN(pipe)); 704 705 /* 706 * Display WA #1153: icl 707 * enable hardware to bypass the alpha math 708 * and rounding for per-pixel values 00 and 0xff 709 */ 710 tmp |= PER_PIXEL_ALPHA_BYPASS_EN; 711 /* 712 * Display WA # 1605353570: icl 713 * Set the pixel rounding bit to 1 for allowing 714 * passthrough of Frame buffer pixels unmodified 715 * across pipe 716 */ 717 tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU; 718 719 /* 720 * Underrun recovery must always be disabled on display 13+. 721 * DG2 chicken bit meaning is inverted compared to other platforms. 722 */ 723 if (IS_DG2(dev_priv)) 724 tmp &= ~UNDERRUN_RECOVERY_ENABLE_DG2; 725 else if (DISPLAY_VER(dev_priv) >= 13) 726 tmp |= UNDERRUN_RECOVERY_DISABLE_ADLP; 727 728 /* Wa_14010547955:dg2 */ 729 if (IS_DG2_DISPLAY_STEP(dev_priv, STEP_B0, STEP_FOREVER)) 730 tmp |= DG2_RENDER_CCSTAG_4_3_EN; 731 732 intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp); 733} 734 735bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv) 736{ 737 struct drm_crtc *crtc; 738 bool cleanup_done; 739 740 drm_for_each_crtc(crtc, &dev_priv->drm) { 741 struct drm_crtc_commit *commit; 742 spin_lock(&crtc->commit_lock); 743 commit = list_first_entry_or_null(&crtc->commit_list, 744 struct drm_crtc_commit, commit_entry); 745 cleanup_done = commit ? 746 try_wait_for_completion(&commit->cleanup_done) : true; 747 spin_unlock(&crtc->commit_lock); 748 749 if (cleanup_done) 750 continue; 751 752 intel_crtc_wait_for_next_vblank(to_intel_crtc(crtc)); 753 754 return true; 755 } 756 757 return false; 758} 759 760/* 761 * Finds the encoder associated with the given CRTC. This can only be 762 * used when we know that the CRTC isn't feeding multiple encoders! 763 */ 764struct intel_encoder * 765intel_get_crtc_new_encoder(const struct intel_atomic_state *state, 766 const struct intel_crtc_state *crtc_state) 767{ 768 const struct drm_connector_state *connector_state; 769 const struct drm_connector *connector; 770 struct intel_encoder *encoder = NULL; 771 struct intel_crtc *master_crtc; 772 int num_encoders = 0; 773 int i; 774 775 master_crtc = intel_master_crtc(crtc_state); 776 777 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 778 if (connector_state->crtc != &master_crtc->base) 779 continue; 780 781 encoder = to_intel_encoder(connector_state->best_encoder); 782 num_encoders++; 783 } 784 785 drm_WARN(state->base.dev, num_encoders != 1, 786 "%d encoders for pipe %c\n", 787 num_encoders, pipe_name(master_crtc->pipe)); 788 789 return encoder; 790} 791 792static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state) 793{ 794 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 795 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 796 const struct drm_rect *dst = &crtc_state->pch_pfit.dst; 797 enum pipe pipe = crtc->pipe; 798 int width = drm_rect_width(dst); 799 int height = drm_rect_height(dst); 800 int x = dst->x1; 801 int y = dst->y1; 802 803 if (!crtc_state->pch_pfit.enabled) 804 return; 805 806 /* Force use of hard-coded filter coefficients 807 * as some pre-programmed values are broken, 808 * e.g. x201. 809 */ 810 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) 811 intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE | 812 PF_FILTER_MED_3x3 | PF_PIPE_SEL_IVB(pipe)); 813 else 814 intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE | 815 PF_FILTER_MED_3x3); 816 intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), 817 PF_WIN_XPOS(x) | PF_WIN_YPOS(y)); 818 intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), 819 PF_WIN_XSIZE(width) | PF_WIN_YSIZE(height)); 820} 821 822static void intel_crtc_dpms_overlay_disable(struct intel_crtc *crtc) 823{ 824 if (crtc->overlay) 825 (void) intel_overlay_switch_off(crtc->overlay); 826 827 /* Let userspace switch the overlay on again. In most cases userspace 828 * has to recompute where to put it anyway. 829 */ 830} 831 832static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state) 833{ 834 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 835 836 if (!crtc_state->nv12_planes) 837 return false; 838 839 /* WA Display #0827: Gen9:all */ 840 if (DISPLAY_VER(dev_priv) == 9) 841 return true; 842 843 return false; 844} 845 846static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state) 847{ 848 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 849 850 /* Wa_2006604312:icl,ehl */ 851 if (crtc_state->scaler_state.scaler_users > 0 && DISPLAY_VER(dev_priv) == 11) 852 return true; 853 854 return false; 855} 856 857static bool needs_cursorclk_wa(const struct intel_crtc_state *crtc_state) 858{ 859 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 860 861 /* Wa_1604331009:icl,jsl,ehl */ 862 if (is_hdr_mode(crtc_state) && 863 crtc_state->active_planes & BIT(PLANE_CURSOR) && 864 DISPLAY_VER(dev_priv) == 11) 865 return true; 866 867 return false; 868} 869 870static void intel_async_flip_vtd_wa(struct drm_i915_private *i915, 871 enum pipe pipe, bool enable) 872{ 873 if (DISPLAY_VER(i915) == 9) { 874 /* 875 * "Plane N strech max must be programmed to 11b (x1) 876 * when Async flips are enabled on that plane." 877 */ 878 intel_de_rmw(i915, CHICKEN_PIPESL_1(pipe), 879 SKL_PLANE1_STRETCH_MAX_MASK, 880 enable ? SKL_PLANE1_STRETCH_MAX_X1 : SKL_PLANE1_STRETCH_MAX_X8); 881 } else { 882 /* Also needed on HSW/BDW albeit undocumented */ 883 intel_de_rmw(i915, CHICKEN_PIPESL_1(pipe), 884 HSW_PRI_STRETCH_MAX_MASK, 885 enable ? HSW_PRI_STRETCH_MAX_X1 : HSW_PRI_STRETCH_MAX_X8); 886 } 887} 888 889static bool needs_async_flip_vtd_wa(const struct intel_crtc_state *crtc_state) 890{ 891 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 892 893 return crtc_state->uapi.async_flip && i915_vtd_active(i915) && 894 (DISPLAY_VER(i915) == 9 || IS_BROADWELL(i915) || IS_HASWELL(i915)); 895} 896 897#define is_enabling(feature, old_crtc_state, new_crtc_state) \ 898 ((!(old_crtc_state)->feature || intel_crtc_needs_modeset(new_crtc_state)) && \ 899 (new_crtc_state)->feature) 900#define is_disabling(feature, old_crtc_state, new_crtc_state) \ 901 ((old_crtc_state)->feature && \ 902 (!(new_crtc_state)->feature || intel_crtc_needs_modeset(new_crtc_state))) 903 904static bool planes_enabling(const struct intel_crtc_state *old_crtc_state, 905 const struct intel_crtc_state *new_crtc_state) 906{ 907 return is_enabling(active_planes, old_crtc_state, new_crtc_state); 908} 909 910static bool planes_disabling(const struct intel_crtc_state *old_crtc_state, 911 const struct intel_crtc_state *new_crtc_state) 912{ 913 return is_disabling(active_planes, old_crtc_state, new_crtc_state); 914} 915 916static bool vrr_enabling(const struct intel_crtc_state *old_crtc_state, 917 const struct intel_crtc_state *new_crtc_state) 918{ 919 return is_enabling(vrr.enable, old_crtc_state, new_crtc_state); 920} 921 922static bool vrr_disabling(const struct intel_crtc_state *old_crtc_state, 923 const struct intel_crtc_state *new_crtc_state) 924{ 925 return is_disabling(vrr.enable, old_crtc_state, new_crtc_state); 926} 927 928#undef is_disabling 929#undef is_enabling 930 931static void intel_post_plane_update(struct intel_atomic_state *state, 932 struct intel_crtc *crtc) 933{ 934 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 935 const struct intel_crtc_state *old_crtc_state = 936 intel_atomic_get_old_crtc_state(state, crtc); 937 const struct intel_crtc_state *new_crtc_state = 938 intel_atomic_get_new_crtc_state(state, crtc); 939 enum pipe pipe = crtc->pipe; 940 941 intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits); 942 943 if (new_crtc_state->update_wm_post && new_crtc_state->hw.active) 944 intel_update_watermarks(dev_priv); 945 946 intel_fbc_post_update(state, crtc); 947 948 if (needs_async_flip_vtd_wa(old_crtc_state) && 949 !needs_async_flip_vtd_wa(new_crtc_state)) 950 intel_async_flip_vtd_wa(dev_priv, pipe, false); 951 952 if (needs_nv12_wa(old_crtc_state) && 953 !needs_nv12_wa(new_crtc_state)) 954 skl_wa_827(dev_priv, pipe, false); 955 956 if (needs_scalerclk_wa(old_crtc_state) && 957 !needs_scalerclk_wa(new_crtc_state)) 958 icl_wa_scalerclkgating(dev_priv, pipe, false); 959 960 if (needs_cursorclk_wa(old_crtc_state) && 961 !needs_cursorclk_wa(new_crtc_state)) 962 icl_wa_cursorclkgating(dev_priv, pipe, false); 963 964 if (intel_crtc_needs_color_update(new_crtc_state)) 965 intel_color_post_update(new_crtc_state); 966} 967 968static void intel_crtc_enable_flip_done(struct intel_atomic_state *state, 969 struct intel_crtc *crtc) 970{ 971 const struct intel_crtc_state *crtc_state = 972 intel_atomic_get_new_crtc_state(state, crtc); 973 u8 update_planes = crtc_state->update_planes; 974 const struct intel_plane_state __maybe_unused *plane_state; 975 struct intel_plane *plane; 976 int i; 977 978 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 979 if (plane->pipe == crtc->pipe && 980 update_planes & BIT(plane->id)) 981 plane->enable_flip_done(plane); 982 } 983} 984 985static void intel_crtc_disable_flip_done(struct intel_atomic_state *state, 986 struct intel_crtc *crtc) 987{ 988 const struct intel_crtc_state *crtc_state = 989 intel_atomic_get_new_crtc_state(state, crtc); 990 u8 update_planes = crtc_state->update_planes; 991 const struct intel_plane_state __maybe_unused *plane_state; 992 struct intel_plane *plane; 993 int i; 994 995 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 996 if (plane->pipe == crtc->pipe && 997 update_planes & BIT(plane->id)) 998 plane->disable_flip_done(plane); 999 } 1000} 1001 1002static void intel_crtc_async_flip_disable_wa(struct intel_atomic_state *state, 1003 struct intel_crtc *crtc) 1004{ 1005 const struct intel_crtc_state *old_crtc_state = 1006 intel_atomic_get_old_crtc_state(state, crtc); 1007 const struct intel_crtc_state *new_crtc_state = 1008 intel_atomic_get_new_crtc_state(state, crtc); 1009 u8 disable_async_flip_planes = old_crtc_state->async_flip_planes & 1010 ~new_crtc_state->async_flip_planes; 1011 const struct intel_plane_state *old_plane_state; 1012 struct intel_plane *plane; 1013 bool need_vbl_wait = false; 1014 int i; 1015 1016 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) { 1017 if (plane->need_async_flip_disable_wa && 1018 plane->pipe == crtc->pipe && 1019 disable_async_flip_planes & BIT(plane->id)) { 1020 /* 1021 * Apart from the async flip bit we want to 1022 * preserve the old state for the plane. 1023 */ 1024 plane->async_flip(plane, old_crtc_state, 1025 old_plane_state, false); 1026 need_vbl_wait = true; 1027 } 1028 } 1029 1030 if (need_vbl_wait) 1031 intel_crtc_wait_for_next_vblank(crtc); 1032} 1033 1034static void intel_pre_plane_update(struct intel_atomic_state *state, 1035 struct intel_crtc *crtc) 1036{ 1037 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1038 const struct intel_crtc_state *old_crtc_state = 1039 intel_atomic_get_old_crtc_state(state, crtc); 1040 const struct intel_crtc_state *new_crtc_state = 1041 intel_atomic_get_new_crtc_state(state, crtc); 1042 enum pipe pipe = crtc->pipe; 1043 1044 if (vrr_disabling(old_crtc_state, new_crtc_state)) { 1045 intel_vrr_disable(old_crtc_state); 1046 intel_crtc_update_active_timings(old_crtc_state, false); 1047 } 1048 1049 intel_drrs_deactivate(old_crtc_state); 1050 1051 intel_psr_pre_plane_update(state, crtc); 1052 1053 if (hsw_ips_pre_update(state, crtc)) 1054 intel_crtc_wait_for_next_vblank(crtc); 1055 1056 if (intel_fbc_pre_update(state, crtc)) 1057 intel_crtc_wait_for_next_vblank(crtc); 1058 1059 if (!needs_async_flip_vtd_wa(old_crtc_state) && 1060 needs_async_flip_vtd_wa(new_crtc_state)) 1061 intel_async_flip_vtd_wa(dev_priv, pipe, true); 1062 1063 /* Display WA 827 */ 1064 if (!needs_nv12_wa(old_crtc_state) && 1065 needs_nv12_wa(new_crtc_state)) 1066 skl_wa_827(dev_priv, pipe, true); 1067 1068 /* Wa_2006604312:icl,ehl */ 1069 if (!needs_scalerclk_wa(old_crtc_state) && 1070 needs_scalerclk_wa(new_crtc_state)) 1071 icl_wa_scalerclkgating(dev_priv, pipe, true); 1072 1073 /* Wa_1604331009:icl,jsl,ehl */ 1074 if (!needs_cursorclk_wa(old_crtc_state) && 1075 needs_cursorclk_wa(new_crtc_state)) 1076 icl_wa_cursorclkgating(dev_priv, pipe, true); 1077 1078 /* 1079 * Vblank time updates from the shadow to live plane control register 1080 * are blocked if the memory self-refresh mode is active at that 1081 * moment. So to make sure the plane gets truly disabled, disable 1082 * first the self-refresh mode. The self-refresh enable bit in turn 1083 * will be checked/applied by the HW only at the next frame start 1084 * event which is after the vblank start event, so we need to have a 1085 * wait-for-vblank between disabling the plane and the pipe. 1086 */ 1087 if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active && 1088 new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv, false)) 1089 intel_crtc_wait_for_next_vblank(crtc); 1090 1091 /* 1092 * IVB workaround: must disable low power watermarks for at least 1093 * one frame before enabling scaling. LP watermarks can be re-enabled 1094 * when scaling is disabled. 1095 * 1096 * WaCxSRDisabledForSpriteScaling:ivb 1097 */ 1098 if (old_crtc_state->hw.active && 1099 new_crtc_state->disable_lp_wm && ilk_disable_lp_wm(dev_priv)) 1100 intel_crtc_wait_for_next_vblank(crtc); 1101 1102 /* 1103 * If we're doing a modeset we don't need to do any 1104 * pre-vblank watermark programming here. 1105 */ 1106 if (!intel_crtc_needs_modeset(new_crtc_state)) { 1107 /* 1108 * For platforms that support atomic watermarks, program the 1109 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these 1110 * will be the intermediate values that are safe for both pre- and 1111 * post- vblank; when vblank happens, the 'active' values will be set 1112 * to the final 'target' values and we'll do this again to get the 1113 * optimal watermarks. For gen9+ platforms, the values we program here 1114 * will be the final target values which will get automatically latched 1115 * at vblank time; no further programming will be necessary. 1116 * 1117 * If a platform hasn't been transitioned to atomic watermarks yet, 1118 * we'll continue to update watermarks the old way, if flags tell 1119 * us to. 1120 */ 1121 if (!intel_initial_watermarks(state, crtc)) 1122 if (new_crtc_state->update_wm_pre) 1123 intel_update_watermarks(dev_priv); 1124 } 1125 1126 /* 1127 * Gen2 reports pipe underruns whenever all planes are disabled. 1128 * So disable underrun reporting before all the planes get disabled. 1129 * 1130 * We do this after .initial_watermarks() so that we have a 1131 * chance of catching underruns with the intermediate watermarks 1132 * vs. the old plane configuration. 1133 */ 1134 if (DISPLAY_VER(dev_priv) == 2 && planes_disabling(old_crtc_state, new_crtc_state)) 1135 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 1136 1137 /* 1138 * WA for platforms where async address update enable bit 1139 * is double buffered and only latched at start of vblank. 1140 */ 1141 if (old_crtc_state->async_flip_planes & ~new_crtc_state->async_flip_planes) 1142 intel_crtc_async_flip_disable_wa(state, crtc); 1143} 1144 1145static void intel_crtc_disable_planes(struct intel_atomic_state *state, 1146 struct intel_crtc *crtc) 1147{ 1148 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1149 const struct intel_crtc_state *new_crtc_state = 1150 intel_atomic_get_new_crtc_state(state, crtc); 1151 unsigned int update_mask = new_crtc_state->update_planes; 1152 const struct intel_plane_state *old_plane_state; 1153 struct intel_plane *plane; 1154 unsigned fb_bits = 0; 1155 int i; 1156 1157 intel_crtc_dpms_overlay_disable(crtc); 1158 1159 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) { 1160 if (crtc->pipe != plane->pipe || 1161 !(update_mask & BIT(plane->id))) 1162 continue; 1163 1164 intel_plane_disable_arm(plane, new_crtc_state); 1165 1166 if (old_plane_state->uapi.visible) 1167 fb_bits |= plane->frontbuffer_bit; 1168 } 1169 1170 intel_frontbuffer_flip(dev_priv, fb_bits); 1171} 1172 1173static void intel_encoders_update_prepare(struct intel_atomic_state *state) 1174{ 1175 struct drm_i915_private *i915 = to_i915(state->base.dev); 1176 struct intel_crtc_state *new_crtc_state, *old_crtc_state; 1177 struct intel_crtc *crtc; 1178 int i; 1179 1180 /* 1181 * Make sure the DPLL state is up-to-date for fastset TypeC ports after non-blocking commits. 1182 * TODO: Update the DPLL state for all cases in the encoder->update_prepare() hook. 1183 */ 1184 if (i915->display.dpll.mgr) { 1185 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 1186 if (intel_crtc_needs_modeset(new_crtc_state)) 1187 continue; 1188 1189 new_crtc_state->shared_dpll = old_crtc_state->shared_dpll; 1190 new_crtc_state->dpll_hw_state = old_crtc_state->dpll_hw_state; 1191 } 1192 } 1193} 1194 1195static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state, 1196 struct intel_crtc *crtc) 1197{ 1198 const struct intel_crtc_state *crtc_state = 1199 intel_atomic_get_new_crtc_state(state, crtc); 1200 const struct drm_connector_state *conn_state; 1201 struct drm_connector *conn; 1202 int i; 1203 1204 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1205 struct intel_encoder *encoder = 1206 to_intel_encoder(conn_state->best_encoder); 1207 1208 if (conn_state->crtc != &crtc->base) 1209 continue; 1210 1211 if (encoder->pre_pll_enable) 1212 encoder->pre_pll_enable(state, encoder, 1213 crtc_state, conn_state); 1214 } 1215} 1216 1217static void intel_encoders_pre_enable(struct intel_atomic_state *state, 1218 struct intel_crtc *crtc) 1219{ 1220 const struct intel_crtc_state *crtc_state = 1221 intel_atomic_get_new_crtc_state(state, crtc); 1222 const struct drm_connector_state *conn_state; 1223 struct drm_connector *conn; 1224 int i; 1225 1226 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1227 struct intel_encoder *encoder = 1228 to_intel_encoder(conn_state->best_encoder); 1229 1230 if (conn_state->crtc != &crtc->base) 1231 continue; 1232 1233 if (encoder->pre_enable) 1234 encoder->pre_enable(state, encoder, 1235 crtc_state, conn_state); 1236 } 1237} 1238 1239static void intel_encoders_enable(struct intel_atomic_state *state, 1240 struct intel_crtc *crtc) 1241{ 1242 const struct intel_crtc_state *crtc_state = 1243 intel_atomic_get_new_crtc_state(state, crtc); 1244 const struct drm_connector_state *conn_state; 1245 struct drm_connector *conn; 1246 int i; 1247 1248 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1249 struct intel_encoder *encoder = 1250 to_intel_encoder(conn_state->best_encoder); 1251 1252 if (conn_state->crtc != &crtc->base) 1253 continue; 1254 1255 if (encoder->enable) 1256 encoder->enable(state, encoder, 1257 crtc_state, conn_state); 1258 intel_opregion_notify_encoder(encoder, true); 1259 } 1260} 1261 1262static void intel_encoders_disable(struct intel_atomic_state *state, 1263 struct intel_crtc *crtc) 1264{ 1265 const struct intel_crtc_state *old_crtc_state = 1266 intel_atomic_get_old_crtc_state(state, crtc); 1267 const struct drm_connector_state *old_conn_state; 1268 struct drm_connector *conn; 1269 int i; 1270 1271 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 1272 struct intel_encoder *encoder = 1273 to_intel_encoder(old_conn_state->best_encoder); 1274 1275 if (old_conn_state->crtc != &crtc->base) 1276 continue; 1277 1278 intel_opregion_notify_encoder(encoder, false); 1279 if (encoder->disable) 1280 encoder->disable(state, encoder, 1281 old_crtc_state, old_conn_state); 1282 } 1283} 1284 1285static void intel_encoders_post_disable(struct intel_atomic_state *state, 1286 struct intel_crtc *crtc) 1287{ 1288 const struct intel_crtc_state *old_crtc_state = 1289 intel_atomic_get_old_crtc_state(state, crtc); 1290 const struct drm_connector_state *old_conn_state; 1291 struct drm_connector *conn; 1292 int i; 1293 1294 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 1295 struct intel_encoder *encoder = 1296 to_intel_encoder(old_conn_state->best_encoder); 1297 1298 if (old_conn_state->crtc != &crtc->base) 1299 continue; 1300 1301 if (encoder->post_disable) 1302 encoder->post_disable(state, encoder, 1303 old_crtc_state, old_conn_state); 1304 } 1305} 1306 1307static void intel_encoders_post_pll_disable(struct intel_atomic_state *state, 1308 struct intel_crtc *crtc) 1309{ 1310 const struct intel_crtc_state *old_crtc_state = 1311 intel_atomic_get_old_crtc_state(state, crtc); 1312 const struct drm_connector_state *old_conn_state; 1313 struct drm_connector *conn; 1314 int i; 1315 1316 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 1317 struct intel_encoder *encoder = 1318 to_intel_encoder(old_conn_state->best_encoder); 1319 1320 if (old_conn_state->crtc != &crtc->base) 1321 continue; 1322 1323 if (encoder->post_pll_disable) 1324 encoder->post_pll_disable(state, encoder, 1325 old_crtc_state, old_conn_state); 1326 } 1327} 1328 1329static void intel_encoders_update_pipe(struct intel_atomic_state *state, 1330 struct intel_crtc *crtc) 1331{ 1332 const struct intel_crtc_state *crtc_state = 1333 intel_atomic_get_new_crtc_state(state, crtc); 1334 const struct drm_connector_state *conn_state; 1335 struct drm_connector *conn; 1336 int i; 1337 1338 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1339 struct intel_encoder *encoder = 1340 to_intel_encoder(conn_state->best_encoder); 1341 1342 if (conn_state->crtc != &crtc->base) 1343 continue; 1344 1345 if (encoder->update_pipe) 1346 encoder->update_pipe(state, encoder, 1347 crtc_state, conn_state); 1348 } 1349} 1350 1351static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_state) 1352{ 1353 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1354 struct intel_plane *plane = to_intel_plane(crtc->base.primary); 1355 1356 plane->disable_arm(plane, crtc_state); 1357} 1358 1359static void ilk_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) 1360{ 1361 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1362 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1363 1364 if (crtc_state->has_pch_encoder) { 1365 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1366 &crtc_state->fdi_m_n); 1367 } else if (intel_crtc_has_dp_encoder(crtc_state)) { 1368 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1369 &crtc_state->dp_m_n); 1370 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, 1371 &crtc_state->dp_m2_n2); 1372 } 1373 1374 intel_set_transcoder_timings(crtc_state); 1375 1376 ilk_set_pipeconf(crtc_state); 1377} 1378 1379static void ilk_crtc_enable(struct intel_atomic_state *state, 1380 struct intel_crtc *crtc) 1381{ 1382 const struct intel_crtc_state *new_crtc_state = 1383 intel_atomic_get_new_crtc_state(state, crtc); 1384 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1385 enum pipe pipe = crtc->pipe; 1386 1387 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 1388 return; 1389 1390 /* 1391 * Sometimes spurious CPU pipe underruns happen during FDI 1392 * training, at least with VGA+HDMI cloning. Suppress them. 1393 * 1394 * On ILK we get an occasional spurious CPU pipe underruns 1395 * between eDP port A enable and vdd enable. Also PCH port 1396 * enable seems to result in the occasional CPU pipe underrun. 1397 * 1398 * Spurious PCH underruns also occur during PCH enabling. 1399 */ 1400 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 1401 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); 1402 1403 ilk_configure_cpu_transcoder(new_crtc_state); 1404 1405 intel_set_pipe_src_size(new_crtc_state); 1406 1407 crtc->active = true; 1408 1409 intel_encoders_pre_enable(state, crtc); 1410 1411 if (new_crtc_state->has_pch_encoder) { 1412 ilk_pch_pre_enable(state, crtc); 1413 } else { 1414 assert_fdi_tx_disabled(dev_priv, pipe); 1415 assert_fdi_rx_disabled(dev_priv, pipe); 1416 } 1417 1418 ilk_pfit_enable(new_crtc_state); 1419 1420 /* 1421 * On ILK+ LUT must be loaded before the pipe is running but with 1422 * clocks enabled 1423 */ 1424 intel_color_load_luts(new_crtc_state); 1425 intel_color_commit_noarm(new_crtc_state); 1426 intel_color_commit_arm(new_crtc_state); 1427 /* update DSPCNTR to configure gamma for pipe bottom color */ 1428 intel_disable_primary_plane(new_crtc_state); 1429 1430 intel_initial_watermarks(state, crtc); 1431 intel_enable_transcoder(new_crtc_state); 1432 1433 if (new_crtc_state->has_pch_encoder) 1434 ilk_pch_enable(state, crtc); 1435 1436 intel_crtc_vblank_on(new_crtc_state); 1437 1438 intel_encoders_enable(state, crtc); 1439 1440 if (HAS_PCH_CPT(dev_priv)) 1441 intel_wait_for_pipe_scanline_moving(crtc); 1442 1443 /* 1444 * Must wait for vblank to avoid spurious PCH FIFO underruns. 1445 * And a second vblank wait is needed at least on ILK with 1446 * some interlaced HDMI modes. Let's do the double wait always 1447 * in case there are more corner cases we don't know about. 1448 */ 1449 if (new_crtc_state->has_pch_encoder) { 1450 intel_crtc_wait_for_next_vblank(crtc); 1451 intel_crtc_wait_for_next_vblank(crtc); 1452 } 1453 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 1454 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); 1455} 1456 1457static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv, 1458 enum pipe pipe, bool apply) 1459{ 1460 u32 val = intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)); 1461 u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS; 1462 1463 if (apply) 1464 val |= mask; 1465 else 1466 val &= ~mask; 1467 1468 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), val); 1469} 1470 1471static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state) 1472{ 1473 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1474 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1475 1476 intel_de_write(dev_priv, WM_LINETIME(crtc->pipe), 1477 HSW_LINETIME(crtc_state->linetime) | 1478 HSW_IPS_LINETIME(crtc_state->ips_linetime)); 1479} 1480 1481static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state) 1482{ 1483 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1484 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1485 enum transcoder transcoder = crtc_state->cpu_transcoder; 1486 i915_reg_t reg = DISPLAY_VER(dev_priv) >= 14 ? MTL_CHICKEN_TRANS(transcoder) : 1487 CHICKEN_TRANS(transcoder); 1488 1489 intel_de_rmw(dev_priv, reg, 1490 HSW_FRAME_START_DELAY_MASK, 1491 HSW_FRAME_START_DELAY(crtc_state->framestart_delay - 1)); 1492} 1493 1494static void icl_ddi_bigjoiner_pre_enable(struct intel_atomic_state *state, 1495 const struct intel_crtc_state *crtc_state) 1496{ 1497 struct intel_crtc *master_crtc = intel_master_crtc(crtc_state); 1498 1499 /* 1500 * Enable sequence steps 1-7 on bigjoiner master 1501 */ 1502 if (intel_crtc_is_bigjoiner_slave(crtc_state)) 1503 intel_encoders_pre_pll_enable(state, master_crtc); 1504 1505 if (crtc_state->shared_dpll) 1506 intel_enable_shared_dpll(crtc_state); 1507 1508 if (intel_crtc_is_bigjoiner_slave(crtc_state)) 1509 intel_encoders_pre_enable(state, master_crtc); 1510} 1511 1512static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) 1513{ 1514 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1515 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1516 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1517 1518 if (crtc_state->has_pch_encoder) { 1519 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1520 &crtc_state->fdi_m_n); 1521 } else if (intel_crtc_has_dp_encoder(crtc_state)) { 1522 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1523 &crtc_state->dp_m_n); 1524 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, 1525 &crtc_state->dp_m2_n2); 1526 } 1527 1528 intel_set_transcoder_timings(crtc_state); 1529 if (HAS_VRR(dev_priv)) 1530 intel_vrr_set_transcoder_timings(crtc_state); 1531 1532 if (cpu_transcoder != TRANSCODER_EDP) 1533 intel_de_write(dev_priv, TRANS_MULT(cpu_transcoder), 1534 crtc_state->pixel_multiplier - 1); 1535 1536 hsw_set_frame_start_delay(crtc_state); 1537 1538 hsw_set_transconf(crtc_state); 1539} 1540 1541static void hsw_crtc_enable(struct intel_atomic_state *state, 1542 struct intel_crtc *crtc) 1543{ 1544 const struct intel_crtc_state *new_crtc_state = 1545 intel_atomic_get_new_crtc_state(state, crtc); 1546 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1547 enum pipe pipe = crtc->pipe, hsw_workaround_pipe; 1548 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; 1549 bool psl_clkgate_wa; 1550 1551 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 1552 return; 1553 1554 intel_dmc_enable_pipe(dev_priv, crtc->pipe); 1555 1556 if (!new_crtc_state->bigjoiner_pipes) { 1557 intel_encoders_pre_pll_enable(state, crtc); 1558 1559 if (new_crtc_state->shared_dpll) 1560 intel_enable_shared_dpll(new_crtc_state); 1561 1562 intel_encoders_pre_enable(state, crtc); 1563 } else { 1564 icl_ddi_bigjoiner_pre_enable(state, new_crtc_state); 1565 } 1566 1567 intel_dsc_enable(new_crtc_state); 1568 1569 if (DISPLAY_VER(dev_priv) >= 13) 1570 intel_uncompressed_joiner_enable(new_crtc_state); 1571 1572 intel_set_pipe_src_size(new_crtc_state); 1573 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) 1574 bdw_set_pipe_misc(new_crtc_state); 1575 1576 if (!intel_crtc_is_bigjoiner_slave(new_crtc_state) && 1577 !transcoder_is_dsi(cpu_transcoder)) 1578 hsw_configure_cpu_transcoder(new_crtc_state); 1579 1580 crtc->active = true; 1581 1582 /* Display WA #1180: WaDisableScalarClockGating: glk */ 1583 psl_clkgate_wa = DISPLAY_VER(dev_priv) == 10 && 1584 new_crtc_state->pch_pfit.enabled; 1585 if (psl_clkgate_wa) 1586 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true); 1587 1588 if (DISPLAY_VER(dev_priv) >= 9) 1589 skl_pfit_enable(new_crtc_state); 1590 else 1591 ilk_pfit_enable(new_crtc_state); 1592 1593 /* 1594 * On ILK+ LUT must be loaded before the pipe is running but with 1595 * clocks enabled 1596 */ 1597 intel_color_load_luts(new_crtc_state); 1598 intel_color_commit_noarm(new_crtc_state); 1599 intel_color_commit_arm(new_crtc_state); 1600 /* update DSPCNTR to configure gamma/csc for pipe bottom color */ 1601 if (DISPLAY_VER(dev_priv) < 9) 1602 intel_disable_primary_plane(new_crtc_state); 1603 1604 hsw_set_linetime_wm(new_crtc_state); 1605 1606 if (DISPLAY_VER(dev_priv) >= 11) 1607 icl_set_pipe_chicken(new_crtc_state); 1608 1609 intel_initial_watermarks(state, crtc); 1610 1611 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) 1612 intel_crtc_vblank_on(new_crtc_state); 1613 1614 intel_encoders_enable(state, crtc); 1615 1616 if (psl_clkgate_wa) { 1617 intel_crtc_wait_for_next_vblank(crtc); 1618 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false); 1619 } 1620 1621 /* If we change the relative order between pipe/planes enabling, we need 1622 * to change the workaround. */ 1623 hsw_workaround_pipe = new_crtc_state->hsw_workaround_pipe; 1624 if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) { 1625 struct intel_crtc *wa_crtc; 1626 1627 wa_crtc = intel_crtc_for_pipe(dev_priv, hsw_workaround_pipe); 1628 1629 intel_crtc_wait_for_next_vblank(wa_crtc); 1630 intel_crtc_wait_for_next_vblank(wa_crtc); 1631 } 1632} 1633 1634void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state) 1635{ 1636 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 1637 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1638 enum pipe pipe = crtc->pipe; 1639 1640 /* To avoid upsetting the power well on haswell only disable the pfit if 1641 * it's in use. The hw state code will make sure we get this right. */ 1642 if (!old_crtc_state->pch_pfit.enabled) 1643 return; 1644 1645 intel_de_write_fw(dev_priv, PF_CTL(pipe), 0); 1646 intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), 0); 1647 intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), 0); 1648} 1649 1650static void ilk_crtc_disable(struct intel_atomic_state *state, 1651 struct intel_crtc *crtc) 1652{ 1653 const struct intel_crtc_state *old_crtc_state = 1654 intel_atomic_get_old_crtc_state(state, crtc); 1655 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1656 enum pipe pipe = crtc->pipe; 1657 1658 /* 1659 * Sometimes spurious CPU pipe underruns happen when the 1660 * pipe is already disabled, but FDI RX/TX is still enabled. 1661 * Happens at least with VGA+HDMI cloning. Suppress them. 1662 */ 1663 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 1664 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); 1665 1666 intel_encoders_disable(state, crtc); 1667 1668 intel_crtc_vblank_off(old_crtc_state); 1669 1670 intel_disable_transcoder(old_crtc_state); 1671 1672 ilk_pfit_disable(old_crtc_state); 1673 1674 if (old_crtc_state->has_pch_encoder) 1675 ilk_pch_disable(state, crtc); 1676 1677 intel_encoders_post_disable(state, crtc); 1678 1679 if (old_crtc_state->has_pch_encoder) 1680 ilk_pch_post_disable(state, crtc); 1681 1682 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 1683 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); 1684 1685 intel_disable_shared_dpll(old_crtc_state); 1686} 1687 1688static void hsw_crtc_disable(struct intel_atomic_state *state, 1689 struct intel_crtc *crtc) 1690{ 1691 const struct intel_crtc_state *old_crtc_state = 1692 intel_atomic_get_old_crtc_state(state, crtc); 1693 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 1694 1695 /* 1696 * FIXME collapse everything to one hook. 1697 * Need care with mst->ddi interactions. 1698 */ 1699 if (!intel_crtc_is_bigjoiner_slave(old_crtc_state)) { 1700 intel_encoders_disable(state, crtc); 1701 intel_encoders_post_disable(state, crtc); 1702 } 1703 1704 intel_disable_shared_dpll(old_crtc_state); 1705 1706 if (!intel_crtc_is_bigjoiner_slave(old_crtc_state)) { 1707 struct intel_crtc *slave_crtc; 1708 1709 intel_encoders_post_pll_disable(state, crtc); 1710 1711 intel_dmc_disable_pipe(i915, crtc->pipe); 1712 1713 for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc, 1714 intel_crtc_bigjoiner_slave_pipes(old_crtc_state)) 1715 intel_dmc_disable_pipe(i915, slave_crtc->pipe); 1716 } 1717} 1718 1719static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state) 1720{ 1721 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1722 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1723 1724 if (!crtc_state->gmch_pfit.control) 1725 return; 1726 1727 /* 1728 * The panel fitter should only be adjusted whilst the pipe is disabled, 1729 * according to register description and PRM. 1730 */ 1731 drm_WARN_ON(&dev_priv->drm, 1732 intel_de_read(dev_priv, PFIT_CONTROL) & PFIT_ENABLE); 1733 assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder); 1734 1735 intel_de_write(dev_priv, PFIT_PGM_RATIOS, 1736 crtc_state->gmch_pfit.pgm_ratios); 1737 intel_de_write(dev_priv, PFIT_CONTROL, crtc_state->gmch_pfit.control); 1738 1739 /* Border color in case we don't scale up to the full screen. Black by 1740 * default, change to something else for debugging. */ 1741 intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0); 1742} 1743 1744bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy) 1745{ 1746 if (phy == PHY_NONE) 1747 return false; 1748 else if (IS_ALDERLAKE_S(dev_priv)) 1749 return phy <= PHY_E; 1750 else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) 1751 return phy <= PHY_D; 1752 else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) 1753 return phy <= PHY_C; 1754 else if (IS_ALDERLAKE_P(dev_priv) || IS_DISPLAY_VER(dev_priv, 11, 12)) 1755 return phy <= PHY_B; 1756 else 1757 /* 1758 * DG2 outputs labelled as "combo PHY" in the bspec use 1759 * SNPS PHYs with completely different programming, 1760 * hence we always return false here. 1761 */ 1762 return false; 1763} 1764 1765bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy) 1766{ 1767 if (IS_DG2(dev_priv)) 1768 /* DG2's "TC1" output uses a SNPS PHY */ 1769 return false; 1770 else if (IS_ALDERLAKE_P(dev_priv) || IS_METEORLAKE(dev_priv)) 1771 return phy >= PHY_F && phy <= PHY_I; 1772 else if (IS_TIGERLAKE(dev_priv)) 1773 return phy >= PHY_D && phy <= PHY_I; 1774 else if (IS_ICELAKE(dev_priv)) 1775 return phy >= PHY_C && phy <= PHY_F; 1776 else 1777 return false; 1778} 1779 1780bool intel_phy_is_snps(struct drm_i915_private *dev_priv, enum phy phy) 1781{ 1782 if (phy == PHY_NONE) 1783 return false; 1784 else if (IS_DG2(dev_priv)) 1785 /* 1786 * All four "combo" ports and the TC1 port (PHY E) use 1787 * Synopsis PHYs. 1788 */ 1789 return phy <= PHY_E; 1790 1791 return false; 1792} 1793 1794enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port) 1795{ 1796 if (DISPLAY_VER(i915) >= 13 && port >= PORT_D_XELPD) 1797 return PHY_D + port - PORT_D_XELPD; 1798 else if (DISPLAY_VER(i915) >= 13 && port >= PORT_TC1) 1799 return PHY_F + port - PORT_TC1; 1800 else if (IS_ALDERLAKE_S(i915) && port >= PORT_TC1) 1801 return PHY_B + port - PORT_TC1; 1802 else if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1) 1803 return PHY_C + port - PORT_TC1; 1804 else if ((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) && 1805 port == PORT_D) 1806 return PHY_A; 1807 1808 return PHY_A + port - PORT_A; 1809} 1810 1811enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port) 1812{ 1813 if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port))) 1814 return TC_PORT_NONE; 1815 1816 if (DISPLAY_VER(dev_priv) >= 12) 1817 return TC_PORT_1 + port - PORT_TC1; 1818 else 1819 return TC_PORT_1 + port - PORT_C; 1820} 1821 1822enum intel_display_power_domain 1823intel_aux_power_domain(struct intel_digital_port *dig_port) 1824{ 1825 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1826 1827 if (intel_tc_port_in_tbt_alt_mode(dig_port)) 1828 return intel_display_power_tbt_aux_domain(i915, dig_port->aux_ch); 1829 1830 return intel_display_power_legacy_aux_domain(i915, dig_port->aux_ch); 1831} 1832 1833static void get_crtc_power_domains(struct intel_crtc_state *crtc_state, 1834 struct intel_power_domain_mask *mask) 1835{ 1836 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1837 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1838 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1839 struct drm_encoder *encoder; 1840 enum pipe pipe = crtc->pipe; 1841 1842 bitmap_zero(mask->bits, POWER_DOMAIN_NUM); 1843 1844 if (!crtc_state->hw.active) 1845 return; 1846 1847 set_bit(POWER_DOMAIN_PIPE(pipe), mask->bits); 1848 set_bit(POWER_DOMAIN_TRANSCODER(cpu_transcoder), mask->bits); 1849 if (crtc_state->pch_pfit.enabled || 1850 crtc_state->pch_pfit.force_thru) 1851 set_bit(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe), mask->bits); 1852 1853 drm_for_each_encoder_mask(encoder, &dev_priv->drm, 1854 crtc_state->uapi.encoder_mask) { 1855 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 1856 1857 set_bit(intel_encoder->power_domain, mask->bits); 1858 } 1859 1860 if (HAS_DDI(dev_priv) && crtc_state->has_audio) 1861 set_bit(POWER_DOMAIN_AUDIO_MMIO, mask->bits); 1862 1863 if (crtc_state->shared_dpll) 1864 set_bit(POWER_DOMAIN_DISPLAY_CORE, mask->bits); 1865 1866 if (crtc_state->dsc.compression_enable) 1867 set_bit(intel_dsc_power_domain(crtc, cpu_transcoder), mask->bits); 1868} 1869 1870void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state, 1871 struct intel_power_domain_mask *old_domains) 1872{ 1873 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1874 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1875 enum intel_display_power_domain domain; 1876 struct intel_power_domain_mask domains, new_domains; 1877 1878 get_crtc_power_domains(crtc_state, &domains); 1879 1880 bitmap_andnot(new_domains.bits, 1881 domains.bits, 1882 crtc->enabled_power_domains.mask.bits, 1883 POWER_DOMAIN_NUM); 1884 bitmap_andnot(old_domains->bits, 1885 crtc->enabled_power_domains.mask.bits, 1886 domains.bits, 1887 POWER_DOMAIN_NUM); 1888 1889 for_each_power_domain(domain, &new_domains) 1890 intel_display_power_get_in_set(dev_priv, 1891 &crtc->enabled_power_domains, 1892 domain); 1893} 1894 1895void intel_modeset_put_crtc_power_domains(struct intel_crtc *crtc, 1896 struct intel_power_domain_mask *domains) 1897{ 1898 intel_display_power_put_mask_in_set(to_i915(crtc->base.dev), 1899 &crtc->enabled_power_domains, 1900 domains); 1901} 1902 1903static void i9xx_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) 1904{ 1905 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1906 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1907 1908 if (intel_crtc_has_dp_encoder(crtc_state)) { 1909 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1910 &crtc_state->dp_m_n); 1911 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, 1912 &crtc_state->dp_m2_n2); 1913 } 1914 1915 intel_set_transcoder_timings(crtc_state); 1916 1917 i9xx_set_pipeconf(crtc_state); 1918} 1919 1920static void valleyview_crtc_enable(struct intel_atomic_state *state, 1921 struct intel_crtc *crtc) 1922{ 1923 const struct intel_crtc_state *new_crtc_state = 1924 intel_atomic_get_new_crtc_state(state, crtc); 1925 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1926 enum pipe pipe = crtc->pipe; 1927 1928 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 1929 return; 1930 1931 i9xx_configure_cpu_transcoder(new_crtc_state); 1932 1933 intel_set_pipe_src_size(new_crtc_state); 1934 1935 intel_de_write(dev_priv, VLV_PIPE_MSA_MISC(pipe), 0); 1936 1937 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { 1938 intel_de_write(dev_priv, CHV_BLEND(pipe), CHV_BLEND_LEGACY); 1939 intel_de_write(dev_priv, CHV_CANVAS(pipe), 0); 1940 } 1941 1942 crtc->active = true; 1943 1944 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 1945 1946 intel_encoders_pre_pll_enable(state, crtc); 1947 1948 if (IS_CHERRYVIEW(dev_priv)) 1949 chv_enable_pll(new_crtc_state); 1950 else 1951 vlv_enable_pll(new_crtc_state); 1952 1953 intel_encoders_pre_enable(state, crtc); 1954 1955 i9xx_pfit_enable(new_crtc_state); 1956 1957 intel_color_load_luts(new_crtc_state); 1958 intel_color_commit_noarm(new_crtc_state); 1959 intel_color_commit_arm(new_crtc_state); 1960 /* update DSPCNTR to configure gamma for pipe bottom color */ 1961 intel_disable_primary_plane(new_crtc_state); 1962 1963 intel_initial_watermarks(state, crtc); 1964 intel_enable_transcoder(new_crtc_state); 1965 1966 intel_crtc_vblank_on(new_crtc_state); 1967 1968 intel_encoders_enable(state, crtc); 1969} 1970 1971static void i9xx_crtc_enable(struct intel_atomic_state *state, 1972 struct intel_crtc *crtc) 1973{ 1974 const struct intel_crtc_state *new_crtc_state = 1975 intel_atomic_get_new_crtc_state(state, crtc); 1976 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1977 enum pipe pipe = crtc->pipe; 1978 1979 if (drm_WARN_ON(&dev_priv->drm, crtc->active)) 1980 return; 1981 1982 i9xx_configure_cpu_transcoder(new_crtc_state); 1983 1984 intel_set_pipe_src_size(new_crtc_state); 1985 1986 crtc->active = true; 1987 1988 if (DISPLAY_VER(dev_priv) != 2) 1989 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 1990 1991 intel_encoders_pre_enable(state, crtc); 1992 1993 i9xx_enable_pll(new_crtc_state); 1994 1995 i9xx_pfit_enable(new_crtc_state); 1996 1997 intel_color_load_luts(new_crtc_state); 1998 intel_color_commit_noarm(new_crtc_state); 1999 intel_color_commit_arm(new_crtc_state); 2000 /* update DSPCNTR to configure gamma for pipe bottom color */ 2001 intel_disable_primary_plane(new_crtc_state); 2002 2003 if (!intel_initial_watermarks(state, crtc)) 2004 intel_update_watermarks(dev_priv); 2005 intel_enable_transcoder(new_crtc_state); 2006 2007 intel_crtc_vblank_on(new_crtc_state); 2008 2009 intel_encoders_enable(state, crtc); 2010 2011 /* prevents spurious underruns */ 2012 if (DISPLAY_VER(dev_priv) == 2) 2013 intel_crtc_wait_for_next_vblank(crtc); 2014} 2015 2016static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state) 2017{ 2018 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 2019 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2020 2021 if (!old_crtc_state->gmch_pfit.control) 2022 return; 2023 2024 assert_transcoder_disabled(dev_priv, old_crtc_state->cpu_transcoder); 2025 2026 drm_dbg_kms(&dev_priv->drm, "disabling pfit, current: 0x%08x\n", 2027 intel_de_read(dev_priv, PFIT_CONTROL)); 2028 intel_de_write(dev_priv, PFIT_CONTROL, 0); 2029} 2030 2031static void i9xx_crtc_disable(struct intel_atomic_state *state, 2032 struct intel_crtc *crtc) 2033{ 2034 struct intel_crtc_state *old_crtc_state = 2035 intel_atomic_get_old_crtc_state(state, crtc); 2036 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2037 enum pipe pipe = crtc->pipe; 2038 2039 /* 2040 * On gen2 planes are double buffered but the pipe isn't, so we must 2041 * wait for planes to fully turn off before disabling the pipe. 2042 */ 2043 if (DISPLAY_VER(dev_priv) == 2) 2044 intel_crtc_wait_for_next_vblank(crtc); 2045 2046 intel_encoders_disable(state, crtc); 2047 2048 intel_crtc_vblank_off(old_crtc_state); 2049 2050 intel_disable_transcoder(old_crtc_state); 2051 2052 i9xx_pfit_disable(old_crtc_state); 2053 2054 intel_encoders_post_disable(state, crtc); 2055 2056 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) { 2057 if (IS_CHERRYVIEW(dev_priv)) 2058 chv_disable_pll(dev_priv, pipe); 2059 else if (IS_VALLEYVIEW(dev_priv)) 2060 vlv_disable_pll(dev_priv, pipe); 2061 else 2062 i9xx_disable_pll(old_crtc_state); 2063 } 2064 2065 intel_encoders_post_pll_disable(state, crtc); 2066 2067 if (DISPLAY_VER(dev_priv) != 2) 2068 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 2069 2070 if (!dev_priv->display.funcs.wm->initial_watermarks) 2071 intel_update_watermarks(dev_priv); 2072 2073 /* clock the pipe down to 640x480@60 to potentially save power */ 2074 if (IS_I830(dev_priv)) 2075 i830_enable_pipe(dev_priv, pipe); 2076} 2077 2078void intel_encoder_destroy(struct drm_encoder *encoder) 2079{ 2080 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 2081 2082 drm_encoder_cleanup(encoder); 2083 kfree(intel_encoder); 2084} 2085 2086static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) 2087{ 2088 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2089 2090 /* GDG double wide on either pipe, otherwise pipe A only */ 2091 return DISPLAY_VER(dev_priv) < 4 && 2092 (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); 2093} 2094 2095static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state) 2096{ 2097 u32 pixel_rate = crtc_state->hw.pipe_mode.crtc_clock; 2098 struct drm_rect src; 2099 2100 /* 2101 * We only use IF-ID interlacing. If we ever use 2102 * PF-ID we'll need to adjust the pixel_rate here. 2103 */ 2104 2105 if (!crtc_state->pch_pfit.enabled) 2106 return pixel_rate; 2107 2108 drm_rect_init(&src, 0, 0, 2109 drm_rect_width(&crtc_state->pipe_src) << 16, 2110 drm_rect_height(&crtc_state->pipe_src) << 16); 2111 2112 return intel_adjusted_rate(&src, &crtc_state->pch_pfit.dst, 2113 pixel_rate); 2114} 2115 2116static void intel_mode_from_crtc_timings(struct drm_display_mode *mode, 2117 const struct drm_display_mode *timings) 2118{ 2119 mode->hdisplay = timings->crtc_hdisplay; 2120 mode->htotal = timings->crtc_htotal; 2121 mode->hsync_start = timings->crtc_hsync_start; 2122 mode->hsync_end = timings->crtc_hsync_end; 2123 2124 mode->vdisplay = timings->crtc_vdisplay; 2125 mode->vtotal = timings->crtc_vtotal; 2126 mode->vsync_start = timings->crtc_vsync_start; 2127 mode->vsync_end = timings->crtc_vsync_end; 2128 2129 mode->flags = timings->flags; 2130 mode->type = DRM_MODE_TYPE_DRIVER; 2131 2132 mode->clock = timings->crtc_clock; 2133 2134 drm_mode_set_name(mode); 2135} 2136 2137static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state) 2138{ 2139 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 2140 2141 if (HAS_GMCH(dev_priv)) 2142 /* FIXME calculate proper pipe pixel rate for GMCH pfit */ 2143 crtc_state->pixel_rate = 2144 crtc_state->hw.pipe_mode.crtc_clock; 2145 else 2146 crtc_state->pixel_rate = 2147 ilk_pipe_pixel_rate(crtc_state); 2148} 2149 2150static void intel_bigjoiner_adjust_timings(const struct intel_crtc_state *crtc_state, 2151 struct drm_display_mode *mode) 2152{ 2153 int num_pipes = intel_bigjoiner_num_pipes(crtc_state); 2154 2155 if (num_pipes < 2) 2156 return; 2157 2158 mode->crtc_clock /= num_pipes; 2159 mode->crtc_hdisplay /= num_pipes; 2160 mode->crtc_hblank_start /= num_pipes; 2161 mode->crtc_hblank_end /= num_pipes; 2162 mode->crtc_hsync_start /= num_pipes; 2163 mode->crtc_hsync_end /= num_pipes; 2164 mode->crtc_htotal /= num_pipes; 2165} 2166 2167static void intel_splitter_adjust_timings(const struct intel_crtc_state *crtc_state, 2168 struct drm_display_mode *mode) 2169{ 2170 int overlap = crtc_state->splitter.pixel_overlap; 2171 int n = crtc_state->splitter.link_count; 2172 2173 if (!crtc_state->splitter.enable) 2174 return; 2175 2176 /* 2177 * eDP MSO uses segment timings from EDID for transcoder 2178 * timings, but full mode for everything else. 2179 * 2180 * h_full = (h_segment - pixel_overlap) * link_count 2181 */ 2182 mode->crtc_hdisplay = (mode->crtc_hdisplay - overlap) * n; 2183 mode->crtc_hblank_start = (mode->crtc_hblank_start - overlap) * n; 2184 mode->crtc_hblank_end = (mode->crtc_hblank_end - overlap) * n; 2185 mode->crtc_hsync_start = (mode->crtc_hsync_start - overlap) * n; 2186 mode->crtc_hsync_end = (mode->crtc_hsync_end - overlap) * n; 2187 mode->crtc_htotal = (mode->crtc_htotal - overlap) * n; 2188 mode->crtc_clock *= n; 2189} 2190 2191static void intel_crtc_readout_derived_state(struct intel_crtc_state *crtc_state) 2192{ 2193 struct drm_display_mode *mode = &crtc_state->hw.mode; 2194 struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode; 2195 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2196 2197 /* 2198 * Start with the adjusted_mode crtc timings, which 2199 * have been filled with the transcoder timings. 2200 */ 2201 drm_mode_copy(pipe_mode, adjusted_mode); 2202 2203 /* Expand MSO per-segment transcoder timings to full */ 2204 intel_splitter_adjust_timings(crtc_state, pipe_mode); 2205 2206 /* 2207 * We want the full numbers in adjusted_mode normal timings, 2208 * adjusted_mode crtc timings are left with the raw transcoder 2209 * timings. 2210 */ 2211 intel_mode_from_crtc_timings(adjusted_mode, pipe_mode); 2212 2213 /* Populate the "user" mode with full numbers */ 2214 drm_mode_copy(mode, pipe_mode); 2215 intel_mode_from_crtc_timings(mode, mode); 2216 mode->hdisplay = drm_rect_width(&crtc_state->pipe_src) * 2217 (intel_bigjoiner_num_pipes(crtc_state) ?: 1); 2218 mode->vdisplay = drm_rect_height(&crtc_state->pipe_src); 2219 2220 /* Derive per-pipe timings in case bigjoiner is used */ 2221 intel_bigjoiner_adjust_timings(crtc_state, pipe_mode); 2222 intel_mode_from_crtc_timings(pipe_mode, pipe_mode); 2223 2224 intel_crtc_compute_pixel_rate(crtc_state); 2225} 2226 2227void intel_encoder_get_config(struct intel_encoder *encoder, 2228 struct intel_crtc_state *crtc_state) 2229{ 2230 encoder->get_config(encoder, crtc_state); 2231 2232 intel_crtc_readout_derived_state(crtc_state); 2233} 2234 2235static void intel_bigjoiner_compute_pipe_src(struct intel_crtc_state *crtc_state) 2236{ 2237 int num_pipes = intel_bigjoiner_num_pipes(crtc_state); 2238 int width, height; 2239 2240 if (num_pipes < 2) 2241 return; 2242 2243 width = drm_rect_width(&crtc_state->pipe_src); 2244 height = drm_rect_height(&crtc_state->pipe_src); 2245 2246 drm_rect_init(&crtc_state->pipe_src, 0, 0, 2247 width / num_pipes, height); 2248} 2249 2250static int intel_crtc_compute_pipe_src(struct intel_crtc_state *crtc_state) 2251{ 2252 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2253 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2254 2255 intel_bigjoiner_compute_pipe_src(crtc_state); 2256 2257 /* 2258 * Pipe horizontal size must be even in: 2259 * - DVO ganged mode 2260 * - LVDS dual channel mode 2261 * - Double wide pipe 2262 */ 2263 if (drm_rect_width(&crtc_state->pipe_src) & 1) { 2264 if (crtc_state->double_wide) { 2265 drm_dbg_kms(&i915->drm, 2266 "[CRTC:%d:%s] Odd pipe source width not supported with double wide pipe\n", 2267 crtc->base.base.id, crtc->base.name); 2268 return -EINVAL; 2269 } 2270 2271 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && 2272 intel_is_dual_link_lvds(i915)) { 2273 drm_dbg_kms(&i915->drm, 2274 "[CRTC:%d:%s] Odd pipe source width not supported with dual link LVDS\n", 2275 crtc->base.base.id, crtc->base.name); 2276 return -EINVAL; 2277 } 2278 } 2279 2280 return 0; 2281} 2282 2283static int intel_crtc_compute_pipe_mode(struct intel_crtc_state *crtc_state) 2284{ 2285 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2286 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2287 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2288 struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode; 2289 int clock_limit = i915->max_dotclk_freq; 2290 2291 /* 2292 * Start with the adjusted_mode crtc timings, which 2293 * have been filled with the transcoder timings. 2294 */ 2295 drm_mode_copy(pipe_mode, adjusted_mode); 2296 2297 /* Expand MSO per-segment transcoder timings to full */ 2298 intel_splitter_adjust_timings(crtc_state, pipe_mode); 2299 2300 /* Derive per-pipe timings in case bigjoiner is used */ 2301 intel_bigjoiner_adjust_timings(crtc_state, pipe_mode); 2302 intel_mode_from_crtc_timings(pipe_mode, pipe_mode); 2303 2304 if (DISPLAY_VER(i915) < 4) { 2305 clock_limit = i915->display.cdclk.max_cdclk_freq * 9 / 10; 2306 2307 /* 2308 * Enable double wide mode when the dot clock 2309 * is > 90% of the (display) core speed. 2310 */ 2311 if (intel_crtc_supports_double_wide(crtc) && 2312 pipe_mode->crtc_clock > clock_limit) { 2313 clock_limit = i915->max_dotclk_freq; 2314 crtc_state->double_wide = true; 2315 } 2316 } 2317 2318 if (pipe_mode->crtc_clock > clock_limit) { 2319 drm_dbg_kms(&i915->drm, 2320 "[CRTC:%d:%s] requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n", 2321 crtc->base.base.id, crtc->base.name, 2322 pipe_mode->crtc_clock, clock_limit, 2323 str_yes_no(crtc_state->double_wide)); 2324 return -EINVAL; 2325 } 2326 2327 return 0; 2328} 2329 2330static int intel_crtc_compute_config(struct intel_atomic_state *state, 2331 struct intel_crtc *crtc) 2332{ 2333 struct intel_crtc_state *crtc_state = 2334 intel_atomic_get_new_crtc_state(state, crtc); 2335 int ret; 2336 2337 ret = intel_dpll_crtc_compute_clock(state, crtc); 2338 if (ret) 2339 return ret; 2340 2341 ret = intel_crtc_compute_pipe_src(crtc_state); 2342 if (ret) 2343 return ret; 2344 2345 ret = intel_crtc_compute_pipe_mode(crtc_state); 2346 if (ret) 2347 return ret; 2348 2349 intel_crtc_compute_pixel_rate(crtc_state); 2350 2351 if (crtc_state->has_pch_encoder) 2352 return ilk_fdi_compute_config(crtc, crtc_state); 2353 2354 return 0; 2355} 2356 2357static void 2358intel_reduce_m_n_ratio(u32 *num, u32 *den) 2359{ 2360 while (*num > DATA_LINK_M_N_MASK || 2361 *den > DATA_LINK_M_N_MASK) { 2362 *num >>= 1; 2363 *den >>= 1; 2364 } 2365} 2366 2367static void compute_m_n(u32 *ret_m, u32 *ret_n, 2368 u32 m, u32 n, u32 constant_n) 2369{ 2370 if (constant_n) 2371 *ret_n = constant_n; 2372 else 2373 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); 2374 2375 *ret_m = div_u64(mul_u32_u32(m, *ret_n), n); 2376 intel_reduce_m_n_ratio(ret_m, ret_n); 2377} 2378 2379void 2380intel_link_compute_m_n(u16 bits_per_pixel, int nlanes, 2381 int pixel_clock, int link_clock, 2382 struct intel_link_m_n *m_n, 2383 bool fec_enable) 2384{ 2385 u32 data_clock = bits_per_pixel * pixel_clock; 2386 2387 if (fec_enable) 2388 data_clock = intel_dp_mode_to_fec_clock(data_clock); 2389 2390 /* 2391 * Windows/BIOS uses fixed M/N values always. Follow suit. 2392 * 2393 * Also several DP dongles in particular seem to be fussy 2394 * about too large link M/N values. Presumably the 20bit 2395 * value used by Windows/BIOS is acceptable to everyone. 2396 */ 2397 m_n->tu = 64; 2398 compute_m_n(&m_n->data_m, &m_n->data_n, 2399 data_clock, link_clock * nlanes * 8, 2400 0x8000000); 2401 2402 compute_m_n(&m_n->link_m, &m_n->link_n, 2403 pixel_clock, link_clock, 2404 0x80000); 2405} 2406 2407void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv) 2408{ 2409 /* 2410 * There may be no VBT; and if the BIOS enabled SSC we can 2411 * just keep using it to avoid unnecessary flicker. Whereas if the 2412 * BIOS isn't using it, don't assume it will work even if the VBT 2413 * indicates as much. 2414 */ 2415 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) { 2416 bool bios_lvds_use_ssc = intel_de_read(dev_priv, 2417 PCH_DREF_CONTROL) & 2418 DREF_SSC1_ENABLE; 2419 2420 if (dev_priv->display.vbt.lvds_use_ssc != bios_lvds_use_ssc) { 2421 drm_dbg_kms(&dev_priv->drm, 2422 "SSC %s by BIOS, overriding VBT which says %s\n", 2423 str_enabled_disabled(bios_lvds_use_ssc), 2424 str_enabled_disabled(dev_priv->display.vbt.lvds_use_ssc)); 2425 dev_priv->display.vbt.lvds_use_ssc = bios_lvds_use_ssc; 2426 } 2427 } 2428} 2429 2430void intel_zero_m_n(struct intel_link_m_n *m_n) 2431{ 2432 /* corresponds to 0 register value */ 2433 memset(m_n, 0, sizeof(*m_n)); 2434 m_n->tu = 1; 2435} 2436 2437void intel_set_m_n(struct drm_i915_private *i915, 2438 const struct intel_link_m_n *m_n, 2439 i915_reg_t data_m_reg, i915_reg_t data_n_reg, 2440 i915_reg_t link_m_reg, i915_reg_t link_n_reg) 2441{ 2442 intel_de_write(i915, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m); 2443 intel_de_write(i915, data_n_reg, m_n->data_n); 2444 intel_de_write(i915, link_m_reg, m_n->link_m); 2445 /* 2446 * On BDW+ writing LINK_N arms the double buffered update 2447 * of all the M/N registers, so it must be written last. 2448 */ 2449 intel_de_write(i915, link_n_reg, m_n->link_n); 2450} 2451 2452bool intel_cpu_transcoder_has_m2_n2(struct drm_i915_private *dev_priv, 2453 enum transcoder transcoder) 2454{ 2455 if (IS_HASWELL(dev_priv)) 2456 return transcoder == TRANSCODER_EDP; 2457 2458 return IS_DISPLAY_VER(dev_priv, 5, 7) || IS_CHERRYVIEW(dev_priv); 2459} 2460 2461void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc, 2462 enum transcoder transcoder, 2463 const struct intel_link_m_n *m_n) 2464{ 2465 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2466 enum pipe pipe = crtc->pipe; 2467 2468 if (DISPLAY_VER(dev_priv) >= 5) 2469 intel_set_m_n(dev_priv, m_n, 2470 PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder), 2471 PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder)); 2472 else 2473 intel_set_m_n(dev_priv, m_n, 2474 PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe), 2475 PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe)); 2476} 2477 2478void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc, 2479 enum transcoder transcoder, 2480 const struct intel_link_m_n *m_n) 2481{ 2482 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2483 2484 if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder)) 2485 return; 2486 2487 intel_set_m_n(dev_priv, m_n, 2488 PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder), 2489 PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder)); 2490} 2491 2492static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state) 2493{ 2494 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2495 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2496 enum pipe pipe = crtc->pipe; 2497 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2498 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2499 u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end; 2500 int vsyncshift = 0; 2501 2502 /* We need to be careful not to changed the adjusted mode, for otherwise 2503 * the hw state checker will get angry at the mismatch. */ 2504 crtc_vdisplay = adjusted_mode->crtc_vdisplay; 2505 crtc_vtotal = adjusted_mode->crtc_vtotal; 2506 crtc_vblank_start = adjusted_mode->crtc_vblank_start; 2507 crtc_vblank_end = adjusted_mode->crtc_vblank_end; 2508 2509 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { 2510 /* the chip adds 2 halflines automatically */ 2511 crtc_vtotal -= 1; 2512 crtc_vblank_end -= 1; 2513 2514 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 2515 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; 2516 else 2517 vsyncshift = adjusted_mode->crtc_hsync_start - 2518 adjusted_mode->crtc_htotal / 2; 2519 if (vsyncshift < 0) 2520 vsyncshift += adjusted_mode->crtc_htotal; 2521 } 2522 2523 /* 2524 * VBLANK_START no longer works on ADL+, instead we must use 2525 * TRANS_SET_CONTEXT_LATENCY to configure the pipe vblank start. 2526 */ 2527 if (DISPLAY_VER(dev_priv) >= 13) { 2528 intel_de_write(dev_priv, TRANS_SET_CONTEXT_LATENCY(cpu_transcoder), 2529 crtc_vblank_start - crtc_vdisplay); 2530 2531 /* 2532 * VBLANK_START not used by hw, just clear it 2533 * to make it stand out in register dumps. 2534 */ 2535 crtc_vblank_start = 1; 2536 } 2537 2538 if (DISPLAY_VER(dev_priv) > 3) 2539 intel_de_write(dev_priv, TRANS_VSYNCSHIFT(cpu_transcoder), 2540 vsyncshift); 2541 2542 intel_de_write(dev_priv, TRANS_HTOTAL(cpu_transcoder), 2543 HACTIVE(adjusted_mode->crtc_hdisplay - 1) | 2544 HTOTAL(adjusted_mode->crtc_htotal - 1)); 2545 intel_de_write(dev_priv, TRANS_HBLANK(cpu_transcoder), 2546 HBLANK_START(adjusted_mode->crtc_hblank_start - 1) | 2547 HBLANK_END(adjusted_mode->crtc_hblank_end - 1)); 2548 intel_de_write(dev_priv, TRANS_HSYNC(cpu_transcoder), 2549 HSYNC_START(adjusted_mode->crtc_hsync_start - 1) | 2550 HSYNC_END(adjusted_mode->crtc_hsync_end - 1)); 2551 2552 intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder), 2553 VACTIVE(crtc_vdisplay - 1) | 2554 VTOTAL(crtc_vtotal - 1)); 2555 intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder), 2556 VBLANK_START(crtc_vblank_start - 1) | 2557 VBLANK_END(crtc_vblank_end - 1)); 2558 intel_de_write(dev_priv, TRANS_VSYNC(cpu_transcoder), 2559 VSYNC_START(adjusted_mode->crtc_vsync_start - 1) | 2560 VSYNC_END(adjusted_mode->crtc_vsync_end - 1)); 2561 2562 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be 2563 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is 2564 * documented on the DDI_FUNC_CTL register description, EDP Input Select 2565 * bits. */ 2566 if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP && 2567 (pipe == PIPE_B || pipe == PIPE_C)) 2568 intel_de_write(dev_priv, TRANS_VTOTAL(pipe), 2569 VACTIVE(crtc_vdisplay - 1) | 2570 VTOTAL(crtc_vtotal - 1)); 2571} 2572 2573static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state) 2574{ 2575 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2576 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2577 int width = drm_rect_width(&crtc_state->pipe_src); 2578 int height = drm_rect_height(&crtc_state->pipe_src); 2579 enum pipe pipe = crtc->pipe; 2580 2581 /* pipesrc controls the size that is scaled from, which should 2582 * always be the user's requested size. 2583 */ 2584 intel_de_write(dev_priv, PIPESRC(pipe), 2585 PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1)); 2586} 2587 2588static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state) 2589{ 2590 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 2591 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2592 2593 if (DISPLAY_VER(dev_priv) == 2) 2594 return false; 2595 2596 if (DISPLAY_VER(dev_priv) >= 9 || 2597 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 2598 return intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)) & TRANSCONF_INTERLACE_MASK_HSW; 2599 else 2600 return intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)) & TRANSCONF_INTERLACE_MASK; 2601} 2602 2603static void intel_get_transcoder_timings(struct intel_crtc *crtc, 2604 struct intel_crtc_state *pipe_config) 2605{ 2606 struct drm_device *dev = crtc->base.dev; 2607 struct drm_i915_private *dev_priv = to_i915(dev); 2608 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 2609 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 2610 u32 tmp; 2611 2612 tmp = intel_de_read(dev_priv, TRANS_HTOTAL(cpu_transcoder)); 2613 adjusted_mode->crtc_hdisplay = REG_FIELD_GET(HACTIVE_MASK, tmp) + 1; 2614 adjusted_mode->crtc_htotal = REG_FIELD_GET(HTOTAL_MASK, tmp) + 1; 2615 2616 if (!transcoder_is_dsi(cpu_transcoder)) { 2617 tmp = intel_de_read(dev_priv, TRANS_HBLANK(cpu_transcoder)); 2618 adjusted_mode->crtc_hblank_start = REG_FIELD_GET(HBLANK_START_MASK, tmp) + 1; 2619 adjusted_mode->crtc_hblank_end = REG_FIELD_GET(HBLANK_END_MASK, tmp) + 1; 2620 } 2621 2622 tmp = intel_de_read(dev_priv, TRANS_HSYNC(cpu_transcoder)); 2623 adjusted_mode->crtc_hsync_start = REG_FIELD_GET(HSYNC_START_MASK, tmp) + 1; 2624 adjusted_mode->crtc_hsync_end = REG_FIELD_GET(HSYNC_END_MASK, tmp) + 1; 2625 2626 tmp = intel_de_read(dev_priv, TRANS_VTOTAL(cpu_transcoder)); 2627 adjusted_mode->crtc_vdisplay = REG_FIELD_GET(VACTIVE_MASK, tmp) + 1; 2628 adjusted_mode->crtc_vtotal = REG_FIELD_GET(VTOTAL_MASK, tmp) + 1; 2629 2630 /* FIXME TGL+ DSI transcoders have this! */ 2631 if (!transcoder_is_dsi(cpu_transcoder)) { 2632 tmp = intel_de_read(dev_priv, TRANS_VBLANK(cpu_transcoder)); 2633 adjusted_mode->crtc_vblank_start = REG_FIELD_GET(VBLANK_START_MASK, tmp) + 1; 2634 adjusted_mode->crtc_vblank_end = REG_FIELD_GET(VBLANK_END_MASK, tmp) + 1; 2635 } 2636 tmp = intel_de_read(dev_priv, TRANS_VSYNC(cpu_transcoder)); 2637 adjusted_mode->crtc_vsync_start = REG_FIELD_GET(VSYNC_START_MASK, tmp) + 1; 2638 adjusted_mode->crtc_vsync_end = REG_FIELD_GET(VSYNC_END_MASK, tmp) + 1; 2639 2640 if (intel_pipe_is_interlaced(pipe_config)) { 2641 adjusted_mode->flags |= DRM_MODE_FLAG_INTERLACE; 2642 adjusted_mode->crtc_vtotal += 1; 2643 adjusted_mode->crtc_vblank_end += 1; 2644 } 2645 2646 if (DISPLAY_VER(dev_priv) >= 13 && !transcoder_is_dsi(cpu_transcoder)) 2647 adjusted_mode->crtc_vblank_start = 2648 adjusted_mode->crtc_vdisplay + 2649 intel_de_read(dev_priv, TRANS_SET_CONTEXT_LATENCY(cpu_transcoder)); 2650} 2651 2652static void intel_bigjoiner_adjust_pipe_src(struct intel_crtc_state *crtc_state) 2653{ 2654 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2655 int num_pipes = intel_bigjoiner_num_pipes(crtc_state); 2656 enum pipe master_pipe, pipe = crtc->pipe; 2657 int width; 2658 2659 if (num_pipes < 2) 2660 return; 2661 2662 master_pipe = bigjoiner_master_pipe(crtc_state); 2663 width = drm_rect_width(&crtc_state->pipe_src); 2664 2665 drm_rect_translate_to(&crtc_state->pipe_src, 2666 (pipe - master_pipe) * width, 0); 2667} 2668 2669static void intel_get_pipe_src_size(struct intel_crtc *crtc, 2670 struct intel_crtc_state *pipe_config) 2671{ 2672 struct drm_device *dev = crtc->base.dev; 2673 struct drm_i915_private *dev_priv = to_i915(dev); 2674 u32 tmp; 2675 2676 tmp = intel_de_read(dev_priv, PIPESRC(crtc->pipe)); 2677 2678 drm_rect_init(&pipe_config->pipe_src, 0, 0, 2679 REG_FIELD_GET(PIPESRC_WIDTH_MASK, tmp) + 1, 2680 REG_FIELD_GET(PIPESRC_HEIGHT_MASK, tmp) + 1); 2681 2682 intel_bigjoiner_adjust_pipe_src(pipe_config); 2683} 2684 2685void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state) 2686{ 2687 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2688 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2689 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2690 u32 val = 0; 2691 2692 /* 2693 * - We keep both pipes enabled on 830 2694 * - During modeset the pipe is still disabled and must remain so 2695 * - During fastset the pipe is already enabled and must remain so 2696 */ 2697 if (IS_I830(dev_priv) || !intel_crtc_needs_modeset(crtc_state)) 2698 val |= TRANSCONF_ENABLE; 2699 2700 if (crtc_state->double_wide) 2701 val |= TRANSCONF_DOUBLE_WIDE; 2702 2703 /* only g4x and later have fancy bpc/dither controls */ 2704 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || 2705 IS_CHERRYVIEW(dev_priv)) { 2706 /* Bspec claims that we can't use dithering for 30bpp pipes. */ 2707 if (crtc_state->dither && crtc_state->pipe_bpp != 30) 2708 val |= TRANSCONF_DITHER_EN | 2709 TRANSCONF_DITHER_TYPE_SP; 2710 2711 switch (crtc_state->pipe_bpp) { 2712 default: 2713 /* Case prevented by intel_choose_pipe_bpp_dither. */ 2714 MISSING_CASE(crtc_state->pipe_bpp); 2715 fallthrough; 2716 case 18: 2717 val |= TRANSCONF_BPC_6; 2718 break; 2719 case 24: 2720 val |= TRANSCONF_BPC_8; 2721 break; 2722 case 30: 2723 val |= TRANSCONF_BPC_10; 2724 break; 2725 } 2726 } 2727 2728 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { 2729 if (DISPLAY_VER(dev_priv) < 4 || 2730 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 2731 val |= TRANSCONF_INTERLACE_W_FIELD_INDICATION; 2732 else 2733 val |= TRANSCONF_INTERLACE_W_SYNC_SHIFT; 2734 } else { 2735 val |= TRANSCONF_INTERLACE_PROGRESSIVE; 2736 } 2737 2738 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 2739 crtc_state->limited_color_range) 2740 val |= TRANSCONF_COLOR_RANGE_SELECT; 2741 2742 val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode); 2743 2744 if (crtc_state->wgc_enable) 2745 val |= TRANSCONF_WGC_ENABLE; 2746 2747 val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1); 2748 2749 intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val); 2750 intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder)); 2751} 2752 2753static bool i9xx_has_pfit(struct drm_i915_private *dev_priv) 2754{ 2755 if (IS_I830(dev_priv)) 2756 return false; 2757 2758 return DISPLAY_VER(dev_priv) >= 4 || 2759 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv); 2760} 2761 2762static void i9xx_get_pfit_config(struct intel_crtc_state *crtc_state) 2763{ 2764 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2765 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2766 enum pipe pipe; 2767 u32 tmp; 2768 2769 if (!i9xx_has_pfit(dev_priv)) 2770 return; 2771 2772 tmp = intel_de_read(dev_priv, PFIT_CONTROL); 2773 if (!(tmp & PFIT_ENABLE)) 2774 return; 2775 2776 /* Check whether the pfit is attached to our pipe. */ 2777 if (DISPLAY_VER(dev_priv) >= 4) 2778 pipe = REG_FIELD_GET(PFIT_PIPE_MASK, tmp); 2779 else 2780 pipe = PIPE_B; 2781 2782 if (pipe != crtc->pipe) 2783 return; 2784 2785 crtc_state->gmch_pfit.control = tmp; 2786 crtc_state->gmch_pfit.pgm_ratios = 2787 intel_de_read(dev_priv, PFIT_PGM_RATIOS); 2788} 2789 2790static void vlv_crtc_clock_get(struct intel_crtc *crtc, 2791 struct intel_crtc_state *pipe_config) 2792{ 2793 struct drm_device *dev = crtc->base.dev; 2794 struct drm_i915_private *dev_priv = to_i915(dev); 2795 enum pipe pipe = crtc->pipe; 2796 struct dpll clock; 2797 u32 mdiv; 2798 int refclk = 100000; 2799 2800 /* In case of DSI, DPLL will not be used */ 2801 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) 2802 return; 2803 2804 vlv_dpio_get(dev_priv); 2805 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); 2806 vlv_dpio_put(dev_priv); 2807 2808 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; 2809 clock.m2 = mdiv & DPIO_M2DIV_MASK; 2810 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; 2811 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; 2812 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; 2813 2814 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); 2815} 2816 2817static void chv_crtc_clock_get(struct intel_crtc *crtc, 2818 struct intel_crtc_state *pipe_config) 2819{ 2820 struct drm_device *dev = crtc->base.dev; 2821 struct drm_i915_private *dev_priv = to_i915(dev); 2822 enum pipe pipe = crtc->pipe; 2823 enum dpio_channel port = vlv_pipe_to_channel(pipe); 2824 struct dpll clock; 2825 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; 2826 int refclk = 100000; 2827 2828 /* In case of DSI, DPLL will not be used */ 2829 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) 2830 return; 2831 2832 vlv_dpio_get(dev_priv); 2833 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); 2834 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); 2835 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); 2836 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); 2837 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); 2838 vlv_dpio_put(dev_priv); 2839 2840 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; 2841 clock.m2 = (pll_dw0 & 0xff) << 22; 2842 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) 2843 clock.m2 |= pll_dw2 & 0x3fffff; 2844 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; 2845 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; 2846 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; 2847 2848 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); 2849} 2850 2851static enum intel_output_format 2852bdw_get_pipe_misc_output_format(struct intel_crtc *crtc) 2853{ 2854 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2855 u32 tmp; 2856 2857 tmp = intel_de_read(dev_priv, PIPE_MISC(crtc->pipe)); 2858 2859 if (tmp & PIPE_MISC_YUV420_ENABLE) { 2860 /* We support 4:2:0 in full blend mode only */ 2861 drm_WARN_ON(&dev_priv->drm, 2862 (tmp & PIPE_MISC_YUV420_MODE_FULL_BLEND) == 0); 2863 2864 return INTEL_OUTPUT_FORMAT_YCBCR420; 2865 } else if (tmp & PIPE_MISC_OUTPUT_COLORSPACE_YUV) { 2866 return INTEL_OUTPUT_FORMAT_YCBCR444; 2867 } else { 2868 return INTEL_OUTPUT_FORMAT_RGB; 2869 } 2870} 2871 2872static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state) 2873{ 2874 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2875 struct intel_plane *plane = to_intel_plane(crtc->base.primary); 2876 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2877 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; 2878 u32 tmp; 2879 2880 tmp = intel_de_read(dev_priv, DSPCNTR(i9xx_plane)); 2881 2882 if (tmp & DISP_PIPE_GAMMA_ENABLE) 2883 crtc_state->gamma_enable = true; 2884 2885 if (!HAS_GMCH(dev_priv) && 2886 tmp & DISP_PIPE_CSC_ENABLE) 2887 crtc_state->csc_enable = true; 2888} 2889 2890static bool i9xx_get_pipe_config(struct intel_crtc *crtc, 2891 struct intel_crtc_state *pipe_config) 2892{ 2893 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2894 enum intel_display_power_domain power_domain; 2895 intel_wakeref_t wakeref; 2896 u32 tmp; 2897 bool ret; 2898 2899 power_domain = POWER_DOMAIN_PIPE(crtc->pipe); 2900 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 2901 if (!wakeref) 2902 return false; 2903 2904 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 2905 pipe_config->sink_format = pipe_config->output_format; 2906 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; 2907 pipe_config->shared_dpll = NULL; 2908 2909 ret = false; 2910 2911 tmp = intel_de_read(dev_priv, TRANSCONF(pipe_config->cpu_transcoder)); 2912 if (!(tmp & TRANSCONF_ENABLE)) 2913 goto out; 2914 2915 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || 2916 IS_CHERRYVIEW(dev_priv)) { 2917 switch (tmp & TRANSCONF_BPC_MASK) { 2918 case TRANSCONF_BPC_6: 2919 pipe_config->pipe_bpp = 18; 2920 break; 2921 case TRANSCONF_BPC_8: 2922 pipe_config->pipe_bpp = 24; 2923 break; 2924 case TRANSCONF_BPC_10: 2925 pipe_config->pipe_bpp = 30; 2926 break; 2927 default: 2928 MISSING_CASE(tmp); 2929 break; 2930 } 2931 } 2932 2933 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 2934 (tmp & TRANSCONF_COLOR_RANGE_SELECT)) 2935 pipe_config->limited_color_range = true; 2936 2937 pipe_config->gamma_mode = REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_I9XX, tmp); 2938 2939 pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1; 2940 2941 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 2942 (tmp & TRANSCONF_WGC_ENABLE)) 2943 pipe_config->wgc_enable = true; 2944 2945 if (IS_CHERRYVIEW(dev_priv)) 2946 pipe_config->cgm_mode = intel_de_read(dev_priv, 2947 CGM_PIPE_MODE(crtc->pipe)); 2948 2949 i9xx_get_pipe_color_config(pipe_config); 2950 intel_color_get_config(pipe_config); 2951 2952 if (DISPLAY_VER(dev_priv) < 4) 2953 pipe_config->double_wide = tmp & TRANSCONF_DOUBLE_WIDE; 2954 2955 intel_get_transcoder_timings(crtc, pipe_config); 2956 intel_get_pipe_src_size(crtc, pipe_config); 2957 2958 i9xx_get_pfit_config(pipe_config); 2959 2960 if (DISPLAY_VER(dev_priv) >= 4) { 2961 /* No way to read it out on pipes B and C */ 2962 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A) 2963 tmp = dev_priv->display.state.chv_dpll_md[crtc->pipe]; 2964 else 2965 tmp = intel_de_read(dev_priv, DPLL_MD(crtc->pipe)); 2966 pipe_config->pixel_multiplier = 2967 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) 2968 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; 2969 pipe_config->dpll_hw_state.dpll_md = tmp; 2970 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || 2971 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) { 2972 tmp = intel_de_read(dev_priv, DPLL(crtc->pipe)); 2973 pipe_config->pixel_multiplier = 2974 ((tmp & SDVO_MULTIPLIER_MASK) 2975 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; 2976 } else { 2977 /* Note that on i915G/GM the pixel multiplier is in the sdvo 2978 * port and will be fixed up in the encoder->get_config 2979 * function. */ 2980 pipe_config->pixel_multiplier = 1; 2981 } 2982 pipe_config->dpll_hw_state.dpll = intel_de_read(dev_priv, 2983 DPLL(crtc->pipe)); 2984 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { 2985 pipe_config->dpll_hw_state.fp0 = intel_de_read(dev_priv, 2986 FP0(crtc->pipe)); 2987 pipe_config->dpll_hw_state.fp1 = intel_de_read(dev_priv, 2988 FP1(crtc->pipe)); 2989 } else { 2990 /* Mask out read-only status bits. */ 2991 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | 2992 DPLL_PORTC_READY_MASK | 2993 DPLL_PORTB_READY_MASK); 2994 } 2995 2996 if (IS_CHERRYVIEW(dev_priv)) 2997 chv_crtc_clock_get(crtc, pipe_config); 2998 else if (IS_VALLEYVIEW(dev_priv)) 2999 vlv_crtc_clock_get(crtc, pipe_config); 3000 else 3001 i9xx_crtc_clock_get(crtc, pipe_config); 3002 3003 /* 3004 * Normally the dotclock is filled in by the encoder .get_config() 3005 * but in case the pipe is enabled w/o any ports we need a sane 3006 * default. 3007 */ 3008 pipe_config->hw.adjusted_mode.crtc_clock = 3009 pipe_config->port_clock / pipe_config->pixel_multiplier; 3010 3011 ret = true; 3012 3013out: 3014 intel_display_power_put(dev_priv, power_domain, wakeref); 3015 3016 return ret; 3017} 3018 3019void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state) 3020{ 3021 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3022 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3023 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3024 u32 val = 0; 3025 3026 /* 3027 * - During modeset the pipe is still disabled and must remain so 3028 * - During fastset the pipe is already enabled and must remain so 3029 */ 3030 if (!intel_crtc_needs_modeset(crtc_state)) 3031 val |= TRANSCONF_ENABLE; 3032 3033 switch (crtc_state->pipe_bpp) { 3034 default: 3035 /* Case prevented by intel_choose_pipe_bpp_dither. */ 3036 MISSING_CASE(crtc_state->pipe_bpp); 3037 fallthrough; 3038 case 18: 3039 val |= TRANSCONF_BPC_6; 3040 break; 3041 case 24: 3042 val |= TRANSCONF_BPC_8; 3043 break; 3044 case 30: 3045 val |= TRANSCONF_BPC_10; 3046 break; 3047 case 36: 3048 val |= TRANSCONF_BPC_12; 3049 break; 3050 } 3051 3052 if (crtc_state->dither) 3053 val |= TRANSCONF_DITHER_EN | TRANSCONF_DITHER_TYPE_SP; 3054 3055 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 3056 val |= TRANSCONF_INTERLACE_IF_ID_ILK; 3057 else 3058 val |= TRANSCONF_INTERLACE_PF_PD_ILK; 3059 3060 /* 3061 * This would end up with an odd purple hue over 3062 * the entire display. Make sure we don't do it. 3063 */ 3064 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range && 3065 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 3066 3067 if (crtc_state->limited_color_range && 3068 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 3069 val |= TRANSCONF_COLOR_RANGE_SELECT; 3070 3071 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 3072 val |= TRANSCONF_OUTPUT_COLORSPACE_YUV709; 3073 3074 val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode); 3075 3076 val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1); 3077 val |= TRANSCONF_MSA_TIMING_DELAY(crtc_state->msa_timing_delay); 3078 3079 intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val); 3080 intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder)); 3081} 3082 3083static void hsw_set_transconf(const struct intel_crtc_state *crtc_state) 3084{ 3085 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3086 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3087 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3088 u32 val = 0; 3089 3090 /* 3091 * - During modeset the pipe is still disabled and must remain so 3092 * - During fastset the pipe is already enabled and must remain so 3093 */ 3094 if (!intel_crtc_needs_modeset(crtc_state)) 3095 val |= TRANSCONF_ENABLE; 3096 3097 if (IS_HASWELL(dev_priv) && crtc_state->dither) 3098 val |= TRANSCONF_DITHER_EN | TRANSCONF_DITHER_TYPE_SP; 3099 3100 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 3101 val |= TRANSCONF_INTERLACE_IF_ID_ILK; 3102 else 3103 val |= TRANSCONF_INTERLACE_PF_PD_ILK; 3104 3105 if (IS_HASWELL(dev_priv) && 3106 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 3107 val |= TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW; 3108 3109 intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val); 3110 intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder)); 3111} 3112 3113static void bdw_set_pipe_misc(const struct intel_crtc_state *crtc_state) 3114{ 3115 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3116 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3117 u32 val = 0; 3118 3119 switch (crtc_state->pipe_bpp) { 3120 case 18: 3121 val |= PIPE_MISC_BPC_6; 3122 break; 3123 case 24: 3124 val |= PIPE_MISC_BPC_8; 3125 break; 3126 case 30: 3127 val |= PIPE_MISC_BPC_10; 3128 break; 3129 case 36: 3130 /* Port output 12BPC defined for ADLP+ */ 3131 if (DISPLAY_VER(dev_priv) > 12) 3132 val |= PIPE_MISC_BPC_12_ADLP; 3133 break; 3134 default: 3135 MISSING_CASE(crtc_state->pipe_bpp); 3136 break; 3137 } 3138 3139 if (crtc_state->dither) 3140 val |= PIPE_MISC_DITHER_ENABLE | PIPE_MISC_DITHER_TYPE_SP; 3141 3142 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 || 3143 crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 3144 val |= PIPE_MISC_OUTPUT_COLORSPACE_YUV; 3145 3146 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 3147 val |= PIPE_MISC_YUV420_ENABLE | 3148 PIPE_MISC_YUV420_MODE_FULL_BLEND; 3149 3150 if (DISPLAY_VER(dev_priv) >= 11 && is_hdr_mode(crtc_state)) 3151 val |= PIPE_MISC_HDR_MODE_PRECISION; 3152 3153 if (DISPLAY_VER(dev_priv) >= 12) 3154 val |= PIPE_MISC_PIXEL_ROUNDING_TRUNC; 3155 3156 /* allow PSR with sprite enabled */ 3157 if (IS_BROADWELL(dev_priv)) 3158 val |= PIPE_MISC_PSR_MASK_SPRITE_ENABLE; 3159 3160 intel_de_write(dev_priv, PIPE_MISC(crtc->pipe), val); 3161} 3162 3163int bdw_get_pipe_misc_bpp(struct intel_crtc *crtc) 3164{ 3165 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3166 u32 tmp; 3167 3168 tmp = intel_de_read(dev_priv, PIPE_MISC(crtc->pipe)); 3169 3170 switch (tmp & PIPE_MISC_BPC_MASK) { 3171 case PIPE_MISC_BPC_6: 3172 return 18; 3173 case PIPE_MISC_BPC_8: 3174 return 24; 3175 case PIPE_MISC_BPC_10: 3176 return 30; 3177 /* 3178 * PORT OUTPUT 12 BPC defined for ADLP+. 3179 * 3180 * TODO: 3181 * For previous platforms with DSI interface, bits 5:7 3182 * are used for storing pipe_bpp irrespective of dithering. 3183 * Since the value of 12 BPC is not defined for these bits 3184 * on older platforms, need to find a workaround for 12 BPC 3185 * MIPI DSI HW readout. 3186 */ 3187 case PIPE_MISC_BPC_12_ADLP: 3188 if (DISPLAY_VER(dev_priv) > 12) 3189 return 36; 3190 fallthrough; 3191 default: 3192 MISSING_CASE(tmp); 3193 return 0; 3194 } 3195} 3196 3197int ilk_get_lanes_required(int target_clock, int link_bw, int bpp) 3198{ 3199 /* 3200 * Account for spread spectrum to avoid 3201 * oversubscribing the link. Max center spread 3202 * is 2.5%; use 5% for safety's sake. 3203 */ 3204 u32 bps = target_clock * bpp * 21 / 20; 3205 return DIV_ROUND_UP(bps, link_bw * 8); 3206} 3207 3208void intel_get_m_n(struct drm_i915_private *i915, 3209 struct intel_link_m_n *m_n, 3210 i915_reg_t data_m_reg, i915_reg_t data_n_reg, 3211 i915_reg_t link_m_reg, i915_reg_t link_n_reg) 3212{ 3213 m_n->link_m = intel_de_read(i915, link_m_reg) & DATA_LINK_M_N_MASK; 3214 m_n->link_n = intel_de_read(i915, link_n_reg) & DATA_LINK_M_N_MASK; 3215 m_n->data_m = intel_de_read(i915, data_m_reg) & DATA_LINK_M_N_MASK; 3216 m_n->data_n = intel_de_read(i915, data_n_reg) & DATA_LINK_M_N_MASK; 3217 m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(i915, data_m_reg)) + 1; 3218} 3219 3220void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc, 3221 enum transcoder transcoder, 3222 struct intel_link_m_n *m_n) 3223{ 3224 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3225 enum pipe pipe = crtc->pipe; 3226 3227 if (DISPLAY_VER(dev_priv) >= 5) 3228 intel_get_m_n(dev_priv, m_n, 3229 PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder), 3230 PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder)); 3231 else 3232 intel_get_m_n(dev_priv, m_n, 3233 PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe), 3234 PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe)); 3235} 3236 3237void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc, 3238 enum transcoder transcoder, 3239 struct intel_link_m_n *m_n) 3240{ 3241 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3242 3243 if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder)) 3244 return; 3245 3246 intel_get_m_n(dev_priv, m_n, 3247 PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder), 3248 PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder)); 3249} 3250 3251static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state) 3252{ 3253 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3254 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3255 u32 ctl, pos, size; 3256 enum pipe pipe; 3257 3258 ctl = intel_de_read(dev_priv, PF_CTL(crtc->pipe)); 3259 if ((ctl & PF_ENABLE) == 0) 3260 return; 3261 3262 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) 3263 pipe = REG_FIELD_GET(PF_PIPE_SEL_MASK_IVB, ctl); 3264 else 3265 pipe = crtc->pipe; 3266 3267 crtc_state->pch_pfit.enabled = true; 3268 3269 pos = intel_de_read(dev_priv, PF_WIN_POS(crtc->pipe)); 3270 size = intel_de_read(dev_priv, PF_WIN_SZ(crtc->pipe)); 3271 3272 drm_rect_init(&crtc_state->pch_pfit.dst, 3273 REG_FIELD_GET(PF_WIN_XPOS_MASK, pos), 3274 REG_FIELD_GET(PF_WIN_YPOS_MASK, pos), 3275 REG_FIELD_GET(PF_WIN_XSIZE_MASK, size), 3276 REG_FIELD_GET(PF_WIN_YSIZE_MASK, size)); 3277 3278 /* 3279 * We currently do not free assignements of panel fitters on 3280 * ivb/hsw (since we don't use the higher upscaling modes which 3281 * differentiates them) so just WARN about this case for now. 3282 */ 3283 drm_WARN_ON(&dev_priv->drm, pipe != crtc->pipe); 3284} 3285 3286static bool ilk_get_pipe_config(struct intel_crtc *crtc, 3287 struct intel_crtc_state *pipe_config) 3288{ 3289 struct drm_device *dev = crtc->base.dev; 3290 struct drm_i915_private *dev_priv = to_i915(dev); 3291 enum intel_display_power_domain power_domain; 3292 intel_wakeref_t wakeref; 3293 u32 tmp; 3294 bool ret; 3295 3296 power_domain = POWER_DOMAIN_PIPE(crtc->pipe); 3297 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 3298 if (!wakeref) 3299 return false; 3300 3301 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; 3302 pipe_config->shared_dpll = NULL; 3303 3304 ret = false; 3305 tmp = intel_de_read(dev_priv, TRANSCONF(pipe_config->cpu_transcoder)); 3306 if (!(tmp & TRANSCONF_ENABLE)) 3307 goto out; 3308 3309 switch (tmp & TRANSCONF_BPC_MASK) { 3310 case TRANSCONF_BPC_6: 3311 pipe_config->pipe_bpp = 18; 3312 break; 3313 case TRANSCONF_BPC_8: 3314 pipe_config->pipe_bpp = 24; 3315 break; 3316 case TRANSCONF_BPC_10: 3317 pipe_config->pipe_bpp = 30; 3318 break; 3319 case TRANSCONF_BPC_12: 3320 pipe_config->pipe_bpp = 36; 3321 break; 3322 default: 3323 break; 3324 } 3325 3326 if (tmp & TRANSCONF_COLOR_RANGE_SELECT) 3327 pipe_config->limited_color_range = true; 3328 3329 switch (tmp & TRANSCONF_OUTPUT_COLORSPACE_MASK) { 3330 case TRANSCONF_OUTPUT_COLORSPACE_YUV601: 3331 case TRANSCONF_OUTPUT_COLORSPACE_YUV709: 3332 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444; 3333 break; 3334 default: 3335 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 3336 break; 3337 } 3338 3339 pipe_config->sink_format = pipe_config->output_format; 3340 3341 pipe_config->gamma_mode = REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_ILK, tmp); 3342 3343 pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1; 3344 3345 pipe_config->msa_timing_delay = REG_FIELD_GET(TRANSCONF_MSA_TIMING_DELAY_MASK, tmp); 3346 3347 pipe_config->csc_mode = intel_de_read(dev_priv, 3348 PIPE_CSC_MODE(crtc->pipe)); 3349 3350 i9xx_get_pipe_color_config(pipe_config); 3351 intel_color_get_config(pipe_config); 3352 3353 pipe_config->pixel_multiplier = 1; 3354 3355 ilk_pch_get_config(pipe_config); 3356 3357 intel_get_transcoder_timings(crtc, pipe_config); 3358 intel_get_pipe_src_size(crtc, pipe_config); 3359 3360 ilk_get_pfit_config(pipe_config); 3361 3362 ret = true; 3363 3364out: 3365 intel_display_power_put(dev_priv, power_domain, wakeref); 3366 3367 return ret; 3368} 3369 3370static u8 bigjoiner_pipes(struct drm_i915_private *i915) 3371{ 3372 u8 pipes; 3373 3374 if (DISPLAY_VER(i915) >= 12) 3375 pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D); 3376 else if (DISPLAY_VER(i915) >= 11) 3377 pipes = BIT(PIPE_B) | BIT(PIPE_C); 3378 else 3379 pipes = 0; 3380 3381 return pipes & DISPLAY_RUNTIME_INFO(i915)->pipe_mask; 3382} 3383 3384static bool transcoder_ddi_func_is_enabled(struct drm_i915_private *dev_priv, 3385 enum transcoder cpu_transcoder) 3386{ 3387 enum intel_display_power_domain power_domain; 3388 intel_wakeref_t wakeref; 3389 u32 tmp = 0; 3390 3391 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3392 3393 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) 3394 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3395 3396 return tmp & TRANS_DDI_FUNC_ENABLE; 3397} 3398 3399static void enabled_bigjoiner_pipes(struct drm_i915_private *dev_priv, 3400 u8 *master_pipes, u8 *slave_pipes) 3401{ 3402 struct intel_crtc *crtc; 3403 3404 *master_pipes = 0; 3405 *slave_pipes = 0; 3406 3407 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, 3408 bigjoiner_pipes(dev_priv)) { 3409 enum intel_display_power_domain power_domain; 3410 enum pipe pipe = crtc->pipe; 3411 intel_wakeref_t wakeref; 3412 3413 power_domain = intel_dsc_power_domain(crtc, (enum transcoder) pipe); 3414 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) { 3415 u32 tmp = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe)); 3416 3417 if (!(tmp & BIG_JOINER_ENABLE)) 3418 continue; 3419 3420 if (tmp & MASTER_BIG_JOINER_ENABLE) 3421 *master_pipes |= BIT(pipe); 3422 else 3423 *slave_pipes |= BIT(pipe); 3424 } 3425 3426 if (DISPLAY_VER(dev_priv) < 13) 3427 continue; 3428 3429 power_domain = POWER_DOMAIN_PIPE(pipe); 3430 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) { 3431 u32 tmp = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe)); 3432 3433 if (tmp & UNCOMPRESSED_JOINER_MASTER) 3434 *master_pipes |= BIT(pipe); 3435 if (tmp & UNCOMPRESSED_JOINER_SLAVE) 3436 *slave_pipes |= BIT(pipe); 3437 } 3438 } 3439 3440 /* Bigjoiner pipes should always be consecutive master and slave */ 3441 drm_WARN(&dev_priv->drm, *slave_pipes != *master_pipes << 1, 3442 "Bigjoiner misconfigured (master pipes 0x%x, slave pipes 0x%x)\n", 3443 *master_pipes, *slave_pipes); 3444} 3445 3446static enum pipe get_bigjoiner_master_pipe(enum pipe pipe, u8 master_pipes, u8 slave_pipes) 3447{ 3448 if ((slave_pipes & BIT(pipe)) == 0) 3449 return pipe; 3450 3451 /* ignore everything above our pipe */ 3452 master_pipes &= ~GENMASK(7, pipe); 3453 3454 /* highest remaining bit should be our master pipe */ 3455 return fls(master_pipes) - 1; 3456} 3457 3458static u8 get_bigjoiner_slave_pipes(enum pipe pipe, u8 master_pipes, u8 slave_pipes) 3459{ 3460 enum pipe master_pipe, next_master_pipe; 3461 3462 master_pipe = get_bigjoiner_master_pipe(pipe, master_pipes, slave_pipes); 3463 3464 if ((master_pipes & BIT(master_pipe)) == 0) 3465 return 0; 3466 3467 /* ignore our master pipe and everything below it */ 3468 master_pipes &= ~GENMASK(master_pipe, 0); 3469 /* make sure a high bit is set for the ffs() */ 3470 master_pipes |= BIT(7); 3471 /* lowest remaining bit should be the next master pipe */ 3472 next_master_pipe = ffs(master_pipes) - 1; 3473 3474 return slave_pipes & GENMASK(next_master_pipe - 1, master_pipe); 3475} 3476 3477static u8 hsw_panel_transcoders(struct drm_i915_private *i915) 3478{ 3479 u8 panel_transcoder_mask = BIT(TRANSCODER_EDP); 3480 3481 if (DISPLAY_VER(i915) >= 11) 3482 panel_transcoder_mask |= BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1); 3483 3484 return panel_transcoder_mask; 3485} 3486 3487static u8 hsw_enabled_transcoders(struct intel_crtc *crtc) 3488{ 3489 struct drm_device *dev = crtc->base.dev; 3490 struct drm_i915_private *dev_priv = to_i915(dev); 3491 u8 panel_transcoder_mask = hsw_panel_transcoders(dev_priv); 3492 enum transcoder cpu_transcoder; 3493 u8 master_pipes, slave_pipes; 3494 u8 enabled_transcoders = 0; 3495 3496 /* 3497 * XXX: Do intel_display_power_get_if_enabled before reading this (for 3498 * consistency and less surprising code; it's in always on power). 3499 */ 3500 for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, 3501 panel_transcoder_mask) { 3502 enum intel_display_power_domain power_domain; 3503 intel_wakeref_t wakeref; 3504 enum pipe trans_pipe; 3505 u32 tmp = 0; 3506 3507 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3508 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) 3509 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3510 3511 if (!(tmp & TRANS_DDI_FUNC_ENABLE)) 3512 continue; 3513 3514 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 3515 default: 3516 drm_WARN(dev, 1, 3517 "unknown pipe linked to transcoder %s\n", 3518 transcoder_name(cpu_transcoder)); 3519 fallthrough; 3520 case TRANS_DDI_EDP_INPUT_A_ONOFF: 3521 case TRANS_DDI_EDP_INPUT_A_ON: 3522 trans_pipe = PIPE_A; 3523 break; 3524 case TRANS_DDI_EDP_INPUT_B_ONOFF: 3525 trans_pipe = PIPE_B; 3526 break; 3527 case TRANS_DDI_EDP_INPUT_C_ONOFF: 3528 trans_pipe = PIPE_C; 3529 break; 3530 case TRANS_DDI_EDP_INPUT_D_ONOFF: 3531 trans_pipe = PIPE_D; 3532 break; 3533 } 3534 3535 if (trans_pipe == crtc->pipe) 3536 enabled_transcoders |= BIT(cpu_transcoder); 3537 } 3538 3539 /* single pipe or bigjoiner master */ 3540 cpu_transcoder = (enum transcoder) crtc->pipe; 3541 if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder)) 3542 enabled_transcoders |= BIT(cpu_transcoder); 3543 3544 /* bigjoiner slave -> consider the master pipe's transcoder as well */ 3545 enabled_bigjoiner_pipes(dev_priv, &master_pipes, &slave_pipes); 3546 if (slave_pipes & BIT(crtc->pipe)) { 3547 cpu_transcoder = (enum transcoder) 3548 get_bigjoiner_master_pipe(crtc->pipe, master_pipes, slave_pipes); 3549 if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder)) 3550 enabled_transcoders |= BIT(cpu_transcoder); 3551 } 3552 3553 return enabled_transcoders; 3554} 3555 3556static bool has_edp_transcoders(u8 enabled_transcoders) 3557{ 3558 return enabled_transcoders & BIT(TRANSCODER_EDP); 3559} 3560 3561static bool has_dsi_transcoders(u8 enabled_transcoders) 3562{ 3563 return enabled_transcoders & (BIT(TRANSCODER_DSI_0) | 3564 BIT(TRANSCODER_DSI_1)); 3565} 3566 3567static bool has_pipe_transcoders(u8 enabled_transcoders) 3568{ 3569 return enabled_transcoders & ~(BIT(TRANSCODER_EDP) | 3570 BIT(TRANSCODER_DSI_0) | 3571 BIT(TRANSCODER_DSI_1)); 3572} 3573 3574static void assert_enabled_transcoders(struct drm_i915_private *i915, 3575 u8 enabled_transcoders) 3576{ 3577 /* Only one type of transcoder please */ 3578 drm_WARN_ON(&i915->drm, 3579 has_edp_transcoders(enabled_transcoders) + 3580 has_dsi_transcoders(enabled_transcoders) + 3581 has_pipe_transcoders(enabled_transcoders) > 1); 3582 3583 /* Only DSI transcoders can be ganged */ 3584 drm_WARN_ON(&i915->drm, 3585 !has_dsi_transcoders(enabled_transcoders) && 3586 !is_power_of_2(enabled_transcoders)); 3587} 3588 3589static bool hsw_get_transcoder_state(struct intel_crtc *crtc, 3590 struct intel_crtc_state *pipe_config, 3591 struct intel_display_power_domain_set *power_domain_set) 3592{ 3593 struct drm_device *dev = crtc->base.dev; 3594 struct drm_i915_private *dev_priv = to_i915(dev); 3595 unsigned long enabled_transcoders; 3596 u32 tmp; 3597 3598 enabled_transcoders = hsw_enabled_transcoders(crtc); 3599 if (!enabled_transcoders) 3600 return false; 3601 3602 assert_enabled_transcoders(dev_priv, enabled_transcoders); 3603 3604 /* 3605 * With the exception of DSI we should only ever have 3606 * a single enabled transcoder. With DSI let's just 3607 * pick the first one. 3608 */ 3609 pipe_config->cpu_transcoder = ffs(enabled_transcoders) - 1; 3610 3611 if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set, 3612 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) 3613 return false; 3614 3615 if (hsw_panel_transcoders(dev_priv) & BIT(pipe_config->cpu_transcoder)) { 3616 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); 3617 3618 if ((tmp & TRANS_DDI_EDP_INPUT_MASK) == TRANS_DDI_EDP_INPUT_A_ONOFF) 3619 pipe_config->pch_pfit.force_thru = true; 3620 } 3621 3622 tmp = intel_de_read(dev_priv, TRANSCONF(pipe_config->cpu_transcoder)); 3623 3624 return tmp & TRANSCONF_ENABLE; 3625} 3626 3627static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, 3628 struct intel_crtc_state *pipe_config, 3629 struct intel_display_power_domain_set *power_domain_set) 3630{ 3631 struct drm_device *dev = crtc->base.dev; 3632 struct drm_i915_private *dev_priv = to_i915(dev); 3633 enum transcoder cpu_transcoder; 3634 enum port port; 3635 u32 tmp; 3636 3637 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) { 3638 if (port == PORT_A) 3639 cpu_transcoder = TRANSCODER_DSI_A; 3640 else 3641 cpu_transcoder = TRANSCODER_DSI_C; 3642 3643 if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set, 3644 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) 3645 continue; 3646 3647 /* 3648 * The PLL needs to be enabled with a valid divider 3649 * configuration, otherwise accessing DSI registers will hang 3650 * the machine. See BSpec North Display Engine 3651 * registers/MIPI[BXT]. We can break out here early, since we 3652 * need the same DSI PLL to be enabled for both DSI ports. 3653 */ 3654 if (!bxt_dsi_pll_is_enabled(dev_priv)) 3655 break; 3656 3657 /* XXX: this works for video mode only */ 3658 tmp = intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port)); 3659 if (!(tmp & DPI_ENABLE)) 3660 continue; 3661 3662 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); 3663 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe)) 3664 continue; 3665 3666 pipe_config->cpu_transcoder = cpu_transcoder; 3667 break; 3668 } 3669 3670 return transcoder_is_dsi(pipe_config->cpu_transcoder); 3671} 3672 3673static void intel_bigjoiner_get_config(struct intel_crtc_state *crtc_state) 3674{ 3675 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3676 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 3677 u8 master_pipes, slave_pipes; 3678 enum pipe pipe = crtc->pipe; 3679 3680 enabled_bigjoiner_pipes(i915, &master_pipes, &slave_pipes); 3681 3682 if (((master_pipes | slave_pipes) & BIT(pipe)) == 0) 3683 return; 3684 3685 crtc_state->bigjoiner_pipes = 3686 BIT(get_bigjoiner_master_pipe(pipe, master_pipes, slave_pipes)) | 3687 get_bigjoiner_slave_pipes(pipe, master_pipes, slave_pipes); 3688} 3689 3690static bool hsw_get_pipe_config(struct intel_crtc *crtc, 3691 struct intel_crtc_state *pipe_config) 3692{ 3693 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3694 bool active; 3695 u32 tmp; 3696 3697 if (!intel_display_power_get_in_set_if_enabled(dev_priv, &crtc->hw_readout_power_domains, 3698 POWER_DOMAIN_PIPE(crtc->pipe))) 3699 return false; 3700 3701 pipe_config->shared_dpll = NULL; 3702 3703 active = hsw_get_transcoder_state(crtc, pipe_config, &crtc->hw_readout_power_domains); 3704 3705 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && 3706 bxt_get_dsi_transcoder_state(crtc, pipe_config, &crtc->hw_readout_power_domains)) { 3707 drm_WARN_ON(&dev_priv->drm, active); 3708 active = true; 3709 } 3710 3711 if (!active) 3712 goto out; 3713 3714 intel_dsc_get_config(pipe_config); 3715 intel_bigjoiner_get_config(pipe_config); 3716 3717 if (!transcoder_is_dsi(pipe_config->cpu_transcoder) || 3718 DISPLAY_VER(dev_priv) >= 11) 3719 intel_get_transcoder_timings(crtc, pipe_config); 3720 3721 if (HAS_VRR(dev_priv) && !transcoder_is_dsi(pipe_config->cpu_transcoder)) 3722 intel_vrr_get_config(pipe_config); 3723 3724 intel_get_pipe_src_size(crtc, pipe_config); 3725 3726 if (IS_HASWELL(dev_priv)) { 3727 u32 tmp = intel_de_read(dev_priv, 3728 TRANSCONF(pipe_config->cpu_transcoder)); 3729 3730 if (tmp & TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW) 3731 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444; 3732 else 3733 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 3734 } else { 3735 pipe_config->output_format = 3736 bdw_get_pipe_misc_output_format(crtc); 3737 } 3738 3739 pipe_config->sink_format = pipe_config->output_format; 3740 3741 pipe_config->gamma_mode = intel_de_read(dev_priv, 3742 GAMMA_MODE(crtc->pipe)); 3743 3744 pipe_config->csc_mode = intel_de_read(dev_priv, 3745 PIPE_CSC_MODE(crtc->pipe)); 3746 3747 if (DISPLAY_VER(dev_priv) >= 9) { 3748 tmp = intel_de_read(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe)); 3749 3750 if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE) 3751 pipe_config->gamma_enable = true; 3752 3753 if (tmp & SKL_BOTTOM_COLOR_CSC_ENABLE) 3754 pipe_config->csc_enable = true; 3755 } else { 3756 i9xx_get_pipe_color_config(pipe_config); 3757 } 3758 3759 intel_color_get_config(pipe_config); 3760 3761 tmp = intel_de_read(dev_priv, WM_LINETIME(crtc->pipe)); 3762 pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp); 3763 if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 3764 pipe_config->ips_linetime = 3765 REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp); 3766 3767 if (intel_display_power_get_in_set_if_enabled(dev_priv, &crtc->hw_readout_power_domains, 3768 POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe))) { 3769 if (DISPLAY_VER(dev_priv) >= 9) 3770 skl_scaler_get_config(pipe_config); 3771 else 3772 ilk_get_pfit_config(pipe_config); 3773 } 3774 3775 hsw_ips_get_config(pipe_config); 3776 3777 if (pipe_config->cpu_transcoder != TRANSCODER_EDP && 3778 !transcoder_is_dsi(pipe_config->cpu_transcoder)) { 3779 pipe_config->pixel_multiplier = 3780 intel_de_read(dev_priv, 3781 TRANS_MULT(pipe_config->cpu_transcoder)) + 1; 3782 } else { 3783 pipe_config->pixel_multiplier = 1; 3784 } 3785 3786 if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) { 3787 tmp = intel_de_read(dev_priv, DISPLAY_VER(dev_priv) >= 14 ? 3788 MTL_CHICKEN_TRANS(pipe_config->cpu_transcoder) : 3789 CHICKEN_TRANS(pipe_config->cpu_transcoder)); 3790 3791 pipe_config->framestart_delay = REG_FIELD_GET(HSW_FRAME_START_DELAY_MASK, tmp) + 1; 3792 } else { 3793 /* no idea if this is correct */ 3794 pipe_config->framestart_delay = 1; 3795 } 3796 3797out: 3798 intel_display_power_put_all_in_set(dev_priv, &crtc->hw_readout_power_domains); 3799 3800 return active; 3801} 3802 3803bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state) 3804{ 3805 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3806 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 3807 3808 if (!i915->display.funcs.display->get_pipe_config(crtc, crtc_state)) 3809 return false; 3810 3811 crtc_state->hw.active = true; 3812 3813 intel_crtc_readout_derived_state(crtc_state); 3814 3815 return true; 3816} 3817 3818static int i9xx_pll_refclk(struct drm_device *dev, 3819 const struct intel_crtc_state *pipe_config) 3820{ 3821 struct drm_i915_private *dev_priv = to_i915(dev); 3822 u32 dpll = pipe_config->dpll_hw_state.dpll; 3823 3824 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) 3825 return dev_priv->display.vbt.lvds_ssc_freq; 3826 else if (HAS_PCH_SPLIT(dev_priv)) 3827 return 120000; 3828 else if (DISPLAY_VER(dev_priv) != 2) 3829 return 96000; 3830 else 3831 return 48000; 3832} 3833 3834/* Returns the clock of the currently programmed mode of the given pipe. */ 3835void i9xx_crtc_clock_get(struct intel_crtc *crtc, 3836 struct intel_crtc_state *pipe_config) 3837{ 3838 struct drm_device *dev = crtc->base.dev; 3839 struct drm_i915_private *dev_priv = to_i915(dev); 3840 u32 dpll = pipe_config->dpll_hw_state.dpll; 3841 u32 fp; 3842 struct dpll clock; 3843 int port_clock; 3844 int refclk = i9xx_pll_refclk(dev, pipe_config); 3845 3846 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) 3847 fp = pipe_config->dpll_hw_state.fp0; 3848 else 3849 fp = pipe_config->dpll_hw_state.fp1; 3850 3851 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; 3852 if (IS_PINEVIEW(dev_priv)) { 3853 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; 3854 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; 3855 } else { 3856 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; 3857 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; 3858 } 3859 3860 if (DISPLAY_VER(dev_priv) != 2) { 3861 if (IS_PINEVIEW(dev_priv)) 3862 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> 3863 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); 3864 else 3865 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> 3866 DPLL_FPA01_P1_POST_DIV_SHIFT); 3867 3868 switch (dpll & DPLL_MODE_MASK) { 3869 case DPLLB_MODE_DAC_SERIAL: 3870 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? 3871 5 : 10; 3872 break; 3873 case DPLLB_MODE_LVDS: 3874 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? 3875 7 : 14; 3876 break; 3877 default: 3878 drm_dbg_kms(&dev_priv->drm, 3879 "Unknown DPLL mode %08x in programmed " 3880 "mode\n", (int)(dpll & DPLL_MODE_MASK)); 3881 return; 3882 } 3883 3884 if (IS_PINEVIEW(dev_priv)) 3885 port_clock = pnv_calc_dpll_params(refclk, &clock); 3886 else 3887 port_clock = i9xx_calc_dpll_params(refclk, &clock); 3888 } else { 3889 enum pipe lvds_pipe; 3890 3891 if (IS_I85X(dev_priv) && 3892 intel_lvds_port_enabled(dev_priv, LVDS, &lvds_pipe) && 3893 lvds_pipe == crtc->pipe) { 3894 u32 lvds = intel_de_read(dev_priv, LVDS); 3895 3896 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> 3897 DPLL_FPA01_P1_POST_DIV_SHIFT); 3898 3899 if (lvds & LVDS_CLKB_POWER_UP) 3900 clock.p2 = 7; 3901 else 3902 clock.p2 = 14; 3903 } else { 3904 if (dpll & PLL_P1_DIVIDE_BY_TWO) 3905 clock.p1 = 2; 3906 else { 3907 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> 3908 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; 3909 } 3910 if (dpll & PLL_P2_DIVIDE_BY_4) 3911 clock.p2 = 4; 3912 else 3913 clock.p2 = 2; 3914 } 3915 3916 port_clock = i9xx_calc_dpll_params(refclk, &clock); 3917 } 3918 3919 /* 3920 * This value includes pixel_multiplier. We will use 3921 * port_clock to compute adjusted_mode.crtc_clock in the 3922 * encoder's get_config() function. 3923 */ 3924 pipe_config->port_clock = port_clock; 3925} 3926 3927int intel_dotclock_calculate(int link_freq, 3928 const struct intel_link_m_n *m_n) 3929{ 3930 /* 3931 * The calculation for the data clock is: 3932 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp 3933 * But we want to avoid losing precison if possible, so: 3934 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) 3935 * 3936 * and the link clock is simpler: 3937 * link_clock = (m * link_clock) / n 3938 */ 3939 3940 if (!m_n->link_n) 3941 return 0; 3942 3943 return DIV_ROUND_UP_ULL(mul_u32_u32(m_n->link_m, link_freq), 3944 m_n->link_n); 3945} 3946 3947int intel_crtc_dotclock(const struct intel_crtc_state *pipe_config) 3948{ 3949 int dotclock; 3950 3951 if (intel_crtc_has_dp_encoder(pipe_config)) 3952 dotclock = intel_dotclock_calculate(pipe_config->port_clock, 3953 &pipe_config->dp_m_n); 3954 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24) 3955 dotclock = DIV_ROUND_CLOSEST(pipe_config->port_clock * 24, 3956 pipe_config->pipe_bpp); 3957 else 3958 dotclock = pipe_config->port_clock; 3959 3960 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 && 3961 !intel_crtc_has_dp_encoder(pipe_config)) 3962 dotclock *= 2; 3963 3964 if (pipe_config->pixel_multiplier) 3965 dotclock /= pipe_config->pixel_multiplier; 3966 3967 return dotclock; 3968} 3969 3970/* Returns the currently programmed mode of the given encoder. */ 3971struct drm_display_mode * 3972intel_encoder_current_mode(struct intel_encoder *encoder) 3973{ 3974 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3975 struct intel_crtc_state *crtc_state; 3976 struct drm_display_mode *mode; 3977 struct intel_crtc *crtc; 3978 enum pipe pipe; 3979 3980 if (!encoder->get_hw_state(encoder, &pipe)) 3981 return NULL; 3982 3983 crtc = intel_crtc_for_pipe(dev_priv, pipe); 3984 3985 mode = kzalloc(sizeof(*mode), GFP_KERNEL); 3986 if (!mode) 3987 return NULL; 3988 3989 crtc_state = intel_crtc_state_alloc(crtc); 3990 if (!crtc_state) { 3991 kfree(mode); 3992 return NULL; 3993 } 3994 3995 if (!intel_crtc_get_pipe_config(crtc_state)) { 3996 kfree(crtc_state); 3997 kfree(mode); 3998 return NULL; 3999 } 4000 4001 intel_encoder_get_config(encoder, crtc_state); 4002 4003 intel_mode_from_crtc_timings(mode, &crtc_state->hw.adjusted_mode); 4004 4005 kfree(crtc_state); 4006 4007 return mode; 4008} 4009 4010static bool encoders_cloneable(const struct intel_encoder *a, 4011 const struct intel_encoder *b) 4012{ 4013 /* masks could be asymmetric, so check both ways */ 4014 return a == b || (a->cloneable & BIT(b->type) && 4015 b->cloneable & BIT(a->type)); 4016} 4017 4018static bool check_single_encoder_cloning(struct intel_atomic_state *state, 4019 struct intel_crtc *crtc, 4020 struct intel_encoder *encoder) 4021{ 4022 struct intel_encoder *source_encoder; 4023 struct drm_connector *connector; 4024 struct drm_connector_state *connector_state; 4025 int i; 4026 4027 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 4028 if (connector_state->crtc != &crtc->base) 4029 continue; 4030 4031 source_encoder = 4032 to_intel_encoder(connector_state->best_encoder); 4033 if (!encoders_cloneable(encoder, source_encoder)) 4034 return false; 4035 } 4036 4037 return true; 4038} 4039 4040static int icl_add_linked_planes(struct intel_atomic_state *state) 4041{ 4042 struct intel_plane *plane, *linked; 4043 struct intel_plane_state *plane_state, *linked_plane_state; 4044 int i; 4045 4046 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 4047 linked = plane_state->planar_linked_plane; 4048 4049 if (!linked) 4050 continue; 4051 4052 linked_plane_state = intel_atomic_get_plane_state(state, linked); 4053 if (IS_ERR(linked_plane_state)) 4054 return PTR_ERR(linked_plane_state); 4055 4056 drm_WARN_ON(state->base.dev, 4057 linked_plane_state->planar_linked_plane != plane); 4058 drm_WARN_ON(state->base.dev, 4059 linked_plane_state->planar_slave == plane_state->planar_slave); 4060 } 4061 4062 return 0; 4063} 4064 4065static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state) 4066{ 4067 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4068 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4069 struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state); 4070 struct intel_plane *plane, *linked; 4071 struct intel_plane_state *plane_state; 4072 int i; 4073 4074 if (DISPLAY_VER(dev_priv) < 11) 4075 return 0; 4076 4077 /* 4078 * Destroy all old plane links and make the slave plane invisible 4079 * in the crtc_state->active_planes mask. 4080 */ 4081 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 4082 if (plane->pipe != crtc->pipe || !plane_state->planar_linked_plane) 4083 continue; 4084 4085 plane_state->planar_linked_plane = NULL; 4086 if (plane_state->planar_slave && !plane_state->uapi.visible) { 4087 crtc_state->enabled_planes &= ~BIT(plane->id); 4088 crtc_state->active_planes &= ~BIT(plane->id); 4089 crtc_state->update_planes |= BIT(plane->id); 4090 crtc_state->data_rate[plane->id] = 0; 4091 crtc_state->rel_data_rate[plane->id] = 0; 4092 } 4093 4094 plane_state->planar_slave = false; 4095 } 4096 4097 if (!crtc_state->nv12_planes) 4098 return 0; 4099 4100 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 4101 struct intel_plane_state *linked_state = NULL; 4102 4103 if (plane->pipe != crtc->pipe || 4104 !(crtc_state->nv12_planes & BIT(plane->id))) 4105 continue; 4106 4107 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) { 4108 if (!icl_is_nv12_y_plane(dev_priv, linked->id)) 4109 continue; 4110 4111 if (crtc_state->active_planes & BIT(linked->id)) 4112 continue; 4113 4114 linked_state = intel_atomic_get_plane_state(state, linked); 4115 if (IS_ERR(linked_state)) 4116 return PTR_ERR(linked_state); 4117 4118 break; 4119 } 4120 4121 if (!linked_state) { 4122 drm_dbg_kms(&dev_priv->drm, 4123 "Need %d free Y planes for planar YUV\n", 4124 hweight8(crtc_state->nv12_planes)); 4125 4126 return -EINVAL; 4127 } 4128 4129 plane_state->planar_linked_plane = linked; 4130 4131 linked_state->planar_slave = true; 4132 linked_state->planar_linked_plane = plane; 4133 crtc_state->enabled_planes |= BIT(linked->id); 4134 crtc_state->active_planes |= BIT(linked->id); 4135 crtc_state->update_planes |= BIT(linked->id); 4136 crtc_state->data_rate[linked->id] = 4137 crtc_state->data_rate_y[plane->id]; 4138 crtc_state->rel_data_rate[linked->id] = 4139 crtc_state->rel_data_rate_y[plane->id]; 4140 drm_dbg_kms(&dev_priv->drm, "Using %s as Y plane for %s\n", 4141 linked->base.name, plane->base.name); 4142 4143 /* Copy parameters to slave plane */ 4144 linked_state->ctl = plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE; 4145 linked_state->color_ctl = plane_state->color_ctl; 4146 linked_state->view = plane_state->view; 4147 linked_state->decrypt = plane_state->decrypt; 4148 4149 intel_plane_copy_hw_state(linked_state, plane_state); 4150 linked_state->uapi.src = plane_state->uapi.src; 4151 linked_state->uapi.dst = plane_state->uapi.dst; 4152 4153 if (icl_is_hdr_plane(dev_priv, plane->id)) { 4154 if (linked->id == PLANE_SPRITE5) 4155 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_7_ICL; 4156 else if (linked->id == PLANE_SPRITE4) 4157 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_6_ICL; 4158 else if (linked->id == PLANE_SPRITE3) 4159 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_5_RKL; 4160 else if (linked->id == PLANE_SPRITE2) 4161 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_4_RKL; 4162 else 4163 MISSING_CASE(linked->id); 4164 } 4165 } 4166 4167 return 0; 4168} 4169 4170static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state) 4171{ 4172 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 4173 struct intel_atomic_state *state = 4174 to_intel_atomic_state(new_crtc_state->uapi.state); 4175 const struct intel_crtc_state *old_crtc_state = 4176 intel_atomic_get_old_crtc_state(state, crtc); 4177 4178 return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes; 4179} 4180 4181static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state) 4182{ 4183 const struct drm_display_mode *pipe_mode = 4184 &crtc_state->hw.pipe_mode; 4185 int linetime_wm; 4186 4187 if (!crtc_state->hw.enable) 4188 return 0; 4189 4190 linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8, 4191 pipe_mode->crtc_clock); 4192 4193 return min(linetime_wm, 0x1ff); 4194} 4195 4196static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state, 4197 const struct intel_cdclk_state *cdclk_state) 4198{ 4199 const struct drm_display_mode *pipe_mode = 4200 &crtc_state->hw.pipe_mode; 4201 int linetime_wm; 4202 4203 if (!crtc_state->hw.enable) 4204 return 0; 4205 4206 linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8, 4207 cdclk_state->logical.cdclk); 4208 4209 return min(linetime_wm, 0x1ff); 4210} 4211 4212static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state) 4213{ 4214 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4215 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4216 const struct drm_display_mode *pipe_mode = 4217 &crtc_state->hw.pipe_mode; 4218 int linetime_wm; 4219 4220 if (!crtc_state->hw.enable) 4221 return 0; 4222 4223 linetime_wm = DIV_ROUND_UP(pipe_mode->crtc_htotal * 1000 * 8, 4224 crtc_state->pixel_rate); 4225 4226 /* Display WA #1135: BXT:ALL GLK:ALL */ 4227 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && 4228 skl_watermark_ipc_enabled(dev_priv)) 4229 linetime_wm /= 2; 4230 4231 return min(linetime_wm, 0x1ff); 4232} 4233 4234static int hsw_compute_linetime_wm(struct intel_atomic_state *state, 4235 struct intel_crtc *crtc) 4236{ 4237 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4238 struct intel_crtc_state *crtc_state = 4239 intel_atomic_get_new_crtc_state(state, crtc); 4240 const struct intel_cdclk_state *cdclk_state; 4241 4242 if (DISPLAY_VER(dev_priv) >= 9) 4243 crtc_state->linetime = skl_linetime_wm(crtc_state); 4244 else 4245 crtc_state->linetime = hsw_linetime_wm(crtc_state); 4246 4247 if (!hsw_crtc_supports_ips(crtc)) 4248 return 0; 4249 4250 cdclk_state = intel_atomic_get_cdclk_state(state); 4251 if (IS_ERR(cdclk_state)) 4252 return PTR_ERR(cdclk_state); 4253 4254 crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state, 4255 cdclk_state); 4256 4257 return 0; 4258} 4259 4260static int intel_crtc_atomic_check(struct intel_atomic_state *state, 4261 struct intel_crtc *crtc) 4262{ 4263 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4264 struct intel_crtc_state *crtc_state = 4265 intel_atomic_get_new_crtc_state(state, crtc); 4266 int ret; 4267 4268 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv) && 4269 intel_crtc_needs_modeset(crtc_state) && 4270 !crtc_state->hw.active) 4271 crtc_state->update_wm_post = true; 4272 4273 if (intel_crtc_needs_modeset(crtc_state)) { 4274 ret = intel_dpll_crtc_get_shared_dpll(state, crtc); 4275 if (ret) 4276 return ret; 4277 } 4278 4279 /* 4280 * May need to update pipe gamma enable bits 4281 * when C8 planes are getting enabled/disabled. 4282 */ 4283 if (c8_planes_changed(crtc_state)) 4284 crtc_state->uapi.color_mgmt_changed = true; 4285 4286 if (intel_crtc_needs_color_update(crtc_state)) { 4287 ret = intel_color_check(crtc_state); 4288 if (ret) 4289 return ret; 4290 } 4291 4292 ret = intel_compute_pipe_wm(state, crtc); 4293 if (ret) { 4294 drm_dbg_kms(&dev_priv->drm, 4295 "Target pipe watermarks are invalid\n"); 4296 return ret; 4297 } 4298 4299 /* 4300 * Calculate 'intermediate' watermarks that satisfy both the 4301 * old state and the new state. We can program these 4302 * immediately. 4303 */ 4304 ret = intel_compute_intermediate_wm(state, crtc); 4305 if (ret) { 4306 drm_dbg_kms(&dev_priv->drm, 4307 "No valid intermediate pipe watermarks are possible\n"); 4308 return ret; 4309 } 4310 4311 if (DISPLAY_VER(dev_priv) >= 9) { 4312 if (intel_crtc_needs_modeset(crtc_state) || 4313 intel_crtc_needs_fastset(crtc_state)) { 4314 ret = skl_update_scaler_crtc(crtc_state); 4315 if (ret) 4316 return ret; 4317 } 4318 4319 ret = intel_atomic_setup_scalers(dev_priv, crtc, crtc_state); 4320 if (ret) 4321 return ret; 4322 } 4323 4324 if (HAS_IPS(dev_priv)) { 4325 ret = hsw_ips_compute_config(state, crtc); 4326 if (ret) 4327 return ret; 4328 } 4329 4330 if (DISPLAY_VER(dev_priv) >= 9 || 4331 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { 4332 ret = hsw_compute_linetime_wm(state, crtc); 4333 if (ret) 4334 return ret; 4335 4336 } 4337 4338 ret = intel_psr2_sel_fetch_update(state, crtc); 4339 if (ret) 4340 return ret; 4341 4342 return 0; 4343} 4344 4345static int 4346compute_sink_pipe_bpp(const struct drm_connector_state *conn_state, 4347 struct intel_crtc_state *crtc_state) 4348{ 4349 struct drm_connector *connector = conn_state->connector; 4350 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 4351 const struct drm_display_info *info = &connector->display_info; 4352 int bpp; 4353 4354 switch (conn_state->max_bpc) { 4355 case 6 ... 7: 4356 bpp = 6 * 3; 4357 break; 4358 case 8 ... 9: 4359 bpp = 8 * 3; 4360 break; 4361 case 10 ... 11: 4362 bpp = 10 * 3; 4363 break; 4364 case 12 ... 16: 4365 bpp = 12 * 3; 4366 break; 4367 default: 4368 MISSING_CASE(conn_state->max_bpc); 4369 return -EINVAL; 4370 } 4371 4372 if (bpp < crtc_state->pipe_bpp) { 4373 drm_dbg_kms(&i915->drm, 4374 "[CONNECTOR:%d:%s] Limiting display bpp to %d " 4375 "(EDID bpp %d, max requested bpp %d, max platform bpp %d)\n", 4376 connector->base.id, connector->name, 4377 bpp, 3 * info->bpc, 4378 3 * conn_state->max_requested_bpc, 4379 crtc_state->pipe_bpp); 4380 4381 crtc_state->pipe_bpp = bpp; 4382 } 4383 4384 return 0; 4385} 4386 4387static int 4388compute_baseline_pipe_bpp(struct intel_atomic_state *state, 4389 struct intel_crtc *crtc) 4390{ 4391 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4392 struct intel_crtc_state *crtc_state = 4393 intel_atomic_get_new_crtc_state(state, crtc); 4394 struct drm_connector *connector; 4395 struct drm_connector_state *connector_state; 4396 int bpp, i; 4397 4398 if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || 4399 IS_CHERRYVIEW(dev_priv))) 4400 bpp = 10*3; 4401 else if (DISPLAY_VER(dev_priv) >= 5) 4402 bpp = 12*3; 4403 else 4404 bpp = 8*3; 4405 4406 crtc_state->pipe_bpp = bpp; 4407 4408 /* Clamp display bpp to connector max bpp */ 4409 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 4410 int ret; 4411 4412 if (connector_state->crtc != &crtc->base) 4413 continue; 4414 4415 ret = compute_sink_pipe_bpp(connector_state, crtc_state); 4416 if (ret) 4417 return ret; 4418 } 4419 4420 return 0; 4421} 4422 4423static bool check_digital_port_conflicts(struct intel_atomic_state *state) 4424{ 4425 struct drm_device *dev = state->base.dev; 4426 struct drm_connector *connector; 4427 struct drm_connector_list_iter conn_iter; 4428 unsigned int used_ports = 0; 4429 unsigned int used_mst_ports = 0; 4430 bool ret = true; 4431 4432 /* 4433 * We're going to peek into connector->state, 4434 * hence connection_mutex must be held. 4435 */ 4436 drm_modeset_lock_assert_held(&dev->mode_config.connection_mutex); 4437 4438 /* 4439 * Walk the connector list instead of the encoder 4440 * list to detect the problem on ddi platforms 4441 * where there's just one encoder per digital port. 4442 */ 4443 drm_connector_list_iter_begin(dev, &conn_iter); 4444 drm_for_each_connector_iter(connector, &conn_iter) { 4445 struct drm_connector_state *connector_state; 4446 struct intel_encoder *encoder; 4447 4448 connector_state = 4449 drm_atomic_get_new_connector_state(&state->base, 4450 connector); 4451 if (!connector_state) 4452 connector_state = connector->state; 4453 4454 if (!connector_state->best_encoder) 4455 continue; 4456 4457 encoder = to_intel_encoder(connector_state->best_encoder); 4458 4459 drm_WARN_ON(dev, !connector_state->crtc); 4460 4461 switch (encoder->type) { 4462 case INTEL_OUTPUT_DDI: 4463 if (drm_WARN_ON(dev, !HAS_DDI(to_i915(dev)))) 4464 break; 4465 fallthrough; 4466 case INTEL_OUTPUT_DP: 4467 case INTEL_OUTPUT_HDMI: 4468 case INTEL_OUTPUT_EDP: 4469 /* the same port mustn't appear more than once */ 4470 if (used_ports & BIT(encoder->port)) 4471 ret = false; 4472 4473 used_ports |= BIT(encoder->port); 4474 break; 4475 case INTEL_OUTPUT_DP_MST: 4476 used_mst_ports |= 4477 1 << encoder->port; 4478 break; 4479 default: 4480 break; 4481 } 4482 } 4483 drm_connector_list_iter_end(&conn_iter); 4484 4485 /* can't mix MST and SST/HDMI on the same port */ 4486 if (used_ports & used_mst_ports) 4487 return false; 4488 4489 return ret; 4490} 4491 4492static void 4493intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_atomic_state *state, 4494 struct intel_crtc *crtc) 4495{ 4496 struct intel_crtc_state *crtc_state = 4497 intel_atomic_get_new_crtc_state(state, crtc); 4498 4499 WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state)); 4500 4501 drm_property_replace_blob(&crtc_state->hw.degamma_lut, 4502 crtc_state->uapi.degamma_lut); 4503 drm_property_replace_blob(&crtc_state->hw.gamma_lut, 4504 crtc_state->uapi.gamma_lut); 4505 drm_property_replace_blob(&crtc_state->hw.ctm, 4506 crtc_state->uapi.ctm); 4507} 4508 4509static void 4510intel_crtc_copy_uapi_to_hw_state_modeset(struct intel_atomic_state *state, 4511 struct intel_crtc *crtc) 4512{ 4513 struct intel_crtc_state *crtc_state = 4514 intel_atomic_get_new_crtc_state(state, crtc); 4515 4516 WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state)); 4517 4518 crtc_state->hw.enable = crtc_state->uapi.enable; 4519 crtc_state->hw.active = crtc_state->uapi.active; 4520 drm_mode_copy(&crtc_state->hw.mode, 4521 &crtc_state->uapi.mode); 4522 drm_mode_copy(&crtc_state->hw.adjusted_mode, 4523 &crtc_state->uapi.adjusted_mode); 4524 crtc_state->hw.scaling_filter = crtc_state->uapi.scaling_filter; 4525 4526 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc); 4527} 4528 4529static void 4530copy_bigjoiner_crtc_state_nomodeset(struct intel_atomic_state *state, 4531 struct intel_crtc *slave_crtc) 4532{ 4533 struct intel_crtc_state *slave_crtc_state = 4534 intel_atomic_get_new_crtc_state(state, slave_crtc); 4535 struct intel_crtc *master_crtc = intel_master_crtc(slave_crtc_state); 4536 const struct intel_crtc_state *master_crtc_state = 4537 intel_atomic_get_new_crtc_state(state, master_crtc); 4538 4539 drm_property_replace_blob(&slave_crtc_state->hw.degamma_lut, 4540 master_crtc_state->hw.degamma_lut); 4541 drm_property_replace_blob(&slave_crtc_state->hw.gamma_lut, 4542 master_crtc_state->hw.gamma_lut); 4543 drm_property_replace_blob(&slave_crtc_state->hw.ctm, 4544 master_crtc_state->hw.ctm); 4545 4546 slave_crtc_state->uapi.color_mgmt_changed = master_crtc_state->uapi.color_mgmt_changed; 4547} 4548 4549static int 4550copy_bigjoiner_crtc_state_modeset(struct intel_atomic_state *state, 4551 struct intel_crtc *slave_crtc) 4552{ 4553 struct intel_crtc_state *slave_crtc_state = 4554 intel_atomic_get_new_crtc_state(state, slave_crtc); 4555 struct intel_crtc *master_crtc = intel_master_crtc(slave_crtc_state); 4556 const struct intel_crtc_state *master_crtc_state = 4557 intel_atomic_get_new_crtc_state(state, master_crtc); 4558 struct intel_crtc_state *saved_state; 4559 4560 WARN_ON(master_crtc_state->bigjoiner_pipes != 4561 slave_crtc_state->bigjoiner_pipes); 4562 4563 saved_state = kmemdup(master_crtc_state, sizeof(*saved_state), GFP_KERNEL); 4564 if (!saved_state) 4565 return -ENOMEM; 4566 4567 /* preserve some things from the slave's original crtc state */ 4568 saved_state->uapi = slave_crtc_state->uapi; 4569 saved_state->scaler_state = slave_crtc_state->scaler_state; 4570 saved_state->shared_dpll = slave_crtc_state->shared_dpll; 4571 saved_state->crc_enabled = slave_crtc_state->crc_enabled; 4572 4573 intel_crtc_free_hw_state(slave_crtc_state); 4574 memcpy(slave_crtc_state, saved_state, sizeof(*slave_crtc_state)); 4575 kfree(saved_state); 4576 4577 /* Re-init hw state */ 4578 memset(&slave_crtc_state->hw, 0, sizeof(slave_crtc_state->hw)); 4579 slave_crtc_state->hw.enable = master_crtc_state->hw.enable; 4580 slave_crtc_state->hw.active = master_crtc_state->hw.active; 4581 drm_mode_copy(&slave_crtc_state->hw.mode, 4582 &master_crtc_state->hw.mode); 4583 drm_mode_copy(&slave_crtc_state->hw.pipe_mode, 4584 &master_crtc_state->hw.pipe_mode); 4585 drm_mode_copy(&slave_crtc_state->hw.adjusted_mode, 4586 &master_crtc_state->hw.adjusted_mode); 4587 slave_crtc_state->hw.scaling_filter = master_crtc_state->hw.scaling_filter; 4588 4589 copy_bigjoiner_crtc_state_nomodeset(state, slave_crtc); 4590 4591 slave_crtc_state->uapi.mode_changed = master_crtc_state->uapi.mode_changed; 4592 slave_crtc_state->uapi.connectors_changed = master_crtc_state->uapi.connectors_changed; 4593 slave_crtc_state->uapi.active_changed = master_crtc_state->uapi.active_changed; 4594 4595 WARN_ON(master_crtc_state->bigjoiner_pipes != 4596 slave_crtc_state->bigjoiner_pipes); 4597 4598 return 0; 4599} 4600 4601static int 4602intel_crtc_prepare_cleared_state(struct intel_atomic_state *state, 4603 struct intel_crtc *crtc) 4604{ 4605 struct intel_crtc_state *crtc_state = 4606 intel_atomic_get_new_crtc_state(state, crtc); 4607 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4608 struct intel_crtc_state *saved_state; 4609 4610 saved_state = intel_crtc_state_alloc(crtc); 4611 if (!saved_state) 4612 return -ENOMEM; 4613 4614 /* free the old crtc_state->hw members */ 4615 intel_crtc_free_hw_state(crtc_state); 4616 4617 /* FIXME: before the switch to atomic started, a new pipe_config was 4618 * kzalloc'd. Code that depends on any field being zero should be 4619 * fixed, so that the crtc_state can be safely duplicated. For now, 4620 * only fields that are know to not cause problems are preserved. */ 4621 4622 saved_state->uapi = crtc_state->uapi; 4623 saved_state->inherited = crtc_state->inherited; 4624 saved_state->scaler_state = crtc_state->scaler_state; 4625 saved_state->shared_dpll = crtc_state->shared_dpll; 4626 saved_state->dpll_hw_state = crtc_state->dpll_hw_state; 4627 memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls, 4628 sizeof(saved_state->icl_port_dplls)); 4629 saved_state->crc_enabled = crtc_state->crc_enabled; 4630 if (IS_G4X(dev_priv) || 4631 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 4632 saved_state->wm = crtc_state->wm; 4633 4634 memcpy(crtc_state, saved_state, sizeof(*crtc_state)); 4635 kfree(saved_state); 4636 4637 intel_crtc_copy_uapi_to_hw_state_modeset(state, crtc); 4638 4639 return 0; 4640} 4641 4642static int 4643intel_modeset_pipe_config(struct intel_atomic_state *state, 4644 struct intel_crtc *crtc) 4645{ 4646 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 4647 struct intel_crtc_state *crtc_state = 4648 intel_atomic_get_new_crtc_state(state, crtc); 4649 struct drm_connector *connector; 4650 struct drm_connector_state *connector_state; 4651 int pipe_src_w, pipe_src_h; 4652 int base_bpp, ret, i; 4653 bool retry = true; 4654 4655 crtc_state->cpu_transcoder = (enum transcoder) crtc->pipe; 4656 4657 crtc_state->framestart_delay = 1; 4658 4659 /* 4660 * Sanitize sync polarity flags based on requested ones. If neither 4661 * positive or negative polarity is requested, treat this as meaning 4662 * negative polarity. 4663 */ 4664 if (!(crtc_state->hw.adjusted_mode.flags & 4665 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) 4666 crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; 4667 4668 if (!(crtc_state->hw.adjusted_mode.flags & 4669 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) 4670 crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; 4671 4672 ret = compute_baseline_pipe_bpp(state, crtc); 4673 if (ret) 4674 return ret; 4675 4676 base_bpp = crtc_state->pipe_bpp; 4677 4678 /* 4679 * Determine the real pipe dimensions. Note that stereo modes can 4680 * increase the actual pipe size due to the frame doubling and 4681 * insertion of additional space for blanks between the frame. This 4682 * is stored in the crtc timings. We use the requested mode to do this 4683 * computation to clearly distinguish it from the adjusted mode, which 4684 * can be changed by the connectors in the below retry loop. 4685 */ 4686 drm_mode_get_hv_timing(&crtc_state->hw.mode, 4687 &pipe_src_w, &pipe_src_h); 4688 drm_rect_init(&crtc_state->pipe_src, 0, 0, 4689 pipe_src_w, pipe_src_h); 4690 4691 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 4692 struct intel_encoder *encoder = 4693 to_intel_encoder(connector_state->best_encoder); 4694 4695 if (connector_state->crtc != &crtc->base) 4696 continue; 4697 4698 if (!check_single_encoder_cloning(state, crtc, encoder)) { 4699 drm_dbg_kms(&i915->drm, 4700 "[ENCODER:%d:%s] rejecting invalid cloning configuration\n", 4701 encoder->base.base.id, encoder->base.name); 4702 return -EINVAL; 4703 } 4704 4705 /* 4706 * Determine output_types before calling the .compute_config() 4707 * hooks so that the hooks can use this information safely. 4708 */ 4709 if (encoder->compute_output_type) 4710 crtc_state->output_types |= 4711 BIT(encoder->compute_output_type(encoder, crtc_state, 4712 connector_state)); 4713 else 4714 crtc_state->output_types |= BIT(encoder->type); 4715 } 4716 4717encoder_retry: 4718 /* Ensure the port clock defaults are reset when retrying. */ 4719 crtc_state->port_clock = 0; 4720 crtc_state->pixel_multiplier = 1; 4721 4722 /* Fill in default crtc timings, allow encoders to overwrite them. */ 4723 drm_mode_set_crtcinfo(&crtc_state->hw.adjusted_mode, 4724 CRTC_STEREO_DOUBLE); 4725 4726 /* Pass our mode to the connectors and the CRTC to give them a chance to 4727 * adjust it according to limitations or connector properties, and also 4728 * a chance to reject the mode entirely. 4729 */ 4730 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 4731 struct intel_encoder *encoder = 4732 to_intel_encoder(connector_state->best_encoder); 4733 4734 if (connector_state->crtc != &crtc->base) 4735 continue; 4736 4737 ret = encoder->compute_config(encoder, crtc_state, 4738 connector_state); 4739 if (ret == -EDEADLK) 4740 return ret; 4741 if (ret < 0) { 4742 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] config failure: %d\n", 4743 encoder->base.base.id, encoder->base.name, ret); 4744 return ret; 4745 } 4746 } 4747 4748 /* Set default port clock if not overwritten by the encoder. Needs to be 4749 * done afterwards in case the encoder adjusts the mode. */ 4750 if (!crtc_state->port_clock) 4751 crtc_state->port_clock = crtc_state->hw.adjusted_mode.crtc_clock 4752 * crtc_state->pixel_multiplier; 4753 4754 ret = intel_crtc_compute_config(state, crtc); 4755 if (ret == -EDEADLK) 4756 return ret; 4757 if (ret == -EAGAIN) { 4758 if (drm_WARN(&i915->drm, !retry, 4759 "[CRTC:%d:%s] loop in pipe configuration computation\n", 4760 crtc->base.base.id, crtc->base.name)) 4761 return -EINVAL; 4762 4763 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] bw constrained, retrying\n", 4764 crtc->base.base.id, crtc->base.name); 4765 retry = false; 4766 goto encoder_retry; 4767 } 4768 if (ret < 0) { 4769 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] config failure: %d\n", 4770 crtc->base.base.id, crtc->base.name, ret); 4771 return ret; 4772 } 4773 4774 /* Dithering seems to not pass-through bits correctly when it should, so 4775 * only enable it on 6bpc panels and when its not a compliance 4776 * test requesting 6bpc video pattern. 4777 */ 4778 crtc_state->dither = (crtc_state->pipe_bpp == 6*3) && 4779 !crtc_state->dither_force_disable; 4780 drm_dbg_kms(&i915->drm, 4781 "[CRTC:%d:%s] hw max bpp: %i, pipe bpp: %i, dithering: %i\n", 4782 crtc->base.base.id, crtc->base.name, 4783 base_bpp, crtc_state->pipe_bpp, crtc_state->dither); 4784 4785 return 0; 4786} 4787 4788static int 4789intel_modeset_pipe_config_late(struct intel_atomic_state *state, 4790 struct intel_crtc *crtc) 4791{ 4792 struct intel_crtc_state *crtc_state = 4793 intel_atomic_get_new_crtc_state(state, crtc); 4794 struct drm_connector_state *conn_state; 4795 struct drm_connector *connector; 4796 int i; 4797 4798 intel_bigjoiner_adjust_pipe_src(crtc_state); 4799 4800 for_each_new_connector_in_state(&state->base, connector, 4801 conn_state, i) { 4802 struct intel_encoder *encoder = 4803 to_intel_encoder(conn_state->best_encoder); 4804 int ret; 4805 4806 if (conn_state->crtc != &crtc->base || 4807 !encoder->compute_config_late) 4808 continue; 4809 4810 ret = encoder->compute_config_late(encoder, crtc_state, 4811 conn_state); 4812 if (ret) 4813 return ret; 4814 } 4815 4816 return 0; 4817} 4818 4819bool intel_fuzzy_clock_check(int clock1, int clock2) 4820{ 4821 int diff; 4822 4823 if (clock1 == clock2) 4824 return true; 4825 4826 if (!clock1 || !clock2) 4827 return false; 4828 4829 diff = abs(clock1 - clock2); 4830 4831 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) 4832 return true; 4833 4834 return false; 4835} 4836 4837static bool 4838intel_compare_link_m_n(const struct intel_link_m_n *m_n, 4839 const struct intel_link_m_n *m2_n2) 4840{ 4841 return m_n->tu == m2_n2->tu && 4842 m_n->data_m == m2_n2->data_m && 4843 m_n->data_n == m2_n2->data_n && 4844 m_n->link_m == m2_n2->link_m && 4845 m_n->link_n == m2_n2->link_n; 4846} 4847 4848static bool 4849intel_compare_infoframe(const union hdmi_infoframe *a, 4850 const union hdmi_infoframe *b) 4851{ 4852 return memcmp(a, b, sizeof(*a)) == 0; 4853} 4854 4855static bool 4856intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a, 4857 const struct drm_dp_vsc_sdp *b) 4858{ 4859 return memcmp(a, b, sizeof(*a)) == 0; 4860} 4861 4862static bool 4863intel_compare_buffer(const u8 *a, const u8 *b, size_t len) 4864{ 4865 return memcmp(a, b, len) == 0; 4866} 4867 4868static void 4869pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv, 4870 bool fastset, const char *name, 4871 const union hdmi_infoframe *a, 4872 const union hdmi_infoframe *b) 4873{ 4874 if (fastset) { 4875 if (!drm_debug_enabled(DRM_UT_KMS)) 4876 return; 4877 4878 drm_dbg_kms(&dev_priv->drm, 4879 "fastset requirement not met in %s infoframe\n", name); 4880 drm_dbg_kms(&dev_priv->drm, "expected:\n"); 4881 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, a); 4882 drm_dbg_kms(&dev_priv->drm, "found:\n"); 4883 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, b); 4884 } else { 4885 drm_err(&dev_priv->drm, "mismatch in %s infoframe\n", name); 4886 drm_err(&dev_priv->drm, "expected:\n"); 4887 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, a); 4888 drm_err(&dev_priv->drm, "found:\n"); 4889 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, b); 4890 } 4891} 4892 4893static void 4894pipe_config_dp_vsc_sdp_mismatch(struct drm_i915_private *dev_priv, 4895 bool fastset, const char *name, 4896 const struct drm_dp_vsc_sdp *a, 4897 const struct drm_dp_vsc_sdp *b) 4898{ 4899 if (fastset) { 4900 if (!drm_debug_enabled(DRM_UT_KMS)) 4901 return; 4902 4903 drm_dbg_kms(&dev_priv->drm, 4904 "fastset requirement not met in %s dp sdp\n", name); 4905 drm_dbg_kms(&dev_priv->drm, "expected:\n"); 4906 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, a); 4907 drm_dbg_kms(&dev_priv->drm, "found:\n"); 4908 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, b); 4909 } else { 4910 drm_err(&dev_priv->drm, "mismatch in %s dp sdp\n", name); 4911 drm_err(&dev_priv->drm, "expected:\n"); 4912 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, a); 4913 drm_err(&dev_priv->drm, "found:\n"); 4914 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, b); 4915 } 4916} 4917 4918/* Returns the length up to and including the last differing byte */ 4919static size_t 4920memcmp_diff_len(const u8 *a, const u8 *b, size_t len) 4921{ 4922 int i; 4923 4924 for (i = len - 1; i >= 0; i--) { 4925 if (a[i] != b[i]) 4926 return i + 1; 4927 } 4928 4929 return 0; 4930} 4931 4932static void 4933pipe_config_buffer_mismatch(struct drm_i915_private *dev_priv, 4934 bool fastset, const char *name, 4935 const u8 *a, const u8 *b, size_t len) 4936{ 4937 if (fastset) { 4938 if (!drm_debug_enabled(DRM_UT_KMS)) 4939 return; 4940 4941 /* only dump up to the last difference */ 4942 len = memcmp_diff_len(a, b, len); 4943 4944 drm_dbg_kms(&dev_priv->drm, 4945 "fastset requirement not met in %s buffer\n", name); 4946 print_hex_dump(KERN_DEBUG, "expected: ", DUMP_PREFIX_NONE, 4947 16, 0, a, len, false); 4948 print_hex_dump(KERN_DEBUG, "found: ", DUMP_PREFIX_NONE, 4949 16, 0, b, len, false); 4950 } else { 4951 /* only dump up to the last difference */ 4952 len = memcmp_diff_len(a, b, len); 4953 4954 drm_err(&dev_priv->drm, "mismatch in %s buffer\n", name); 4955 print_hex_dump(KERN_ERR, "expected: ", DUMP_PREFIX_NONE, 4956 16, 0, a, len, false); 4957 print_hex_dump(KERN_ERR, "found: ", DUMP_PREFIX_NONE, 4958 16, 0, b, len, false); 4959 } 4960} 4961 4962static void __printf(4, 5) 4963pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc, 4964 const char *name, const char *format, ...) 4965{ 4966 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 4967 struct va_format vaf; 4968 va_list args; 4969 4970 va_start(args, format); 4971 vaf.fmt = format; 4972 vaf.va = &args; 4973 4974 if (fastset) 4975 drm_dbg_kms(&i915->drm, 4976 "[CRTC:%d:%s] fastset requirement not met in %s %pV\n", 4977 crtc->base.base.id, crtc->base.name, name, &vaf); 4978 else 4979 drm_err(&i915->drm, "[CRTC:%d:%s] mismatch in %s %pV\n", 4980 crtc->base.base.id, crtc->base.name, name, &vaf); 4981 4982 va_end(args); 4983} 4984 4985static bool fastboot_enabled(struct drm_i915_private *dev_priv) 4986{ 4987 if (dev_priv->params.fastboot != -1) 4988 return dev_priv->params.fastboot; 4989 4990 /* Enable fastboot by default on Skylake and newer */ 4991 if (DISPLAY_VER(dev_priv) >= 9) 4992 return true; 4993 4994 /* Enable fastboot by default on VLV and CHV */ 4995 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 4996 return true; 4997 4998 /* Disabled by default on all others */ 4999 return false; 5000} 5001 5002bool 5003intel_pipe_config_compare(const struct intel_crtc_state *current_config, 5004 const struct intel_crtc_state *pipe_config, 5005 bool fastset) 5006{ 5007 struct drm_i915_private *dev_priv = to_i915(current_config->uapi.crtc->dev); 5008 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 5009 bool ret = true; 5010 bool fixup_inherited = fastset && 5011 current_config->inherited && !pipe_config->inherited; 5012 5013 if (fixup_inherited && !fastboot_enabled(dev_priv)) { 5014 drm_dbg_kms(&dev_priv->drm, 5015 "initial modeset and fastboot not set\n"); 5016 ret = false; 5017 } 5018 5019#define PIPE_CONF_CHECK_X(name) do { \ 5020 if (current_config->name != pipe_config->name) { \ 5021 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5022 "(expected 0x%08x, found 0x%08x)", \ 5023 current_config->name, \ 5024 pipe_config->name); \ 5025 ret = false; \ 5026 } \ 5027} while (0) 5028 5029#define PIPE_CONF_CHECK_X_WITH_MASK(name, mask) do { \ 5030 if ((current_config->name & (mask)) != (pipe_config->name & (mask))) { \ 5031 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5032 "(expected 0x%08x, found 0x%08x)", \ 5033 current_config->name & (mask), \ 5034 pipe_config->name & (mask)); \ 5035 ret = false; \ 5036 } \ 5037} while (0) 5038 5039#define PIPE_CONF_CHECK_I(name) do { \ 5040 if (current_config->name != pipe_config->name) { \ 5041 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5042 "(expected %i, found %i)", \ 5043 current_config->name, \ 5044 pipe_config->name); \ 5045 ret = false; \ 5046 } \ 5047} while (0) 5048 5049#define PIPE_CONF_CHECK_BOOL(name) do { \ 5050 if (current_config->name != pipe_config->name) { \ 5051 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5052 "(expected %s, found %s)", \ 5053 str_yes_no(current_config->name), \ 5054 str_yes_no(pipe_config->name)); \ 5055 ret = false; \ 5056 } \ 5057} while (0) 5058 5059/* 5060 * Checks state where we only read out the enabling, but not the entire 5061 * state itself (like full infoframes or ELD for audio). These states 5062 * require a full modeset on bootup to fix up. 5063 */ 5064#define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) do { \ 5065 if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \ 5066 PIPE_CONF_CHECK_BOOL(name); \ 5067 } else { \ 5068 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5069 "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)", \ 5070 str_yes_no(current_config->name), \ 5071 str_yes_no(pipe_config->name)); \ 5072 ret = false; \ 5073 } \ 5074} while (0) 5075 5076#define PIPE_CONF_CHECK_P(name) do { \ 5077 if (current_config->name != pipe_config->name) { \ 5078 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5079 "(expected %p, found %p)", \ 5080 current_config->name, \ 5081 pipe_config->name); \ 5082 ret = false; \ 5083 } \ 5084} while (0) 5085 5086#define PIPE_CONF_CHECK_M_N(name) do { \ 5087 if (!intel_compare_link_m_n(¤t_config->name, \ 5088 &pipe_config->name)) { \ 5089 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5090 "(expected tu %i data %i/%i link %i/%i, " \ 5091 "found tu %i, data %i/%i link %i/%i)", \ 5092 current_config->name.tu, \ 5093 current_config->name.data_m, \ 5094 current_config->name.data_n, \ 5095 current_config->name.link_m, \ 5096 current_config->name.link_n, \ 5097 pipe_config->name.tu, \ 5098 pipe_config->name.data_m, \ 5099 pipe_config->name.data_n, \ 5100 pipe_config->name.link_m, \ 5101 pipe_config->name.link_n); \ 5102 ret = false; \ 5103 } \ 5104} while (0) 5105 5106#define PIPE_CONF_CHECK_TIMINGS(name) do { \ 5107 PIPE_CONF_CHECK_I(name.crtc_hdisplay); \ 5108 PIPE_CONF_CHECK_I(name.crtc_htotal); \ 5109 PIPE_CONF_CHECK_I(name.crtc_hblank_start); \ 5110 PIPE_CONF_CHECK_I(name.crtc_hblank_end); \ 5111 PIPE_CONF_CHECK_I(name.crtc_hsync_start); \ 5112 PIPE_CONF_CHECK_I(name.crtc_hsync_end); \ 5113 PIPE_CONF_CHECK_I(name.crtc_vdisplay); \ 5114 PIPE_CONF_CHECK_I(name.crtc_vtotal); \ 5115 PIPE_CONF_CHECK_I(name.crtc_vblank_start); \ 5116 PIPE_CONF_CHECK_I(name.crtc_vblank_end); \ 5117 PIPE_CONF_CHECK_I(name.crtc_vsync_start); \ 5118 PIPE_CONF_CHECK_I(name.crtc_vsync_end); \ 5119} while (0) 5120 5121#define PIPE_CONF_CHECK_RECT(name) do { \ 5122 PIPE_CONF_CHECK_I(name.x1); \ 5123 PIPE_CONF_CHECK_I(name.x2); \ 5124 PIPE_CONF_CHECK_I(name.y1); \ 5125 PIPE_CONF_CHECK_I(name.y2); \ 5126} while (0) 5127 5128#define PIPE_CONF_CHECK_FLAGS(name, mask) do { \ 5129 if ((current_config->name ^ pipe_config->name) & (mask)) { \ 5130 pipe_config_mismatch(fastset, crtc, __stringify(name), \ 5131 "(%x) (expected %i, found %i)", \ 5132 (mask), \ 5133 current_config->name & (mask), \ 5134 pipe_config->name & (mask)); \ 5135 ret = false; \ 5136 } \ 5137} while (0) 5138 5139#define PIPE_CONF_CHECK_INFOFRAME(name) do { \ 5140 if (!intel_compare_infoframe(¤t_config->infoframes.name, \ 5141 &pipe_config->infoframes.name)) { \ 5142 pipe_config_infoframe_mismatch(dev_priv, fastset, __stringify(name), \ 5143 ¤t_config->infoframes.name, \ 5144 &pipe_config->infoframes.name); \ 5145 ret = false; \ 5146 } \ 5147} while (0) 5148 5149#define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \ 5150 if (!current_config->has_psr && !pipe_config->has_psr && \ 5151 !intel_compare_dp_vsc_sdp(¤t_config->infoframes.name, \ 5152 &pipe_config->infoframes.name)) { \ 5153 pipe_config_dp_vsc_sdp_mismatch(dev_priv, fastset, __stringify(name), \ 5154 ¤t_config->infoframes.name, \ 5155 &pipe_config->infoframes.name); \ 5156 ret = false; \ 5157 } \ 5158} while (0) 5159 5160#define PIPE_CONF_CHECK_BUFFER(name, len) do { \ 5161 BUILD_BUG_ON(sizeof(current_config->name) != (len)); \ 5162 BUILD_BUG_ON(sizeof(pipe_config->name) != (len)); \ 5163 if (!intel_compare_buffer(current_config->name, pipe_config->name, (len))) { \ 5164 pipe_config_buffer_mismatch(dev_priv, fastset, __stringify(name), \ 5165 current_config->name, \ 5166 pipe_config->name, \ 5167 (len)); \ 5168 ret = false; \ 5169 } \ 5170} while (0) 5171 5172#define PIPE_CONF_CHECK_COLOR_LUT(lut, is_pre_csc_lut) do { \ 5173 if (current_config->gamma_mode == pipe_config->gamma_mode && \ 5174 !intel_color_lut_equal(current_config, \ 5175 current_config->lut, pipe_config->lut, \ 5176 is_pre_csc_lut)) { \ 5177 pipe_config_mismatch(fastset, crtc, __stringify(lut), \ 5178 "hw_state doesn't match sw_state"); \ 5179 ret = false; \ 5180 } \ 5181} while (0) 5182 5183#define PIPE_CONF_CHECK_CSC(name) do { \ 5184 PIPE_CONF_CHECK_X(name.preoff[0]); \ 5185 PIPE_CONF_CHECK_X(name.preoff[1]); \ 5186 PIPE_CONF_CHECK_X(name.preoff[2]); \ 5187 PIPE_CONF_CHECK_X(name.coeff[0]); \ 5188 PIPE_CONF_CHECK_X(name.coeff[1]); \ 5189 PIPE_CONF_CHECK_X(name.coeff[2]); \ 5190 PIPE_CONF_CHECK_X(name.coeff[3]); \ 5191 PIPE_CONF_CHECK_X(name.coeff[4]); \ 5192 PIPE_CONF_CHECK_X(name.coeff[5]); \ 5193 PIPE_CONF_CHECK_X(name.coeff[6]); \ 5194 PIPE_CONF_CHECK_X(name.coeff[7]); \ 5195 PIPE_CONF_CHECK_X(name.coeff[8]); \ 5196 PIPE_CONF_CHECK_X(name.postoff[0]); \ 5197 PIPE_CONF_CHECK_X(name.postoff[1]); \ 5198 PIPE_CONF_CHECK_X(name.postoff[2]); \ 5199} while (0) 5200 5201#define PIPE_CONF_QUIRK(quirk) \ 5202 ((current_config->quirks | pipe_config->quirks) & (quirk)) 5203 5204 PIPE_CONF_CHECK_I(hw.enable); 5205 PIPE_CONF_CHECK_I(hw.active); 5206 5207 PIPE_CONF_CHECK_I(cpu_transcoder); 5208 PIPE_CONF_CHECK_I(mst_master_transcoder); 5209 5210 PIPE_CONF_CHECK_BOOL(has_pch_encoder); 5211 PIPE_CONF_CHECK_I(fdi_lanes); 5212 PIPE_CONF_CHECK_M_N(fdi_m_n); 5213 5214 PIPE_CONF_CHECK_I(lane_count); 5215 PIPE_CONF_CHECK_X(lane_lat_optim_mask); 5216 5217 if (HAS_DOUBLE_BUFFERED_M_N(dev_priv)) { 5218 if (!fastset || !pipe_config->seamless_m_n) 5219 PIPE_CONF_CHECK_M_N(dp_m_n); 5220 } else { 5221 PIPE_CONF_CHECK_M_N(dp_m_n); 5222 PIPE_CONF_CHECK_M_N(dp_m2_n2); 5223 } 5224 5225 PIPE_CONF_CHECK_X(output_types); 5226 5227 PIPE_CONF_CHECK_I(framestart_delay); 5228 PIPE_CONF_CHECK_I(msa_timing_delay); 5229 5230 PIPE_CONF_CHECK_TIMINGS(hw.pipe_mode); 5231 PIPE_CONF_CHECK_TIMINGS(hw.adjusted_mode); 5232 5233 PIPE_CONF_CHECK_I(pixel_multiplier); 5234 5235 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5236 DRM_MODE_FLAG_INTERLACE); 5237 5238 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { 5239 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5240 DRM_MODE_FLAG_PHSYNC); 5241 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5242 DRM_MODE_FLAG_NHSYNC); 5243 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5244 DRM_MODE_FLAG_PVSYNC); 5245 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5246 DRM_MODE_FLAG_NVSYNC); 5247 } 5248 5249 PIPE_CONF_CHECK_I(output_format); 5250 PIPE_CONF_CHECK_BOOL(has_hdmi_sink); 5251 if ((DISPLAY_VER(dev_priv) < 8 && !IS_HASWELL(dev_priv)) || 5252 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 5253 PIPE_CONF_CHECK_BOOL(limited_color_range); 5254 5255 PIPE_CONF_CHECK_BOOL(hdmi_scrambling); 5256 PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio); 5257 PIPE_CONF_CHECK_BOOL(has_infoframe); 5258 PIPE_CONF_CHECK_BOOL(enhanced_framing); 5259 PIPE_CONF_CHECK_BOOL(fec_enable); 5260 5261 PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio); 5262 PIPE_CONF_CHECK_BUFFER(eld, MAX_ELD_BYTES); 5263 5264 PIPE_CONF_CHECK_X(gmch_pfit.control); 5265 /* pfit ratios are autocomputed by the hw on gen4+ */ 5266 if (DISPLAY_VER(dev_priv) < 4) 5267 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios); 5268 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); 5269 5270 /* 5271 * Changing the EDP transcoder input mux 5272 * (A_ONOFF vs. A_ON) requires a full modeset. 5273 */ 5274 PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru); 5275 5276 if (!fastset) { 5277 PIPE_CONF_CHECK_RECT(pipe_src); 5278 5279 PIPE_CONF_CHECK_BOOL(pch_pfit.enabled); 5280 PIPE_CONF_CHECK_RECT(pch_pfit.dst); 5281 5282 PIPE_CONF_CHECK_I(scaler_state.scaler_id); 5283 PIPE_CONF_CHECK_I(pixel_rate); 5284 5285 PIPE_CONF_CHECK_X(gamma_mode); 5286 if (IS_CHERRYVIEW(dev_priv)) 5287 PIPE_CONF_CHECK_X(cgm_mode); 5288 else 5289 PIPE_CONF_CHECK_X(csc_mode); 5290 PIPE_CONF_CHECK_BOOL(gamma_enable); 5291 PIPE_CONF_CHECK_BOOL(csc_enable); 5292 PIPE_CONF_CHECK_BOOL(wgc_enable); 5293 5294 PIPE_CONF_CHECK_I(linetime); 5295 PIPE_CONF_CHECK_I(ips_linetime); 5296 5297 PIPE_CONF_CHECK_COLOR_LUT(pre_csc_lut, true); 5298 PIPE_CONF_CHECK_COLOR_LUT(post_csc_lut, false); 5299 5300 PIPE_CONF_CHECK_CSC(csc); 5301 PIPE_CONF_CHECK_CSC(output_csc); 5302 5303 if (current_config->active_planes) { 5304 PIPE_CONF_CHECK_BOOL(has_psr); 5305 PIPE_CONF_CHECK_BOOL(has_psr2); 5306 PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch); 5307 PIPE_CONF_CHECK_I(dc3co_exitline); 5308 } 5309 } 5310 5311 PIPE_CONF_CHECK_BOOL(double_wide); 5312 5313 if (dev_priv->display.dpll.mgr) { 5314 PIPE_CONF_CHECK_P(shared_dpll); 5315 5316 PIPE_CONF_CHECK_X(dpll_hw_state.dpll); 5317 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); 5318 PIPE_CONF_CHECK_X(dpll_hw_state.fp0); 5319 PIPE_CONF_CHECK_X(dpll_hw_state.fp1); 5320 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); 5321 PIPE_CONF_CHECK_X(dpll_hw_state.spll); 5322 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); 5323 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); 5324 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); 5325 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0); 5326 PIPE_CONF_CHECK_X(dpll_hw_state.div0); 5327 PIPE_CONF_CHECK_X(dpll_hw_state.ebb0); 5328 PIPE_CONF_CHECK_X(dpll_hw_state.ebb4); 5329 PIPE_CONF_CHECK_X(dpll_hw_state.pll0); 5330 PIPE_CONF_CHECK_X(dpll_hw_state.pll1); 5331 PIPE_CONF_CHECK_X(dpll_hw_state.pll2); 5332 PIPE_CONF_CHECK_X(dpll_hw_state.pll3); 5333 PIPE_CONF_CHECK_X(dpll_hw_state.pll6); 5334 PIPE_CONF_CHECK_X(dpll_hw_state.pll8); 5335 PIPE_CONF_CHECK_X(dpll_hw_state.pll9); 5336 PIPE_CONF_CHECK_X(dpll_hw_state.pll10); 5337 PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12); 5338 PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl); 5339 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1); 5340 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl); 5341 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0); 5342 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1); 5343 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf); 5344 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock); 5345 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc); 5346 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias); 5347 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias); 5348 } 5349 5350 PIPE_CONF_CHECK_X(dsi_pll.ctrl); 5351 PIPE_CONF_CHECK_X(dsi_pll.div); 5352 5353 if (IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) >= 5) 5354 PIPE_CONF_CHECK_I(pipe_bpp); 5355 5356 if (!fastset || !pipe_config->seamless_m_n) { 5357 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_clock); 5358 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_clock); 5359 } 5360 PIPE_CONF_CHECK_I(port_clock); 5361 5362 PIPE_CONF_CHECK_I(min_voltage_level); 5363 5364 if (current_config->has_psr || pipe_config->has_psr) 5365 PIPE_CONF_CHECK_X_WITH_MASK(infoframes.enable, 5366 ~intel_hdmi_infoframe_enable(DP_SDP_VSC)); 5367 else 5368 PIPE_CONF_CHECK_X(infoframes.enable); 5369 5370 PIPE_CONF_CHECK_X(infoframes.gcp); 5371 PIPE_CONF_CHECK_INFOFRAME(avi); 5372 PIPE_CONF_CHECK_INFOFRAME(spd); 5373 PIPE_CONF_CHECK_INFOFRAME(hdmi); 5374 PIPE_CONF_CHECK_INFOFRAME(drm); 5375 PIPE_CONF_CHECK_DP_VSC_SDP(vsc); 5376 5377 PIPE_CONF_CHECK_X(sync_mode_slaves_mask); 5378 PIPE_CONF_CHECK_I(master_transcoder); 5379 PIPE_CONF_CHECK_X(bigjoiner_pipes); 5380 5381 PIPE_CONF_CHECK_I(dsc.compression_enable); 5382 PIPE_CONF_CHECK_I(dsc.dsc_split); 5383 PIPE_CONF_CHECK_I(dsc.compressed_bpp); 5384 5385 PIPE_CONF_CHECK_BOOL(splitter.enable); 5386 PIPE_CONF_CHECK_I(splitter.link_count); 5387 PIPE_CONF_CHECK_I(splitter.pixel_overlap); 5388 5389 if (!fastset) 5390 PIPE_CONF_CHECK_BOOL(vrr.enable); 5391 PIPE_CONF_CHECK_I(vrr.vmin); 5392 PIPE_CONF_CHECK_I(vrr.vmax); 5393 PIPE_CONF_CHECK_I(vrr.flipline); 5394 PIPE_CONF_CHECK_I(vrr.pipeline_full); 5395 PIPE_CONF_CHECK_I(vrr.guardband); 5396 5397#undef PIPE_CONF_CHECK_X 5398#undef PIPE_CONF_CHECK_I 5399#undef PIPE_CONF_CHECK_BOOL 5400#undef PIPE_CONF_CHECK_BOOL_INCOMPLETE 5401#undef PIPE_CONF_CHECK_P 5402#undef PIPE_CONF_CHECK_FLAGS 5403#undef PIPE_CONF_CHECK_COLOR_LUT 5404#undef PIPE_CONF_CHECK_TIMINGS 5405#undef PIPE_CONF_CHECK_RECT 5406#undef PIPE_CONF_QUIRK 5407 5408 return ret; 5409} 5410 5411static void 5412intel_verify_planes(struct intel_atomic_state *state) 5413{ 5414 struct intel_plane *plane; 5415 const struct intel_plane_state *plane_state; 5416 int i; 5417 5418 for_each_new_intel_plane_in_state(state, plane, 5419 plane_state, i) 5420 assert_plane(plane, plane_state->planar_slave || 5421 plane_state->uapi.visible); 5422} 5423 5424int intel_modeset_all_pipes(struct intel_atomic_state *state, 5425 const char *reason) 5426{ 5427 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 5428 struct intel_crtc *crtc; 5429 5430 /* 5431 * Add all pipes to the state, and force 5432 * a modeset on all the active ones. 5433 */ 5434 for_each_intel_crtc(&dev_priv->drm, crtc) { 5435 struct intel_crtc_state *crtc_state; 5436 int ret; 5437 5438 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 5439 if (IS_ERR(crtc_state)) 5440 return PTR_ERR(crtc_state); 5441 5442 if (!crtc_state->hw.active || 5443 intel_crtc_needs_modeset(crtc_state)) 5444 continue; 5445 5446 drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] Full modeset due to %s\n", 5447 crtc->base.base.id, crtc->base.name, reason); 5448 5449 crtc_state->uapi.mode_changed = true; 5450 crtc_state->update_pipe = false; 5451 5452 ret = drm_atomic_add_affected_connectors(&state->base, 5453 &crtc->base); 5454 if (ret) 5455 return ret; 5456 5457 ret = intel_dp_mst_add_topology_state_for_crtc(state, crtc); 5458 if (ret) 5459 return ret; 5460 5461 ret = intel_atomic_add_affected_planes(state, crtc); 5462 if (ret) 5463 return ret; 5464 5465 crtc_state->update_planes |= crtc_state->active_planes; 5466 crtc_state->async_flip_planes = 0; 5467 crtc_state->do_async_flip = false; 5468 } 5469 5470 return 0; 5471} 5472 5473/* 5474 * This implements the workaround described in the "notes" section of the mode 5475 * set sequence documentation. When going from no pipes or single pipe to 5476 * multiple pipes, and planes are enabled after the pipe, we need to wait at 5477 * least 2 vblanks on the first pipe before enabling planes on the second pipe. 5478 */ 5479static int hsw_mode_set_planes_workaround(struct intel_atomic_state *state) 5480{ 5481 struct intel_crtc_state *crtc_state; 5482 struct intel_crtc *crtc; 5483 struct intel_crtc_state *first_crtc_state = NULL; 5484 struct intel_crtc_state *other_crtc_state = NULL; 5485 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; 5486 int i; 5487 5488 /* look at all crtc's that are going to be enabled in during modeset */ 5489 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 5490 if (!crtc_state->hw.active || 5491 !intel_crtc_needs_modeset(crtc_state)) 5492 continue; 5493 5494 if (first_crtc_state) { 5495 other_crtc_state = crtc_state; 5496 break; 5497 } else { 5498 first_crtc_state = crtc_state; 5499 first_pipe = crtc->pipe; 5500 } 5501 } 5502 5503 /* No workaround needed? */ 5504 if (!first_crtc_state) 5505 return 0; 5506 5507 /* w/a possibly needed, check how many crtc's are already enabled. */ 5508 for_each_intel_crtc(state->base.dev, crtc) { 5509 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 5510 if (IS_ERR(crtc_state)) 5511 return PTR_ERR(crtc_state); 5512 5513 crtc_state->hsw_workaround_pipe = INVALID_PIPE; 5514 5515 if (!crtc_state->hw.active || 5516 intel_crtc_needs_modeset(crtc_state)) 5517 continue; 5518 5519 /* 2 or more enabled crtcs means no need for w/a */ 5520 if (enabled_pipe != INVALID_PIPE) 5521 return 0; 5522 5523 enabled_pipe = crtc->pipe; 5524 } 5525 5526 if (enabled_pipe != INVALID_PIPE) 5527 first_crtc_state->hsw_workaround_pipe = enabled_pipe; 5528 else if (other_crtc_state) 5529 other_crtc_state->hsw_workaround_pipe = first_pipe; 5530 5531 return 0; 5532} 5533 5534u8 intel_calc_active_pipes(struct intel_atomic_state *state, 5535 u8 active_pipes) 5536{ 5537 const struct intel_crtc_state *crtc_state; 5538 struct intel_crtc *crtc; 5539 int i; 5540 5541 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 5542 if (crtc_state->hw.active) 5543 active_pipes |= BIT(crtc->pipe); 5544 else 5545 active_pipes &= ~BIT(crtc->pipe); 5546 } 5547 5548 return active_pipes; 5549} 5550 5551static int intel_modeset_checks(struct intel_atomic_state *state) 5552{ 5553 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 5554 5555 state->modeset = true; 5556 5557 if (IS_HASWELL(dev_priv)) 5558 return hsw_mode_set_planes_workaround(state); 5559 5560 return 0; 5561} 5562 5563static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_state, 5564 struct intel_crtc_state *new_crtc_state) 5565{ 5566 struct drm_i915_private *i915 = to_i915(old_crtc_state->uapi.crtc->dev); 5567 5568 if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true)) { 5569 drm_dbg_kms(&i915->drm, "fastset requirement not met, forcing full modeset\n"); 5570 5571 return; 5572 } 5573 5574 new_crtc_state->uapi.mode_changed = false; 5575 if (!intel_crtc_needs_modeset(new_crtc_state)) 5576 new_crtc_state->update_pipe = true; 5577} 5578 5579static int intel_crtc_add_planes_to_state(struct intel_atomic_state *state, 5580 struct intel_crtc *crtc, 5581 u8 plane_ids_mask) 5582{ 5583 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 5584 struct intel_plane *plane; 5585 5586 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { 5587 struct intel_plane_state *plane_state; 5588 5589 if ((plane_ids_mask & BIT(plane->id)) == 0) 5590 continue; 5591 5592 plane_state = intel_atomic_get_plane_state(state, plane); 5593 if (IS_ERR(plane_state)) 5594 return PTR_ERR(plane_state); 5595 } 5596 5597 return 0; 5598} 5599 5600int intel_atomic_add_affected_planes(struct intel_atomic_state *state, 5601 struct intel_crtc *crtc) 5602{ 5603 const struct intel_crtc_state *old_crtc_state = 5604 intel_atomic_get_old_crtc_state(state, crtc); 5605 const struct intel_crtc_state *new_crtc_state = 5606 intel_atomic_get_new_crtc_state(state, crtc); 5607 5608 return intel_crtc_add_planes_to_state(state, crtc, 5609 old_crtc_state->enabled_planes | 5610 new_crtc_state->enabled_planes); 5611} 5612 5613static bool active_planes_affects_min_cdclk(struct drm_i915_private *dev_priv) 5614{ 5615 /* See {hsw,vlv,ivb}_plane_ratio() */ 5616 return IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv) || 5617 IS_CHERRYVIEW(dev_priv) || IS_VALLEYVIEW(dev_priv) || 5618 IS_IVYBRIDGE(dev_priv); 5619} 5620 5621static int intel_crtc_add_bigjoiner_planes(struct intel_atomic_state *state, 5622 struct intel_crtc *crtc, 5623 struct intel_crtc *other) 5624{ 5625 const struct intel_plane_state __maybe_unused *plane_state; 5626 struct intel_plane *plane; 5627 u8 plane_ids = 0; 5628 int i; 5629 5630 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 5631 if (plane->pipe == crtc->pipe) 5632 plane_ids |= BIT(plane->id); 5633 } 5634 5635 return intel_crtc_add_planes_to_state(state, other, plane_ids); 5636} 5637 5638static int intel_bigjoiner_add_affected_planes(struct intel_atomic_state *state) 5639{ 5640 struct drm_i915_private *i915 = to_i915(state->base.dev); 5641 const struct intel_crtc_state *crtc_state; 5642 struct intel_crtc *crtc; 5643 int i; 5644 5645 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 5646 struct intel_crtc *other; 5647 5648 for_each_intel_crtc_in_pipe_mask(&i915->drm, other, 5649 crtc_state->bigjoiner_pipes) { 5650 int ret; 5651 5652 if (crtc == other) 5653 continue; 5654 5655 ret = intel_crtc_add_bigjoiner_planes(state, crtc, other); 5656 if (ret) 5657 return ret; 5658 } 5659 } 5660 5661 return 0; 5662} 5663 5664static int intel_atomic_check_planes(struct intel_atomic_state *state) 5665{ 5666 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 5667 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 5668 struct intel_plane_state __maybe_unused *plane_state; 5669 struct intel_plane *plane; 5670 struct intel_crtc *crtc; 5671 int i, ret; 5672 5673 ret = icl_add_linked_planes(state); 5674 if (ret) 5675 return ret; 5676 5677 ret = intel_bigjoiner_add_affected_planes(state); 5678 if (ret) 5679 return ret; 5680 5681 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 5682 ret = intel_plane_atomic_check(state, plane); 5683 if (ret) { 5684 drm_dbg_atomic(&dev_priv->drm, 5685 "[PLANE:%d:%s] atomic driver check failed\n", 5686 plane->base.base.id, plane->base.name); 5687 return ret; 5688 } 5689 } 5690 5691 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 5692 new_crtc_state, i) { 5693 u8 old_active_planes, new_active_planes; 5694 5695 ret = icl_check_nv12_planes(new_crtc_state); 5696 if (ret) 5697 return ret; 5698 5699 /* 5700 * On some platforms the number of active planes affects 5701 * the planes' minimum cdclk calculation. Add such planes 5702 * to the state before we compute the minimum cdclk. 5703 */ 5704 if (!active_planes_affects_min_cdclk(dev_priv)) 5705 continue; 5706 5707 old_active_planes = old_crtc_state->active_planes & ~BIT(PLANE_CURSOR); 5708 new_active_planes = new_crtc_state->active_planes & ~BIT(PLANE_CURSOR); 5709 5710 if (hweight8(old_active_planes) == hweight8(new_active_planes)) 5711 continue; 5712 5713 ret = intel_crtc_add_planes_to_state(state, crtc, new_active_planes); 5714 if (ret) 5715 return ret; 5716 } 5717 5718 return 0; 5719} 5720 5721static int intel_atomic_check_crtcs(struct intel_atomic_state *state) 5722{ 5723 struct intel_crtc_state __maybe_unused *crtc_state; 5724 struct intel_crtc *crtc; 5725 int i; 5726 5727 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 5728 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 5729 int ret; 5730 5731 ret = intel_crtc_atomic_check(state, crtc); 5732 if (ret) { 5733 drm_dbg_atomic(&i915->drm, 5734 "[CRTC:%d:%s] atomic driver check failed\n", 5735 crtc->base.base.id, crtc->base.name); 5736 return ret; 5737 } 5738 } 5739 5740 return 0; 5741} 5742 5743static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state, 5744 u8 transcoders) 5745{ 5746 const struct intel_crtc_state *new_crtc_state; 5747 struct intel_crtc *crtc; 5748 int i; 5749 5750 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 5751 if (new_crtc_state->hw.enable && 5752 transcoders & BIT(new_crtc_state->cpu_transcoder) && 5753 intel_crtc_needs_modeset(new_crtc_state)) 5754 return true; 5755 } 5756 5757 return false; 5758} 5759 5760static bool intel_pipes_need_modeset(struct intel_atomic_state *state, 5761 u8 pipes) 5762{ 5763 const struct intel_crtc_state *new_crtc_state; 5764 struct intel_crtc *crtc; 5765 int i; 5766 5767 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 5768 if (new_crtc_state->hw.enable && 5769 pipes & BIT(crtc->pipe) && 5770 intel_crtc_needs_modeset(new_crtc_state)) 5771 return true; 5772 } 5773 5774 return false; 5775} 5776 5777static int intel_atomic_check_bigjoiner(struct intel_atomic_state *state, 5778 struct intel_crtc *master_crtc) 5779{ 5780 struct drm_i915_private *i915 = to_i915(state->base.dev); 5781 struct intel_crtc_state *master_crtc_state = 5782 intel_atomic_get_new_crtc_state(state, master_crtc); 5783 struct intel_crtc *slave_crtc; 5784 5785 if (!master_crtc_state->bigjoiner_pipes) 5786 return 0; 5787 5788 /* sanity check */ 5789 if (drm_WARN_ON(&i915->drm, 5790 master_crtc->pipe != bigjoiner_master_pipe(master_crtc_state))) 5791 return -EINVAL; 5792 5793 if (master_crtc_state->bigjoiner_pipes & ~bigjoiner_pipes(i915)) { 5794 drm_dbg_kms(&i915->drm, 5795 "[CRTC:%d:%s] Cannot act as big joiner master " 5796 "(need 0x%x as pipes, only 0x%x possible)\n", 5797 master_crtc->base.base.id, master_crtc->base.name, 5798 master_crtc_state->bigjoiner_pipes, bigjoiner_pipes(i915)); 5799 return -EINVAL; 5800 } 5801 5802 for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc, 5803 intel_crtc_bigjoiner_slave_pipes(master_crtc_state)) { 5804 struct intel_crtc_state *slave_crtc_state; 5805 int ret; 5806 5807 slave_crtc_state = intel_atomic_get_crtc_state(&state->base, slave_crtc); 5808 if (IS_ERR(slave_crtc_state)) 5809 return PTR_ERR(slave_crtc_state); 5810 5811 /* master being enabled, slave was already configured? */ 5812 if (slave_crtc_state->uapi.enable) { 5813 drm_dbg_kms(&i915->drm, 5814 "[CRTC:%d:%s] Slave is enabled as normal CRTC, but " 5815 "[CRTC:%d:%s] claiming this CRTC for bigjoiner.\n", 5816 slave_crtc->base.base.id, slave_crtc->base.name, 5817 master_crtc->base.base.id, master_crtc->base.name); 5818 return -EINVAL; 5819 } 5820 5821 /* 5822 * The state copy logic assumes the master crtc gets processed 5823 * before the slave crtc during the main compute_config loop. 5824 * This works because the crtcs are created in pipe order, 5825 * and the hardware requires master pipe < slave pipe as well. 5826 * Should that change we need to rethink the logic. 5827 */ 5828 if (WARN_ON(drm_crtc_index(&master_crtc->base) > 5829 drm_crtc_index(&slave_crtc->base))) 5830 return -EINVAL; 5831 5832 drm_dbg_kms(&i915->drm, 5833 "[CRTC:%d:%s] Used as slave for big joiner master [CRTC:%d:%s]\n", 5834 slave_crtc->base.base.id, slave_crtc->base.name, 5835 master_crtc->base.base.id, master_crtc->base.name); 5836 5837 slave_crtc_state->bigjoiner_pipes = 5838 master_crtc_state->bigjoiner_pipes; 5839 5840 ret = copy_bigjoiner_crtc_state_modeset(state, slave_crtc); 5841 if (ret) 5842 return ret; 5843 } 5844 5845 return 0; 5846} 5847 5848static void kill_bigjoiner_slave(struct intel_atomic_state *state, 5849 struct intel_crtc *master_crtc) 5850{ 5851 struct drm_i915_private *i915 = to_i915(state->base.dev); 5852 struct intel_crtc_state *master_crtc_state = 5853 intel_atomic_get_new_crtc_state(state, master_crtc); 5854 struct intel_crtc *slave_crtc; 5855 5856 for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc, 5857 intel_crtc_bigjoiner_slave_pipes(master_crtc_state)) { 5858 struct intel_crtc_state *slave_crtc_state = 5859 intel_atomic_get_new_crtc_state(state, slave_crtc); 5860 5861 slave_crtc_state->bigjoiner_pipes = 0; 5862 5863 intel_crtc_copy_uapi_to_hw_state_modeset(state, slave_crtc); 5864 } 5865 5866 master_crtc_state->bigjoiner_pipes = 0; 5867} 5868 5869/** 5870 * DOC: asynchronous flip implementation 5871 * 5872 * Asynchronous page flip is the implementation for the DRM_MODE_PAGE_FLIP_ASYNC 5873 * flag. Currently async flip is only supported via the drmModePageFlip IOCTL. 5874 * Correspondingly, support is currently added for primary plane only. 5875 * 5876 * Async flip can only change the plane surface address, so anything else 5877 * changing is rejected from the intel_async_flip_check_hw() function. 5878 * Once this check is cleared, flip done interrupt is enabled using 5879 * the intel_crtc_enable_flip_done() function. 5880 * 5881 * As soon as the surface address register is written, flip done interrupt is 5882 * generated and the requested events are sent to the usersapce in the interrupt 5883 * handler itself. The timestamp and sequence sent during the flip done event 5884 * correspond to the last vblank and have no relation to the actual time when 5885 * the flip done event was sent. 5886 */ 5887static int intel_async_flip_check_uapi(struct intel_atomic_state *state, 5888 struct intel_crtc *crtc) 5889{ 5890 struct drm_i915_private *i915 = to_i915(state->base.dev); 5891 const struct intel_crtc_state *new_crtc_state = 5892 intel_atomic_get_new_crtc_state(state, crtc); 5893 const struct intel_plane_state *old_plane_state; 5894 struct intel_plane_state *new_plane_state; 5895 struct intel_plane *plane; 5896 int i; 5897 5898 if (!new_crtc_state->uapi.async_flip) 5899 return 0; 5900 5901 if (!new_crtc_state->uapi.active) { 5902 drm_dbg_kms(&i915->drm, 5903 "[CRTC:%d:%s] not active\n", 5904 crtc->base.base.id, crtc->base.name); 5905 return -EINVAL; 5906 } 5907 5908 if (intel_crtc_needs_modeset(new_crtc_state)) { 5909 drm_dbg_kms(&i915->drm, 5910 "[CRTC:%d:%s] modeset required\n", 5911 crtc->base.base.id, crtc->base.name); 5912 return -EINVAL; 5913 } 5914 5915 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 5916 new_plane_state, i) { 5917 if (plane->pipe != crtc->pipe) 5918 continue; 5919 5920 /* 5921 * TODO: Async flip is only supported through the page flip IOCTL 5922 * as of now. So support currently added for primary plane only. 5923 * Support for other planes on platforms on which supports 5924 * this(vlv/chv and icl+) should be added when async flip is 5925 * enabled in the atomic IOCTL path. 5926 */ 5927 if (!plane->async_flip) { 5928 drm_dbg_kms(&i915->drm, 5929 "[PLANE:%d:%s] async flip not supported\n", 5930 plane->base.base.id, plane->base.name); 5931 return -EINVAL; 5932 } 5933 5934 if (!old_plane_state->uapi.fb || !new_plane_state->uapi.fb) { 5935 drm_dbg_kms(&i915->drm, 5936 "[PLANE:%d:%s] no old or new framebuffer\n", 5937 plane->base.base.id, plane->base.name); 5938 return -EINVAL; 5939 } 5940 } 5941 5942 return 0; 5943} 5944 5945static int intel_async_flip_check_hw(struct intel_atomic_state *state, struct intel_crtc *crtc) 5946{ 5947 struct drm_i915_private *i915 = to_i915(state->base.dev); 5948 const struct intel_crtc_state *old_crtc_state, *new_crtc_state; 5949 const struct intel_plane_state *new_plane_state, *old_plane_state; 5950 struct intel_plane *plane; 5951 int i; 5952 5953 old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); 5954 new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 5955 5956 if (!new_crtc_state->uapi.async_flip) 5957 return 0; 5958 5959 if (!new_crtc_state->hw.active) { 5960 drm_dbg_kms(&i915->drm, 5961 "[CRTC:%d:%s] not active\n", 5962 crtc->base.base.id, crtc->base.name); 5963 return -EINVAL; 5964 } 5965 5966 if (intel_crtc_needs_modeset(new_crtc_state)) { 5967 drm_dbg_kms(&i915->drm, 5968 "[CRTC:%d:%s] modeset required\n", 5969 crtc->base.base.id, crtc->base.name); 5970 return -EINVAL; 5971 } 5972 5973 if (old_crtc_state->active_planes != new_crtc_state->active_planes) { 5974 drm_dbg_kms(&i915->drm, 5975 "[CRTC:%d:%s] Active planes cannot be in async flip\n", 5976 crtc->base.base.id, crtc->base.name); 5977 return -EINVAL; 5978 } 5979 5980 /* 5981 * FIXME: Bigjoiner+async flip is busted currently. 5982 * Remove this check once the issues are fixed. 5983 */ 5984 if (new_crtc_state->bigjoiner_pipes) { 5985 drm_dbg_kms(&i915->drm, 5986 "[CRTC:%d:%s] async flip disallowed with bigjoiner\n", 5987 crtc->base.base.id, crtc->base.name); 5988 return -EINVAL; 5989 } 5990 5991 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 5992 new_plane_state, i) { 5993 if (plane->pipe != crtc->pipe) 5994 continue; 5995 5996 /* 5997 * Only async flip capable planes should be in the state 5998 * if we're really about to ask the hardware to perform 5999 * an async flip. We should never get this far otherwise. 6000 */ 6001 if (drm_WARN_ON(&i915->drm, 6002 new_crtc_state->do_async_flip && !plane->async_flip)) 6003 return -EINVAL; 6004 6005 /* 6006 * Only check async flip capable planes other planes 6007 * may be involved in the initial commit due to 6008 * the wm0/ddb optimization. 6009 * 6010 * TODO maybe should track which planes actually 6011 * were requested to do the async flip... 6012 */ 6013 if (!plane->async_flip) 6014 continue; 6015 6016 /* 6017 * FIXME: This check is kept generic for all platforms. 6018 * Need to verify this for all gen9 platforms to enable 6019 * this selectively if required. 6020 */ 6021 switch (new_plane_state->hw.fb->modifier) { 6022 case DRM_FORMAT_MOD_LINEAR: 6023 /* 6024 * FIXME: Async on Linear buffer is supported on ICL as 6025 * but with additional alignment and fbc restrictions 6026 * need to be taken care of. These aren't applicable for 6027 * gen12+. 6028 */ 6029 if (DISPLAY_VER(i915) < 12) { 6030 drm_dbg_kms(&i915->drm, 6031 "[PLANE:%d:%s] Modifier 0x%llx does not support async flip on display ver %d\n", 6032 plane->base.base.id, plane->base.name, 6033 new_plane_state->hw.fb->modifier, DISPLAY_VER(i915)); 6034 return -EINVAL; 6035 } 6036 break; 6037 6038 case I915_FORMAT_MOD_X_TILED: 6039 case I915_FORMAT_MOD_Y_TILED: 6040 case I915_FORMAT_MOD_Yf_TILED: 6041 case I915_FORMAT_MOD_4_TILED: 6042 break; 6043 default: 6044 drm_dbg_kms(&i915->drm, 6045 "[PLANE:%d:%s] Modifier 0x%llx does not support async flip\n", 6046 plane->base.base.id, plane->base.name, 6047 new_plane_state->hw.fb->modifier); 6048 return -EINVAL; 6049 } 6050 6051 if (new_plane_state->hw.fb->format->num_planes > 1) { 6052 drm_dbg_kms(&i915->drm, 6053 "[PLANE:%d:%s] Planar formats do not support async flips\n", 6054 plane->base.base.id, plane->base.name); 6055 return -EINVAL; 6056 } 6057 6058 if (old_plane_state->view.color_plane[0].mapping_stride != 6059 new_plane_state->view.color_plane[0].mapping_stride) { 6060 drm_dbg_kms(&i915->drm, 6061 "[PLANE:%d:%s] Stride cannot be changed in async flip\n", 6062 plane->base.base.id, plane->base.name); 6063 return -EINVAL; 6064 } 6065 6066 if (old_plane_state->hw.fb->modifier != 6067 new_plane_state->hw.fb->modifier) { 6068 drm_dbg_kms(&i915->drm, 6069 "[PLANE:%d:%s] Modifier cannot be changed in async flip\n", 6070 plane->base.base.id, plane->base.name); 6071 return -EINVAL; 6072 } 6073 6074 if (old_plane_state->hw.fb->format != 6075 new_plane_state->hw.fb->format) { 6076 drm_dbg_kms(&i915->drm, 6077 "[PLANE:%d:%s] Pixel format cannot be changed in async flip\n", 6078 plane->base.base.id, plane->base.name); 6079 return -EINVAL; 6080 } 6081 6082 if (old_plane_state->hw.rotation != 6083 new_plane_state->hw.rotation) { 6084 drm_dbg_kms(&i915->drm, 6085 "[PLANE:%d:%s] Rotation cannot be changed in async flip\n", 6086 plane->base.base.id, plane->base.name); 6087 return -EINVAL; 6088 } 6089 6090 if (!drm_rect_equals(&old_plane_state->uapi.src, &new_plane_state->uapi.src) || 6091 !drm_rect_equals(&old_plane_state->uapi.dst, &new_plane_state->uapi.dst)) { 6092 drm_dbg_kms(&i915->drm, 6093 "[PLANE:%d:%s] Size/co-ordinates cannot be changed in async flip\n", 6094 plane->base.base.id, plane->base.name); 6095 return -EINVAL; 6096 } 6097 6098 if (old_plane_state->hw.alpha != new_plane_state->hw.alpha) { 6099 drm_dbg_kms(&i915->drm, 6100 "[PLANES:%d:%s] Alpha value cannot be changed in async flip\n", 6101 plane->base.base.id, plane->base.name); 6102 return -EINVAL; 6103 } 6104 6105 if (old_plane_state->hw.pixel_blend_mode != 6106 new_plane_state->hw.pixel_blend_mode) { 6107 drm_dbg_kms(&i915->drm, 6108 "[PLANE:%d:%s] Pixel blend mode cannot be changed in async flip\n", 6109 plane->base.base.id, plane->base.name); 6110 return -EINVAL; 6111 } 6112 6113 if (old_plane_state->hw.color_encoding != new_plane_state->hw.color_encoding) { 6114 drm_dbg_kms(&i915->drm, 6115 "[PLANE:%d:%s] Color encoding cannot be changed in async flip\n", 6116 plane->base.base.id, plane->base.name); 6117 return -EINVAL; 6118 } 6119 6120 if (old_plane_state->hw.color_range != new_plane_state->hw.color_range) { 6121 drm_dbg_kms(&i915->drm, 6122 "[PLANE:%d:%s] Color range cannot be changed in async flip\n", 6123 plane->base.base.id, plane->base.name); 6124 return -EINVAL; 6125 } 6126 6127 /* plane decryption is allow to change only in synchronous flips */ 6128 if (old_plane_state->decrypt != new_plane_state->decrypt) { 6129 drm_dbg_kms(&i915->drm, 6130 "[PLANE:%d:%s] Decryption cannot be changed in async flip\n", 6131 plane->base.base.id, plane->base.name); 6132 return -EINVAL; 6133 } 6134 } 6135 6136 return 0; 6137} 6138 6139static int intel_bigjoiner_add_affected_crtcs(struct intel_atomic_state *state) 6140{ 6141 struct drm_i915_private *i915 = to_i915(state->base.dev); 6142 struct intel_crtc_state *crtc_state; 6143 struct intel_crtc *crtc; 6144 u8 affected_pipes = 0; 6145 u8 modeset_pipes = 0; 6146 int i; 6147 6148 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 6149 affected_pipes |= crtc_state->bigjoiner_pipes; 6150 if (intel_crtc_needs_modeset(crtc_state)) 6151 modeset_pipes |= crtc_state->bigjoiner_pipes; 6152 } 6153 6154 for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, affected_pipes) { 6155 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 6156 if (IS_ERR(crtc_state)) 6157 return PTR_ERR(crtc_state); 6158 } 6159 6160 for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, modeset_pipes) { 6161 int ret; 6162 6163 crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 6164 6165 crtc_state->uapi.mode_changed = true; 6166 6167 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base); 6168 if (ret) 6169 return ret; 6170 6171 ret = intel_atomic_add_affected_planes(state, crtc); 6172 if (ret) 6173 return ret; 6174 } 6175 6176 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 6177 /* Kill old bigjoiner link, we may re-establish afterwards */ 6178 if (intel_crtc_needs_modeset(crtc_state) && 6179 intel_crtc_is_bigjoiner_master(crtc_state)) 6180 kill_bigjoiner_slave(state, crtc); 6181 } 6182 6183 return 0; 6184} 6185 6186/** 6187 * intel_atomic_check - validate state object 6188 * @dev: drm device 6189 * @_state: state to validate 6190 */ 6191int intel_atomic_check(struct drm_device *dev, 6192 struct drm_atomic_state *_state) 6193{ 6194 struct drm_i915_private *dev_priv = to_i915(dev); 6195 struct intel_atomic_state *state = to_intel_atomic_state(_state); 6196 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 6197 struct intel_crtc *crtc; 6198 int ret, i; 6199 bool any_ms = false; 6200 6201 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6202 new_crtc_state, i) { 6203 /* 6204 * crtc's state no longer considered to be inherited 6205 * after the first userspace/client initiated commit. 6206 */ 6207 if (!state->internal) 6208 new_crtc_state->inherited = false; 6209 6210 if (new_crtc_state->inherited != old_crtc_state->inherited) 6211 new_crtc_state->uapi.mode_changed = true; 6212 6213 if (new_crtc_state->uapi.scaling_filter != 6214 old_crtc_state->uapi.scaling_filter) 6215 new_crtc_state->uapi.mode_changed = true; 6216 } 6217 6218 intel_vrr_check_modeset(state); 6219 6220 ret = drm_atomic_helper_check_modeset(dev, &state->base); 6221 if (ret) 6222 goto fail; 6223 6224 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6225 ret = intel_async_flip_check_uapi(state, crtc); 6226 if (ret) 6227 return ret; 6228 } 6229 6230 ret = intel_bigjoiner_add_affected_crtcs(state); 6231 if (ret) 6232 goto fail; 6233 6234 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6235 new_crtc_state, i) { 6236 if (!intel_crtc_needs_modeset(new_crtc_state)) { 6237 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) 6238 copy_bigjoiner_crtc_state_nomodeset(state, crtc); 6239 else 6240 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc); 6241 continue; 6242 } 6243 6244 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) { 6245 drm_WARN_ON(&dev_priv->drm, new_crtc_state->uapi.enable); 6246 continue; 6247 } 6248 6249 ret = intel_crtc_prepare_cleared_state(state, crtc); 6250 if (ret) 6251 goto fail; 6252 6253 if (!new_crtc_state->hw.enable) 6254 continue; 6255 6256 ret = intel_modeset_pipe_config(state, crtc); 6257 if (ret) 6258 goto fail; 6259 6260 ret = intel_atomic_check_bigjoiner(state, crtc); 6261 if (ret) 6262 goto fail; 6263 } 6264 6265 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6266 new_crtc_state, i) { 6267 if (!intel_crtc_needs_modeset(new_crtc_state)) 6268 continue; 6269 6270 if (new_crtc_state->hw.enable) { 6271 ret = intel_modeset_pipe_config_late(state, crtc); 6272 if (ret) 6273 goto fail; 6274 } 6275 6276 intel_crtc_check_fastset(old_crtc_state, new_crtc_state); 6277 } 6278 6279 /** 6280 * Check if fastset is allowed by external dependencies like other 6281 * pipes and transcoders. 6282 * 6283 * Right now it only forces a fullmodeset when the MST master 6284 * transcoder did not changed but the pipe of the master transcoder 6285 * needs a fullmodeset so all slaves also needs to do a fullmodeset or 6286 * in case of port synced crtcs, if one of the synced crtcs 6287 * needs a full modeset, all other synced crtcs should be 6288 * forced a full modeset. 6289 */ 6290 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6291 if (!new_crtc_state->hw.enable || intel_crtc_needs_modeset(new_crtc_state)) 6292 continue; 6293 6294 if (intel_dp_mst_is_slave_trans(new_crtc_state)) { 6295 enum transcoder master = new_crtc_state->mst_master_transcoder; 6296 6297 if (intel_cpu_transcoders_need_modeset(state, BIT(master))) { 6298 new_crtc_state->uapi.mode_changed = true; 6299 new_crtc_state->update_pipe = false; 6300 } 6301 } 6302 6303 if (is_trans_port_sync_mode(new_crtc_state)) { 6304 u8 trans = new_crtc_state->sync_mode_slaves_mask; 6305 6306 if (new_crtc_state->master_transcoder != INVALID_TRANSCODER) 6307 trans |= BIT(new_crtc_state->master_transcoder); 6308 6309 if (intel_cpu_transcoders_need_modeset(state, trans)) { 6310 new_crtc_state->uapi.mode_changed = true; 6311 new_crtc_state->update_pipe = false; 6312 } 6313 } 6314 6315 if (new_crtc_state->bigjoiner_pipes) { 6316 if (intel_pipes_need_modeset(state, new_crtc_state->bigjoiner_pipes)) { 6317 new_crtc_state->uapi.mode_changed = true; 6318 new_crtc_state->update_pipe = false; 6319 } 6320 } 6321 } 6322 6323 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6324 new_crtc_state, i) { 6325 if (!intel_crtc_needs_modeset(new_crtc_state)) 6326 continue; 6327 6328 any_ms = true; 6329 6330 intel_release_shared_dplls(state, crtc); 6331 } 6332 6333 if (any_ms && !check_digital_port_conflicts(state)) { 6334 drm_dbg_kms(&dev_priv->drm, 6335 "rejecting conflicting digital port configuration\n"); 6336 ret = -EINVAL; 6337 goto fail; 6338 } 6339 6340 ret = drm_dp_mst_atomic_check(&state->base); 6341 if (ret) 6342 goto fail; 6343 6344 ret = intel_atomic_check_planes(state); 6345 if (ret) 6346 goto fail; 6347 6348 ret = intel_compute_global_watermarks(state); 6349 if (ret) 6350 goto fail; 6351 6352 ret = intel_bw_atomic_check(state); 6353 if (ret) 6354 goto fail; 6355 6356 ret = intel_cdclk_atomic_check(state, &any_ms); 6357 if (ret) 6358 goto fail; 6359 6360 if (intel_any_crtc_needs_modeset(state)) 6361 any_ms = true; 6362 6363 if (any_ms) { 6364 ret = intel_modeset_checks(state); 6365 if (ret) 6366 goto fail; 6367 6368 ret = intel_modeset_calc_cdclk(state); 6369 if (ret) 6370 return ret; 6371 } 6372 6373 ret = intel_pmdemand_atomic_check(state); 6374 if (ret) 6375 goto fail; 6376 6377 ret = intel_atomic_check_crtcs(state); 6378 if (ret) 6379 goto fail; 6380 6381 ret = intel_fbc_atomic_check(state); 6382 if (ret) 6383 goto fail; 6384 6385 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6386 new_crtc_state, i) { 6387 intel_color_assert_luts(new_crtc_state); 6388 6389 ret = intel_async_flip_check_hw(state, crtc); 6390 if (ret) 6391 goto fail; 6392 6393 /* Either full modeset or fastset (or neither), never both */ 6394 drm_WARN_ON(&dev_priv->drm, 6395 intel_crtc_needs_modeset(new_crtc_state) && 6396 intel_crtc_needs_fastset(new_crtc_state)); 6397 6398 if (!intel_crtc_needs_modeset(new_crtc_state) && 6399 !intel_crtc_needs_fastset(new_crtc_state)) 6400 continue; 6401 6402 intel_crtc_state_dump(new_crtc_state, state, 6403 intel_crtc_needs_modeset(new_crtc_state) ? 6404 "modeset" : "fastset"); 6405 } 6406 6407 return 0; 6408 6409 fail: 6410 if (ret == -EDEADLK) 6411 return ret; 6412 6413 /* 6414 * FIXME would probably be nice to know which crtc specifically 6415 * caused the failure, in cases where we can pinpoint it. 6416 */ 6417 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6418 new_crtc_state, i) 6419 intel_crtc_state_dump(new_crtc_state, state, "failed"); 6420 6421 return ret; 6422} 6423 6424static int intel_atomic_prepare_commit(struct intel_atomic_state *state) 6425{ 6426 struct intel_crtc_state *crtc_state; 6427 struct intel_crtc *crtc; 6428 int i, ret; 6429 6430 ret = drm_atomic_helper_prepare_planes(state->base.dev, &state->base); 6431 if (ret < 0) 6432 return ret; 6433 6434 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 6435 if (intel_crtc_needs_color_update(crtc_state)) 6436 intel_color_prepare_commit(crtc_state); 6437 } 6438 6439 return 0; 6440} 6441 6442void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc, 6443 struct intel_crtc_state *crtc_state) 6444{ 6445 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 6446 6447 if (DISPLAY_VER(dev_priv) != 2 || crtc_state->active_planes) 6448 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); 6449 6450 if (crtc_state->has_pch_encoder) { 6451 enum pipe pch_transcoder = 6452 intel_crtc_pch_transcoder(crtc); 6453 6454 intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true); 6455 } 6456} 6457 6458static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state, 6459 const struct intel_crtc_state *new_crtc_state) 6460{ 6461 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 6462 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 6463 6464 /* 6465 * Update pipe size and adjust fitter if needed: the reason for this is 6466 * that in compute_mode_changes we check the native mode (not the pfit 6467 * mode) to see if we can flip rather than do a full mode set. In the 6468 * fastboot case, we'll flip, but if we don't update the pipesrc and 6469 * pfit state, we'll end up with a big fb scanned out into the wrong 6470 * sized surface. 6471 */ 6472 intel_set_pipe_src_size(new_crtc_state); 6473 6474 /* on skylake this is done by detaching scalers */ 6475 if (DISPLAY_VER(dev_priv) >= 9) { 6476 if (new_crtc_state->pch_pfit.enabled) 6477 skl_pfit_enable(new_crtc_state); 6478 } else if (HAS_PCH_SPLIT(dev_priv)) { 6479 if (new_crtc_state->pch_pfit.enabled) 6480 ilk_pfit_enable(new_crtc_state); 6481 else if (old_crtc_state->pch_pfit.enabled) 6482 ilk_pfit_disable(old_crtc_state); 6483 } 6484 6485 /* 6486 * The register is supposedly single buffered so perhaps 6487 * not 100% correct to do this here. But SKL+ calculate 6488 * this based on the adjust pixel rate so pfit changes do 6489 * affect it and so it must be updated for fastsets. 6490 * HSW/BDW only really need this here for fastboot, after 6491 * that the value should not change without a full modeset. 6492 */ 6493 if (DISPLAY_VER(dev_priv) >= 9 || 6494 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 6495 hsw_set_linetime_wm(new_crtc_state); 6496 6497 if (new_crtc_state->seamless_m_n) 6498 intel_cpu_transcoder_set_m1_n1(crtc, new_crtc_state->cpu_transcoder, 6499 &new_crtc_state->dp_m_n); 6500} 6501 6502static void commit_pipe_pre_planes(struct intel_atomic_state *state, 6503 struct intel_crtc *crtc) 6504{ 6505 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 6506 const struct intel_crtc_state *old_crtc_state = 6507 intel_atomic_get_old_crtc_state(state, crtc); 6508 const struct intel_crtc_state *new_crtc_state = 6509 intel_atomic_get_new_crtc_state(state, crtc); 6510 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 6511 6512 /* 6513 * During modesets pipe configuration was programmed as the 6514 * CRTC was enabled. 6515 */ 6516 if (!modeset) { 6517 if (intel_crtc_needs_color_update(new_crtc_state)) 6518 intel_color_commit_arm(new_crtc_state); 6519 6520 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) 6521 bdw_set_pipe_misc(new_crtc_state); 6522 6523 if (intel_crtc_needs_fastset(new_crtc_state)) 6524 intel_pipe_fastset(old_crtc_state, new_crtc_state); 6525 } 6526 6527 intel_psr2_program_trans_man_trk_ctl(new_crtc_state); 6528 6529 intel_atomic_update_watermarks(state, crtc); 6530} 6531 6532static void commit_pipe_post_planes(struct intel_atomic_state *state, 6533 struct intel_crtc *crtc) 6534{ 6535 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 6536 const struct intel_crtc_state *new_crtc_state = 6537 intel_atomic_get_new_crtc_state(state, crtc); 6538 6539 /* 6540 * Disable the scaler(s) after the plane(s) so that we don't 6541 * get a catastrophic underrun even if the two operations 6542 * end up happening in two different frames. 6543 */ 6544 if (DISPLAY_VER(dev_priv) >= 9 && 6545 !intel_crtc_needs_modeset(new_crtc_state)) 6546 skl_detach_scalers(new_crtc_state); 6547} 6548 6549static void intel_enable_crtc(struct intel_atomic_state *state, 6550 struct intel_crtc *crtc) 6551{ 6552 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 6553 const struct intel_crtc_state *new_crtc_state = 6554 intel_atomic_get_new_crtc_state(state, crtc); 6555 6556 if (!intel_crtc_needs_modeset(new_crtc_state)) 6557 return; 6558 6559 /* VRR will be enable later, if required */ 6560 intel_crtc_update_active_timings(new_crtc_state, false); 6561 6562 dev_priv->display.funcs.display->crtc_enable(state, crtc); 6563 6564 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) 6565 return; 6566 6567 /* vblanks work again, re-enable pipe CRC. */ 6568 intel_crtc_enable_pipe_crc(crtc); 6569} 6570 6571static void intel_update_crtc(struct intel_atomic_state *state, 6572 struct intel_crtc *crtc) 6573{ 6574 struct drm_i915_private *i915 = to_i915(state->base.dev); 6575 const struct intel_crtc_state *old_crtc_state = 6576 intel_atomic_get_old_crtc_state(state, crtc); 6577 struct intel_crtc_state *new_crtc_state = 6578 intel_atomic_get_new_crtc_state(state, crtc); 6579 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 6580 6581 if (old_crtc_state->inherited || 6582 intel_crtc_needs_modeset(new_crtc_state)) { 6583 if (HAS_DPT(i915)) 6584 intel_dpt_configure(crtc); 6585 } 6586 6587 if (vrr_enabling(old_crtc_state, new_crtc_state)) { 6588 intel_vrr_enable(new_crtc_state); 6589 intel_crtc_update_active_timings(new_crtc_state, 6590 new_crtc_state->vrr.enable); 6591 } 6592 6593 if (!modeset) { 6594 if (new_crtc_state->preload_luts && 6595 intel_crtc_needs_color_update(new_crtc_state)) 6596 intel_color_load_luts(new_crtc_state); 6597 6598 intel_pre_plane_update(state, crtc); 6599 6600 if (intel_crtc_needs_fastset(new_crtc_state)) 6601 intel_encoders_update_pipe(state, crtc); 6602 6603 if (DISPLAY_VER(i915) >= 11 && 6604 intel_crtc_needs_fastset(new_crtc_state)) 6605 icl_set_pipe_chicken(new_crtc_state); 6606 } 6607 6608 intel_fbc_update(state, crtc); 6609 6610 drm_WARN_ON(&i915->drm, !intel_display_power_is_enabled(i915, POWER_DOMAIN_DC_OFF)); 6611 6612 if (!modeset && 6613 intel_crtc_needs_color_update(new_crtc_state)) 6614 intel_color_commit_noarm(new_crtc_state); 6615 6616 intel_crtc_planes_update_noarm(state, crtc); 6617 6618 /* Perform vblank evasion around commit operation */ 6619 intel_pipe_update_start(new_crtc_state); 6620 6621 commit_pipe_pre_planes(state, crtc); 6622 6623 intel_crtc_planes_update_arm(state, crtc); 6624 6625 commit_pipe_post_planes(state, crtc); 6626 6627 intel_pipe_update_end(new_crtc_state); 6628 6629 /* 6630 * We usually enable FIFO underrun interrupts as part of the 6631 * CRTC enable sequence during modesets. But when we inherit a 6632 * valid pipe configuration from the BIOS we need to take care 6633 * of enabling them on the CRTC's first fastset. 6634 */ 6635 if (intel_crtc_needs_fastset(new_crtc_state) && !modeset && 6636 old_crtc_state->inherited) 6637 intel_crtc_arm_fifo_underrun(crtc, new_crtc_state); 6638} 6639 6640static void intel_old_crtc_state_disables(struct intel_atomic_state *state, 6641 struct intel_crtc_state *old_crtc_state, 6642 struct intel_crtc_state *new_crtc_state, 6643 struct intel_crtc *crtc) 6644{ 6645 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 6646 6647 /* 6648 * We need to disable pipe CRC before disabling the pipe, 6649 * or we race against vblank off. 6650 */ 6651 intel_crtc_disable_pipe_crc(crtc); 6652 6653 dev_priv->display.funcs.display->crtc_disable(state, crtc); 6654 crtc->active = false; 6655 intel_fbc_disable(crtc); 6656 6657 if (!new_crtc_state->hw.active) 6658 intel_initial_watermarks(state, crtc); 6659} 6660 6661static void intel_commit_modeset_disables(struct intel_atomic_state *state) 6662{ 6663 struct intel_crtc_state *new_crtc_state, *old_crtc_state; 6664 struct intel_crtc *crtc; 6665 u32 handled = 0; 6666 int i; 6667 6668 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6669 new_crtc_state, i) { 6670 if (!intel_crtc_needs_modeset(new_crtc_state)) 6671 continue; 6672 6673 intel_pre_plane_update(state, crtc); 6674 6675 if (!old_crtc_state->hw.active) 6676 continue; 6677 6678 intel_crtc_disable_planes(state, crtc); 6679 } 6680 6681 /* Only disable port sync and MST slaves */ 6682 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6683 new_crtc_state, i) { 6684 if (!intel_crtc_needs_modeset(new_crtc_state)) 6685 continue; 6686 6687 if (!old_crtc_state->hw.active) 6688 continue; 6689 6690 /* In case of Transcoder port Sync master slave CRTCs can be 6691 * assigned in any order and we need to make sure that 6692 * slave CRTCs are disabled first and then master CRTC since 6693 * Slave vblanks are masked till Master Vblanks. 6694 */ 6695 if (!is_trans_port_sync_slave(old_crtc_state) && 6696 !intel_dp_mst_is_slave_trans(old_crtc_state) && 6697 !intel_crtc_is_bigjoiner_slave(old_crtc_state)) 6698 continue; 6699 6700 intel_old_crtc_state_disables(state, old_crtc_state, 6701 new_crtc_state, crtc); 6702 handled |= BIT(crtc->pipe); 6703 } 6704 6705 /* Disable everything else left on */ 6706 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6707 new_crtc_state, i) { 6708 if (!intel_crtc_needs_modeset(new_crtc_state) || 6709 (handled & BIT(crtc->pipe))) 6710 continue; 6711 6712 if (!old_crtc_state->hw.active) 6713 continue; 6714 6715 intel_old_crtc_state_disables(state, old_crtc_state, 6716 new_crtc_state, crtc); 6717 } 6718} 6719 6720static void intel_commit_modeset_enables(struct intel_atomic_state *state) 6721{ 6722 struct intel_crtc_state *new_crtc_state; 6723 struct intel_crtc *crtc; 6724 int i; 6725 6726 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6727 if (!new_crtc_state->hw.active) 6728 continue; 6729 6730 intel_enable_crtc(state, crtc); 6731 intel_update_crtc(state, crtc); 6732 } 6733} 6734 6735static void skl_commit_modeset_enables(struct intel_atomic_state *state) 6736{ 6737 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 6738 struct intel_crtc *crtc; 6739 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 6740 struct skl_ddb_entry entries[I915_MAX_PIPES] = {}; 6741 u8 update_pipes = 0, modeset_pipes = 0; 6742 int i; 6743 6744 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 6745 enum pipe pipe = crtc->pipe; 6746 6747 if (!new_crtc_state->hw.active) 6748 continue; 6749 6750 /* ignore allocations for crtc's that have been turned off. */ 6751 if (!intel_crtc_needs_modeset(new_crtc_state)) { 6752 entries[pipe] = old_crtc_state->wm.skl.ddb; 6753 update_pipes |= BIT(pipe); 6754 } else { 6755 modeset_pipes |= BIT(pipe); 6756 } 6757 } 6758 6759 /* 6760 * Whenever the number of active pipes changes, we need to make sure we 6761 * update the pipes in the right order so that their ddb allocations 6762 * never overlap with each other between CRTC updates. Otherwise we'll 6763 * cause pipe underruns and other bad stuff. 6764 * 6765 * So first lets enable all pipes that do not need a fullmodeset as 6766 * those don't have any external dependency. 6767 */ 6768 while (update_pipes) { 6769 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6770 new_crtc_state, i) { 6771 enum pipe pipe = crtc->pipe; 6772 6773 if ((update_pipes & BIT(pipe)) == 0) 6774 continue; 6775 6776 if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, 6777 entries, I915_MAX_PIPES, pipe)) 6778 continue; 6779 6780 entries[pipe] = new_crtc_state->wm.skl.ddb; 6781 update_pipes &= ~BIT(pipe); 6782 6783 intel_update_crtc(state, crtc); 6784 6785 /* 6786 * If this is an already active pipe, it's DDB changed, 6787 * and this isn't the last pipe that needs updating 6788 * then we need to wait for a vblank to pass for the 6789 * new ddb allocation to take effect. 6790 */ 6791 if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb, 6792 &old_crtc_state->wm.skl.ddb) && 6793 (update_pipes | modeset_pipes)) 6794 intel_crtc_wait_for_next_vblank(crtc); 6795 } 6796 } 6797 6798 update_pipes = modeset_pipes; 6799 6800 /* 6801 * Enable all pipes that needs a modeset and do not depends on other 6802 * pipes 6803 */ 6804 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6805 enum pipe pipe = crtc->pipe; 6806 6807 if ((modeset_pipes & BIT(pipe)) == 0) 6808 continue; 6809 6810 if (intel_dp_mst_is_slave_trans(new_crtc_state) || 6811 is_trans_port_sync_master(new_crtc_state) || 6812 intel_crtc_is_bigjoiner_master(new_crtc_state)) 6813 continue; 6814 6815 modeset_pipes &= ~BIT(pipe); 6816 6817 intel_enable_crtc(state, crtc); 6818 } 6819 6820 /* 6821 * Then we enable all remaining pipes that depend on other 6822 * pipes: MST slaves and port sync masters, big joiner master 6823 */ 6824 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6825 enum pipe pipe = crtc->pipe; 6826 6827 if ((modeset_pipes & BIT(pipe)) == 0) 6828 continue; 6829 6830 modeset_pipes &= ~BIT(pipe); 6831 6832 intel_enable_crtc(state, crtc); 6833 } 6834 6835 /* 6836 * Finally we do the plane updates/etc. for all pipes that got enabled. 6837 */ 6838 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6839 enum pipe pipe = crtc->pipe; 6840 6841 if ((update_pipes & BIT(pipe)) == 0) 6842 continue; 6843 6844 drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, 6845 entries, I915_MAX_PIPES, pipe)); 6846 6847 entries[pipe] = new_crtc_state->wm.skl.ddb; 6848 update_pipes &= ~BIT(pipe); 6849 6850 intel_update_crtc(state, crtc); 6851 } 6852 6853 drm_WARN_ON(&dev_priv->drm, modeset_pipes); 6854 drm_WARN_ON(&dev_priv->drm, update_pipes); 6855} 6856 6857static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv) 6858{ 6859 struct intel_atomic_state *state, *next; 6860 struct llist_node *freed; 6861 6862 freed = llist_del_all(&dev_priv->display.atomic_helper.free_list); 6863 llist_for_each_entry_safe(state, next, freed, freed) 6864 drm_atomic_state_put(&state->base); 6865} 6866 6867void intel_atomic_helper_free_state_worker(struct work_struct *work) 6868{ 6869 struct drm_i915_private *dev_priv = 6870 container_of(work, typeof(*dev_priv), display.atomic_helper.free_work); 6871 6872 intel_atomic_helper_free_state(dev_priv); 6873} 6874 6875static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state) 6876{ 6877 struct wait_queue_entry wait_fence, wait_reset; 6878 struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev); 6879 6880 init_wait_entry(&wait_fence, 0); 6881 init_wait_entry(&wait_reset, 0); 6882 for (;;) { 6883 prepare_to_wait(&intel_state->commit_ready.wait, 6884 &wait_fence, TASK_UNINTERRUPTIBLE); 6885 prepare_to_wait(bit_waitqueue(&to_gt(dev_priv)->reset.flags, 6886 I915_RESET_MODESET), 6887 &wait_reset, TASK_UNINTERRUPTIBLE); 6888 6889 6890 if (i915_sw_fence_done(&intel_state->commit_ready) || 6891 test_bit(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags)) 6892 break; 6893 6894 schedule(); 6895 } 6896 finish_wait(&intel_state->commit_ready.wait, &wait_fence); 6897 finish_wait(bit_waitqueue(&to_gt(dev_priv)->reset.flags, 6898 I915_RESET_MODESET), 6899 &wait_reset); 6900} 6901 6902static void intel_atomic_cleanup_work(struct work_struct *work) 6903{ 6904 struct intel_atomic_state *state = 6905 container_of(work, struct intel_atomic_state, base.commit_work); 6906 struct drm_i915_private *i915 = to_i915(state->base.dev); 6907 struct intel_crtc_state *old_crtc_state; 6908 struct intel_crtc *crtc; 6909 int i; 6910 6911 for_each_old_intel_crtc_in_state(state, crtc, old_crtc_state, i) 6912 intel_color_cleanup_commit(old_crtc_state); 6913 6914 drm_atomic_helper_cleanup_planes(&i915->drm, &state->base); 6915 drm_atomic_helper_commit_cleanup_done(&state->base); 6916 drm_atomic_state_put(&state->base); 6917 6918 intel_atomic_helper_free_state(i915); 6919} 6920 6921static void intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *state) 6922{ 6923 struct drm_i915_private *i915 = to_i915(state->base.dev); 6924 struct intel_plane *plane; 6925 struct intel_plane_state *plane_state; 6926 int i; 6927 6928 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 6929 struct drm_framebuffer *fb = plane_state->hw.fb; 6930 int cc_plane; 6931 int ret; 6932 6933 if (!fb) 6934 continue; 6935 6936 cc_plane = intel_fb_rc_ccs_cc_plane(fb); 6937 if (cc_plane < 0) 6938 continue; 6939 6940 /* 6941 * The layout of the fast clear color value expected by HW 6942 * (the DRM ABI requiring this value to be located in fb at 6943 * offset 0 of cc plane, plane #2 previous generations or 6944 * plane #1 for flat ccs): 6945 * - 4 x 4 bytes per-channel value 6946 * (in surface type specific float/int format provided by the fb user) 6947 * - 8 bytes native color value used by the display 6948 * (converted/written by GPU during a fast clear operation using the 6949 * above per-channel values) 6950 * 6951 * The commit's FB prepare hook already ensured that FB obj is pinned and the 6952 * caller made sure that the object is synced wrt. the related color clear value 6953 * GPU write on it. 6954 */ 6955 ret = i915_gem_object_read_from_page(intel_fb_obj(fb), 6956 fb->offsets[cc_plane] + 16, 6957 &plane_state->ccval, 6958 sizeof(plane_state->ccval)); 6959 /* The above could only fail if the FB obj has an unexpected backing store type. */ 6960 drm_WARN_ON(&i915->drm, ret); 6961 } 6962} 6963 6964static void intel_atomic_commit_tail(struct intel_atomic_state *state) 6965{ 6966 struct drm_device *dev = state->base.dev; 6967 struct drm_i915_private *dev_priv = to_i915(dev); 6968 struct intel_crtc_state *new_crtc_state, *old_crtc_state; 6969 struct intel_crtc *crtc; 6970 struct intel_power_domain_mask put_domains[I915_MAX_PIPES] = {}; 6971 intel_wakeref_t wakeref = 0; 6972 int i; 6973 6974 intel_atomic_commit_fence_wait(state); 6975 6976 drm_atomic_helper_wait_for_dependencies(&state->base); 6977 drm_dp_mst_atomic_wait_for_dependencies(&state->base); 6978 6979 /* 6980 * During full modesets we write a lot of registers, wait 6981 * for PLLs, etc. Doing that while DC states are enabled 6982 * is not a good idea. 6983 * 6984 * During fastsets and other updates we also need to 6985 * disable DC states due to the following scenario: 6986 * 1. DC5 exit and PSR exit happen 6987 * 2. Some or all _noarm() registers are written 6988 * 3. Due to some long delay PSR is re-entered 6989 * 4. DC5 entry -> DMC saves the already written new 6990 * _noarm() registers and the old not yet written 6991 * _arm() registers 6992 * 5. DC5 exit -> DMC restores a mixture of old and 6993 * new register values and arms the update 6994 * 6. PSR exit -> hardware latches a mixture of old and 6995 * new register values -> corrupted frame, or worse 6996 * 7. New _arm() registers are finally written 6997 * 8. Hardware finally latches a complete set of new 6998 * register values, and subsequent frames will be OK again 6999 * 7000 * Also note that due to the pipe CSC hardware issues on 7001 * SKL/GLK DC states must remain off until the pipe CSC 7002 * state readout has happened. Otherwise we risk corrupting 7003 * the CSC latched register values with the readout (see 7004 * skl_read_csc() and skl_color_commit_noarm()). 7005 */ 7006 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DC_OFF); 7007 7008 intel_atomic_prepare_plane_clear_colors(state); 7009 7010 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7011 new_crtc_state, i) { 7012 if (intel_crtc_needs_modeset(new_crtc_state) || 7013 intel_crtc_needs_fastset(new_crtc_state)) 7014 intel_modeset_get_crtc_power_domains(new_crtc_state, &put_domains[crtc->pipe]); 7015 } 7016 7017 intel_commit_modeset_disables(state); 7018 7019 /* FIXME: Eventually get rid of our crtc->config pointer */ 7020 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) 7021 crtc->config = new_crtc_state; 7022 7023 /* 7024 * In XE_LPD+ Pmdemand combines many parameters such as voltage index, 7025 * plls, cdclk frequency, QGV point selection parameter etc. Voltage 7026 * index, cdclk/ddiclk frequencies are supposed to be configured before 7027 * the cdclk config is set. 7028 */ 7029 intel_pmdemand_pre_plane_update(state); 7030 7031 if (state->modeset) { 7032 drm_atomic_helper_update_legacy_modeset_state(dev, &state->base); 7033 7034 intel_set_cdclk_pre_plane_update(state); 7035 7036 intel_modeset_verify_disabled(dev_priv, state); 7037 } 7038 7039 intel_sagv_pre_plane_update(state); 7040 7041 /* Complete the events for pipes that have now been disabled */ 7042 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7043 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 7044 7045 /* Complete events for now disable pipes here. */ 7046 if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) { 7047 spin_lock_irq(&dev->event_lock); 7048 drm_crtc_send_vblank_event(&crtc->base, 7049 new_crtc_state->uapi.event); 7050 spin_unlock_irq(&dev->event_lock); 7051 7052 new_crtc_state->uapi.event = NULL; 7053 } 7054 } 7055 7056 intel_encoders_update_prepare(state); 7057 7058 intel_dbuf_pre_plane_update(state); 7059 intel_mbus_dbox_update(state); 7060 7061 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7062 if (new_crtc_state->do_async_flip) 7063 intel_crtc_enable_flip_done(state, crtc); 7064 } 7065 7066 /* Now enable the clocks, plane, pipe, and connectors that we set up. */ 7067 dev_priv->display.funcs.display->commit_modeset_enables(state); 7068 7069 if (state->modeset) 7070 intel_set_cdclk_post_plane_update(state); 7071 7072 intel_wait_for_vblank_workers(state); 7073 7074 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here 7075 * already, but still need the state for the delayed optimization. To 7076 * fix this: 7077 * - wrap the optimization/post_plane_update stuff into a per-crtc work. 7078 * - schedule that vblank worker _before_ calling hw_done 7079 * - at the start of commit_tail, cancel it _synchrously 7080 * - switch over to the vblank wait helper in the core after that since 7081 * we don't need out special handling any more. 7082 */ 7083 drm_atomic_helper_wait_for_flip_done(dev, &state->base); 7084 7085 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7086 if (new_crtc_state->do_async_flip) 7087 intel_crtc_disable_flip_done(state, crtc); 7088 } 7089 7090 /* 7091 * Now that the vblank has passed, we can go ahead and program the 7092 * optimal watermarks on platforms that need two-step watermark 7093 * programming. 7094 * 7095 * TODO: Move this (and other cleanup) to an async worker eventually. 7096 */ 7097 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7098 new_crtc_state, i) { 7099 /* 7100 * Gen2 reports pipe underruns whenever all planes are disabled. 7101 * So re-enable underrun reporting after some planes get enabled. 7102 * 7103 * We do this before .optimize_watermarks() so that we have a 7104 * chance of catching underruns with the intermediate watermarks 7105 * vs. the new plane configuration. 7106 */ 7107 if (DISPLAY_VER(dev_priv) == 2 && planes_enabling(old_crtc_state, new_crtc_state)) 7108 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); 7109 7110 intel_optimize_watermarks(state, crtc); 7111 } 7112 7113 intel_dbuf_post_plane_update(state); 7114 intel_psr_post_plane_update(state); 7115 7116 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 7117 intel_post_plane_update(state, crtc); 7118 7119 intel_modeset_put_crtc_power_domains(crtc, &put_domains[crtc->pipe]); 7120 7121 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state); 7122 7123 /* Must be done after gamma readout due to HSW split gamma vs. IPS w/a */ 7124 hsw_ips_post_update(state, crtc); 7125 7126 /* 7127 * Activate DRRS after state readout to avoid 7128 * dp_m_n vs. dp_m2_n2 confusion on BDW+. 7129 */ 7130 intel_drrs_activate(new_crtc_state); 7131 7132 /* 7133 * DSB cleanup is done in cleanup_work aligning with framebuffer 7134 * cleanup. So copy and reset the dsb structure to sync with 7135 * commit_done and later do dsb cleanup in cleanup_work. 7136 * 7137 * FIXME get rid of this funny new->old swapping 7138 */ 7139 old_crtc_state->dsb = fetch_and_zero(&new_crtc_state->dsb); 7140 } 7141 7142 /* Underruns don't always raise interrupts, so check manually */ 7143 intel_check_cpu_fifo_underruns(dev_priv); 7144 intel_check_pch_fifo_underruns(dev_priv); 7145 7146 if (state->modeset) 7147 intel_verify_planes(state); 7148 7149 intel_sagv_post_plane_update(state); 7150 intel_pmdemand_post_plane_update(state); 7151 7152 drm_atomic_helper_commit_hw_done(&state->base); 7153 7154 if (state->modeset) { 7155 /* As one of the primary mmio accessors, KMS has a high 7156 * likelihood of triggering bugs in unclaimed access. After we 7157 * finish modesetting, see if an error has been flagged, and if 7158 * so enable debugging for the next modeset - and hope we catch 7159 * the culprit. 7160 */ 7161 intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore); 7162 } 7163 /* 7164 * Delay re-enabling DC states by 17 ms to avoid the off->on->off 7165 * toggling overhead at and above 60 FPS. 7166 */ 7167 intel_display_power_put_async_delay(dev_priv, POWER_DOMAIN_DC_OFF, wakeref, 17); 7168 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); 7169 7170 /* 7171 * Defer the cleanup of the old state to a separate worker to not 7172 * impede the current task (userspace for blocking modesets) that 7173 * are executed inline. For out-of-line asynchronous modesets/flips, 7174 * deferring to a new worker seems overkill, but we would place a 7175 * schedule point (cond_resched()) here anyway to keep latencies 7176 * down. 7177 */ 7178 INIT_WORK(&state->base.commit_work, intel_atomic_cleanup_work); 7179 queue_work(system_highpri_wq, &state->base.commit_work); 7180} 7181 7182static void intel_atomic_commit_work(struct work_struct *work) 7183{ 7184 struct intel_atomic_state *state = 7185 container_of(work, struct intel_atomic_state, base.commit_work); 7186 7187 intel_atomic_commit_tail(state); 7188} 7189 7190static int 7191intel_atomic_commit_ready(struct i915_sw_fence *fence, 7192 enum i915_sw_fence_notify notify) 7193{ 7194 struct intel_atomic_state *state = 7195 container_of(fence, struct intel_atomic_state, commit_ready); 7196 7197 switch (notify) { 7198 case FENCE_COMPLETE: 7199 /* we do blocking waits in the worker, nothing to do here */ 7200 break; 7201 case FENCE_FREE: 7202 { 7203 struct drm_i915_private *i915 = to_i915(state->base.dev); 7204 struct intel_atomic_helper *helper = 7205 &i915->display.atomic_helper; 7206 7207 if (llist_add(&state->freed, &helper->free_list)) 7208 queue_work(i915->unordered_wq, &helper->free_work); 7209 break; 7210 } 7211 } 7212 7213 return NOTIFY_DONE; 7214} 7215 7216static void intel_atomic_track_fbs(struct intel_atomic_state *state) 7217{ 7218 struct intel_plane_state *old_plane_state, *new_plane_state; 7219 struct intel_plane *plane; 7220 int i; 7221 7222 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 7223 new_plane_state, i) 7224 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb), 7225 to_intel_frontbuffer(new_plane_state->hw.fb), 7226 plane->frontbuffer_bit); 7227} 7228 7229int intel_atomic_commit(struct drm_device *dev, struct drm_atomic_state *_state, 7230 bool nonblock) 7231{ 7232 struct intel_atomic_state *state = to_intel_atomic_state(_state); 7233 struct drm_i915_private *dev_priv = to_i915(dev); 7234 int ret = 0; 7235 7236 state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); 7237 7238 drm_atomic_state_get(&state->base); 7239 i915_sw_fence_init(&state->commit_ready, 7240 intel_atomic_commit_ready); 7241 7242 /* 7243 * The intel_legacy_cursor_update() fast path takes care 7244 * of avoiding the vblank waits for simple cursor 7245 * movement and flips. For cursor on/off and size changes, 7246 * we want to perform the vblank waits so that watermark 7247 * updates happen during the correct frames. Gen9+ have 7248 * double buffered watermarks and so shouldn't need this. 7249 * 7250 * Unset state->legacy_cursor_update before the call to 7251 * drm_atomic_helper_setup_commit() because otherwise 7252 * drm_atomic_helper_wait_for_flip_done() is a noop and 7253 * we get FIFO underruns because we didn't wait 7254 * for vblank. 7255 * 7256 * FIXME doing watermarks and fb cleanup from a vblank worker 7257 * (assuming we had any) would solve these problems. 7258 */ 7259 if (DISPLAY_VER(dev_priv) < 9 && state->base.legacy_cursor_update) { 7260 struct intel_crtc_state *new_crtc_state; 7261 struct intel_crtc *crtc; 7262 int i; 7263 7264 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) 7265 if (new_crtc_state->wm.need_postvbl_update || 7266 new_crtc_state->update_wm_post) 7267 state->base.legacy_cursor_update = false; 7268 } 7269 7270 ret = intel_atomic_prepare_commit(state); 7271 if (ret) { 7272 drm_dbg_atomic(&dev_priv->drm, 7273 "Preparing state failed with %i\n", ret); 7274 i915_sw_fence_commit(&state->commit_ready); 7275 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); 7276 return ret; 7277 } 7278 7279 ret = drm_atomic_helper_setup_commit(&state->base, nonblock); 7280 if (!ret) 7281 ret = drm_atomic_helper_swap_state(&state->base, true); 7282 if (!ret) 7283 intel_atomic_swap_global_state(state); 7284 7285 if (ret) { 7286 struct intel_crtc_state *new_crtc_state; 7287 struct intel_crtc *crtc; 7288 int i; 7289 7290 i915_sw_fence_commit(&state->commit_ready); 7291 7292 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) 7293 intel_color_cleanup_commit(new_crtc_state); 7294 7295 drm_atomic_helper_unprepare_planes(dev, &state->base); 7296 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); 7297 return ret; 7298 } 7299 intel_shared_dpll_swap_state(state); 7300 intel_atomic_track_fbs(state); 7301 7302 drm_atomic_state_get(&state->base); 7303 INIT_WORK(&state->base.commit_work, intel_atomic_commit_work); 7304 7305 i915_sw_fence_commit(&state->commit_ready); 7306 if (nonblock && state->modeset) { 7307 queue_work(dev_priv->display.wq.modeset, &state->base.commit_work); 7308 } else if (nonblock) { 7309 queue_work(dev_priv->display.wq.flip, &state->base.commit_work); 7310 } else { 7311 if (state->modeset) 7312 flush_workqueue(dev_priv->display.wq.modeset); 7313 intel_atomic_commit_tail(state); 7314 } 7315 7316 return 0; 7317} 7318 7319/** 7320 * intel_plane_destroy - destroy a plane 7321 * @plane: plane to destroy 7322 * 7323 * Common destruction function for all types of planes (primary, cursor, 7324 * sprite). 7325 */ 7326void intel_plane_destroy(struct drm_plane *plane) 7327{ 7328 drm_plane_cleanup(plane); 7329 kfree(to_intel_plane(plane)); 7330} 7331 7332int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data, 7333 struct drm_file *file) 7334{ 7335 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; 7336 struct drm_crtc *drmmode_crtc; 7337 struct intel_crtc *crtc; 7338 7339 drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id); 7340 if (!drmmode_crtc) 7341 return -ENOENT; 7342 7343 crtc = to_intel_crtc(drmmode_crtc); 7344 pipe_from_crtc_id->pipe = crtc->pipe; 7345 7346 return 0; 7347} 7348 7349static u32 intel_encoder_possible_clones(struct intel_encoder *encoder) 7350{ 7351 struct drm_device *dev = encoder->base.dev; 7352 struct intel_encoder *source_encoder; 7353 u32 possible_clones = 0; 7354 7355 for_each_intel_encoder(dev, source_encoder) { 7356 if (encoders_cloneable(encoder, source_encoder)) 7357 possible_clones |= drm_encoder_mask(&source_encoder->base); 7358 } 7359 7360 return possible_clones; 7361} 7362 7363static u32 intel_encoder_possible_crtcs(struct intel_encoder *encoder) 7364{ 7365 struct drm_device *dev = encoder->base.dev; 7366 struct intel_crtc *crtc; 7367 u32 possible_crtcs = 0; 7368 7369 for_each_intel_crtc_in_pipe_mask(dev, crtc, encoder->pipe_mask) 7370 possible_crtcs |= drm_crtc_mask(&crtc->base); 7371 7372 return possible_crtcs; 7373} 7374 7375static bool ilk_has_edp_a(struct drm_i915_private *dev_priv) 7376{ 7377 if (!IS_MOBILE(dev_priv)) 7378 return false; 7379 7380 if ((intel_de_read(dev_priv, DP_A) & DP_DETECTED) == 0) 7381 return false; 7382 7383 if (IS_IRONLAKE(dev_priv) && (intel_de_read(dev_priv, FUSE_STRAP) & ILK_eDP_A_DISABLE)) 7384 return false; 7385 7386 return true; 7387} 7388 7389static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv) 7390{ 7391 if (DISPLAY_VER(dev_priv) >= 9) 7392 return false; 7393 7394 if (IS_HASWELL_ULT(dev_priv) || IS_BROADWELL_ULT(dev_priv)) 7395 return false; 7396 7397 if (HAS_PCH_LPT_H(dev_priv) && 7398 intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) 7399 return false; 7400 7401 /* DDI E can't be used if DDI A requires 4 lanes */ 7402 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) 7403 return false; 7404 7405 if (!dev_priv->display.vbt.int_crt_support) 7406 return false; 7407 7408 return true; 7409} 7410 7411bool assert_port_valid(struct drm_i915_private *i915, enum port port) 7412{ 7413 return !drm_WARN(&i915->drm, !(DISPLAY_RUNTIME_INFO(i915)->port_mask & BIT(port)), 7414 "Platform does not support port %c\n", port_name(port)); 7415} 7416 7417void intel_setup_outputs(struct drm_i915_private *dev_priv) 7418{ 7419 struct intel_encoder *encoder; 7420 bool dpd_is_edp = false; 7421 7422 intel_pps_unlock_regs_wa(dev_priv); 7423 7424 if (!HAS_DISPLAY(dev_priv)) 7425 return; 7426 7427 if (HAS_DDI(dev_priv)) { 7428 if (intel_ddi_crt_present(dev_priv)) 7429 intel_crt_init(dev_priv); 7430 7431 intel_bios_for_each_encoder(dev_priv, intel_ddi_init); 7432 7433 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 7434 vlv_dsi_init(dev_priv); 7435 } else if (HAS_PCH_SPLIT(dev_priv)) { 7436 int found; 7437 7438 /* 7439 * intel_edp_init_connector() depends on this completing first, 7440 * to prevent the registration of both eDP and LVDS and the 7441 * incorrect sharing of the PPS. 7442 */ 7443 intel_lvds_init(dev_priv); 7444 intel_crt_init(dev_priv); 7445 7446 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D); 7447 7448 if (ilk_has_edp_a(dev_priv)) 7449 g4x_dp_init(dev_priv, DP_A, PORT_A); 7450 7451 if (intel_de_read(dev_priv, PCH_HDMIB) & SDVO_DETECTED) { 7452 /* PCH SDVOB multiplex with HDMIB */ 7453 found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B); 7454 if (!found) 7455 g4x_hdmi_init(dev_priv, PCH_HDMIB, PORT_B); 7456 if (!found && (intel_de_read(dev_priv, PCH_DP_B) & DP_DETECTED)) 7457 g4x_dp_init(dev_priv, PCH_DP_B, PORT_B); 7458 } 7459 7460 if (intel_de_read(dev_priv, PCH_HDMIC) & SDVO_DETECTED) 7461 g4x_hdmi_init(dev_priv, PCH_HDMIC, PORT_C); 7462 7463 if (!dpd_is_edp && intel_de_read(dev_priv, PCH_HDMID) & SDVO_DETECTED) 7464 g4x_hdmi_init(dev_priv, PCH_HDMID, PORT_D); 7465 7466 if (intel_de_read(dev_priv, PCH_DP_C) & DP_DETECTED) 7467 g4x_dp_init(dev_priv, PCH_DP_C, PORT_C); 7468 7469 if (intel_de_read(dev_priv, PCH_DP_D) & DP_DETECTED) 7470 g4x_dp_init(dev_priv, PCH_DP_D, PORT_D); 7471 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 7472 bool has_edp, has_port; 7473 7474 if (IS_VALLEYVIEW(dev_priv) && dev_priv->display.vbt.int_crt_support) 7475 intel_crt_init(dev_priv); 7476 7477 /* 7478 * The DP_DETECTED bit is the latched state of the DDC 7479 * SDA pin at boot. However since eDP doesn't require DDC 7480 * (no way to plug in a DP->HDMI dongle) the DDC pins for 7481 * eDP ports may have been muxed to an alternate function. 7482 * Thus we can't rely on the DP_DETECTED bit alone to detect 7483 * eDP ports. Consult the VBT as well as DP_DETECTED to 7484 * detect eDP ports. 7485 * 7486 * Sadly the straps seem to be missing sometimes even for HDMI 7487 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap 7488 * and VBT for the presence of the port. Additionally we can't 7489 * trust the port type the VBT declares as we've seen at least 7490 * HDMI ports that the VBT claim are DP or eDP. 7491 */ 7492 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B); 7493 has_port = intel_bios_is_port_present(dev_priv, PORT_B); 7494 if (intel_de_read(dev_priv, VLV_DP_B) & DP_DETECTED || has_port) 7495 has_edp &= g4x_dp_init(dev_priv, VLV_DP_B, PORT_B); 7496 if ((intel_de_read(dev_priv, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp) 7497 g4x_hdmi_init(dev_priv, VLV_HDMIB, PORT_B); 7498 7499 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C); 7500 has_port = intel_bios_is_port_present(dev_priv, PORT_C); 7501 if (intel_de_read(dev_priv, VLV_DP_C) & DP_DETECTED || has_port) 7502 has_edp &= g4x_dp_init(dev_priv, VLV_DP_C, PORT_C); 7503 if ((intel_de_read(dev_priv, VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp) 7504 g4x_hdmi_init(dev_priv, VLV_HDMIC, PORT_C); 7505 7506 if (IS_CHERRYVIEW(dev_priv)) { 7507 /* 7508 * eDP not supported on port D, 7509 * so no need to worry about it 7510 */ 7511 has_port = intel_bios_is_port_present(dev_priv, PORT_D); 7512 if (intel_de_read(dev_priv, CHV_DP_D) & DP_DETECTED || has_port) 7513 g4x_dp_init(dev_priv, CHV_DP_D, PORT_D); 7514 if (intel_de_read(dev_priv, CHV_HDMID) & SDVO_DETECTED || has_port) 7515 g4x_hdmi_init(dev_priv, CHV_HDMID, PORT_D); 7516 } 7517 7518 vlv_dsi_init(dev_priv); 7519 } else if (IS_PINEVIEW(dev_priv)) { 7520 intel_lvds_init(dev_priv); 7521 intel_crt_init(dev_priv); 7522 } else if (IS_DISPLAY_VER(dev_priv, 3, 4)) { 7523 bool found = false; 7524 7525 if (IS_MOBILE(dev_priv)) 7526 intel_lvds_init(dev_priv); 7527 7528 intel_crt_init(dev_priv); 7529 7530 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) { 7531 drm_dbg_kms(&dev_priv->drm, "probing SDVOB\n"); 7532 found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B); 7533 if (!found && IS_G4X(dev_priv)) { 7534 drm_dbg_kms(&dev_priv->drm, 7535 "probing HDMI on SDVOB\n"); 7536 g4x_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B); 7537 } 7538 7539 if (!found && IS_G4X(dev_priv)) 7540 g4x_dp_init(dev_priv, DP_B, PORT_B); 7541 } 7542 7543 /* Before G4X SDVOC doesn't have its own detect register */ 7544 7545 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) { 7546 drm_dbg_kms(&dev_priv->drm, "probing SDVOC\n"); 7547 found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C); 7548 } 7549 7550 if (!found && (intel_de_read(dev_priv, GEN3_SDVOC) & SDVO_DETECTED)) { 7551 7552 if (IS_G4X(dev_priv)) { 7553 drm_dbg_kms(&dev_priv->drm, 7554 "probing HDMI on SDVOC\n"); 7555 g4x_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C); 7556 } 7557 if (IS_G4X(dev_priv)) 7558 g4x_dp_init(dev_priv, DP_C, PORT_C); 7559 } 7560 7561 if (IS_G4X(dev_priv) && (intel_de_read(dev_priv, DP_D) & DP_DETECTED)) 7562 g4x_dp_init(dev_priv, DP_D, PORT_D); 7563 7564 if (SUPPORTS_TV(dev_priv)) 7565 intel_tv_init(dev_priv); 7566 } else if (DISPLAY_VER(dev_priv) == 2) { 7567 if (IS_I85X(dev_priv)) 7568 intel_lvds_init(dev_priv); 7569 7570 intel_crt_init(dev_priv); 7571 intel_dvo_init(dev_priv); 7572 } 7573 7574 for_each_intel_encoder(&dev_priv->drm, encoder) { 7575 encoder->base.possible_crtcs = 7576 intel_encoder_possible_crtcs(encoder); 7577 encoder->base.possible_clones = 7578 intel_encoder_possible_clones(encoder); 7579 } 7580 7581 intel_init_pch_refclk(dev_priv); 7582 7583 drm_helper_move_panel_connectors_to_head(&dev_priv->drm); 7584} 7585 7586static int max_dotclock(struct drm_i915_private *i915) 7587{ 7588 int max_dotclock = i915->max_dotclk_freq; 7589 7590 /* icl+ might use bigjoiner */ 7591 if (DISPLAY_VER(i915) >= 11) 7592 max_dotclock *= 2; 7593 7594 return max_dotclock; 7595} 7596 7597enum drm_mode_status intel_mode_valid(struct drm_device *dev, 7598 const struct drm_display_mode *mode) 7599{ 7600 struct drm_i915_private *dev_priv = to_i915(dev); 7601 int hdisplay_max, htotal_max; 7602 int vdisplay_max, vtotal_max; 7603 7604 /* 7605 * Can't reject DBLSCAN here because Xorg ddxen can add piles 7606 * of DBLSCAN modes to the output's mode list when they detect 7607 * the scaling mode property on the connector. And they don't 7608 * ask the kernel to validate those modes in any way until 7609 * modeset time at which point the client gets a protocol error. 7610 * So in order to not upset those clients we silently ignore the 7611 * DBLSCAN flag on such connectors. For other connectors we will 7612 * reject modes with the DBLSCAN flag in encoder->compute_config(). 7613 * And we always reject DBLSCAN modes in connector->mode_valid() 7614 * as we never want such modes on the connector's mode list. 7615 */ 7616 7617 if (mode->vscan > 1) 7618 return MODE_NO_VSCAN; 7619 7620 if (mode->flags & DRM_MODE_FLAG_HSKEW) 7621 return MODE_H_ILLEGAL; 7622 7623 if (mode->flags & (DRM_MODE_FLAG_CSYNC | 7624 DRM_MODE_FLAG_NCSYNC | 7625 DRM_MODE_FLAG_PCSYNC)) 7626 return MODE_HSYNC; 7627 7628 if (mode->flags & (DRM_MODE_FLAG_BCAST | 7629 DRM_MODE_FLAG_PIXMUX | 7630 DRM_MODE_FLAG_CLKDIV2)) 7631 return MODE_BAD; 7632 7633 /* 7634 * Reject clearly excessive dotclocks early to 7635 * avoid having to worry about huge integers later. 7636 */ 7637 if (mode->clock > max_dotclock(dev_priv)) 7638 return MODE_CLOCK_HIGH; 7639 7640 /* Transcoder timing limits */ 7641 if (DISPLAY_VER(dev_priv) >= 11) { 7642 hdisplay_max = 16384; 7643 vdisplay_max = 8192; 7644 htotal_max = 16384; 7645 vtotal_max = 8192; 7646 } else if (DISPLAY_VER(dev_priv) >= 9 || 7647 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { 7648 hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */ 7649 vdisplay_max = 4096; 7650 htotal_max = 8192; 7651 vtotal_max = 8192; 7652 } else if (DISPLAY_VER(dev_priv) >= 3) { 7653 hdisplay_max = 4096; 7654 vdisplay_max = 4096; 7655 htotal_max = 8192; 7656 vtotal_max = 8192; 7657 } else { 7658 hdisplay_max = 2048; 7659 vdisplay_max = 2048; 7660 htotal_max = 4096; 7661 vtotal_max = 4096; 7662 } 7663 7664 if (mode->hdisplay > hdisplay_max || 7665 mode->hsync_start > htotal_max || 7666 mode->hsync_end > htotal_max || 7667 mode->htotal > htotal_max) 7668 return MODE_H_ILLEGAL; 7669 7670 if (mode->vdisplay > vdisplay_max || 7671 mode->vsync_start > vtotal_max || 7672 mode->vsync_end > vtotal_max || 7673 mode->vtotal > vtotal_max) 7674 return MODE_V_ILLEGAL; 7675 7676 return MODE_OK; 7677} 7678 7679enum drm_mode_status intel_cpu_transcoder_mode_valid(struct drm_i915_private *dev_priv, 7680 const struct drm_display_mode *mode) 7681{ 7682 /* 7683 * Additional transcoder timing limits, 7684 * excluding BXT/GLK DSI transcoders. 7685 */ 7686 if (DISPLAY_VER(dev_priv) >= 5) { 7687 if (mode->hdisplay < 64 || 7688 mode->htotal - mode->hdisplay < 32) 7689 return MODE_H_ILLEGAL; 7690 7691 if (mode->vtotal - mode->vdisplay < 5) 7692 return MODE_V_ILLEGAL; 7693 } else { 7694 if (mode->htotal - mode->hdisplay < 32) 7695 return MODE_H_ILLEGAL; 7696 7697 if (mode->vtotal - mode->vdisplay < 3) 7698 return MODE_V_ILLEGAL; 7699 } 7700 7701 /* 7702 * Cantiga+ cannot handle modes with a hsync front porch of 0. 7703 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. 7704 */ 7705 if ((DISPLAY_VER(dev_priv) > 4 || IS_G4X(dev_priv)) && 7706 mode->hsync_start == mode->hdisplay) 7707 return MODE_H_ILLEGAL; 7708 7709 return MODE_OK; 7710} 7711 7712enum drm_mode_status 7713intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv, 7714 const struct drm_display_mode *mode, 7715 bool bigjoiner) 7716{ 7717 int plane_width_max, plane_height_max; 7718 7719 /* 7720 * intel_mode_valid() should be 7721 * sufficient on older platforms. 7722 */ 7723 if (DISPLAY_VER(dev_priv) < 9) 7724 return MODE_OK; 7725 7726 /* 7727 * Most people will probably want a fullscreen 7728 * plane so let's not advertize modes that are 7729 * too big for that. 7730 */ 7731 if (DISPLAY_VER(dev_priv) >= 11) { 7732 plane_width_max = 5120 << bigjoiner; 7733 plane_height_max = 4320; 7734 } else { 7735 plane_width_max = 5120; 7736 plane_height_max = 4096; 7737 } 7738 7739 if (mode->hdisplay > plane_width_max) 7740 return MODE_H_ILLEGAL; 7741 7742 if (mode->vdisplay > plane_height_max) 7743 return MODE_V_ILLEGAL; 7744 7745 return MODE_OK; 7746} 7747 7748static const struct intel_display_funcs skl_display_funcs = { 7749 .get_pipe_config = hsw_get_pipe_config, 7750 .crtc_enable = hsw_crtc_enable, 7751 .crtc_disable = hsw_crtc_disable, 7752 .commit_modeset_enables = skl_commit_modeset_enables, 7753 .get_initial_plane_config = skl_get_initial_plane_config, 7754}; 7755 7756static const struct intel_display_funcs ddi_display_funcs = { 7757 .get_pipe_config = hsw_get_pipe_config, 7758 .crtc_enable = hsw_crtc_enable, 7759 .crtc_disable = hsw_crtc_disable, 7760 .commit_modeset_enables = intel_commit_modeset_enables, 7761 .get_initial_plane_config = i9xx_get_initial_plane_config, 7762}; 7763 7764static const struct intel_display_funcs pch_split_display_funcs = { 7765 .get_pipe_config = ilk_get_pipe_config, 7766 .crtc_enable = ilk_crtc_enable, 7767 .crtc_disable = ilk_crtc_disable, 7768 .commit_modeset_enables = intel_commit_modeset_enables, 7769 .get_initial_plane_config = i9xx_get_initial_plane_config, 7770}; 7771 7772static const struct intel_display_funcs vlv_display_funcs = { 7773 .get_pipe_config = i9xx_get_pipe_config, 7774 .crtc_enable = valleyview_crtc_enable, 7775 .crtc_disable = i9xx_crtc_disable, 7776 .commit_modeset_enables = intel_commit_modeset_enables, 7777 .get_initial_plane_config = i9xx_get_initial_plane_config, 7778}; 7779 7780static const struct intel_display_funcs i9xx_display_funcs = { 7781 .get_pipe_config = i9xx_get_pipe_config, 7782 .crtc_enable = i9xx_crtc_enable, 7783 .crtc_disable = i9xx_crtc_disable, 7784 .commit_modeset_enables = intel_commit_modeset_enables, 7785 .get_initial_plane_config = i9xx_get_initial_plane_config, 7786}; 7787 7788/** 7789 * intel_init_display_hooks - initialize the display modesetting hooks 7790 * @dev_priv: device private 7791 */ 7792void intel_init_display_hooks(struct drm_i915_private *dev_priv) 7793{ 7794 if (DISPLAY_VER(dev_priv) >= 9) { 7795 dev_priv->display.funcs.display = &skl_display_funcs; 7796 } else if (HAS_DDI(dev_priv)) { 7797 dev_priv->display.funcs.display = &ddi_display_funcs; 7798 } else if (HAS_PCH_SPLIT(dev_priv)) { 7799 dev_priv->display.funcs.display = &pch_split_display_funcs; 7800 } else if (IS_CHERRYVIEW(dev_priv) || 7801 IS_VALLEYVIEW(dev_priv)) { 7802 dev_priv->display.funcs.display = &vlv_display_funcs; 7803 } else { 7804 dev_priv->display.funcs.display = &i9xx_display_funcs; 7805 } 7806} 7807 7808int intel_initial_commit(struct drm_device *dev) 7809{ 7810 struct drm_atomic_state *state = NULL; 7811 struct drm_modeset_acquire_ctx ctx; 7812 struct intel_crtc *crtc; 7813 int ret = 0; 7814 7815 state = drm_atomic_state_alloc(dev); 7816 if (!state) 7817 return -ENOMEM; 7818 7819 drm_modeset_acquire_init(&ctx, 0); 7820 7821 state->acquire_ctx = &ctx; 7822 to_intel_atomic_state(state)->internal = true; 7823 7824retry: 7825 for_each_intel_crtc(dev, crtc) { 7826 struct intel_crtc_state *crtc_state = 7827 intel_atomic_get_crtc_state(state, crtc); 7828 7829 if (IS_ERR(crtc_state)) { 7830 ret = PTR_ERR(crtc_state); 7831 goto out; 7832 } 7833 7834 if (crtc_state->hw.active) { 7835 struct intel_encoder *encoder; 7836 7837 ret = drm_atomic_add_affected_planes(state, &crtc->base); 7838 if (ret) 7839 goto out; 7840 7841 /* 7842 * FIXME hack to force a LUT update to avoid the 7843 * plane update forcing the pipe gamma on without 7844 * having a proper LUT loaded. Remove once we 7845 * have readout for pipe gamma enable. 7846 */ 7847 crtc_state->uapi.color_mgmt_changed = true; 7848 7849 for_each_intel_encoder_mask(dev, encoder, 7850 crtc_state->uapi.encoder_mask) { 7851 if (encoder->initial_fastset_check && 7852 !encoder->initial_fastset_check(encoder, crtc_state)) { 7853 ret = drm_atomic_add_affected_connectors(state, 7854 &crtc->base); 7855 if (ret) 7856 goto out; 7857 } 7858 } 7859 } 7860 } 7861 7862 ret = drm_atomic_commit(state); 7863 7864out: 7865 if (ret == -EDEADLK) { 7866 drm_atomic_state_clear(state); 7867 drm_modeset_backoff(&ctx); 7868 goto retry; 7869 } 7870 7871 drm_atomic_state_put(state); 7872 7873 drm_modeset_drop_locks(&ctx); 7874 drm_modeset_acquire_fini(&ctx); 7875 7876 return ret; 7877} 7878 7879void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) 7880{ 7881 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe); 7882 enum transcoder cpu_transcoder = (enum transcoder)pipe; 7883 /* 640x480@60Hz, ~25175 kHz */ 7884 struct dpll clock = { 7885 .m1 = 18, 7886 .m2 = 7, 7887 .p1 = 13, 7888 .p2 = 4, 7889 .n = 2, 7890 }; 7891 u32 dpll, fp; 7892 int i; 7893 7894 drm_WARN_ON(&dev_priv->drm, 7895 i9xx_calc_dpll_params(48000, &clock) != 25154); 7896 7897 drm_dbg_kms(&dev_priv->drm, 7898 "enabling pipe %c due to force quirk (vco=%d dot=%d)\n", 7899 pipe_name(pipe), clock.vco, clock.dot); 7900 7901 fp = i9xx_dpll_compute_fp(&clock); 7902 dpll = DPLL_DVO_2X_MODE | 7903 DPLL_VGA_MODE_DIS | 7904 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) | 7905 PLL_P2_DIVIDE_BY_4 | 7906 PLL_REF_INPUT_DREFCLK | 7907 DPLL_VCO_ENABLE; 7908 7909 intel_de_write(dev_priv, TRANS_HTOTAL(cpu_transcoder), 7910 HACTIVE(640 - 1) | HTOTAL(800 - 1)); 7911 intel_de_write(dev_priv, TRANS_HBLANK(cpu_transcoder), 7912 HBLANK_START(640 - 1) | HBLANK_END(800 - 1)); 7913 intel_de_write(dev_priv, TRANS_HSYNC(cpu_transcoder), 7914 HSYNC_START(656 - 1) | HSYNC_END(752 - 1)); 7915 intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder), 7916 VACTIVE(480 - 1) | VTOTAL(525 - 1)); 7917 intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder), 7918 VBLANK_START(480 - 1) | VBLANK_END(525 - 1)); 7919 intel_de_write(dev_priv, TRANS_VSYNC(cpu_transcoder), 7920 VSYNC_START(490 - 1) | VSYNC_END(492 - 1)); 7921 intel_de_write(dev_priv, PIPESRC(pipe), 7922 PIPESRC_WIDTH(640 - 1) | PIPESRC_HEIGHT(480 - 1)); 7923 7924 intel_de_write(dev_priv, FP0(pipe), fp); 7925 intel_de_write(dev_priv, FP1(pipe), fp); 7926 7927 /* 7928 * Apparently we need to have VGA mode enabled prior to changing 7929 * the P1/P2 dividers. Otherwise the DPLL will keep using the old 7930 * dividers, even though the register value does change. 7931 */ 7932 intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS); 7933 intel_de_write(dev_priv, DPLL(pipe), dpll); 7934 7935 /* Wait for the clocks to stabilize. */ 7936 intel_de_posting_read(dev_priv, DPLL(pipe)); 7937 udelay(150); 7938 7939 /* The pixel multiplier can only be updated once the 7940 * DPLL is enabled and the clocks are stable. 7941 * 7942 * So write it again. 7943 */ 7944 intel_de_write(dev_priv, DPLL(pipe), dpll); 7945 7946 /* We do this three times for luck */ 7947 for (i = 0; i < 3 ; i++) { 7948 intel_de_write(dev_priv, DPLL(pipe), dpll); 7949 intel_de_posting_read(dev_priv, DPLL(pipe)); 7950 udelay(150); /* wait for warmup */ 7951 } 7952 7953 intel_de_write(dev_priv, TRANSCONF(pipe), TRANSCONF_ENABLE); 7954 intel_de_posting_read(dev_priv, TRANSCONF(pipe)); 7955 7956 intel_wait_for_pipe_scanline_moving(crtc); 7957} 7958 7959void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) 7960{ 7961 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe); 7962 7963 drm_dbg_kms(&dev_priv->drm, "disabling pipe %c due to force quirk\n", 7964 pipe_name(pipe)); 7965 7966 drm_WARN_ON(&dev_priv->drm, 7967 intel_de_read(dev_priv, DSPCNTR(PLANE_A)) & DISP_ENABLE); 7968 drm_WARN_ON(&dev_priv->drm, 7969 intel_de_read(dev_priv, DSPCNTR(PLANE_B)) & DISP_ENABLE); 7970 drm_WARN_ON(&dev_priv->drm, 7971 intel_de_read(dev_priv, DSPCNTR(PLANE_C)) & DISP_ENABLE); 7972 drm_WARN_ON(&dev_priv->drm, 7973 intel_de_read(dev_priv, CURCNTR(PIPE_A)) & MCURSOR_MODE_MASK); 7974 drm_WARN_ON(&dev_priv->drm, 7975 intel_de_read(dev_priv, CURCNTR(PIPE_B)) & MCURSOR_MODE_MASK); 7976 7977 intel_de_write(dev_priv, TRANSCONF(pipe), 0); 7978 intel_de_posting_read(dev_priv, TRANSCONF(pipe)); 7979 7980 intel_wait_for_pipe_scanline_stopped(crtc); 7981 7982 intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS); 7983 intel_de_posting_read(dev_priv, DPLL(pipe)); 7984} 7985 7986void intel_hpd_poll_fini(struct drm_i915_private *i915) 7987{ 7988 struct intel_connector *connector; 7989 struct drm_connector_list_iter conn_iter; 7990 7991 /* Kill all the work that may have been queued by hpd. */ 7992 drm_connector_list_iter_begin(&i915->drm, &conn_iter); 7993 for_each_intel_connector_iter(connector, &conn_iter) { 7994 if (connector->modeset_retry_work.func) 7995 cancel_work_sync(&connector->modeset_retry_work); 7996 if (connector->hdcp.shim) { 7997 cancel_delayed_work_sync(&connector->hdcp.check_work); 7998 cancel_work_sync(&connector->hdcp.prop_work); 7999 } 8000 } 8001 drm_connector_list_iter_end(&conn_iter); 8002} 8003 8004bool intel_scanout_needs_vtd_wa(struct drm_i915_private *i915) 8005{ 8006 return DISPLAY_VER(i915) >= 6 && i915_vtd_active(i915); 8007} 8008