1/* SPDX-License-Identifier: GPL-2.0-only */ 2/************************************************************************** 3 * Copyright (c) 2007-2011, Intel Corporation. 4 * All Rights Reserved. 5 * 6 **************************************************************************/ 7 8#ifndef _PSB_DRV_H_ 9#define _PSB_DRV_H_ 10 11#include <linux/kref.h> 12#include <linux/mm_types.h> 13 14#include <drm/drm_device.h> 15 16#include "gtt.h" 17#include "intel_bios.h" 18#include "mmu.h" 19#include "oaktrail.h" 20#include "opregion.h" 21#include "power.h" 22#include "psb_intel_drv.h" 23#include "psb_reg.h" 24 25#define DRIVER_AUTHOR "Alan Cox <alan@linux.intel.com> and others" 26 27#define DRIVER_NAME "gma500" 28#define DRIVER_DESC "DRM driver for the Intel GMA500, GMA600, GMA3600, GMA3650" 29#define DRIVER_DATE "20140314" 30 31#define DRIVER_MAJOR 1 32#define DRIVER_MINOR 0 33#define DRIVER_PATCHLEVEL 0 34 35/* Append new drm mode definition here, align with libdrm definition */ 36#define DRM_MODE_SCALE_NO_SCALE 2 37 38#define IS_PSB(drm) ((to_pci_dev((drm)->dev)->device & 0xfffe) == 0x8108) 39#define IS_MRST(drm) ((to_pci_dev((drm)->dev)->device & 0xfff0) == 0x4100) 40#define IS_CDV(drm) ((to_pci_dev((drm)->dev)->device & 0xfff0) == 0x0be0) 41 42/* Hardware offsets */ 43#define PSB_VDC_OFFSET 0x00000000 44#define PSB_VDC_SIZE 0x000080000 45#define MRST_MMIO_SIZE 0x0000C0000 46#define PSB_SGX_SIZE 0x8000 47#define PSB_SGX_OFFSET 0x00040000 48#define MRST_SGX_OFFSET 0x00080000 49 50/* PCI resource identifiers */ 51#define PSB_MMIO_RESOURCE 0 52#define PSB_AUX_RESOURCE 0 53#define PSB_GATT_RESOURCE 2 54#define PSB_GTT_RESOURCE 3 55 56/* PCI configuration */ 57#define PSB_GMCH_CTRL 0x52 58#define PSB_BSM 0x5C 59#define _PSB_GMCH_ENABLED 0x4 60#define PSB_PGETBL_CTL 0x2020 61#define _PSB_PGETBL_ENABLED 0x00000001 62#define PSB_SGX_2D_SLAVE_PORT 0x4000 63#define PSB_LPC_GBA 0x44 64 65/* TODO: To get rid of */ 66#define PSB_TT_PRIV0_LIMIT (256*1024*1024) 67#define PSB_TT_PRIV0_PLIMIT (PSB_TT_PRIV0_LIMIT >> PAGE_SHIFT) 68 69/* SGX side MMU definitions (these can probably go) */ 70 71/* Flags for external memory type field */ 72#define PSB_MMU_CACHED_MEMORY 0x0001 /* Bind to MMU only */ 73#define PSB_MMU_RO_MEMORY 0x0002 /* MMU RO memory */ 74#define PSB_MMU_WO_MEMORY 0x0004 /* MMU WO memory */ 75 76/* PTE's and PDE's */ 77#define PSB_PDE_MASK 0x003FFFFF 78#define PSB_PDE_SHIFT 22 79#define PSB_PTE_SHIFT 12 80 81/* Cache control */ 82#define PSB_PTE_VALID 0x0001 /* PTE / PDE valid */ 83#define PSB_PTE_WO 0x0002 /* Write only */ 84#define PSB_PTE_RO 0x0004 /* Read only */ 85#define PSB_PTE_CACHED 0x0008 /* CPU cache coherent */ 86 87/* VDC registers and bits */ 88#define PSB_MSVDX_CLOCKGATING 0x2064 89#define PSB_TOPAZ_CLOCKGATING 0x2068 90#define PSB_HWSTAM 0x2098 91#define PSB_INSTPM 0x20C0 92#define PSB_INT_IDENTITY_R 0x20A4 93#define _PSB_IRQ_ASLE (1<<0) 94#define _MDFLD_PIPEC_EVENT_FLAG (1<<2) 95#define _MDFLD_PIPEC_VBLANK_FLAG (1<<3) 96#define _PSB_DPST_PIPEB_FLAG (1<<4) 97#define _MDFLD_PIPEB_EVENT_FLAG (1<<4) 98#define _PSB_VSYNC_PIPEB_FLAG (1<<5) 99#define _PSB_DPST_PIPEA_FLAG (1<<6) 100#define _PSB_PIPEA_EVENT_FLAG (1<<6) 101#define _PSB_VSYNC_PIPEA_FLAG (1<<7) 102#define _PSB_IRQ_DISP_HOTSYNC (1<<17) 103#define _PSB_IRQ_SGX_FLAG (1<<18) 104#define _PSB_IRQ_MSVDX_FLAG (1<<19) 105#define _LNC_IRQ_TOPAZ_FLAG (1<<20) 106 107#define _PSB_PIPE_EVENT_FLAG (_PSB_VSYNC_PIPEA_FLAG | \ 108 _PSB_VSYNC_PIPEB_FLAG) 109 110#define PSB_INT_IDENTITY_R 0x20A4 111#define PSB_INT_MASK_R 0x20A8 112#define PSB_INT_ENABLE_R 0x20A0 113 114#define _PSB_MMU_ER_MASK 0x0001FF00 115#define _PSB_MMU_ER_HOST (1 << 16) 116#define GPIOA 0x5010 117#define GPIOB 0x5014 118#define GPIOC 0x5018 119#define GPIOD 0x501c 120#define GPIOE 0x5020 121#define GPIOF 0x5024 122#define GPIOG 0x5028 123#define GPIOH 0x502c 124#define GPIO_CLOCK_DIR_MASK (1 << 0) 125#define GPIO_CLOCK_DIR_IN (0 << 1) 126#define GPIO_CLOCK_DIR_OUT (1 << 1) 127#define GPIO_CLOCK_VAL_MASK (1 << 2) 128#define GPIO_CLOCK_VAL_OUT (1 << 3) 129#define GPIO_CLOCK_VAL_IN (1 << 4) 130#define GPIO_CLOCK_PULLUP_DISABLE (1 << 5) 131#define GPIO_DATA_DIR_MASK (1 << 8) 132#define GPIO_DATA_DIR_IN (0 << 9) 133#define GPIO_DATA_DIR_OUT (1 << 9) 134#define GPIO_DATA_VAL_MASK (1 << 10) 135#define GPIO_DATA_VAL_OUT (1 << 11) 136#define GPIO_DATA_VAL_IN (1 << 12) 137#define GPIO_DATA_PULLUP_DISABLE (1 << 13) 138 139#define VCLK_DIVISOR_VGA0 0x6000 140#define VCLK_DIVISOR_VGA1 0x6004 141#define VCLK_POST_DIV 0x6010 142 143#define PSB_COMM_2D (PSB_ENGINE_2D << 4) 144#define PSB_COMM_3D (PSB_ENGINE_3D << 4) 145#define PSB_COMM_TA (PSB_ENGINE_TA << 4) 146#define PSB_COMM_HP (PSB_ENGINE_HP << 4) 147#define PSB_COMM_USER_IRQ (1024 >> 2) 148#define PSB_COMM_USER_IRQ_LOST (PSB_COMM_USER_IRQ + 1) 149#define PSB_COMM_FW (2048 >> 2) 150 151#define PSB_UIRQ_VISTEST 1 152#define PSB_UIRQ_OOM_REPLY 2 153#define PSB_UIRQ_FIRE_TA_REPLY 3 154#define PSB_UIRQ_FIRE_RASTER_REPLY 4 155 156#define PSB_2D_SIZE (256*1024*1024) 157#define PSB_MAX_RELOC_PAGES 1024 158 159#define PSB_LOW_REG_OFFS 0x0204 160#define PSB_HIGH_REG_OFFS 0x0600 161 162#define PSB_NUM_VBLANKS 2 163 164 165#define PSB_2D_SIZE (256*1024*1024) 166#define PSB_MAX_RELOC_PAGES 1024 167 168#define PSB_LOW_REG_OFFS 0x0204 169#define PSB_HIGH_REG_OFFS 0x0600 170 171#define PSB_NUM_VBLANKS 2 172#define PSB_WATCHDOG_DELAY (HZ * 2) 173#define PSB_LID_DELAY (HZ / 10) 174 175#define PSB_MAX_BRIGHTNESS 100 176 177#define PSB_PWR_STATE_ON 1 178#define PSB_PWR_STATE_OFF 2 179 180#define PSB_PMPOLICY_NOPM 0 181#define PSB_PMPOLICY_CLOCKGATING 1 182#define PSB_PMPOLICY_POWERDOWN 2 183 184#define PSB_PMSTATE_POWERUP 0 185#define PSB_PMSTATE_CLOCKGATED 1 186#define PSB_PMSTATE_POWERDOWN 2 187#define PSB_PCIx_MSI_ADDR_LOC 0x94 188#define PSB_PCIx_MSI_DATA_LOC 0x98 189 190/* Medfield crystal settings */ 191#define KSEL_CRYSTAL_19 1 192#define KSEL_BYPASS_19 5 193#define KSEL_BYPASS_25 6 194#define KSEL_BYPASS_83_100 7 195 196struct opregion_header; 197struct opregion_acpi; 198struct opregion_swsci; 199struct opregion_asle; 200 201struct psb_intel_opregion { 202 struct opregion_header *header; 203 struct opregion_acpi *acpi; 204 struct opregion_swsci *swsci; 205 struct opregion_asle *asle; 206 void *vbt; 207 u32 __iomem *lid_state; 208 struct work_struct asle_work; 209}; 210 211struct sdvo_device_mapping { 212 u8 initialized; 213 u8 dvo_port; 214 u8 slave_addr; 215 u8 dvo_wiring; 216 u8 i2c_pin; 217 u8 i2c_speed; 218 u8 ddc_pin; 219}; 220 221struct intel_gmbus { 222 struct i2c_adapter adapter; 223 struct i2c_adapter *force_bit; 224 u32 reg0; 225}; 226 227/* Register offset maps */ 228struct psb_offset { 229 u32 fp0; 230 u32 fp1; 231 u32 cntr; 232 u32 conf; 233 u32 src; 234 u32 dpll; 235 u32 dpll_md; 236 u32 htotal; 237 u32 hblank; 238 u32 hsync; 239 u32 vtotal; 240 u32 vblank; 241 u32 vsync; 242 u32 stride; 243 u32 size; 244 u32 pos; 245 u32 surf; 246 u32 addr; 247 u32 base; 248 u32 status; 249 u32 linoff; 250 u32 tileoff; 251 u32 palette; 252}; 253 254/* 255 * Register save state. This is used to hold the context when the 256 * device is powered off. In the case of Oaktrail this can (but does not 257 * yet) include screen blank. Operations occuring during the save 258 * update the register cache instead. 259 */ 260 261/* Common status for pipes */ 262struct psb_pipe { 263 u32 fp0; 264 u32 fp1; 265 u32 cntr; 266 u32 conf; 267 u32 src; 268 u32 dpll; 269 u32 dpll_md; 270 u32 htotal; 271 u32 hblank; 272 u32 hsync; 273 u32 vtotal; 274 u32 vblank; 275 u32 vsync; 276 u32 stride; 277 u32 size; 278 u32 pos; 279 u32 base; 280 u32 surf; 281 u32 addr; 282 u32 status; 283 u32 linoff; 284 u32 tileoff; 285 u32 palette[256]; 286}; 287 288struct psb_state { 289 uint32_t saveVCLK_DIVISOR_VGA0; 290 uint32_t saveVCLK_DIVISOR_VGA1; 291 uint32_t saveVCLK_POST_DIV; 292 uint32_t saveVGACNTRL; 293 uint32_t saveADPA; 294 uint32_t saveLVDS; 295 uint32_t saveDVOA; 296 uint32_t saveDVOB; 297 uint32_t saveDVOC; 298 uint32_t savePP_ON; 299 uint32_t savePP_OFF; 300 uint32_t savePP_CONTROL; 301 uint32_t savePP_CYCLE; 302 uint32_t savePFIT_CONTROL; 303 uint32_t saveCLOCKGATING; 304 uint32_t saveDSPARB; 305 uint32_t savePFIT_AUTO_RATIOS; 306 uint32_t savePFIT_PGM_RATIOS; 307 uint32_t savePP_ON_DELAYS; 308 uint32_t savePP_OFF_DELAYS; 309 uint32_t savePP_DIVISOR; 310 uint32_t saveBCLRPAT_A; 311 uint32_t saveBCLRPAT_B; 312 uint32_t savePERF_MODE; 313 uint32_t saveDSPFW1; 314 uint32_t saveDSPFW2; 315 uint32_t saveDSPFW3; 316 uint32_t saveDSPFW4; 317 uint32_t saveDSPFW5; 318 uint32_t saveDSPFW6; 319 uint32_t saveCHICKENBIT; 320 uint32_t saveDSPACURSOR_CTRL; 321 uint32_t saveDSPBCURSOR_CTRL; 322 uint32_t saveDSPACURSOR_BASE; 323 uint32_t saveDSPBCURSOR_BASE; 324 uint32_t saveDSPACURSOR_POS; 325 uint32_t saveDSPBCURSOR_POS; 326 uint32_t saveOV_OVADD; 327 uint32_t saveOV_OGAMC0; 328 uint32_t saveOV_OGAMC1; 329 uint32_t saveOV_OGAMC2; 330 uint32_t saveOV_OGAMC3; 331 uint32_t saveOV_OGAMC4; 332 uint32_t saveOV_OGAMC5; 333 uint32_t saveOVC_OVADD; 334 uint32_t saveOVC_OGAMC0; 335 uint32_t saveOVC_OGAMC1; 336 uint32_t saveOVC_OGAMC2; 337 uint32_t saveOVC_OGAMC3; 338 uint32_t saveOVC_OGAMC4; 339 uint32_t saveOVC_OGAMC5; 340 341 /* DPST register save */ 342 uint32_t saveHISTOGRAM_INT_CONTROL_REG; 343 uint32_t saveHISTOGRAM_LOGIC_CONTROL_REG; 344 uint32_t savePWM_CONTROL_LOGIC; 345}; 346 347struct cdv_state { 348 uint32_t saveDSPCLK_GATE_D; 349 uint32_t saveRAMCLK_GATE_D; 350 uint32_t saveDSPARB; 351 uint32_t saveDSPFW[6]; 352 uint32_t saveADPA; 353 uint32_t savePP_CONTROL; 354 uint32_t savePFIT_PGM_RATIOS; 355 uint32_t saveLVDS; 356 uint32_t savePFIT_CONTROL; 357 uint32_t savePP_ON_DELAYS; 358 uint32_t savePP_OFF_DELAYS; 359 uint32_t savePP_CYCLE; 360 uint32_t saveVGACNTRL; 361 uint32_t saveIER; 362 uint32_t saveIMR; 363 u8 saveLBB; 364}; 365 366struct psb_save_area { 367 struct psb_pipe pipe[3]; 368 uint32_t saveBSM; 369 uint32_t saveVBT; 370 union { 371 struct psb_state psb; 372 struct cdv_state cdv; 373 }; 374 uint32_t saveBLC_PWM_CTL2; 375 uint32_t saveBLC_PWM_CTL; 376}; 377 378struct psb_ops; 379 380#define PSB_NUM_PIPE 3 381 382struct intel_scu_ipc_dev; 383 384struct drm_psb_private { 385 struct drm_device dev; 386 387 struct pci_dev *aux_pdev; /* Currently only used by mrst */ 388 struct pci_dev *lpc_pdev; /* Currently only used by mrst */ 389 const struct psb_ops *ops; 390 const struct psb_offset *regmap; 391 392 struct child_device_config *child_dev; 393 int child_dev_num; 394 395 struct psb_gtt gtt; 396 397 /* GTT Memory manager */ 398 struct psb_gtt_mm *gtt_mm; 399 struct page *scratch_page; 400 u32 __iomem *gtt_map; 401 uint32_t stolen_base; 402 u8 __iomem *vram_addr; 403 unsigned long vram_stolen_size; 404 u16 gmch_ctrl; /* Saved GTT setup */ 405 u32 pge_ctl; 406 407 struct mutex gtt_mutex; 408 struct resource *gtt_mem; /* Our PCI resource */ 409 410 struct mutex mmap_mutex; 411 412 struct psb_mmu_driver *mmu; 413 struct psb_mmu_pd *pf_pd; 414 415 /* Register base */ 416 uint8_t __iomem *sgx_reg; 417 uint8_t __iomem *vdc_reg; 418 uint8_t __iomem *aux_reg; /* Auxillary vdc pipe regs */ 419 uint16_t lpc_gpio_base; 420 uint32_t gatt_free_offset; 421 422 /* Fencing / irq */ 423 uint32_t vdc_irq_mask; 424 uint32_t pipestat[PSB_NUM_PIPE]; 425 426 spinlock_t irqmask_lock; 427 bool irq_enabled; 428 429 /* Power */ 430 bool pm_initialized; 431 432 /* Modesetting */ 433 struct psb_intel_mode_device mode_dev; 434 bool modeset; /* true if we have done the mode_device setup */ 435 436 struct drm_crtc *plane_to_crtc_mapping[PSB_NUM_PIPE]; 437 struct drm_crtc *pipe_to_crtc_mapping[PSB_NUM_PIPE]; 438 uint32_t num_pipe; 439 440 /* OSPM info (Power management base) (TODO: can go ?) */ 441 uint32_t ospm_base; 442 443 /* Sizes info */ 444 u32 fuse_reg_value; 445 u32 video_device_fuse; 446 447 /* PCI revision ID for B0:D2:F0 */ 448 uint8_t platform_rev_id; 449 450 /* gmbus */ 451 struct intel_gmbus *gmbus; 452 uint8_t __iomem *gmbus_reg; 453 454 /* Used by SDVO */ 455 int crt_ddc_pin; 456 /* FIXME: The mappings should be parsed from bios but for now we can 457 pretend there are no mappings available */ 458 struct sdvo_device_mapping sdvo_mappings[2]; 459 u32 hotplug_supported_mask; 460 struct drm_property *broadcast_rgb_property; 461 struct drm_property *force_audio_property; 462 463 /* LVDS info */ 464 int backlight_duty_cycle; /* restore backlight to this value */ 465 bool panel_wants_dither; 466 struct drm_display_mode *panel_fixed_mode; 467 struct drm_display_mode *lfp_lvds_vbt_mode; 468 struct drm_display_mode *sdvo_lvds_vbt_mode; 469 470 struct bdb_lvds_backlight *lvds_bl; /* LVDS backlight info from VBT */ 471 struct gma_i2c_chan *lvds_i2c_bus; /* FIXME: Remove this? */ 472 473 /* Feature bits from the VBIOS */ 474 unsigned int int_tv_support:1; 475 unsigned int lvds_dither:1; 476 unsigned int lvds_vbt:1; 477 unsigned int int_crt_support:1; 478 unsigned int lvds_use_ssc:1; 479 int lvds_ssc_freq; 480 bool is_lvds_on; 481 bool is_mipi_on; 482 bool lvds_enabled_in_vbt; 483 u32 mipi_ctrl_display; 484 485 unsigned int core_freq; 486 uint32_t iLVDS_enable; 487 488 /* MID specific */ 489 bool use_msi; 490 bool has_gct; 491 struct oaktrail_gct_data gct_data; 492 493 /* Oaktrail HDMI state */ 494 struct oaktrail_hdmi_dev *hdmi_priv; 495 496 /* Register state */ 497 struct psb_save_area regs; 498 499 /* Hotplug handling */ 500 struct work_struct hotplug_work; 501 502 /* LID-Switch */ 503 spinlock_t lid_lock; 504 struct timer_list lid_timer; 505 struct psb_intel_opregion opregion; 506 u32 lid_last_state; 507 508 /* Watchdog */ 509 uint32_t apm_reg; 510 uint16_t apm_base; 511 512 /* 513 * Used for modifying backlight from 514 * xrandr -- consider removing and using HAL instead 515 */ 516 struct intel_scu_ipc_dev *scu; 517 struct backlight_device *backlight_device; 518 struct drm_property *backlight_property; 519 bool backlight_enabled; 520 int backlight_level; 521 uint32_t blc_adj1; 522 uint32_t blc_adj2; 523 524 bool dsr_enable; 525 u32 dsr_fb_update; 526 bool dpi_panel_on[3]; 527 void *dsi_configs[2]; 528 u32 bpp; 529 u32 bpp2; 530 531 u32 pipeconf[3]; 532 u32 dspcntr[3]; 533 534 bool dplla_96mhz; /* DPLL data from the VBT */ 535 536 struct { 537 int rate; 538 int lanes; 539 int preemphasis; 540 int vswing; 541 542 bool initialized; 543 bool support; 544 int bpp; 545 struct edp_power_seq pps; 546 } edp; 547 uint8_t panel_type; 548}; 549 550static inline struct drm_psb_private *to_drm_psb_private(struct drm_device *dev) 551{ 552 return container_of(dev, struct drm_psb_private, dev); 553} 554 555/* Operations for each board type */ 556struct psb_ops { 557 const char *name; 558 int pipes; /* Number of output pipes */ 559 int crtcs; /* Number of CRTCs */ 560 int sgx_offset; /* Base offset of SGX device */ 561 int hdmi_mask; /* Mask of HDMI CRTCs */ 562 int lvds_mask; /* Mask of LVDS CRTCs */ 563 int sdvo_mask; /* Mask of SDVO CRTCs */ 564 int cursor_needs_phys; /* If cursor base reg need physical address */ 565 566 /* Sub functions */ 567 struct drm_crtc_helper_funcs const *crtc_helper; 568 const struct gma_clock_funcs *clock_funcs; 569 570 /* Setup hooks */ 571 int (*chip_setup)(struct drm_device *dev); 572 void (*chip_teardown)(struct drm_device *dev); 573 /* Optional helper caller after modeset */ 574 void (*errata)(struct drm_device *dev); 575 576 /* Display management hooks */ 577 int (*output_init)(struct drm_device *dev); 578 int (*hotplug)(struct drm_device *dev); 579 void (*hotplug_enable)(struct drm_device *dev, bool on); 580 /* Power management hooks */ 581 void (*init_pm)(struct drm_device *dev); 582 int (*save_regs)(struct drm_device *dev); 583 int (*restore_regs)(struct drm_device *dev); 584 void (*save_crtc)(struct drm_crtc *crtc); 585 void (*restore_crtc)(struct drm_crtc *crtc); 586 int (*power_up)(struct drm_device *dev); 587 int (*power_down)(struct drm_device *dev); 588 void (*update_wm)(struct drm_device *dev, struct drm_crtc *crtc); 589 void (*disable_sr)(struct drm_device *dev); 590 591 void (*lvds_bl_power)(struct drm_device *dev, bool on); 592 593 /* Backlight */ 594 int (*backlight_init)(struct drm_device *dev); 595 void (*backlight_set)(struct drm_device *dev, int level); 596 int (*backlight_get)(struct drm_device *dev); 597 const char *backlight_name; 598 599 int i2c_bus; /* I2C bus identifier for Moorestown */ 600}; 601 602/* psb_lid.c */ 603extern void psb_lid_timer_init(struct drm_psb_private *dev_priv); 604extern void psb_lid_timer_takedown(struct drm_psb_private *dev_priv); 605 606/* modesetting */ 607extern void psb_modeset_init(struct drm_device *dev); 608extern void psb_modeset_cleanup(struct drm_device *dev); 609 610/* framebuffer */ 611struct drm_framebuffer *psb_framebuffer_create(struct drm_device *dev, 612 const struct drm_mode_fb_cmd2 *mode_cmd, 613 struct drm_gem_object *obj); 614 615/* fbdev */ 616#if defined(CONFIG_DRM_FBDEV_EMULATION) 617void psb_fbdev_setup(struct drm_psb_private *dev_priv); 618#else 619static inline void psb_fbdev_setup(struct drm_psb_private *dev_priv) 620{ } 621#endif 622 623/* backlight.c */ 624int gma_backlight_init(struct drm_device *dev); 625void gma_backlight_exit(struct drm_device *dev); 626void gma_backlight_disable(struct drm_device *dev); 627void gma_backlight_enable(struct drm_device *dev); 628void gma_backlight_set(struct drm_device *dev, int v); 629 630/* oaktrail_crtc.c */ 631extern const struct drm_crtc_helper_funcs oaktrail_helper_funcs; 632 633/* oaktrail_lvds.c */ 634extern void oaktrail_lvds_init(struct drm_device *dev, 635 struct psb_intel_mode_device *mode_dev); 636 637/* psb_intel_display.c */ 638extern const struct drm_crtc_helper_funcs psb_intel_helper_funcs; 639 640/* psb_intel_lvds.c */ 641extern const struct drm_connector_helper_funcs 642 psb_intel_lvds_connector_helper_funcs; 643extern const struct drm_connector_funcs psb_intel_lvds_connector_funcs; 644 645/* gem.c */ 646extern int psb_gem_dumb_create(struct drm_file *file, struct drm_device *dev, 647 struct drm_mode_create_dumb *args); 648 649/* psb_device.c */ 650extern const struct psb_ops psb_chip_ops; 651 652/* oaktrail_device.c */ 653extern const struct psb_ops oaktrail_chip_ops; 654 655/* cdv_device.c */ 656extern const struct psb_ops cdv_chip_ops; 657 658/* Utilities */ 659static inline uint32_t REGISTER_READ(struct drm_device *dev, uint32_t reg) 660{ 661 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); 662 return ioread32(dev_priv->vdc_reg + reg); 663} 664 665static inline uint32_t REGISTER_READ_AUX(struct drm_device *dev, uint32_t reg) 666{ 667 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); 668 return ioread32(dev_priv->aux_reg + reg); 669} 670 671#define REG_READ(reg) REGISTER_READ(dev, (reg)) 672#define REG_READ_AUX(reg) REGISTER_READ_AUX(dev, (reg)) 673 674/* Useful for post reads */ 675static inline uint32_t REGISTER_READ_WITH_AUX(struct drm_device *dev, 676 uint32_t reg, int aux) 677{ 678 uint32_t val; 679 680 if (aux) 681 val = REG_READ_AUX(reg); 682 else 683 val = REG_READ(reg); 684 685 return val; 686} 687 688#define REG_READ_WITH_AUX(reg, aux) REGISTER_READ_WITH_AUX(dev, (reg), (aux)) 689 690static inline void REGISTER_WRITE(struct drm_device *dev, uint32_t reg, 691 uint32_t val) 692{ 693 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); 694 iowrite32((val), dev_priv->vdc_reg + (reg)); 695} 696 697static inline void REGISTER_WRITE_AUX(struct drm_device *dev, uint32_t reg, 698 uint32_t val) 699{ 700 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); 701 iowrite32((val), dev_priv->aux_reg + (reg)); 702} 703 704#define REG_WRITE(reg, val) REGISTER_WRITE(dev, (reg), (val)) 705#define REG_WRITE_AUX(reg, val) REGISTER_WRITE_AUX(dev, (reg), (val)) 706 707static inline void REGISTER_WRITE_WITH_AUX(struct drm_device *dev, uint32_t reg, 708 uint32_t val, int aux) 709{ 710 if (aux) 711 REG_WRITE_AUX(reg, val); 712 else 713 REG_WRITE(reg, val); 714} 715 716#define REG_WRITE_WITH_AUX(reg, val, aux) REGISTER_WRITE_WITH_AUX(dev, (reg), (val), (aux)) 717 718static inline void REGISTER_WRITE16(struct drm_device *dev, 719 uint32_t reg, uint32_t val) 720{ 721 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); 722 iowrite16((val), dev_priv->vdc_reg + (reg)); 723} 724 725#define REG_WRITE16(reg, val) REGISTER_WRITE16(dev, (reg), (val)) 726 727static inline void REGISTER_WRITE8(struct drm_device *dev, 728 uint32_t reg, uint32_t val) 729{ 730 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); 731 iowrite8((val), dev_priv->vdc_reg + (reg)); 732} 733 734#define REG_WRITE8(reg, val) REGISTER_WRITE8(dev, (reg), (val)) 735 736#define PSB_WVDC32(_val, _offs) iowrite32(_val, dev_priv->vdc_reg + (_offs)) 737#define PSB_RVDC32(_offs) ioread32(dev_priv->vdc_reg + (_offs)) 738 739#define PSB_RSGX32(_offs) ioread32(dev_priv->sgx_reg + (_offs)) 740#define PSB_WSGX32(_val, _offs) iowrite32(_val, dev_priv->sgx_reg + (_offs)) 741 742#define PSB_WMSVDX32(_val, _offs) iowrite32(_val, dev_priv->msvdx_reg + (_offs)) 743#define PSB_RMSVDX32(_offs) ioread32(dev_priv->msvdx_reg + (_offs)) 744 745#endif 746