1/* 2 * Copyright (c) 2006 Luc Verhaegen (quirks list) 3 * Copyright (c) 2007-2008 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * Copyright 2010 Red Hat, Inc. 6 * 7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from 8 * FB layer. 9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com> 10 * 11 * Permission is hereby granted, free of charge, to any person obtaining a 12 * copy of this software and associated documentation files (the "Software"), 13 * to deal in the Software without restriction, including without limitation 14 * the rights to use, copy, modify, merge, publish, distribute, sub license, 15 * and/or sell copies of the Software, and to permit persons to whom the 16 * Software is furnished to do so, subject to the following conditions: 17 * 18 * The above copyright notice and this permission notice (including the 19 * next paragraph) shall be included in all copies or substantial portions 20 * of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 28 * DEALINGS IN THE SOFTWARE. 29 */ 30 31#include <linux/bitfield.h> 32#include <linux/hdmi.h> 33#include <linux/i2c.h> 34#include <linux/kernel.h> 35#include <linux/module.h> 36#include <linux/pci.h> 37#include <linux/slab.h> 38#include <linux/vga_switcheroo.h> 39 40#include <drm/drm_displayid.h> 41#include <drm/drm_drv.h> 42#include <drm/drm_edid.h> 43#include <drm/drm_encoder.h> 44#include <drm/drm_print.h> 45 46#include "drm_crtc_internal.h" 47 48static int oui(u8 first, u8 second, u8 third) 49{ 50 return (first << 16) | (second << 8) | third; 51} 52 53#define EDID_EST_TIMINGS 16 54#define EDID_STD_TIMINGS 8 55#define EDID_DETAILED_TIMINGS 4 56 57/* 58 * EDID blocks out in the wild have a variety of bugs, try to collect 59 * them here (note that userspace may work around broken monitors first, 60 * but fixes should make their way here so that the kernel "just works" 61 * on as many displays as possible). 62 */ 63 64/* First detailed mode wrong, use largest 60Hz mode */ 65#define EDID_QUIRK_PREFER_LARGE_60 (1 << 0) 66/* Reported 135MHz pixel clock is too high, needs adjustment */ 67#define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1) 68/* Prefer the largest mode at 75 Hz */ 69#define EDID_QUIRK_PREFER_LARGE_75 (1 << 2) 70/* Detail timing is in cm not mm */ 71#define EDID_QUIRK_DETAILED_IN_CM (1 << 3) 72/* Detailed timing descriptors have bogus size values, so just take the 73 * maximum size and use that. 74 */ 75#define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4) 76/* use +hsync +vsync for detailed mode */ 77#define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6) 78/* Force reduced-blanking timings for detailed modes */ 79#define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7) 80/* Force 8bpc */ 81#define EDID_QUIRK_FORCE_8BPC (1 << 8) 82/* Force 12bpc */ 83#define EDID_QUIRK_FORCE_12BPC (1 << 9) 84/* Force 6bpc */ 85#define EDID_QUIRK_FORCE_6BPC (1 << 10) 86/* Force 10bpc */ 87#define EDID_QUIRK_FORCE_10BPC (1 << 11) 88/* Non desktop display (i.e. HMD) */ 89#define EDID_QUIRK_NON_DESKTOP (1 << 12) 90/* Cap the DSC target bitrate to 15bpp */ 91#define EDID_QUIRK_CAP_DSC_15BPP (1 << 13) 92 93#define MICROSOFT_IEEE_OUI 0xca125c 94 95struct detailed_mode_closure { 96 struct drm_connector *connector; 97 const struct drm_edid *drm_edid; 98 bool preferred; 99 int modes; 100}; 101 102#define LEVEL_DMT 0 103#define LEVEL_GTF 1 104#define LEVEL_GTF2 2 105#define LEVEL_CVT 3 106 107#define EDID_QUIRK(vend_chr_0, vend_chr_1, vend_chr_2, product_id, _quirks) \ 108{ \ 109 .panel_id = drm_edid_encode_panel_id(vend_chr_0, vend_chr_1, vend_chr_2, \ 110 product_id), \ 111 .quirks = _quirks \ 112} 113 114static const struct edid_quirk { 115 u32 panel_id; 116 u32 quirks; 117} edid_quirk_list[] = { 118 /* Acer AL1706 */ 119 EDID_QUIRK('A', 'C', 'R', 44358, EDID_QUIRK_PREFER_LARGE_60), 120 /* Acer F51 */ 121 EDID_QUIRK('A', 'P', 'I', 0x7602, EDID_QUIRK_PREFER_LARGE_60), 122 123 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */ 124 EDID_QUIRK('A', 'E', 'O', 0, EDID_QUIRK_FORCE_6BPC), 125 126 /* BenQ GW2765 */ 127 EDID_QUIRK('B', 'N', 'Q', 0x78d6, EDID_QUIRK_FORCE_8BPC), 128 129 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */ 130 EDID_QUIRK('B', 'O', 'E', 0x78b, EDID_QUIRK_FORCE_6BPC), 131 132 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */ 133 EDID_QUIRK('C', 'P', 'T', 0x17df, EDID_QUIRK_FORCE_6BPC), 134 135 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */ 136 EDID_QUIRK('S', 'D', 'C', 0x3652, EDID_QUIRK_FORCE_6BPC), 137 138 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */ 139 EDID_QUIRK('B', 'O', 'E', 0x0771, EDID_QUIRK_FORCE_6BPC), 140 141 /* Belinea 10 15 55 */ 142 EDID_QUIRK('M', 'A', 'X', 1516, EDID_QUIRK_PREFER_LARGE_60), 143 EDID_QUIRK('M', 'A', 'X', 0x77e, EDID_QUIRK_PREFER_LARGE_60), 144 145 /* Envision Peripherals, Inc. EN-7100e */ 146 EDID_QUIRK('E', 'P', 'I', 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH), 147 /* Envision EN2028 */ 148 EDID_QUIRK('E', 'P', 'I', 8232, EDID_QUIRK_PREFER_LARGE_60), 149 150 /* Funai Electronics PM36B */ 151 EDID_QUIRK('F', 'C', 'M', 13600, EDID_QUIRK_PREFER_LARGE_75 | 152 EDID_QUIRK_DETAILED_IN_CM), 153 154 /* LG 27GP950 */ 155 EDID_QUIRK('G', 'S', 'M', 0x5bbf, EDID_QUIRK_CAP_DSC_15BPP), 156 157 /* LG 27GN950 */ 158 EDID_QUIRK('G', 'S', 'M', 0x5b9a, EDID_QUIRK_CAP_DSC_15BPP), 159 160 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */ 161 EDID_QUIRK('L', 'G', 'D', 764, EDID_QUIRK_FORCE_10BPC), 162 163 /* LG Philips LCD LP154W01-A5 */ 164 EDID_QUIRK('L', 'P', 'L', 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE), 165 EDID_QUIRK('L', 'P', 'L', 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE), 166 167 /* Samsung SyncMaster 205BW. Note: irony */ 168 EDID_QUIRK('S', 'A', 'M', 541, EDID_QUIRK_DETAILED_SYNC_PP), 169 /* Samsung SyncMaster 22[5-6]BW */ 170 EDID_QUIRK('S', 'A', 'M', 596, EDID_QUIRK_PREFER_LARGE_60), 171 EDID_QUIRK('S', 'A', 'M', 638, EDID_QUIRK_PREFER_LARGE_60), 172 173 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */ 174 EDID_QUIRK('S', 'N', 'Y', 0x2541, EDID_QUIRK_FORCE_12BPC), 175 176 /* ViewSonic VA2026w */ 177 EDID_QUIRK('V', 'S', 'C', 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING), 178 179 /* Medion MD 30217 PG */ 180 EDID_QUIRK('M', 'E', 'D', 0x7b8, EDID_QUIRK_PREFER_LARGE_75), 181 182 /* Lenovo G50 */ 183 EDID_QUIRK('S', 'D', 'C', 18514, EDID_QUIRK_FORCE_6BPC), 184 185 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */ 186 EDID_QUIRK('S', 'E', 'C', 0xd033, EDID_QUIRK_FORCE_8BPC), 187 188 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/ 189 EDID_QUIRK('E', 'T', 'R', 13896, EDID_QUIRK_FORCE_8BPC), 190 191 /* Valve Index Headset */ 192 EDID_QUIRK('V', 'L', 'V', 0x91a8, EDID_QUIRK_NON_DESKTOP), 193 EDID_QUIRK('V', 'L', 'V', 0x91b0, EDID_QUIRK_NON_DESKTOP), 194 EDID_QUIRK('V', 'L', 'V', 0x91b1, EDID_QUIRK_NON_DESKTOP), 195 EDID_QUIRK('V', 'L', 'V', 0x91b2, EDID_QUIRK_NON_DESKTOP), 196 EDID_QUIRK('V', 'L', 'V', 0x91b3, EDID_QUIRK_NON_DESKTOP), 197 EDID_QUIRK('V', 'L', 'V', 0x91b4, EDID_QUIRK_NON_DESKTOP), 198 EDID_QUIRK('V', 'L', 'V', 0x91b5, EDID_QUIRK_NON_DESKTOP), 199 EDID_QUIRK('V', 'L', 'V', 0x91b6, EDID_QUIRK_NON_DESKTOP), 200 EDID_QUIRK('V', 'L', 'V', 0x91b7, EDID_QUIRK_NON_DESKTOP), 201 EDID_QUIRK('V', 'L', 'V', 0x91b8, EDID_QUIRK_NON_DESKTOP), 202 EDID_QUIRK('V', 'L', 'V', 0x91b9, EDID_QUIRK_NON_DESKTOP), 203 EDID_QUIRK('V', 'L', 'V', 0x91ba, EDID_QUIRK_NON_DESKTOP), 204 EDID_QUIRK('V', 'L', 'V', 0x91bb, EDID_QUIRK_NON_DESKTOP), 205 EDID_QUIRK('V', 'L', 'V', 0x91bc, EDID_QUIRK_NON_DESKTOP), 206 EDID_QUIRK('V', 'L', 'V', 0x91bd, EDID_QUIRK_NON_DESKTOP), 207 EDID_QUIRK('V', 'L', 'V', 0x91be, EDID_QUIRK_NON_DESKTOP), 208 EDID_QUIRK('V', 'L', 'V', 0x91bf, EDID_QUIRK_NON_DESKTOP), 209 210 /* HTC Vive and Vive Pro VR Headsets */ 211 EDID_QUIRK('H', 'V', 'R', 0xaa01, EDID_QUIRK_NON_DESKTOP), 212 EDID_QUIRK('H', 'V', 'R', 0xaa02, EDID_QUIRK_NON_DESKTOP), 213 214 /* Oculus Rift DK1, DK2, CV1 and Rift S VR Headsets */ 215 EDID_QUIRK('O', 'V', 'R', 0x0001, EDID_QUIRK_NON_DESKTOP), 216 EDID_QUIRK('O', 'V', 'R', 0x0003, EDID_QUIRK_NON_DESKTOP), 217 EDID_QUIRK('O', 'V', 'R', 0x0004, EDID_QUIRK_NON_DESKTOP), 218 EDID_QUIRK('O', 'V', 'R', 0x0012, EDID_QUIRK_NON_DESKTOP), 219 220 /* Windows Mixed Reality Headsets */ 221 EDID_QUIRK('A', 'C', 'R', 0x7fce, EDID_QUIRK_NON_DESKTOP), 222 EDID_QUIRK('L', 'E', 'N', 0x0408, EDID_QUIRK_NON_DESKTOP), 223 EDID_QUIRK('F', 'U', 'J', 0x1970, EDID_QUIRK_NON_DESKTOP), 224 EDID_QUIRK('D', 'E', 'L', 0x7fce, EDID_QUIRK_NON_DESKTOP), 225 EDID_QUIRK('S', 'E', 'C', 0x144a, EDID_QUIRK_NON_DESKTOP), 226 EDID_QUIRK('A', 'U', 'S', 0xc102, EDID_QUIRK_NON_DESKTOP), 227 228 /* Sony PlayStation VR Headset */ 229 EDID_QUIRK('S', 'N', 'Y', 0x0704, EDID_QUIRK_NON_DESKTOP), 230 231 /* Sensics VR Headsets */ 232 EDID_QUIRK('S', 'E', 'N', 0x1019, EDID_QUIRK_NON_DESKTOP), 233 234 /* OSVR HDK and HDK2 VR Headsets */ 235 EDID_QUIRK('S', 'V', 'R', 0x1019, EDID_QUIRK_NON_DESKTOP), 236 EDID_QUIRK('A', 'U', 'O', 0x1111, EDID_QUIRK_NON_DESKTOP), 237}; 238 239/* 240 * Autogenerated from the DMT spec. 241 * This table is copied from xfree86/modes/xf86EdidModes.c. 242 */ 243static const struct drm_display_mode drm_dmt_modes[] = { 244 /* 0x01 - 640x350@85Hz */ 245 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 246 736, 832, 0, 350, 382, 385, 445, 0, 247 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 248 /* 0x02 - 640x400@85Hz */ 249 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 250 736, 832, 0, 400, 401, 404, 445, 0, 251 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 252 /* 0x03 - 720x400@85Hz */ 253 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756, 254 828, 936, 0, 400, 401, 404, 446, 0, 255 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 256 /* 0x04 - 640x480@60Hz */ 257 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 258 752, 800, 0, 480, 490, 492, 525, 0, 259 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 260 /* 0x05 - 640x480@72Hz */ 261 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 262 704, 832, 0, 480, 489, 492, 520, 0, 263 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 264 /* 0x06 - 640x480@75Hz */ 265 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 266 720, 840, 0, 480, 481, 484, 500, 0, 267 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 268 /* 0x07 - 640x480@85Hz */ 269 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696, 270 752, 832, 0, 480, 481, 484, 509, 0, 271 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 272 /* 0x08 - 800x600@56Hz */ 273 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 274 896, 1024, 0, 600, 601, 603, 625, 0, 275 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 276 /* 0x09 - 800x600@60Hz */ 277 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 278 968, 1056, 0, 600, 601, 605, 628, 0, 279 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 280 /* 0x0a - 800x600@72Hz */ 281 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 282 976, 1040, 0, 600, 637, 643, 666, 0, 283 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 284 /* 0x0b - 800x600@75Hz */ 285 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 286 896, 1056, 0, 600, 601, 604, 625, 0, 287 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 288 /* 0x0c - 800x600@85Hz */ 289 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832, 290 896, 1048, 0, 600, 601, 604, 631, 0, 291 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 292 /* 0x0d - 800x600@120Hz RB */ 293 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848, 294 880, 960, 0, 600, 603, 607, 636, 0, 295 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 296 /* 0x0e - 848x480@60Hz */ 297 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864, 298 976, 1088, 0, 480, 486, 494, 517, 0, 299 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 300 /* 0x0f - 1024x768@43Hz, interlace */ 301 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 302 1208, 1264, 0, 768, 768, 776, 817, 0, 303 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 304 DRM_MODE_FLAG_INTERLACE) }, 305 /* 0x10 - 1024x768@60Hz */ 306 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 307 1184, 1344, 0, 768, 771, 777, 806, 0, 308 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 309 /* 0x11 - 1024x768@70Hz */ 310 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 311 1184, 1328, 0, 768, 771, 777, 806, 0, 312 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 313 /* 0x12 - 1024x768@75Hz */ 314 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 315 1136, 1312, 0, 768, 769, 772, 800, 0, 316 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 317 /* 0x13 - 1024x768@85Hz */ 318 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, 319 1168, 1376, 0, 768, 769, 772, 808, 0, 320 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 321 /* 0x14 - 1024x768@120Hz RB */ 322 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072, 323 1104, 1184, 0, 768, 771, 775, 813, 0, 324 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 325 /* 0x15 - 1152x864@75Hz */ 326 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 327 1344, 1600, 0, 864, 865, 868, 900, 0, 328 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 329 /* 0x55 - 1280x720@60Hz */ 330 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 331 1430, 1650, 0, 720, 725, 730, 750, 0, 332 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 333 /* 0x16 - 1280x768@60Hz RB */ 334 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328, 335 1360, 1440, 0, 768, 771, 778, 790, 0, 336 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 337 /* 0x17 - 1280x768@60Hz */ 338 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, 339 1472, 1664, 0, 768, 771, 778, 798, 0, 340 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 341 /* 0x18 - 1280x768@75Hz */ 342 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, 343 1488, 1696, 0, 768, 771, 778, 805, 0, 344 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 345 /* 0x19 - 1280x768@85Hz */ 346 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, 347 1496, 1712, 0, 768, 771, 778, 809, 0, 348 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 349 /* 0x1a - 1280x768@120Hz RB */ 350 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328, 351 1360, 1440, 0, 768, 771, 778, 813, 0, 352 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 353 /* 0x1b - 1280x800@60Hz RB */ 354 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328, 355 1360, 1440, 0, 800, 803, 809, 823, 0, 356 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 357 /* 0x1c - 1280x800@60Hz */ 358 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, 359 1480, 1680, 0, 800, 803, 809, 831, 0, 360 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 361 /* 0x1d - 1280x800@75Hz */ 362 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, 363 1488, 1696, 0, 800, 803, 809, 838, 0, 364 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 365 /* 0x1e - 1280x800@85Hz */ 366 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, 367 1496, 1712, 0, 800, 803, 809, 843, 0, 368 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 369 /* 0x1f - 1280x800@120Hz RB */ 370 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328, 371 1360, 1440, 0, 800, 803, 809, 847, 0, 372 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 373 /* 0x20 - 1280x960@60Hz */ 374 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, 375 1488, 1800, 0, 960, 961, 964, 1000, 0, 376 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 377 /* 0x21 - 1280x960@85Hz */ 378 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, 379 1504, 1728, 0, 960, 961, 964, 1011, 0, 380 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 381 /* 0x22 - 1280x960@120Hz RB */ 382 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328, 383 1360, 1440, 0, 960, 963, 967, 1017, 0, 384 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 385 /* 0x23 - 1280x1024@60Hz */ 386 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, 387 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 388 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 389 /* 0x24 - 1280x1024@75Hz */ 390 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 391 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 392 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 393 /* 0x25 - 1280x1024@85Hz */ 394 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, 395 1504, 1728, 0, 1024, 1025, 1028, 1072, 0, 396 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 397 /* 0x26 - 1280x1024@120Hz RB */ 398 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328, 399 1360, 1440, 0, 1024, 1027, 1034, 1084, 0, 400 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 401 /* 0x27 - 1360x768@60Hz */ 402 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, 403 1536, 1792, 0, 768, 771, 777, 795, 0, 404 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 405 /* 0x28 - 1360x768@120Hz RB */ 406 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408, 407 1440, 1520, 0, 768, 771, 776, 813, 0, 408 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 409 /* 0x51 - 1366x768@60Hz */ 410 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436, 411 1579, 1792, 0, 768, 771, 774, 798, 0, 412 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 413 /* 0x56 - 1366x768@60Hz */ 414 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380, 415 1436, 1500, 0, 768, 769, 772, 800, 0, 416 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 417 /* 0x29 - 1400x1050@60Hz RB */ 418 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448, 419 1480, 1560, 0, 1050, 1053, 1057, 1080, 0, 420 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 421 /* 0x2a - 1400x1050@60Hz */ 422 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, 423 1632, 1864, 0, 1050, 1053, 1057, 1089, 0, 424 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 425 /* 0x2b - 1400x1050@75Hz */ 426 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, 427 1648, 1896, 0, 1050, 1053, 1057, 1099, 0, 428 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 429 /* 0x2c - 1400x1050@85Hz */ 430 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, 431 1656, 1912, 0, 1050, 1053, 1057, 1105, 0, 432 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 433 /* 0x2d - 1400x1050@120Hz RB */ 434 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448, 435 1480, 1560, 0, 1050, 1053, 1057, 1112, 0, 436 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 437 /* 0x2e - 1440x900@60Hz RB */ 438 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488, 439 1520, 1600, 0, 900, 903, 909, 926, 0, 440 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 441 /* 0x2f - 1440x900@60Hz */ 442 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, 443 1672, 1904, 0, 900, 903, 909, 934, 0, 444 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 445 /* 0x30 - 1440x900@75Hz */ 446 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, 447 1688, 1936, 0, 900, 903, 909, 942, 0, 448 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 449 /* 0x31 - 1440x900@85Hz */ 450 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, 451 1696, 1952, 0, 900, 903, 909, 948, 0, 452 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 453 /* 0x32 - 1440x900@120Hz RB */ 454 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488, 455 1520, 1600, 0, 900, 903, 909, 953, 0, 456 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 457 /* 0x53 - 1600x900@60Hz */ 458 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624, 459 1704, 1800, 0, 900, 901, 904, 1000, 0, 460 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 461 /* 0x33 - 1600x1200@60Hz */ 462 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, 463 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 464 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 465 /* 0x34 - 1600x1200@65Hz */ 466 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, 467 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 468 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 469 /* 0x35 - 1600x1200@70Hz */ 470 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, 471 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 472 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 473 /* 0x36 - 1600x1200@75Hz */ 474 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664, 475 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 476 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 477 /* 0x37 - 1600x1200@85Hz */ 478 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, 479 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 480 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 481 /* 0x38 - 1600x1200@120Hz RB */ 482 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648, 483 1680, 1760, 0, 1200, 1203, 1207, 1271, 0, 484 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 485 /* 0x39 - 1680x1050@60Hz RB */ 486 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728, 487 1760, 1840, 0, 1050, 1053, 1059, 1080, 0, 488 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 489 /* 0x3a - 1680x1050@60Hz */ 490 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, 491 1960, 2240, 0, 1050, 1053, 1059, 1089, 0, 492 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 493 /* 0x3b - 1680x1050@75Hz */ 494 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, 495 1976, 2272, 0, 1050, 1053, 1059, 1099, 0, 496 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 497 /* 0x3c - 1680x1050@85Hz */ 498 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, 499 1984, 2288, 0, 1050, 1053, 1059, 1105, 0, 500 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 501 /* 0x3d - 1680x1050@120Hz RB */ 502 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728, 503 1760, 1840, 0, 1050, 1053, 1059, 1112, 0, 504 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 505 /* 0x3e - 1792x1344@60Hz */ 506 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, 507 2120, 2448, 0, 1344, 1345, 1348, 1394, 0, 508 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 509 /* 0x3f - 1792x1344@75Hz */ 510 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, 511 2104, 2456, 0, 1344, 1345, 1348, 1417, 0, 512 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 513 /* 0x40 - 1792x1344@120Hz RB */ 514 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840, 515 1872, 1952, 0, 1344, 1347, 1351, 1423, 0, 516 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 517 /* 0x41 - 1856x1392@60Hz */ 518 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, 519 2176, 2528, 0, 1392, 1393, 1396, 1439, 0, 520 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 521 /* 0x42 - 1856x1392@75Hz */ 522 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, 523 2208, 2560, 0, 1392, 1393, 1396, 1500, 0, 524 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 525 /* 0x43 - 1856x1392@120Hz RB */ 526 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904, 527 1936, 2016, 0, 1392, 1395, 1399, 1474, 0, 528 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 529 /* 0x52 - 1920x1080@60Hz */ 530 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 531 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 532 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 533 /* 0x44 - 1920x1200@60Hz RB */ 534 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968, 535 2000, 2080, 0, 1200, 1203, 1209, 1235, 0, 536 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 537 /* 0x45 - 1920x1200@60Hz */ 538 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, 539 2256, 2592, 0, 1200, 1203, 1209, 1245, 0, 540 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 541 /* 0x46 - 1920x1200@75Hz */ 542 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, 543 2264, 2608, 0, 1200, 1203, 1209, 1255, 0, 544 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 545 /* 0x47 - 1920x1200@85Hz */ 546 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, 547 2272, 2624, 0, 1200, 1203, 1209, 1262, 0, 548 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 549 /* 0x48 - 1920x1200@120Hz RB */ 550 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968, 551 2000, 2080, 0, 1200, 1203, 1209, 1271, 0, 552 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 553 /* 0x49 - 1920x1440@60Hz */ 554 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, 555 2256, 2600, 0, 1440, 1441, 1444, 1500, 0, 556 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 557 /* 0x4a - 1920x1440@75Hz */ 558 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, 559 2288, 2640, 0, 1440, 1441, 1444, 1500, 0, 560 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 561 /* 0x4b - 1920x1440@120Hz RB */ 562 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968, 563 2000, 2080, 0, 1440, 1443, 1447, 1525, 0, 564 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 565 /* 0x54 - 2048x1152@60Hz */ 566 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074, 567 2154, 2250, 0, 1152, 1153, 1156, 1200, 0, 568 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 569 /* 0x4c - 2560x1600@60Hz RB */ 570 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608, 571 2640, 2720, 0, 1600, 1603, 1609, 1646, 0, 572 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 573 /* 0x4d - 2560x1600@60Hz */ 574 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, 575 3032, 3504, 0, 1600, 1603, 1609, 1658, 0, 576 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 577 /* 0x4e - 2560x1600@75Hz */ 578 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, 579 3048, 3536, 0, 1600, 1603, 1609, 1672, 0, 580 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 581 /* 0x4f - 2560x1600@85Hz */ 582 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, 583 3048, 3536, 0, 1600, 1603, 1609, 1682, 0, 584 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 585 /* 0x50 - 2560x1600@120Hz RB */ 586 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608, 587 2640, 2720, 0, 1600, 1603, 1609, 1694, 0, 588 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 589 /* 0x57 - 4096x2160@60Hz RB */ 590 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104, 591 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 592 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 593 /* 0x58 - 4096x2160@59.94Hz RB */ 594 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104, 595 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 596 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 597}; 598 599/* 600 * These more or less come from the DMT spec. The 720x400 modes are 601 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75 602 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode 603 * should be 1152x870, again for the Mac, but instead we use the x864 DMT 604 * mode. 605 * 606 * The DMT modes have been fact-checked; the rest are mild guesses. 607 */ 608static const struct drm_display_mode edid_est_modes[] = { 609 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 610 968, 1056, 0, 600, 601, 605, 628, 0, 611 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */ 612 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 613 896, 1024, 0, 600, 601, 603, 625, 0, 614 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */ 615 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 616 720, 840, 0, 480, 481, 484, 500, 0, 617 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */ 618 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 619 704, 832, 0, 480, 489, 492, 520, 0, 620 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */ 621 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704, 622 768, 864, 0, 480, 483, 486, 525, 0, 623 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */ 624 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 625 752, 800, 0, 480, 490, 492, 525, 0, 626 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */ 627 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738, 628 846, 900, 0, 400, 421, 423, 449, 0, 629 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */ 630 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738, 631 846, 900, 0, 400, 412, 414, 449, 0, 632 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */ 633 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 634 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 635 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */ 636 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 637 1136, 1312, 0, 768, 769, 772, 800, 0, 638 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */ 639 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 640 1184, 1328, 0, 768, 771, 777, 806, 0, 641 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */ 642 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 643 1184, 1344, 0, 768, 771, 777, 806, 0, 644 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */ 645 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032, 646 1208, 1264, 0, 768, 768, 776, 817, 0, 647 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */ 648 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864, 649 928, 1152, 0, 624, 625, 628, 667, 0, 650 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */ 651 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 652 896, 1056, 0, 600, 601, 604, 625, 0, 653 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */ 654 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 655 976, 1040, 0, 600, 637, 643, 666, 0, 656 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */ 657 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 658 1344, 1600, 0, 864, 865, 868, 900, 0, 659 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */ 660}; 661 662struct minimode { 663 short w; 664 short h; 665 short r; 666 short rb; 667}; 668 669static const struct minimode est3_modes[] = { 670 /* byte 6 */ 671 { 640, 350, 85, 0 }, 672 { 640, 400, 85, 0 }, 673 { 720, 400, 85, 0 }, 674 { 640, 480, 85, 0 }, 675 { 848, 480, 60, 0 }, 676 { 800, 600, 85, 0 }, 677 { 1024, 768, 85, 0 }, 678 { 1152, 864, 75, 0 }, 679 /* byte 7 */ 680 { 1280, 768, 60, 1 }, 681 { 1280, 768, 60, 0 }, 682 { 1280, 768, 75, 0 }, 683 { 1280, 768, 85, 0 }, 684 { 1280, 960, 60, 0 }, 685 { 1280, 960, 85, 0 }, 686 { 1280, 1024, 60, 0 }, 687 { 1280, 1024, 85, 0 }, 688 /* byte 8 */ 689 { 1360, 768, 60, 0 }, 690 { 1440, 900, 60, 1 }, 691 { 1440, 900, 60, 0 }, 692 { 1440, 900, 75, 0 }, 693 { 1440, 900, 85, 0 }, 694 { 1400, 1050, 60, 1 }, 695 { 1400, 1050, 60, 0 }, 696 { 1400, 1050, 75, 0 }, 697 /* byte 9 */ 698 { 1400, 1050, 85, 0 }, 699 { 1680, 1050, 60, 1 }, 700 { 1680, 1050, 60, 0 }, 701 { 1680, 1050, 75, 0 }, 702 { 1680, 1050, 85, 0 }, 703 { 1600, 1200, 60, 0 }, 704 { 1600, 1200, 65, 0 }, 705 { 1600, 1200, 70, 0 }, 706 /* byte 10 */ 707 { 1600, 1200, 75, 0 }, 708 { 1600, 1200, 85, 0 }, 709 { 1792, 1344, 60, 0 }, 710 { 1792, 1344, 75, 0 }, 711 { 1856, 1392, 60, 0 }, 712 { 1856, 1392, 75, 0 }, 713 { 1920, 1200, 60, 1 }, 714 { 1920, 1200, 60, 0 }, 715 /* byte 11 */ 716 { 1920, 1200, 75, 0 }, 717 { 1920, 1200, 85, 0 }, 718 { 1920, 1440, 60, 0 }, 719 { 1920, 1440, 75, 0 }, 720}; 721 722static const struct minimode extra_modes[] = { 723 { 1024, 576, 60, 0 }, 724 { 1366, 768, 60, 0 }, 725 { 1600, 900, 60, 0 }, 726 { 1680, 945, 60, 0 }, 727 { 1920, 1080, 60, 0 }, 728 { 2048, 1152, 60, 0 }, 729 { 2048, 1536, 60, 0 }, 730}; 731 732/* 733 * From CEA/CTA-861 spec. 734 * 735 * Do not access directly, instead always use cea_mode_for_vic(). 736 */ 737static const struct drm_display_mode edid_cea_modes_1[] = { 738 /* 1 - 640x480@60Hz 4:3 */ 739 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 740 752, 800, 0, 480, 490, 492, 525, 0, 741 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 742 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 743 /* 2 - 720x480@60Hz 4:3 */ 744 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 745 798, 858, 0, 480, 489, 495, 525, 0, 746 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 747 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 748 /* 3 - 720x480@60Hz 16:9 */ 749 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 750 798, 858, 0, 480, 489, 495, 525, 0, 751 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 752 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 753 /* 4 - 1280x720@60Hz 16:9 */ 754 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 755 1430, 1650, 0, 720, 725, 730, 750, 0, 756 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 757 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 758 /* 5 - 1920x1080i@60Hz 16:9 */ 759 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 760 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 761 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 762 DRM_MODE_FLAG_INTERLACE), 763 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 764 /* 6 - 720(1440)x480i@60Hz 4:3 */ 765 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 766 801, 858, 0, 480, 488, 494, 525, 0, 767 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 768 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 769 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 770 /* 7 - 720(1440)x480i@60Hz 16:9 */ 771 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 772 801, 858, 0, 480, 488, 494, 525, 0, 773 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 774 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 775 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 776 /* 8 - 720(1440)x240@60Hz 4:3 */ 777 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 778 801, 858, 0, 240, 244, 247, 262, 0, 779 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 780 DRM_MODE_FLAG_DBLCLK), 781 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 782 /* 9 - 720(1440)x240@60Hz 16:9 */ 783 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 784 801, 858, 0, 240, 244, 247, 262, 0, 785 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 786 DRM_MODE_FLAG_DBLCLK), 787 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 788 /* 10 - 2880x480i@60Hz 4:3 */ 789 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 790 3204, 3432, 0, 480, 488, 494, 525, 0, 791 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 792 DRM_MODE_FLAG_INTERLACE), 793 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 794 /* 11 - 2880x480i@60Hz 16:9 */ 795 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 796 3204, 3432, 0, 480, 488, 494, 525, 0, 797 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 798 DRM_MODE_FLAG_INTERLACE), 799 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 800 /* 12 - 2880x240@60Hz 4:3 */ 801 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 802 3204, 3432, 0, 240, 244, 247, 262, 0, 803 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 804 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 805 /* 13 - 2880x240@60Hz 16:9 */ 806 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 807 3204, 3432, 0, 240, 244, 247, 262, 0, 808 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 809 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 810 /* 14 - 1440x480@60Hz 4:3 */ 811 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 812 1596, 1716, 0, 480, 489, 495, 525, 0, 813 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 814 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 815 /* 15 - 1440x480@60Hz 16:9 */ 816 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 817 1596, 1716, 0, 480, 489, 495, 525, 0, 818 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 819 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 820 /* 16 - 1920x1080@60Hz 16:9 */ 821 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 822 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 823 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 824 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 825 /* 17 - 720x576@50Hz 4:3 */ 826 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 827 796, 864, 0, 576, 581, 586, 625, 0, 828 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 829 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 830 /* 18 - 720x576@50Hz 16:9 */ 831 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 832 796, 864, 0, 576, 581, 586, 625, 0, 833 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 834 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 835 /* 19 - 1280x720@50Hz 16:9 */ 836 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 837 1760, 1980, 0, 720, 725, 730, 750, 0, 838 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 839 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 840 /* 20 - 1920x1080i@50Hz 16:9 */ 841 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 842 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 843 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 844 DRM_MODE_FLAG_INTERLACE), 845 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 846 /* 21 - 720(1440)x576i@50Hz 4:3 */ 847 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 848 795, 864, 0, 576, 580, 586, 625, 0, 849 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 850 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 851 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 852 /* 22 - 720(1440)x576i@50Hz 16:9 */ 853 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 854 795, 864, 0, 576, 580, 586, 625, 0, 855 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 856 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 857 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 858 /* 23 - 720(1440)x288@50Hz 4:3 */ 859 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 860 795, 864, 0, 288, 290, 293, 312, 0, 861 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 862 DRM_MODE_FLAG_DBLCLK), 863 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 864 /* 24 - 720(1440)x288@50Hz 16:9 */ 865 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 866 795, 864, 0, 288, 290, 293, 312, 0, 867 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 868 DRM_MODE_FLAG_DBLCLK), 869 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 870 /* 25 - 2880x576i@50Hz 4:3 */ 871 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 872 3180, 3456, 0, 576, 580, 586, 625, 0, 873 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 874 DRM_MODE_FLAG_INTERLACE), 875 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 876 /* 26 - 2880x576i@50Hz 16:9 */ 877 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 878 3180, 3456, 0, 576, 580, 586, 625, 0, 879 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 880 DRM_MODE_FLAG_INTERLACE), 881 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 882 /* 27 - 2880x288@50Hz 4:3 */ 883 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 884 3180, 3456, 0, 288, 290, 293, 312, 0, 885 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 886 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 887 /* 28 - 2880x288@50Hz 16:9 */ 888 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 889 3180, 3456, 0, 288, 290, 293, 312, 0, 890 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 891 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 892 /* 29 - 1440x576@50Hz 4:3 */ 893 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 894 1592, 1728, 0, 576, 581, 586, 625, 0, 895 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 896 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 897 /* 30 - 1440x576@50Hz 16:9 */ 898 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 899 1592, 1728, 0, 576, 581, 586, 625, 0, 900 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 901 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 902 /* 31 - 1920x1080@50Hz 16:9 */ 903 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 904 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 905 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 906 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 907 /* 32 - 1920x1080@24Hz 16:9 */ 908 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 909 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 910 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 911 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 912 /* 33 - 1920x1080@25Hz 16:9 */ 913 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 914 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 915 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 916 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 917 /* 34 - 1920x1080@30Hz 16:9 */ 918 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 919 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 920 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 921 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 922 /* 35 - 2880x480@60Hz 4:3 */ 923 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 924 3192, 3432, 0, 480, 489, 495, 525, 0, 925 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 926 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 927 /* 36 - 2880x480@60Hz 16:9 */ 928 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 929 3192, 3432, 0, 480, 489, 495, 525, 0, 930 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 931 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 932 /* 37 - 2880x576@50Hz 4:3 */ 933 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 934 3184, 3456, 0, 576, 581, 586, 625, 0, 935 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 936 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 937 /* 38 - 2880x576@50Hz 16:9 */ 938 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 939 3184, 3456, 0, 576, 581, 586, 625, 0, 940 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 941 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 942 /* 39 - 1920x1080i@50Hz 16:9 */ 943 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952, 944 2120, 2304, 0, 1080, 1126, 1136, 1250, 0, 945 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | 946 DRM_MODE_FLAG_INTERLACE), 947 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 948 /* 40 - 1920x1080i@100Hz 16:9 */ 949 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 950 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 951 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 952 DRM_MODE_FLAG_INTERLACE), 953 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 954 /* 41 - 1280x720@100Hz 16:9 */ 955 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 956 1760, 1980, 0, 720, 725, 730, 750, 0, 957 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 958 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 959 /* 42 - 720x576@100Hz 4:3 */ 960 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 961 796, 864, 0, 576, 581, 586, 625, 0, 962 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 963 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 964 /* 43 - 720x576@100Hz 16:9 */ 965 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 966 796, 864, 0, 576, 581, 586, 625, 0, 967 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 968 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 969 /* 44 - 720(1440)x576i@100Hz 4:3 */ 970 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 971 795, 864, 0, 576, 580, 586, 625, 0, 972 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 973 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 974 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 975 /* 45 - 720(1440)x576i@100Hz 16:9 */ 976 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 977 795, 864, 0, 576, 580, 586, 625, 0, 978 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 979 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 980 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 981 /* 46 - 1920x1080i@120Hz 16:9 */ 982 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 983 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 984 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 985 DRM_MODE_FLAG_INTERLACE), 986 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 987 /* 47 - 1280x720@120Hz 16:9 */ 988 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 989 1430, 1650, 0, 720, 725, 730, 750, 0, 990 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 991 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 992 /* 48 - 720x480@120Hz 4:3 */ 993 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 994 798, 858, 0, 480, 489, 495, 525, 0, 995 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 996 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 997 /* 49 - 720x480@120Hz 16:9 */ 998 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 999 798, 858, 0, 480, 489, 495, 525, 0, 1000 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1001 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1002 /* 50 - 720(1440)x480i@120Hz 4:3 */ 1003 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 1004 801, 858, 0, 480, 488, 494, 525, 0, 1005 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1006 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1007 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1008 /* 51 - 720(1440)x480i@120Hz 16:9 */ 1009 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 1010 801, 858, 0, 480, 488, 494, 525, 0, 1011 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1012 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1013 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1014 /* 52 - 720x576@200Hz 4:3 */ 1015 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 1016 796, 864, 0, 576, 581, 586, 625, 0, 1017 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1018 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1019 /* 53 - 720x576@200Hz 16:9 */ 1020 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 1021 796, 864, 0, 576, 581, 586, 625, 0, 1022 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1023 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1024 /* 54 - 720(1440)x576i@200Hz 4:3 */ 1025 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 1026 795, 864, 0, 576, 580, 586, 625, 0, 1027 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1028 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1029 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1030 /* 55 - 720(1440)x576i@200Hz 16:9 */ 1031 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 1032 795, 864, 0, 576, 580, 586, 625, 0, 1033 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1034 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1035 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1036 /* 56 - 720x480@240Hz 4:3 */ 1037 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 1038 798, 858, 0, 480, 489, 495, 525, 0, 1039 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1040 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1041 /* 57 - 720x480@240Hz 16:9 */ 1042 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 1043 798, 858, 0, 480, 489, 495, 525, 0, 1044 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1045 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1046 /* 58 - 720(1440)x480i@240Hz 4:3 */ 1047 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 1048 801, 858, 0, 480, 488, 494, 525, 0, 1049 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1050 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1051 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1052 /* 59 - 720(1440)x480i@240Hz 16:9 */ 1053 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 1054 801, 858, 0, 480, 488, 494, 525, 0, 1055 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1056 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1057 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1058 /* 60 - 1280x720@24Hz 16:9 */ 1059 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1060 3080, 3300, 0, 720, 725, 730, 750, 0, 1061 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1062 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1063 /* 61 - 1280x720@25Hz 16:9 */ 1064 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1065 3740, 3960, 0, 720, 725, 730, 750, 0, 1066 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1067 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1068 /* 62 - 1280x720@30Hz 16:9 */ 1069 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1070 3080, 3300, 0, 720, 725, 730, 750, 0, 1071 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1072 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1073 /* 63 - 1920x1080@120Hz 16:9 */ 1074 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1075 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1076 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1077 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1078 /* 64 - 1920x1080@100Hz 16:9 */ 1079 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1080 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1081 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1082 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1083 /* 65 - 1280x720@24Hz 64:27 */ 1084 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1085 3080, 3300, 0, 720, 725, 730, 750, 0, 1086 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1087 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1088 /* 66 - 1280x720@25Hz 64:27 */ 1089 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1090 3740, 3960, 0, 720, 725, 730, 750, 0, 1091 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1092 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1093 /* 67 - 1280x720@30Hz 64:27 */ 1094 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1095 3080, 3300, 0, 720, 725, 730, 750, 0, 1096 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1097 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1098 /* 68 - 1280x720@50Hz 64:27 */ 1099 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 1100 1760, 1980, 0, 720, 725, 730, 750, 0, 1101 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1102 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1103 /* 69 - 1280x720@60Hz 64:27 */ 1104 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 1105 1430, 1650, 0, 720, 725, 730, 750, 0, 1106 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1107 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1108 /* 70 - 1280x720@100Hz 64:27 */ 1109 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 1110 1760, 1980, 0, 720, 725, 730, 750, 0, 1111 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1112 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1113 /* 71 - 1280x720@120Hz 64:27 */ 1114 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 1115 1430, 1650, 0, 720, 725, 730, 750, 0, 1116 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1117 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1118 /* 72 - 1920x1080@24Hz 64:27 */ 1119 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 1120 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1121 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1122 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1123 /* 73 - 1920x1080@25Hz 64:27 */ 1124 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 1125 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1126 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1127 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1128 /* 74 - 1920x1080@30Hz 64:27 */ 1129 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 1130 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1131 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1132 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1133 /* 75 - 1920x1080@50Hz 64:27 */ 1134 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 1135 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1136 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1137 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1138 /* 76 - 1920x1080@60Hz 64:27 */ 1139 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 1140 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1141 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1142 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1143 /* 77 - 1920x1080@100Hz 64:27 */ 1144 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1145 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1146 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1147 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1148 /* 78 - 1920x1080@120Hz 64:27 */ 1149 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1150 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1151 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1152 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1153 /* 79 - 1680x720@24Hz 64:27 */ 1154 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040, 1155 3080, 3300, 0, 720, 725, 730, 750, 0, 1156 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1157 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1158 /* 80 - 1680x720@25Hz 64:27 */ 1159 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908, 1160 2948, 3168, 0, 720, 725, 730, 750, 0, 1161 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1162 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1163 /* 81 - 1680x720@30Hz 64:27 */ 1164 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380, 1165 2420, 2640, 0, 720, 725, 730, 750, 0, 1166 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1167 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1168 /* 82 - 1680x720@50Hz 64:27 */ 1169 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940, 1170 1980, 2200, 0, 720, 725, 730, 750, 0, 1171 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1172 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1173 /* 83 - 1680x720@60Hz 64:27 */ 1174 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940, 1175 1980, 2200, 0, 720, 725, 730, 750, 0, 1176 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1177 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1178 /* 84 - 1680x720@100Hz 64:27 */ 1179 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740, 1180 1780, 2000, 0, 720, 725, 730, 825, 0, 1181 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1182 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1183 /* 85 - 1680x720@120Hz 64:27 */ 1184 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740, 1185 1780, 2000, 0, 720, 725, 730, 825, 0, 1186 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1187 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1188 /* 86 - 2560x1080@24Hz 64:27 */ 1189 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558, 1190 3602, 3750, 0, 1080, 1084, 1089, 1100, 0, 1191 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1192 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1193 /* 87 - 2560x1080@25Hz 64:27 */ 1194 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008, 1195 3052, 3200, 0, 1080, 1084, 1089, 1125, 0, 1196 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1197 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1198 /* 88 - 2560x1080@30Hz 64:27 */ 1199 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328, 1200 3372, 3520, 0, 1080, 1084, 1089, 1125, 0, 1201 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1202 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1203 /* 89 - 2560x1080@50Hz 64:27 */ 1204 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108, 1205 3152, 3300, 0, 1080, 1084, 1089, 1125, 0, 1206 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1207 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1208 /* 90 - 2560x1080@60Hz 64:27 */ 1209 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808, 1210 2852, 3000, 0, 1080, 1084, 1089, 1100, 0, 1211 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1212 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1213 /* 91 - 2560x1080@100Hz 64:27 */ 1214 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778, 1215 2822, 2970, 0, 1080, 1084, 1089, 1250, 0, 1216 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1217 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1218 /* 92 - 2560x1080@120Hz 64:27 */ 1219 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108, 1220 3152, 3300, 0, 1080, 1084, 1089, 1250, 0, 1221 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1222 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1223 /* 93 - 3840x2160@24Hz 16:9 */ 1224 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1225 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1226 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1227 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1228 /* 94 - 3840x2160@25Hz 16:9 */ 1229 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1230 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1231 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1232 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1233 /* 95 - 3840x2160@30Hz 16:9 */ 1234 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1235 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1236 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1237 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1238 /* 96 - 3840x2160@50Hz 16:9 */ 1239 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1240 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1241 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1242 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1243 /* 97 - 3840x2160@60Hz 16:9 */ 1244 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1245 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1246 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1247 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1248 /* 98 - 4096x2160@24Hz 256:135 */ 1249 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116, 1250 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1251 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1252 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1253 /* 99 - 4096x2160@25Hz 256:135 */ 1254 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064, 1255 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1256 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1257 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1258 /* 100 - 4096x2160@30Hz 256:135 */ 1259 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184, 1260 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1261 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1262 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1263 /* 101 - 4096x2160@50Hz 256:135 */ 1264 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064, 1265 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1266 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1267 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1268 /* 102 - 4096x2160@60Hz 256:135 */ 1269 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184, 1270 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1271 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1272 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1273 /* 103 - 3840x2160@24Hz 64:27 */ 1274 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1275 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1276 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1277 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1278 /* 104 - 3840x2160@25Hz 64:27 */ 1279 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1280 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1281 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1282 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1283 /* 105 - 3840x2160@30Hz 64:27 */ 1284 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1285 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1286 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1287 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1288 /* 106 - 3840x2160@50Hz 64:27 */ 1289 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1290 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1291 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1292 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1293 /* 107 - 3840x2160@60Hz 64:27 */ 1294 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1295 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1296 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1297 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1298 /* 108 - 1280x720@48Hz 16:9 */ 1299 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240, 1300 2280, 2500, 0, 720, 725, 730, 750, 0, 1301 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1302 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1303 /* 109 - 1280x720@48Hz 64:27 */ 1304 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240, 1305 2280, 2500, 0, 720, 725, 730, 750, 0, 1306 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1307 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1308 /* 110 - 1680x720@48Hz 64:27 */ 1309 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490, 1310 2530, 2750, 0, 720, 725, 730, 750, 0, 1311 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1312 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1313 /* 111 - 1920x1080@48Hz 16:9 */ 1314 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558, 1315 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1316 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1317 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1318 /* 112 - 1920x1080@48Hz 64:27 */ 1319 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558, 1320 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1321 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1322 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1323 /* 113 - 2560x1080@48Hz 64:27 */ 1324 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558, 1325 3602, 3750, 0, 1080, 1084, 1089, 1100, 0, 1326 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1327 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1328 /* 114 - 3840x2160@48Hz 16:9 */ 1329 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116, 1330 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1331 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1332 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1333 /* 115 - 4096x2160@48Hz 256:135 */ 1334 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116, 1335 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1336 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1337 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1338 /* 116 - 3840x2160@48Hz 64:27 */ 1339 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116, 1340 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1341 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1342 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1343 /* 117 - 3840x2160@100Hz 16:9 */ 1344 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896, 1345 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1346 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1347 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1348 /* 118 - 3840x2160@120Hz 16:9 */ 1349 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016, 1350 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1351 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1352 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1353 /* 119 - 3840x2160@100Hz 64:27 */ 1354 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896, 1355 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1356 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1357 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1358 /* 120 - 3840x2160@120Hz 64:27 */ 1359 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016, 1360 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1361 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1362 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1363 /* 121 - 5120x2160@24Hz 64:27 */ 1364 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116, 1365 7204, 7500, 0, 2160, 2168, 2178, 2200, 0, 1366 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1367 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1368 /* 122 - 5120x2160@25Hz 64:27 */ 1369 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816, 1370 6904, 7200, 0, 2160, 2168, 2178, 2200, 0, 1371 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1372 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1373 /* 123 - 5120x2160@30Hz 64:27 */ 1374 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784, 1375 5872, 6000, 0, 2160, 2168, 2178, 2200, 0, 1376 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1377 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1378 /* 124 - 5120x2160@48Hz 64:27 */ 1379 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866, 1380 5954, 6250, 0, 2160, 2168, 2178, 2475, 0, 1381 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1382 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1383 /* 125 - 5120x2160@50Hz 64:27 */ 1384 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216, 1385 6304, 6600, 0, 2160, 2168, 2178, 2250, 0, 1386 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1387 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1388 /* 126 - 5120x2160@60Hz 64:27 */ 1389 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284, 1390 5372, 5500, 0, 2160, 2168, 2178, 2250, 0, 1391 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1392 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1393 /* 127 - 5120x2160@100Hz 64:27 */ 1394 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216, 1395 6304, 6600, 0, 2160, 2168, 2178, 2250, 0, 1396 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1397 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1398}; 1399 1400/* 1401 * From CEA/CTA-861 spec. 1402 * 1403 * Do not access directly, instead always use cea_mode_for_vic(). 1404 */ 1405static const struct drm_display_mode edid_cea_modes_193[] = { 1406 /* 193 - 5120x2160@120Hz 64:27 */ 1407 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284, 1408 5372, 5500, 0, 2160, 2168, 2178, 2250, 0, 1409 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1410 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1411 /* 194 - 7680x4320@24Hz 16:9 */ 1412 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232, 1413 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1414 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1415 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1416 /* 195 - 7680x4320@25Hz 16:9 */ 1417 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032, 1418 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1419 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1420 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1421 /* 196 - 7680x4320@30Hz 16:9 */ 1422 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232, 1423 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1424 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1425 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1426 /* 197 - 7680x4320@48Hz 16:9 */ 1427 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232, 1428 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1429 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1430 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1431 /* 198 - 7680x4320@50Hz 16:9 */ 1432 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032, 1433 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1434 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1435 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1436 /* 199 - 7680x4320@60Hz 16:9 */ 1437 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232, 1438 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1439 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1440 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1441 /* 200 - 7680x4320@100Hz 16:9 */ 1442 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792, 1443 9968, 10560, 0, 4320, 4336, 4356, 4500, 0, 1444 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1445 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1446 /* 201 - 7680x4320@120Hz 16:9 */ 1447 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032, 1448 8208, 8800, 0, 4320, 4336, 4356, 4500, 0, 1449 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1450 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1451 /* 202 - 7680x4320@24Hz 64:27 */ 1452 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232, 1453 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1454 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1455 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1456 /* 203 - 7680x4320@25Hz 64:27 */ 1457 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032, 1458 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1459 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1460 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1461 /* 204 - 7680x4320@30Hz 64:27 */ 1462 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232, 1463 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1464 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1465 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1466 /* 205 - 7680x4320@48Hz 64:27 */ 1467 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232, 1468 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1469 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1470 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1471 /* 206 - 7680x4320@50Hz 64:27 */ 1472 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032, 1473 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1474 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1475 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1476 /* 207 - 7680x4320@60Hz 64:27 */ 1477 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232, 1478 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1479 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1480 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1481 /* 208 - 7680x4320@100Hz 64:27 */ 1482 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792, 1483 9968, 10560, 0, 4320, 4336, 4356, 4500, 0, 1484 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1485 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1486 /* 209 - 7680x4320@120Hz 64:27 */ 1487 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032, 1488 8208, 8800, 0, 4320, 4336, 4356, 4500, 0, 1489 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1490 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1491 /* 210 - 10240x4320@24Hz 64:27 */ 1492 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732, 1493 11908, 12500, 0, 4320, 4336, 4356, 4950, 0, 1494 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1495 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1496 /* 211 - 10240x4320@25Hz 64:27 */ 1497 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732, 1498 12908, 13500, 0, 4320, 4336, 4356, 4400, 0, 1499 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1500 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1501 /* 212 - 10240x4320@30Hz 64:27 */ 1502 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528, 1503 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1504 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1505 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1506 /* 213 - 10240x4320@48Hz 64:27 */ 1507 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732, 1508 11908, 12500, 0, 4320, 4336, 4356, 4950, 0, 1509 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1510 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1511 /* 214 - 10240x4320@50Hz 64:27 */ 1512 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732, 1513 12908, 13500, 0, 4320, 4336, 4356, 4400, 0, 1514 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1515 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1516 /* 215 - 10240x4320@60Hz 64:27 */ 1517 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528, 1518 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1519 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1520 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1521 /* 216 - 10240x4320@100Hz 64:27 */ 1522 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432, 1523 12608, 13200, 0, 4320, 4336, 4356, 4500, 0, 1524 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1525 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1526 /* 217 - 10240x4320@120Hz 64:27 */ 1527 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528, 1528 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1529 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1530 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1531 /* 218 - 4096x2160@100Hz 256:135 */ 1532 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896, 1533 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1534 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1535 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1536 /* 219 - 4096x2160@120Hz 256:135 */ 1537 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184, 1538 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1539 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1540 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1541}; 1542 1543/* 1544 * HDMI 1.4 4k modes. Index using the VIC. 1545 */ 1546static const struct drm_display_mode edid_4k_modes[] = { 1547 /* 0 - dummy, VICs start at 1 */ 1548 { }, 1549 /* 1 - 3840x2160@30Hz */ 1550 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1551 3840, 4016, 4104, 4400, 0, 1552 2160, 2168, 2178, 2250, 0, 1553 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1554 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1555 /* 2 - 3840x2160@25Hz */ 1556 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1557 3840, 4896, 4984, 5280, 0, 1558 2160, 2168, 2178, 2250, 0, 1559 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1560 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1561 /* 3 - 3840x2160@24Hz */ 1562 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1563 3840, 5116, 5204, 5500, 0, 1564 2160, 2168, 2178, 2250, 0, 1565 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1566 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1567 /* 4 - 4096x2160@24Hz (SMPTE) */ 1568 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 1569 4096, 5116, 5204, 5500, 0, 1570 2160, 2168, 2178, 2250, 0, 1571 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1572 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1573}; 1574 1575/*** DDC fetch and block validation ***/ 1576 1577/* 1578 * The opaque EDID type, internal to drm_edid.c. 1579 */ 1580struct drm_edid { 1581 /* Size allocated for edid */ 1582 size_t size; 1583 const struct edid *edid; 1584}; 1585 1586static int edid_hfeeodb_extension_block_count(const struct edid *edid); 1587 1588static int edid_hfeeodb_block_count(const struct edid *edid) 1589{ 1590 int eeodb = edid_hfeeodb_extension_block_count(edid); 1591 1592 return eeodb ? eeodb + 1 : 0; 1593} 1594 1595static int edid_extension_block_count(const struct edid *edid) 1596{ 1597 return edid->extensions; 1598} 1599 1600static int edid_block_count(const struct edid *edid) 1601{ 1602 return edid_extension_block_count(edid) + 1; 1603} 1604 1605static int edid_size_by_blocks(int num_blocks) 1606{ 1607 return num_blocks * EDID_LENGTH; 1608} 1609 1610static int edid_size(const struct edid *edid) 1611{ 1612 return edid_size_by_blocks(edid_block_count(edid)); 1613} 1614 1615static const void *edid_block_data(const struct edid *edid, int index) 1616{ 1617 BUILD_BUG_ON(sizeof(*edid) != EDID_LENGTH); 1618 1619 return edid + index; 1620} 1621 1622static const void *edid_extension_block_data(const struct edid *edid, int index) 1623{ 1624 return edid_block_data(edid, index + 1); 1625} 1626 1627/* EDID block count indicated in EDID, may exceed allocated size */ 1628static int __drm_edid_block_count(const struct drm_edid *drm_edid) 1629{ 1630 int num_blocks; 1631 1632 /* Starting point */ 1633 num_blocks = edid_block_count(drm_edid->edid); 1634 1635 /* HF-EEODB override */ 1636 if (drm_edid->size >= edid_size_by_blocks(2)) { 1637 int eeodb; 1638 1639 /* 1640 * Note: HF-EEODB may specify a smaller extension count than the 1641 * regular one. Unlike in buffer allocation, here we can use it. 1642 */ 1643 eeodb = edid_hfeeodb_block_count(drm_edid->edid); 1644 if (eeodb) 1645 num_blocks = eeodb; 1646 } 1647 1648 return num_blocks; 1649} 1650 1651/* EDID block count, limited by allocated size */ 1652static int drm_edid_block_count(const struct drm_edid *drm_edid) 1653{ 1654 /* Limit by allocated size */ 1655 return min(__drm_edid_block_count(drm_edid), 1656 (int)drm_edid->size / EDID_LENGTH); 1657} 1658 1659/* EDID extension block count, limited by allocated size */ 1660static int drm_edid_extension_block_count(const struct drm_edid *drm_edid) 1661{ 1662 return drm_edid_block_count(drm_edid) - 1; 1663} 1664 1665static const void *drm_edid_block_data(const struct drm_edid *drm_edid, int index) 1666{ 1667 return edid_block_data(drm_edid->edid, index); 1668} 1669 1670static const void *drm_edid_extension_block_data(const struct drm_edid *drm_edid, 1671 int index) 1672{ 1673 return edid_extension_block_data(drm_edid->edid, index); 1674} 1675 1676/* 1677 * Initializer helper for legacy interfaces, where we have no choice but to 1678 * trust edid size. Not for general purpose use. 1679 */ 1680static const struct drm_edid *drm_edid_legacy_init(struct drm_edid *drm_edid, 1681 const struct edid *edid) 1682{ 1683 if (!edid) 1684 return NULL; 1685 1686 memset(drm_edid, 0, sizeof(*drm_edid)); 1687 1688 drm_edid->edid = edid; 1689 drm_edid->size = edid_size(edid); 1690 1691 return drm_edid; 1692} 1693 1694/* 1695 * EDID base and extension block iterator. 1696 * 1697 * struct drm_edid_iter iter; 1698 * const u8 *block; 1699 * 1700 * drm_edid_iter_begin(drm_edid, &iter); 1701 * drm_edid_iter_for_each(block, &iter) { 1702 * // do stuff with block 1703 * } 1704 * drm_edid_iter_end(&iter); 1705 */ 1706struct drm_edid_iter { 1707 const struct drm_edid *drm_edid; 1708 1709 /* Current block index. */ 1710 int index; 1711}; 1712 1713static void drm_edid_iter_begin(const struct drm_edid *drm_edid, 1714 struct drm_edid_iter *iter) 1715{ 1716 memset(iter, 0, sizeof(*iter)); 1717 1718 iter->drm_edid = drm_edid; 1719} 1720 1721static const void *__drm_edid_iter_next(struct drm_edid_iter *iter) 1722{ 1723 const void *block = NULL; 1724 1725 if (!iter->drm_edid) 1726 return NULL; 1727 1728 if (iter->index < drm_edid_block_count(iter->drm_edid)) 1729 block = drm_edid_block_data(iter->drm_edid, iter->index++); 1730 1731 return block; 1732} 1733 1734#define drm_edid_iter_for_each(__block, __iter) \ 1735 while (((__block) = __drm_edid_iter_next(__iter))) 1736 1737static void drm_edid_iter_end(struct drm_edid_iter *iter) 1738{ 1739 memset(iter, 0, sizeof(*iter)); 1740} 1741 1742static const u8 edid_header[] = { 1743 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 1744}; 1745 1746static void edid_header_fix(void *edid) 1747{ 1748 memcpy(edid, edid_header, sizeof(edid_header)); 1749} 1750 1751/** 1752 * drm_edid_header_is_valid - sanity check the header of the base EDID block 1753 * @_edid: pointer to raw base EDID block 1754 * 1755 * Sanity check the header of the base EDID block. 1756 * 1757 * Return: 8 if the header is perfect, down to 0 if it's totally wrong. 1758 */ 1759int drm_edid_header_is_valid(const void *_edid) 1760{ 1761 const struct edid *edid = _edid; 1762 int i, score = 0; 1763 1764 for (i = 0; i < sizeof(edid_header); i++) { 1765 if (edid->header[i] == edid_header[i]) 1766 score++; 1767 } 1768 1769 return score; 1770} 1771EXPORT_SYMBOL(drm_edid_header_is_valid); 1772 1773static int edid_fixup __read_mostly = 6; 1774module_param_named(edid_fixup, edid_fixup, int, 0400); 1775MODULE_PARM_DESC(edid_fixup, 1776 "Minimum number of valid EDID header bytes (0-8, default 6)"); 1777 1778static int edid_block_compute_checksum(const void *_block) 1779{ 1780 const u8 *block = _block; 1781 int i; 1782 u8 csum = 0, crc = 0; 1783 1784 for (i = 0; i < EDID_LENGTH - 1; i++) 1785 csum += block[i]; 1786 1787 crc = 0x100 - csum; 1788 1789 return crc; 1790} 1791 1792static int edid_block_get_checksum(const void *_block) 1793{ 1794 const struct edid *block = _block; 1795 1796 return block->checksum; 1797} 1798 1799static int edid_block_tag(const void *_block) 1800{ 1801 const u8 *block = _block; 1802 1803 return block[0]; 1804} 1805 1806static bool edid_block_is_zero(const void *edid) 1807{ 1808 return !memchr_inv(edid, 0, EDID_LENGTH); 1809} 1810 1811/** 1812 * drm_edid_are_equal - compare two edid blobs. 1813 * @edid1: pointer to first blob 1814 * @edid2: pointer to second blob 1815 * This helper can be used during probing to determine if 1816 * edid had changed. 1817 */ 1818bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2) 1819{ 1820 int edid1_len, edid2_len; 1821 bool edid1_present = edid1 != NULL; 1822 bool edid2_present = edid2 != NULL; 1823 1824 if (edid1_present != edid2_present) 1825 return false; 1826 1827 if (edid1) { 1828 edid1_len = edid_size(edid1); 1829 edid2_len = edid_size(edid2); 1830 1831 if (edid1_len != edid2_len) 1832 return false; 1833 1834 if (memcmp(edid1, edid2, edid1_len)) 1835 return false; 1836 } 1837 1838 return true; 1839} 1840EXPORT_SYMBOL(drm_edid_are_equal); 1841 1842enum edid_block_status { 1843 EDID_BLOCK_OK = 0, 1844 EDID_BLOCK_READ_FAIL, 1845 EDID_BLOCK_NULL, 1846 EDID_BLOCK_ZERO, 1847 EDID_BLOCK_HEADER_CORRUPT, 1848 EDID_BLOCK_HEADER_REPAIR, 1849 EDID_BLOCK_HEADER_FIXED, 1850 EDID_BLOCK_CHECKSUM, 1851 EDID_BLOCK_VERSION, 1852}; 1853 1854static enum edid_block_status edid_block_check(const void *_block, 1855 bool is_base_block) 1856{ 1857 const struct edid *block = _block; 1858 1859 if (!block) 1860 return EDID_BLOCK_NULL; 1861 1862 if (is_base_block) { 1863 int score = drm_edid_header_is_valid(block); 1864 1865 if (score < clamp(edid_fixup, 0, 8)) { 1866 if (edid_block_is_zero(block)) 1867 return EDID_BLOCK_ZERO; 1868 else 1869 return EDID_BLOCK_HEADER_CORRUPT; 1870 } 1871 1872 if (score < 8) 1873 return EDID_BLOCK_HEADER_REPAIR; 1874 } 1875 1876 if (edid_block_compute_checksum(block) != edid_block_get_checksum(block)) { 1877 if (edid_block_is_zero(block)) 1878 return EDID_BLOCK_ZERO; 1879 else 1880 return EDID_BLOCK_CHECKSUM; 1881 } 1882 1883 if (is_base_block) { 1884 if (block->version != 1) 1885 return EDID_BLOCK_VERSION; 1886 } 1887 1888 return EDID_BLOCK_OK; 1889} 1890 1891static bool edid_block_status_valid(enum edid_block_status status, int tag) 1892{ 1893 return status == EDID_BLOCK_OK || 1894 status == EDID_BLOCK_HEADER_FIXED || 1895 (status == EDID_BLOCK_CHECKSUM && tag == CEA_EXT); 1896} 1897 1898static bool edid_block_valid(const void *block, bool base) 1899{ 1900 return edid_block_status_valid(edid_block_check(block, base), 1901 edid_block_tag(block)); 1902} 1903 1904static void edid_block_status_print(enum edid_block_status status, 1905 const struct edid *block, 1906 int block_num) 1907{ 1908 switch (status) { 1909 case EDID_BLOCK_OK: 1910 break; 1911 case EDID_BLOCK_READ_FAIL: 1912 pr_debug("EDID block %d read failed\n", block_num); 1913 break; 1914 case EDID_BLOCK_NULL: 1915 pr_debug("EDID block %d pointer is NULL\n", block_num); 1916 break; 1917 case EDID_BLOCK_ZERO: 1918 pr_notice("EDID block %d is all zeroes\n", block_num); 1919 break; 1920 case EDID_BLOCK_HEADER_CORRUPT: 1921 pr_notice("EDID has corrupt header\n"); 1922 break; 1923 case EDID_BLOCK_HEADER_REPAIR: 1924 pr_debug("EDID corrupt header needs repair\n"); 1925 break; 1926 case EDID_BLOCK_HEADER_FIXED: 1927 pr_debug("EDID corrupt header fixed\n"); 1928 break; 1929 case EDID_BLOCK_CHECKSUM: 1930 if (edid_block_status_valid(status, edid_block_tag(block))) { 1931 pr_debug("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d, ignoring\n", 1932 block_num, edid_block_tag(block), 1933 edid_block_compute_checksum(block)); 1934 } else { 1935 pr_notice("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d\n", 1936 block_num, edid_block_tag(block), 1937 edid_block_compute_checksum(block)); 1938 } 1939 break; 1940 case EDID_BLOCK_VERSION: 1941 pr_notice("EDID has major version %d, instead of 1\n", 1942 block->version); 1943 break; 1944 default: 1945 WARN(1, "EDID block %d unknown edid block status code %d\n", 1946 block_num, status); 1947 break; 1948 } 1949} 1950 1951static void edid_block_dump(const char *level, const void *block, int block_num) 1952{ 1953 enum edid_block_status status; 1954 char prefix[20]; 1955 1956 status = edid_block_check(block, block_num == 0); 1957 if (status == EDID_BLOCK_ZERO) 1958 sprintf(prefix, "\t[%02x] ZERO ", block_num); 1959 else if (!edid_block_status_valid(status, edid_block_tag(block))) 1960 sprintf(prefix, "\t[%02x] BAD ", block_num); 1961 else 1962 sprintf(prefix, "\t[%02x] GOOD ", block_num); 1963 1964 print_hex_dump(level, prefix, DUMP_PREFIX_NONE, 16, 1, 1965 block, EDID_LENGTH, false); 1966} 1967 1968/** 1969 * drm_edid_block_valid - Sanity check the EDID block (base or extension) 1970 * @_block: pointer to raw EDID block 1971 * @block_num: type of block to validate (0 for base, extension otherwise) 1972 * @print_bad_edid: if true, dump bad EDID blocks to the console 1973 * @edid_corrupt: if true, the header or checksum is invalid 1974 * 1975 * Validate a base or extension EDID block and optionally dump bad blocks to 1976 * the console. 1977 * 1978 * Return: True if the block is valid, false otherwise. 1979 */ 1980bool drm_edid_block_valid(u8 *_block, int block_num, bool print_bad_edid, 1981 bool *edid_corrupt) 1982{ 1983 struct edid *block = (struct edid *)_block; 1984 enum edid_block_status status; 1985 bool is_base_block = block_num == 0; 1986 bool valid; 1987 1988 if (WARN_ON(!block)) 1989 return false; 1990 1991 status = edid_block_check(block, is_base_block); 1992 if (status == EDID_BLOCK_HEADER_REPAIR) { 1993 DRM_DEBUG_KMS("Fixing EDID header, your hardware may be failing\n"); 1994 edid_header_fix(block); 1995 1996 /* Retry with fixed header, update status if that worked. */ 1997 status = edid_block_check(block, is_base_block); 1998 if (status == EDID_BLOCK_OK) 1999 status = EDID_BLOCK_HEADER_FIXED; 2000 } 2001 2002 if (edid_corrupt) { 2003 /* 2004 * Unknown major version isn't corrupt but we can't use it. Only 2005 * the base block can reset edid_corrupt to false. 2006 */ 2007 if (is_base_block && 2008 (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION)) 2009 *edid_corrupt = false; 2010 else if (status != EDID_BLOCK_OK) 2011 *edid_corrupt = true; 2012 } 2013 2014 edid_block_status_print(status, block, block_num); 2015 2016 /* Determine whether we can use this block with this status. */ 2017 valid = edid_block_status_valid(status, edid_block_tag(block)); 2018 2019 if (!valid && print_bad_edid && status != EDID_BLOCK_ZERO) { 2020 pr_notice("Raw EDID:\n"); 2021 edid_block_dump(KERN_NOTICE, block, block_num); 2022 } 2023 2024 return valid; 2025} 2026EXPORT_SYMBOL(drm_edid_block_valid); 2027 2028/** 2029 * drm_edid_is_valid - sanity check EDID data 2030 * @edid: EDID data 2031 * 2032 * Sanity-check an entire EDID record (including extensions) 2033 * 2034 * Return: True if the EDID data is valid, false otherwise. 2035 */ 2036bool drm_edid_is_valid(struct edid *edid) 2037{ 2038 int i; 2039 2040 if (!edid) 2041 return false; 2042 2043 for (i = 0; i < edid_block_count(edid); i++) { 2044 void *block = (void *)edid_block_data(edid, i); 2045 2046 if (!drm_edid_block_valid(block, i, true, NULL)) 2047 return false; 2048 } 2049 2050 return true; 2051} 2052EXPORT_SYMBOL(drm_edid_is_valid); 2053 2054/** 2055 * drm_edid_valid - sanity check EDID data 2056 * @drm_edid: EDID data 2057 * 2058 * Sanity check an EDID. Cross check block count against allocated size and 2059 * checksum the blocks. 2060 * 2061 * Return: True if the EDID data is valid, false otherwise. 2062 */ 2063bool drm_edid_valid(const struct drm_edid *drm_edid) 2064{ 2065 int i; 2066 2067 if (!drm_edid) 2068 return false; 2069 2070 if (edid_size_by_blocks(__drm_edid_block_count(drm_edid)) != drm_edid->size) 2071 return false; 2072 2073 for (i = 0; i < drm_edid_block_count(drm_edid); i++) { 2074 const void *block = drm_edid_block_data(drm_edid, i); 2075 2076 if (!edid_block_valid(block, i == 0)) 2077 return false; 2078 } 2079 2080 return true; 2081} 2082EXPORT_SYMBOL(drm_edid_valid); 2083 2084static struct edid *edid_filter_invalid_blocks(struct edid *edid, 2085 size_t *alloc_size) 2086{ 2087 struct edid *new; 2088 int i, valid_blocks = 0; 2089 2090 /* 2091 * Note: If the EDID uses HF-EEODB, but has invalid blocks, we'll revert 2092 * back to regular extension count here. We don't want to start 2093 * modifying the HF-EEODB extension too. 2094 */ 2095 for (i = 0; i < edid_block_count(edid); i++) { 2096 const void *src_block = edid_block_data(edid, i); 2097 2098 if (edid_block_valid(src_block, i == 0)) { 2099 void *dst_block = (void *)edid_block_data(edid, valid_blocks); 2100 2101 memmove(dst_block, src_block, EDID_LENGTH); 2102 valid_blocks++; 2103 } 2104 } 2105 2106 /* We already trusted the base block to be valid here... */ 2107 if (WARN_ON(!valid_blocks)) { 2108 kfree(edid); 2109 return NULL; 2110 } 2111 2112 edid->extensions = valid_blocks - 1; 2113 edid->checksum = edid_block_compute_checksum(edid); 2114 2115 *alloc_size = edid_size_by_blocks(valid_blocks); 2116 2117 new = krealloc(edid, *alloc_size, GFP_KERNEL); 2118 if (!new) 2119 kfree(edid); 2120 2121 return new; 2122} 2123 2124#define DDC_SEGMENT_ADDR 0x30 2125/** 2126 * drm_do_probe_ddc_edid() - get EDID information via I2C 2127 * @data: I2C device adapter 2128 * @buf: EDID data buffer to be filled 2129 * @block: 128 byte EDID block to start fetching from 2130 * @len: EDID data buffer length to fetch 2131 * 2132 * Try to fetch EDID information by calling I2C driver functions. 2133 * 2134 * Return: 0 on success or -1 on failure. 2135 */ 2136static int 2137drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len) 2138{ 2139 struct i2c_adapter *adapter = data; 2140 unsigned char start = block * EDID_LENGTH; 2141 unsigned char segment = block >> 1; 2142 unsigned char xfers = segment ? 3 : 2; 2143 int ret, retries = 5; 2144 2145 /* 2146 * The core I2C driver will automatically retry the transfer if the 2147 * adapter reports EAGAIN. However, we find that bit-banging transfers 2148 * are susceptible to errors under a heavily loaded machine and 2149 * generate spurious NAKs and timeouts. Retrying the transfer 2150 * of the individual block a few times seems to overcome this. 2151 */ 2152 do { 2153 struct i2c_msg msgs[] = { 2154 { 2155 .addr = DDC_SEGMENT_ADDR, 2156 .flags = 0, 2157 .len = 1, 2158 .buf = &segment, 2159 }, { 2160 .addr = DDC_ADDR, 2161 .flags = 0, 2162 .len = 1, 2163 .buf = &start, 2164 }, { 2165 .addr = DDC_ADDR, 2166 .flags = I2C_M_RD, 2167 .len = len, 2168 .buf = buf, 2169 } 2170 }; 2171 2172 /* 2173 * Avoid sending the segment addr to not upset non-compliant 2174 * DDC monitors. 2175 */ 2176 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers); 2177 2178 if (ret == -ENXIO) { 2179 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n", 2180 adapter->name); 2181 break; 2182 } 2183 } while (ret != xfers && --retries); 2184 2185 return ret == xfers ? 0 : -1; 2186} 2187 2188static void connector_bad_edid(struct drm_connector *connector, 2189 const struct edid *edid, int num_blocks) 2190{ 2191 int i; 2192 u8 last_block; 2193 2194 /* 2195 * 0x7e in the EDID is the number of extension blocks. The EDID 2196 * is 1 (base block) + num_ext_blocks big. That means we can think 2197 * of 0x7e in the EDID of the _index_ of the last block in the 2198 * combined chunk of memory. 2199 */ 2200 last_block = edid->extensions; 2201 2202 /* Calculate real checksum for the last edid extension block data */ 2203 if (last_block < num_blocks) 2204 connector->real_edid_checksum = 2205 edid_block_compute_checksum(edid + last_block); 2206 2207 if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS)) 2208 return; 2209 2210 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID is invalid:\n", 2211 connector->base.id, connector->name); 2212 for (i = 0; i < num_blocks; i++) 2213 edid_block_dump(KERN_DEBUG, edid + i, i); 2214} 2215 2216/* Get override or firmware EDID */ 2217static const struct drm_edid *drm_edid_override_get(struct drm_connector *connector) 2218{ 2219 const struct drm_edid *override = NULL; 2220 2221 mutex_lock(&connector->edid_override_mutex); 2222 2223 if (connector->edid_override) 2224 override = drm_edid_dup(connector->edid_override); 2225 2226 mutex_unlock(&connector->edid_override_mutex); 2227 2228 if (!override) 2229 override = drm_edid_load_firmware(connector); 2230 2231 return IS_ERR(override) ? NULL : override; 2232} 2233 2234/* For debugfs edid_override implementation */ 2235int drm_edid_override_show(struct drm_connector *connector, struct seq_file *m) 2236{ 2237 const struct drm_edid *drm_edid; 2238 2239 mutex_lock(&connector->edid_override_mutex); 2240 2241 drm_edid = connector->edid_override; 2242 if (drm_edid) 2243 seq_write(m, drm_edid->edid, drm_edid->size); 2244 2245 mutex_unlock(&connector->edid_override_mutex); 2246 2247 return 0; 2248} 2249 2250/* For debugfs edid_override implementation */ 2251int drm_edid_override_set(struct drm_connector *connector, const void *edid, 2252 size_t size) 2253{ 2254 const struct drm_edid *drm_edid; 2255 2256 drm_edid = drm_edid_alloc(edid, size); 2257 if (!drm_edid_valid(drm_edid)) { 2258 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override invalid\n", 2259 connector->base.id, connector->name); 2260 drm_edid_free(drm_edid); 2261 return -EINVAL; 2262 } 2263 2264 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override set\n", 2265 connector->base.id, connector->name); 2266 2267 mutex_lock(&connector->edid_override_mutex); 2268 2269 drm_edid_free(connector->edid_override); 2270 connector->edid_override = drm_edid; 2271 2272 mutex_unlock(&connector->edid_override_mutex); 2273 2274 return 0; 2275} 2276 2277/* For debugfs edid_override implementation */ 2278int drm_edid_override_reset(struct drm_connector *connector) 2279{ 2280 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override reset\n", 2281 connector->base.id, connector->name); 2282 2283 mutex_lock(&connector->edid_override_mutex); 2284 2285 drm_edid_free(connector->edid_override); 2286 connector->edid_override = NULL; 2287 2288 mutex_unlock(&connector->edid_override_mutex); 2289 2290 return 0; 2291} 2292 2293/** 2294 * drm_edid_override_connector_update - add modes from override/firmware EDID 2295 * @connector: connector we're probing 2296 * 2297 * Add modes from the override/firmware EDID, if available. Only to be used from 2298 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe 2299 * failed during drm_get_edid() and caused the override/firmware EDID to be 2300 * skipped. 2301 * 2302 * Return: The number of modes added or 0 if we couldn't find any. 2303 */ 2304int drm_edid_override_connector_update(struct drm_connector *connector) 2305{ 2306 const struct drm_edid *override; 2307 int num_modes = 0; 2308 2309 override = drm_edid_override_get(connector); 2310 if (override) { 2311 if (drm_edid_connector_update(connector, override) == 0) 2312 num_modes = drm_edid_connector_add_modes(connector); 2313 2314 drm_edid_free(override); 2315 2316 drm_dbg_kms(connector->dev, 2317 "[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n", 2318 connector->base.id, connector->name, num_modes); 2319 } 2320 2321 return num_modes; 2322} 2323EXPORT_SYMBOL(drm_edid_override_connector_update); 2324 2325typedef int read_block_fn(void *context, u8 *buf, unsigned int block, size_t len); 2326 2327static enum edid_block_status edid_block_read(void *block, unsigned int block_num, 2328 read_block_fn read_block, 2329 void *context) 2330{ 2331 enum edid_block_status status; 2332 bool is_base_block = block_num == 0; 2333 int try; 2334 2335 for (try = 0; try < 4; try++) { 2336 if (read_block(context, block, block_num, EDID_LENGTH)) 2337 return EDID_BLOCK_READ_FAIL; 2338 2339 status = edid_block_check(block, is_base_block); 2340 if (status == EDID_BLOCK_HEADER_REPAIR) { 2341 edid_header_fix(block); 2342 2343 /* Retry with fixed header, update status if that worked. */ 2344 status = edid_block_check(block, is_base_block); 2345 if (status == EDID_BLOCK_OK) 2346 status = EDID_BLOCK_HEADER_FIXED; 2347 } 2348 2349 if (edid_block_status_valid(status, edid_block_tag(block))) 2350 break; 2351 2352 /* Fail early for unrepairable base block all zeros. */ 2353 if (try == 0 && is_base_block && status == EDID_BLOCK_ZERO) 2354 break; 2355 } 2356 2357 return status; 2358} 2359 2360static struct edid *_drm_do_get_edid(struct drm_connector *connector, 2361 read_block_fn read_block, void *context, 2362 size_t *size) 2363{ 2364 enum edid_block_status status; 2365 int i, num_blocks, invalid_blocks = 0; 2366 const struct drm_edid *override; 2367 struct edid *edid, *new; 2368 size_t alloc_size = EDID_LENGTH; 2369 2370 override = drm_edid_override_get(connector); 2371 if (override) { 2372 alloc_size = override->size; 2373 edid = kmemdup(override->edid, alloc_size, GFP_KERNEL); 2374 drm_edid_free(override); 2375 if (!edid) 2376 return NULL; 2377 goto ok; 2378 } 2379 2380 edid = kmalloc(alloc_size, GFP_KERNEL); 2381 if (!edid) 2382 return NULL; 2383 2384 status = edid_block_read(edid, 0, read_block, context); 2385 2386 edid_block_status_print(status, edid, 0); 2387 2388 if (status == EDID_BLOCK_READ_FAIL) 2389 goto fail; 2390 2391 /* FIXME: Clarify what a corrupt EDID actually means. */ 2392 if (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION) 2393 connector->edid_corrupt = false; 2394 else 2395 connector->edid_corrupt = true; 2396 2397 if (!edid_block_status_valid(status, edid_block_tag(edid))) { 2398 if (status == EDID_BLOCK_ZERO) 2399 connector->null_edid_counter++; 2400 2401 connector_bad_edid(connector, edid, 1); 2402 goto fail; 2403 } 2404 2405 if (!edid_extension_block_count(edid)) 2406 goto ok; 2407 2408 alloc_size = edid_size(edid); 2409 new = krealloc(edid, alloc_size, GFP_KERNEL); 2410 if (!new) 2411 goto fail; 2412 edid = new; 2413 2414 num_blocks = edid_block_count(edid); 2415 for (i = 1; i < num_blocks; i++) { 2416 void *block = (void *)edid_block_data(edid, i); 2417 2418 status = edid_block_read(block, i, read_block, context); 2419 2420 edid_block_status_print(status, block, i); 2421 2422 if (!edid_block_status_valid(status, edid_block_tag(block))) { 2423 if (status == EDID_BLOCK_READ_FAIL) 2424 goto fail; 2425 invalid_blocks++; 2426 } else if (i == 1) { 2427 /* 2428 * If the first EDID extension is a CTA extension, and 2429 * the first Data Block is HF-EEODB, override the 2430 * extension block count. 2431 * 2432 * Note: HF-EEODB could specify a smaller extension 2433 * count too, but we can't risk allocating a smaller 2434 * amount. 2435 */ 2436 int eeodb = edid_hfeeodb_block_count(edid); 2437 2438 if (eeodb > num_blocks) { 2439 num_blocks = eeodb; 2440 alloc_size = edid_size_by_blocks(num_blocks); 2441 new = krealloc(edid, alloc_size, GFP_KERNEL); 2442 if (!new) 2443 goto fail; 2444 edid = new; 2445 } 2446 } 2447 } 2448 2449 if (invalid_blocks) { 2450 connector_bad_edid(connector, edid, num_blocks); 2451 2452 edid = edid_filter_invalid_blocks(edid, &alloc_size); 2453 } 2454 2455ok: 2456 if (size) 2457 *size = alloc_size; 2458 2459 return edid; 2460 2461fail: 2462 kfree(edid); 2463 return NULL; 2464} 2465 2466/** 2467 * drm_do_get_edid - get EDID data using a custom EDID block read function 2468 * @connector: connector we're probing 2469 * @read_block: EDID block read function 2470 * @context: private data passed to the block read function 2471 * 2472 * When the I2C adapter connected to the DDC bus is hidden behind a device that 2473 * exposes a different interface to read EDID blocks this function can be used 2474 * to get EDID data using a custom block read function. 2475 * 2476 * As in the general case the DDC bus is accessible by the kernel at the I2C 2477 * level, drivers must make all reasonable efforts to expose it as an I2C 2478 * adapter and use drm_get_edid() instead of abusing this function. 2479 * 2480 * The EDID may be overridden using debugfs override_edid or firmware EDID 2481 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority 2482 * order. Having either of them bypasses actual EDID reads. 2483 * 2484 * Return: Pointer to valid EDID or NULL if we couldn't find any. 2485 */ 2486struct edid *drm_do_get_edid(struct drm_connector *connector, 2487 read_block_fn read_block, 2488 void *context) 2489{ 2490 return _drm_do_get_edid(connector, read_block, context, NULL); 2491} 2492EXPORT_SYMBOL_GPL(drm_do_get_edid); 2493 2494/** 2495 * drm_edid_raw - Get a pointer to the raw EDID data. 2496 * @drm_edid: drm_edid container 2497 * 2498 * Get a pointer to the raw EDID data. 2499 * 2500 * This is for transition only. Avoid using this like the plague. 2501 * 2502 * Return: Pointer to raw EDID data. 2503 */ 2504const struct edid *drm_edid_raw(const struct drm_edid *drm_edid) 2505{ 2506 if (!drm_edid || !drm_edid->size) 2507 return NULL; 2508 2509 /* 2510 * Do not return pointers where relying on EDID extension count would 2511 * lead to buffer overflow. 2512 */ 2513 if (WARN_ON(edid_size(drm_edid->edid) > drm_edid->size)) 2514 return NULL; 2515 2516 return drm_edid->edid; 2517} 2518EXPORT_SYMBOL(drm_edid_raw); 2519 2520/* Allocate struct drm_edid container *without* duplicating the edid data */ 2521static const struct drm_edid *_drm_edid_alloc(const void *edid, size_t size) 2522{ 2523 struct drm_edid *drm_edid; 2524 2525 if (!edid || !size || size < EDID_LENGTH) 2526 return NULL; 2527 2528 drm_edid = kzalloc(sizeof(*drm_edid), GFP_KERNEL); 2529 if (drm_edid) { 2530 drm_edid->edid = edid; 2531 drm_edid->size = size; 2532 } 2533 2534 return drm_edid; 2535} 2536 2537/** 2538 * drm_edid_alloc - Allocate a new drm_edid container 2539 * @edid: Pointer to raw EDID data 2540 * @size: Size of memory allocated for EDID 2541 * 2542 * Allocate a new drm_edid container. Do not calculate edid size from edid, pass 2543 * the actual size that has been allocated for the data. There is no validation 2544 * of the raw EDID data against the size, but at least the EDID base block must 2545 * fit in the buffer. 2546 * 2547 * The returned pointer must be freed using drm_edid_free(). 2548 * 2549 * Return: drm_edid container, or NULL on errors 2550 */ 2551const struct drm_edid *drm_edid_alloc(const void *edid, size_t size) 2552{ 2553 const struct drm_edid *drm_edid; 2554 2555 if (!edid || !size || size < EDID_LENGTH) 2556 return NULL; 2557 2558 edid = kmemdup(edid, size, GFP_KERNEL); 2559 if (!edid) 2560 return NULL; 2561 2562 drm_edid = _drm_edid_alloc(edid, size); 2563 if (!drm_edid) 2564 kfree(edid); 2565 2566 return drm_edid; 2567} 2568EXPORT_SYMBOL(drm_edid_alloc); 2569 2570/** 2571 * drm_edid_dup - Duplicate a drm_edid container 2572 * @drm_edid: EDID to duplicate 2573 * 2574 * The returned pointer must be freed using drm_edid_free(). 2575 * 2576 * Returns: drm_edid container copy, or NULL on errors 2577 */ 2578const struct drm_edid *drm_edid_dup(const struct drm_edid *drm_edid) 2579{ 2580 if (!drm_edid) 2581 return NULL; 2582 2583 return drm_edid_alloc(drm_edid->edid, drm_edid->size); 2584} 2585EXPORT_SYMBOL(drm_edid_dup); 2586 2587/** 2588 * drm_edid_free - Free the drm_edid container 2589 * @drm_edid: EDID to free 2590 */ 2591void drm_edid_free(const struct drm_edid *drm_edid) 2592{ 2593 if (!drm_edid) 2594 return; 2595 2596 kfree(drm_edid->edid); 2597 kfree(drm_edid); 2598} 2599EXPORT_SYMBOL(drm_edid_free); 2600 2601/** 2602 * drm_probe_ddc() - probe DDC presence 2603 * @adapter: I2C adapter to probe 2604 * 2605 * Return: True on success, false on failure. 2606 */ 2607bool 2608drm_probe_ddc(struct i2c_adapter *adapter) 2609{ 2610 unsigned char out; 2611 2612 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0); 2613} 2614EXPORT_SYMBOL(drm_probe_ddc); 2615 2616/** 2617 * drm_get_edid - get EDID data, if available 2618 * @connector: connector we're probing 2619 * @adapter: I2C adapter to use for DDC 2620 * 2621 * Poke the given I2C channel to grab EDID data if possible. If found, 2622 * attach it to the connector. 2623 * 2624 * Return: Pointer to valid EDID or NULL if we couldn't find any. 2625 */ 2626struct edid *drm_get_edid(struct drm_connector *connector, 2627 struct i2c_adapter *adapter) 2628{ 2629 struct edid *edid; 2630 2631 if (connector->force == DRM_FORCE_OFF) 2632 return NULL; 2633 2634 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter)) 2635 return NULL; 2636 2637 edid = _drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter, NULL); 2638 drm_connector_update_edid_property(connector, edid); 2639 return edid; 2640} 2641EXPORT_SYMBOL(drm_get_edid); 2642 2643/** 2644 * drm_edid_read_custom - Read EDID data using given EDID block read function 2645 * @connector: Connector to use 2646 * @read_block: EDID block read function 2647 * @context: Private data passed to the block read function 2648 * 2649 * When the I2C adapter connected to the DDC bus is hidden behind a device that 2650 * exposes a different interface to read EDID blocks this function can be used 2651 * to get EDID data using a custom block read function. 2652 * 2653 * As in the general case the DDC bus is accessible by the kernel at the I2C 2654 * level, drivers must make all reasonable efforts to expose it as an I2C 2655 * adapter and use drm_edid_read() or drm_edid_read_ddc() instead of abusing 2656 * this function. 2657 * 2658 * The EDID may be overridden using debugfs override_edid or firmware EDID 2659 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority 2660 * order. Having either of them bypasses actual EDID reads. 2661 * 2662 * The returned pointer must be freed using drm_edid_free(). 2663 * 2664 * Return: Pointer to EDID, or NULL if probe/read failed. 2665 */ 2666const struct drm_edid *drm_edid_read_custom(struct drm_connector *connector, 2667 read_block_fn read_block, 2668 void *context) 2669{ 2670 const struct drm_edid *drm_edid; 2671 struct edid *edid; 2672 size_t size = 0; 2673 2674 edid = _drm_do_get_edid(connector, read_block, context, &size); 2675 if (!edid) 2676 return NULL; 2677 2678 /* Sanity check for now */ 2679 drm_WARN_ON(connector->dev, !size); 2680 2681 drm_edid = _drm_edid_alloc(edid, size); 2682 if (!drm_edid) 2683 kfree(edid); 2684 2685 return drm_edid; 2686} 2687EXPORT_SYMBOL(drm_edid_read_custom); 2688 2689/** 2690 * drm_edid_read_ddc - Read EDID data using given I2C adapter 2691 * @connector: Connector to use 2692 * @adapter: I2C adapter to use for DDC 2693 * 2694 * Read EDID using the given I2C adapter. 2695 * 2696 * The EDID may be overridden using debugfs override_edid or firmware EDID 2697 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority 2698 * order. Having either of them bypasses actual EDID reads. 2699 * 2700 * Prefer initializing connector->ddc with drm_connector_init_with_ddc() and 2701 * using drm_edid_read() instead of this function. 2702 * 2703 * The returned pointer must be freed using drm_edid_free(). 2704 * 2705 * Return: Pointer to EDID, or NULL if probe/read failed. 2706 */ 2707const struct drm_edid *drm_edid_read_ddc(struct drm_connector *connector, 2708 struct i2c_adapter *adapter) 2709{ 2710 const struct drm_edid *drm_edid; 2711 2712 if (connector->force == DRM_FORCE_OFF) 2713 return NULL; 2714 2715 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter)) 2716 return NULL; 2717 2718 drm_edid = drm_edid_read_custom(connector, drm_do_probe_ddc_edid, adapter); 2719 2720 /* Note: Do *not* call connector updates here. */ 2721 2722 return drm_edid; 2723} 2724EXPORT_SYMBOL(drm_edid_read_ddc); 2725 2726/** 2727 * drm_edid_read - Read EDID data using connector's I2C adapter 2728 * @connector: Connector to use 2729 * 2730 * Read EDID using the connector's I2C adapter. 2731 * 2732 * The EDID may be overridden using debugfs override_edid or firmware EDID 2733 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority 2734 * order. Having either of them bypasses actual EDID reads. 2735 * 2736 * The returned pointer must be freed using drm_edid_free(). 2737 * 2738 * Return: Pointer to EDID, or NULL if probe/read failed. 2739 */ 2740const struct drm_edid *drm_edid_read(struct drm_connector *connector) 2741{ 2742 if (drm_WARN_ON(connector->dev, !connector->ddc)) 2743 return NULL; 2744 2745 return drm_edid_read_ddc(connector, connector->ddc); 2746} 2747EXPORT_SYMBOL(drm_edid_read); 2748 2749static u32 edid_extract_panel_id(const struct edid *edid) 2750{ 2751 /* 2752 * We represent the ID as a 32-bit number so it can easily be compared 2753 * with "==". 2754 * 2755 * NOTE that we deal with endianness differently for the top half 2756 * of this ID than for the bottom half. The bottom half (the product 2757 * id) gets decoded as little endian by the EDID_PRODUCT_ID because 2758 * that's how everyone seems to interpret it. The top half (the mfg_id) 2759 * gets stored as big endian because that makes 2760 * drm_edid_encode_panel_id() and drm_edid_decode_panel_id() easier 2761 * to write (it's easier to extract the ASCII). It doesn't really 2762 * matter, though, as long as the number here is unique. 2763 */ 2764 return (u32)edid->mfg_id[0] << 24 | 2765 (u32)edid->mfg_id[1] << 16 | 2766 (u32)EDID_PRODUCT_ID(edid); 2767} 2768 2769/** 2770 * drm_edid_get_panel_id - Get a panel's ID through DDC 2771 * @adapter: I2C adapter to use for DDC 2772 * 2773 * This function reads the first block of the EDID of a panel and (assuming 2774 * that the EDID is valid) extracts the ID out of it. The ID is a 32-bit value 2775 * (16 bits of manufacturer ID and 16 bits of per-manufacturer ID) that's 2776 * supposed to be different for each different modem of panel. 2777 * 2778 * This function is intended to be used during early probing on devices where 2779 * more than one panel might be present. Because of its intended use it must 2780 * assume that the EDID of the panel is correct, at least as far as the ID 2781 * is concerned (in other words, we don't process any overrides here). 2782 * 2783 * NOTE: it's expected that this function and drm_do_get_edid() will both 2784 * be read the EDID, but there is no caching between them. Since we're only 2785 * reading the first block, hopefully this extra overhead won't be too big. 2786 * 2787 * Return: A 32-bit ID that should be different for each make/model of panel. 2788 * See the functions drm_edid_encode_panel_id() and 2789 * drm_edid_decode_panel_id() for some details on the structure of this 2790 * ID. 2791 */ 2792 2793u32 drm_edid_get_panel_id(struct i2c_adapter *adapter) 2794{ 2795 enum edid_block_status status; 2796 void *base_block; 2797 u32 panel_id = 0; 2798 2799 /* 2800 * There are no manufacturer IDs of 0, so if there is a problem reading 2801 * the EDID then we'll just return 0. 2802 */ 2803 2804 base_block = kzalloc(EDID_LENGTH, GFP_KERNEL); 2805 if (!base_block) 2806 return 0; 2807 2808 status = edid_block_read(base_block, 0, drm_do_probe_ddc_edid, adapter); 2809 2810 edid_block_status_print(status, base_block, 0); 2811 2812 if (edid_block_status_valid(status, edid_block_tag(base_block))) 2813 panel_id = edid_extract_panel_id(base_block); 2814 else 2815 edid_block_dump(KERN_NOTICE, base_block, 0); 2816 2817 kfree(base_block); 2818 2819 return panel_id; 2820} 2821EXPORT_SYMBOL(drm_edid_get_panel_id); 2822 2823/** 2824 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output 2825 * @connector: connector we're probing 2826 * @adapter: I2C adapter to use for DDC 2827 * 2828 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of 2829 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily 2830 * switch DDC to the GPU which is retrieving EDID. 2831 * 2832 * Return: Pointer to valid EDID or %NULL if we couldn't find any. 2833 */ 2834struct edid *drm_get_edid_switcheroo(struct drm_connector *connector, 2835 struct i2c_adapter *adapter) 2836{ 2837 struct drm_device *dev = connector->dev; 2838 struct pci_dev *pdev = to_pci_dev(dev->dev); 2839 struct edid *edid; 2840 2841 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev))) 2842 return NULL; 2843 2844 vga_switcheroo_lock_ddc(pdev); 2845 edid = drm_get_edid(connector, adapter); 2846 vga_switcheroo_unlock_ddc(pdev); 2847 2848 return edid; 2849} 2850EXPORT_SYMBOL(drm_get_edid_switcheroo); 2851 2852/** 2853 * drm_edid_read_switcheroo - get EDID data for a vga_switcheroo output 2854 * @connector: connector we're probing 2855 * @adapter: I2C adapter to use for DDC 2856 * 2857 * Wrapper around drm_edid_read_ddc() for laptops with dual GPUs using one set 2858 * of outputs. The wrapper adds the requisite vga_switcheroo calls to 2859 * temporarily switch DDC to the GPU which is retrieving EDID. 2860 * 2861 * Return: Pointer to valid EDID or %NULL if we couldn't find any. 2862 */ 2863const struct drm_edid *drm_edid_read_switcheroo(struct drm_connector *connector, 2864 struct i2c_adapter *adapter) 2865{ 2866 struct drm_device *dev = connector->dev; 2867 struct pci_dev *pdev = to_pci_dev(dev->dev); 2868 const struct drm_edid *drm_edid; 2869 2870 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev))) 2871 return NULL; 2872 2873 vga_switcheroo_lock_ddc(pdev); 2874 drm_edid = drm_edid_read_ddc(connector, adapter); 2875 vga_switcheroo_unlock_ddc(pdev); 2876 2877 return drm_edid; 2878} 2879EXPORT_SYMBOL(drm_edid_read_switcheroo); 2880 2881/** 2882 * drm_edid_duplicate - duplicate an EDID and the extensions 2883 * @edid: EDID to duplicate 2884 * 2885 * Return: Pointer to duplicated EDID or NULL on allocation failure. 2886 */ 2887struct edid *drm_edid_duplicate(const struct edid *edid) 2888{ 2889 if (!edid) 2890 return NULL; 2891 2892 return kmemdup(edid, edid_size(edid), GFP_KERNEL); 2893} 2894EXPORT_SYMBOL(drm_edid_duplicate); 2895 2896/*** EDID parsing ***/ 2897 2898/** 2899 * edid_get_quirks - return quirk flags for a given EDID 2900 * @drm_edid: EDID to process 2901 * 2902 * This tells subsequent routines what fixes they need to apply. 2903 */ 2904static u32 edid_get_quirks(const struct drm_edid *drm_edid) 2905{ 2906 u32 panel_id = edid_extract_panel_id(drm_edid->edid); 2907 const struct edid_quirk *quirk; 2908 int i; 2909 2910 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) { 2911 quirk = &edid_quirk_list[i]; 2912 if (quirk->panel_id == panel_id) 2913 return quirk->quirks; 2914 } 2915 2916 return 0; 2917} 2918 2919#define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) 2920#define MODE_REFRESH_DIFF(c,t) (abs((c) - (t))) 2921 2922/* 2923 * Walk the mode list for connector, clearing the preferred status on existing 2924 * modes and setting it anew for the right mode ala quirks. 2925 */ 2926static void edid_fixup_preferred(struct drm_connector *connector) 2927{ 2928 const struct drm_display_info *info = &connector->display_info; 2929 struct drm_display_mode *t, *cur_mode, *preferred_mode; 2930 int target_refresh = 0; 2931 int cur_vrefresh, preferred_vrefresh; 2932 2933 if (list_empty(&connector->probed_modes)) 2934 return; 2935 2936 if (info->quirks & EDID_QUIRK_PREFER_LARGE_60) 2937 target_refresh = 60; 2938 if (info->quirks & EDID_QUIRK_PREFER_LARGE_75) 2939 target_refresh = 75; 2940 2941 preferred_mode = list_first_entry(&connector->probed_modes, 2942 struct drm_display_mode, head); 2943 2944 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) { 2945 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 2946 2947 if (cur_mode == preferred_mode) 2948 continue; 2949 2950 /* Largest mode is preferred */ 2951 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) 2952 preferred_mode = cur_mode; 2953 2954 cur_vrefresh = drm_mode_vrefresh(cur_mode); 2955 preferred_vrefresh = drm_mode_vrefresh(preferred_mode); 2956 /* At a given size, try to get closest to target refresh */ 2957 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) && 2958 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) < 2959 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) { 2960 preferred_mode = cur_mode; 2961 } 2962 } 2963 2964 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; 2965} 2966 2967static bool 2968mode_is_rb(const struct drm_display_mode *mode) 2969{ 2970 return (mode->htotal - mode->hdisplay == 160) && 2971 (mode->hsync_end - mode->hdisplay == 80) && 2972 (mode->hsync_end - mode->hsync_start == 32) && 2973 (mode->vsync_start - mode->vdisplay == 3); 2974} 2975 2976/* 2977 * drm_mode_find_dmt - Create a copy of a mode if present in DMT 2978 * @dev: Device to duplicate against 2979 * @hsize: Mode width 2980 * @vsize: Mode height 2981 * @fresh: Mode refresh rate 2982 * @rb: Mode reduced-blanking-ness 2983 * 2984 * Walk the DMT mode list looking for a match for the given parameters. 2985 * 2986 * Return: A newly allocated copy of the mode, or NULL if not found. 2987 */ 2988struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, 2989 int hsize, int vsize, int fresh, 2990 bool rb) 2991{ 2992 int i; 2993 2994 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 2995 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 2996 2997 if (hsize != ptr->hdisplay) 2998 continue; 2999 if (vsize != ptr->vdisplay) 3000 continue; 3001 if (fresh != drm_mode_vrefresh(ptr)) 3002 continue; 3003 if (rb != mode_is_rb(ptr)) 3004 continue; 3005 3006 return drm_mode_duplicate(dev, ptr); 3007 } 3008 3009 return NULL; 3010} 3011EXPORT_SYMBOL(drm_mode_find_dmt); 3012 3013static bool is_display_descriptor(const struct detailed_timing *descriptor, u8 type) 3014{ 3015 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0); 3016 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.pad1) != 2); 3017 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.type) != 3); 3018 3019 return descriptor->pixel_clock == 0 && 3020 descriptor->data.other_data.pad1 == 0 && 3021 descriptor->data.other_data.type == type; 3022} 3023 3024static bool is_detailed_timing_descriptor(const struct detailed_timing *descriptor) 3025{ 3026 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0); 3027 3028 return descriptor->pixel_clock != 0; 3029} 3030 3031typedef void detailed_cb(const struct detailed_timing *timing, void *closure); 3032 3033static void 3034cea_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure) 3035{ 3036 int i, n; 3037 u8 d = ext[0x02]; 3038 const u8 *det_base = ext + d; 3039 3040 if (d < 4 || d > 127) 3041 return; 3042 3043 n = (127 - d) / 18; 3044 for (i = 0; i < n; i++) 3045 cb((const struct detailed_timing *)(det_base + 18 * i), closure); 3046} 3047 3048static void 3049vtb_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure) 3050{ 3051 unsigned int i, n = min((int)ext[0x02], 6); 3052 const u8 *det_base = ext + 5; 3053 3054 if (ext[0x01] != 1) 3055 return; /* unknown version */ 3056 3057 for (i = 0; i < n; i++) 3058 cb((const struct detailed_timing *)(det_base + 18 * i), closure); 3059} 3060 3061static void drm_for_each_detailed_block(const struct drm_edid *drm_edid, 3062 detailed_cb *cb, void *closure) 3063{ 3064 struct drm_edid_iter edid_iter; 3065 const u8 *ext; 3066 int i; 3067 3068 if (!drm_edid) 3069 return; 3070 3071 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) 3072 cb(&drm_edid->edid->detailed_timings[i], closure); 3073 3074 drm_edid_iter_begin(drm_edid, &edid_iter); 3075 drm_edid_iter_for_each(ext, &edid_iter) { 3076 switch (*ext) { 3077 case CEA_EXT: 3078 cea_for_each_detailed_block(ext, cb, closure); 3079 break; 3080 case VTB_EXT: 3081 vtb_for_each_detailed_block(ext, cb, closure); 3082 break; 3083 default: 3084 break; 3085 } 3086 } 3087 drm_edid_iter_end(&edid_iter); 3088} 3089 3090static void 3091is_rb(const struct detailed_timing *descriptor, void *data) 3092{ 3093 bool *res = data; 3094 3095 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE)) 3096 return; 3097 3098 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10); 3099 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.cvt.flags) != 15); 3100 3101 if (descriptor->data.other_data.data.range.flags == DRM_EDID_CVT_SUPPORT_FLAG && 3102 descriptor->data.other_data.data.range.formula.cvt.flags & DRM_EDID_CVT_FLAGS_REDUCED_BLANKING) 3103 *res = true; 3104} 3105 3106/* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */ 3107static bool 3108drm_monitor_supports_rb(const struct drm_edid *drm_edid) 3109{ 3110 if (drm_edid->edid->revision >= 4) { 3111 bool ret = false; 3112 3113 drm_for_each_detailed_block(drm_edid, is_rb, &ret); 3114 return ret; 3115 } 3116 3117 return ((drm_edid->edid->input & DRM_EDID_INPUT_DIGITAL) != 0); 3118} 3119 3120static void 3121find_gtf2(const struct detailed_timing *descriptor, void *data) 3122{ 3123 const struct detailed_timing **res = data; 3124 3125 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE)) 3126 return; 3127 3128 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10); 3129 3130 if (descriptor->data.other_data.data.range.flags == DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG) 3131 *res = descriptor; 3132} 3133 3134/* Secondary GTF curve kicks in above some break frequency */ 3135static int 3136drm_gtf2_hbreak(const struct drm_edid *drm_edid) 3137{ 3138 const struct detailed_timing *descriptor = NULL; 3139 3140 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 3141 3142 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.hfreq_start_khz) != 12); 3143 3144 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.hfreq_start_khz * 2 : 0; 3145} 3146 3147static int 3148drm_gtf2_2c(const struct drm_edid *drm_edid) 3149{ 3150 const struct detailed_timing *descriptor = NULL; 3151 3152 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 3153 3154 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.c) != 13); 3155 3156 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.c : 0; 3157} 3158 3159static int 3160drm_gtf2_m(const struct drm_edid *drm_edid) 3161{ 3162 const struct detailed_timing *descriptor = NULL; 3163 3164 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 3165 3166 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.m) != 14); 3167 3168 return descriptor ? le16_to_cpu(descriptor->data.other_data.data.range.formula.gtf2.m) : 0; 3169} 3170 3171static int 3172drm_gtf2_k(const struct drm_edid *drm_edid) 3173{ 3174 const struct detailed_timing *descriptor = NULL; 3175 3176 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 3177 3178 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.k) != 16); 3179 3180 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.k : 0; 3181} 3182 3183static int 3184drm_gtf2_2j(const struct drm_edid *drm_edid) 3185{ 3186 const struct detailed_timing *descriptor = NULL; 3187 3188 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 3189 3190 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.j) != 17); 3191 3192 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.j : 0; 3193} 3194 3195static void 3196get_timing_level(const struct detailed_timing *descriptor, void *data) 3197{ 3198 int *res = data; 3199 3200 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE)) 3201 return; 3202 3203 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10); 3204 3205 switch (descriptor->data.other_data.data.range.flags) { 3206 case DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG: 3207 *res = LEVEL_GTF; 3208 break; 3209 case DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG: 3210 *res = LEVEL_GTF2; 3211 break; 3212 case DRM_EDID_CVT_SUPPORT_FLAG: 3213 *res = LEVEL_CVT; 3214 break; 3215 default: 3216 break; 3217 } 3218} 3219 3220/* Get standard timing level (CVT/GTF/DMT). */ 3221static int standard_timing_level(const struct drm_edid *drm_edid) 3222{ 3223 const struct edid *edid = drm_edid->edid; 3224 3225 if (edid->revision >= 4) { 3226 /* 3227 * If the range descriptor doesn't 3228 * indicate otherwise default to CVT 3229 */ 3230 int ret = LEVEL_CVT; 3231 3232 drm_for_each_detailed_block(drm_edid, get_timing_level, &ret); 3233 3234 return ret; 3235 } else if (edid->revision >= 3 && drm_gtf2_hbreak(drm_edid)) { 3236 return LEVEL_GTF2; 3237 } else if (edid->revision >= 2) { 3238 return LEVEL_GTF; 3239 } else { 3240 return LEVEL_DMT; 3241 } 3242} 3243 3244/* 3245 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old 3246 * monitors fill with ascii space (0x20) instead. 3247 */ 3248static int 3249bad_std_timing(u8 a, u8 b) 3250{ 3251 return (a == 0x00 && b == 0x00) || 3252 (a == 0x01 && b == 0x01) || 3253 (a == 0x20 && b == 0x20); 3254} 3255 3256static int drm_mode_hsync(const struct drm_display_mode *mode) 3257{ 3258 if (mode->htotal <= 0) 3259 return 0; 3260 3261 return DIV_ROUND_CLOSEST(mode->clock, mode->htotal); 3262} 3263 3264static struct drm_display_mode * 3265drm_gtf2_mode(struct drm_device *dev, 3266 const struct drm_edid *drm_edid, 3267 int hsize, int vsize, int vrefresh_rate) 3268{ 3269 struct drm_display_mode *mode; 3270 3271 /* 3272 * This is potentially wrong if there's ever a monitor with 3273 * more than one ranges section, each claiming a different 3274 * secondary GTF curve. Please don't do that. 3275 */ 3276 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 3277 if (!mode) 3278 return NULL; 3279 3280 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(drm_edid)) { 3281 drm_mode_destroy(dev, mode); 3282 mode = drm_gtf_mode_complex(dev, hsize, vsize, 3283 vrefresh_rate, 0, 0, 3284 drm_gtf2_m(drm_edid), 3285 drm_gtf2_2c(drm_edid), 3286 drm_gtf2_k(drm_edid), 3287 drm_gtf2_2j(drm_edid)); 3288 } 3289 3290 return mode; 3291} 3292 3293/* 3294 * Take the standard timing params (in this case width, aspect, and refresh) 3295 * and convert them into a real mode using CVT/GTF/DMT. 3296 */ 3297static struct drm_display_mode *drm_mode_std(struct drm_connector *connector, 3298 const struct drm_edid *drm_edid, 3299 const struct std_timing *t) 3300{ 3301 struct drm_device *dev = connector->dev; 3302 struct drm_display_mode *m, *mode = NULL; 3303 int hsize, vsize; 3304 int vrefresh_rate; 3305 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) 3306 >> EDID_TIMING_ASPECT_SHIFT; 3307 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) 3308 >> EDID_TIMING_VFREQ_SHIFT; 3309 int timing_level = standard_timing_level(drm_edid); 3310 3311 if (bad_std_timing(t->hsize, t->vfreq_aspect)) 3312 return NULL; 3313 3314 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ 3315 hsize = t->hsize * 8 + 248; 3316 /* vrefresh_rate = vfreq + 60 */ 3317 vrefresh_rate = vfreq + 60; 3318 /* the vdisplay is calculated based on the aspect ratio */ 3319 if (aspect_ratio == 0) { 3320 if (drm_edid->edid->revision < 3) 3321 vsize = hsize; 3322 else 3323 vsize = (hsize * 10) / 16; 3324 } else if (aspect_ratio == 1) 3325 vsize = (hsize * 3) / 4; 3326 else if (aspect_ratio == 2) 3327 vsize = (hsize * 4) / 5; 3328 else 3329 vsize = (hsize * 9) / 16; 3330 3331 /* HDTV hack, part 1 */ 3332 if (vrefresh_rate == 60 && 3333 ((hsize == 1360 && vsize == 765) || 3334 (hsize == 1368 && vsize == 769))) { 3335 hsize = 1366; 3336 vsize = 768; 3337 } 3338 3339 /* 3340 * If this connector already has a mode for this size and refresh 3341 * rate (because it came from detailed or CVT info), use that 3342 * instead. This way we don't have to guess at interlace or 3343 * reduced blanking. 3344 */ 3345 list_for_each_entry(m, &connector->probed_modes, head) 3346 if (m->hdisplay == hsize && m->vdisplay == vsize && 3347 drm_mode_vrefresh(m) == vrefresh_rate) 3348 return NULL; 3349 3350 /* HDTV hack, part 2 */ 3351 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) { 3352 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0, 3353 false); 3354 if (!mode) 3355 return NULL; 3356 mode->hdisplay = 1366; 3357 mode->hsync_start = mode->hsync_start - 1; 3358 mode->hsync_end = mode->hsync_end - 1; 3359 return mode; 3360 } 3361 3362 /* check whether it can be found in default mode table */ 3363 if (drm_monitor_supports_rb(drm_edid)) { 3364 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, 3365 true); 3366 if (mode) 3367 return mode; 3368 } 3369 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false); 3370 if (mode) 3371 return mode; 3372 3373 /* okay, generate it */ 3374 switch (timing_level) { 3375 case LEVEL_DMT: 3376 break; 3377 case LEVEL_GTF: 3378 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 3379 break; 3380 case LEVEL_GTF2: 3381 mode = drm_gtf2_mode(dev, drm_edid, hsize, vsize, vrefresh_rate); 3382 break; 3383 case LEVEL_CVT: 3384 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0, 3385 false); 3386 break; 3387 } 3388 return mode; 3389} 3390 3391/* 3392 * EDID is delightfully ambiguous about how interlaced modes are to be 3393 * encoded. Our internal representation is of frame height, but some 3394 * HDTV detailed timings are encoded as field height. 3395 * 3396 * The format list here is from CEA, in frame size. Technically we 3397 * should be checking refresh rate too. Whatever. 3398 */ 3399static void 3400drm_mode_do_interlace_quirk(struct drm_display_mode *mode, 3401 const struct detailed_pixel_timing *pt) 3402{ 3403 int i; 3404 static const struct { 3405 int w, h; 3406 } cea_interlaced[] = { 3407 { 1920, 1080 }, 3408 { 720, 480 }, 3409 { 1440, 480 }, 3410 { 2880, 480 }, 3411 { 720, 576 }, 3412 { 1440, 576 }, 3413 { 2880, 576 }, 3414 }; 3415 3416 if (!(pt->misc & DRM_EDID_PT_INTERLACED)) 3417 return; 3418 3419 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) { 3420 if ((mode->hdisplay == cea_interlaced[i].w) && 3421 (mode->vdisplay == cea_interlaced[i].h / 2)) { 3422 mode->vdisplay *= 2; 3423 mode->vsync_start *= 2; 3424 mode->vsync_end *= 2; 3425 mode->vtotal *= 2; 3426 mode->vtotal |= 1; 3427 } 3428 } 3429 3430 mode->flags |= DRM_MODE_FLAG_INTERLACE; 3431} 3432 3433/* 3434 * Create a new mode from an EDID detailed timing section. An EDID detailed 3435 * timing block contains enough info for us to create and return a new struct 3436 * drm_display_mode. 3437 */ 3438static struct drm_display_mode *drm_mode_detailed(struct drm_connector *connector, 3439 const struct drm_edid *drm_edid, 3440 const struct detailed_timing *timing) 3441{ 3442 const struct drm_display_info *info = &connector->display_info; 3443 struct drm_device *dev = connector->dev; 3444 struct drm_display_mode *mode; 3445 const struct detailed_pixel_timing *pt = &timing->data.pixel_data; 3446 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; 3447 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; 3448 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; 3449 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; 3450 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo; 3451 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo; 3452 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4; 3453 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf); 3454 3455 /* ignore tiny modes */ 3456 if (hactive < 64 || vactive < 64) 3457 return NULL; 3458 3459 if (pt->misc & DRM_EDID_PT_STEREO) { 3460 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Stereo mode not supported\n", 3461 connector->base.id, connector->name); 3462 return NULL; 3463 } 3464 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) { 3465 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Composite sync not supported\n", 3466 connector->base.id, connector->name); 3467 } 3468 3469 /* it is incorrect if hsync/vsync width is zero */ 3470 if (!hsync_pulse_width || !vsync_pulse_width) { 3471 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Incorrect Detailed timing. Wrong Hsync/Vsync pulse width\n", 3472 connector->base.id, connector->name); 3473 return NULL; 3474 } 3475 3476 if (info->quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) { 3477 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false); 3478 if (!mode) 3479 return NULL; 3480 3481 goto set_size; 3482 } 3483 3484 mode = drm_mode_create(dev); 3485 if (!mode) 3486 return NULL; 3487 3488 if (info->quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH) 3489 mode->clock = 1088 * 10; 3490 else 3491 mode->clock = le16_to_cpu(timing->pixel_clock) * 10; 3492 3493 mode->hdisplay = hactive; 3494 mode->hsync_start = mode->hdisplay + hsync_offset; 3495 mode->hsync_end = mode->hsync_start + hsync_pulse_width; 3496 mode->htotal = mode->hdisplay + hblank; 3497 3498 mode->vdisplay = vactive; 3499 mode->vsync_start = mode->vdisplay + vsync_offset; 3500 mode->vsync_end = mode->vsync_start + vsync_pulse_width; 3501 mode->vtotal = mode->vdisplay + vblank; 3502 3503 /* Some EDIDs have bogus h/vsync_end values */ 3504 if (mode->hsync_end > mode->htotal) { 3505 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] reducing hsync_end %d->%d\n", 3506 connector->base.id, connector->name, 3507 mode->hsync_end, mode->htotal); 3508 mode->hsync_end = mode->htotal; 3509 } 3510 if (mode->vsync_end > mode->vtotal) { 3511 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] reducing vsync_end %d->%d\n", 3512 connector->base.id, connector->name, 3513 mode->vsync_end, mode->vtotal); 3514 mode->vsync_end = mode->vtotal; 3515 } 3516 3517 drm_mode_do_interlace_quirk(mode, pt); 3518 3519 if (info->quirks & EDID_QUIRK_DETAILED_SYNC_PP) { 3520 mode->flags |= DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC; 3521 } else { 3522 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? 3523 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 3524 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ? 3525 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 3526 } 3527 3528set_size: 3529 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4; 3530 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8; 3531 3532 if (info->quirks & EDID_QUIRK_DETAILED_IN_CM) { 3533 mode->width_mm *= 10; 3534 mode->height_mm *= 10; 3535 } 3536 3537 if (info->quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) { 3538 mode->width_mm = drm_edid->edid->width_cm * 10; 3539 mode->height_mm = drm_edid->edid->height_cm * 10; 3540 } 3541 3542 mode->type = DRM_MODE_TYPE_DRIVER; 3543 drm_mode_set_name(mode); 3544 3545 return mode; 3546} 3547 3548static bool 3549mode_in_hsync_range(const struct drm_display_mode *mode, 3550 const struct edid *edid, const u8 *t) 3551{ 3552 int hsync, hmin, hmax; 3553 3554 hmin = t[7]; 3555 if (edid->revision >= 4) 3556 hmin += ((t[4] & 0x04) ? 255 : 0); 3557 hmax = t[8]; 3558 if (edid->revision >= 4) 3559 hmax += ((t[4] & 0x08) ? 255 : 0); 3560 hsync = drm_mode_hsync(mode); 3561 3562 return (hsync <= hmax && hsync >= hmin); 3563} 3564 3565static bool 3566mode_in_vsync_range(const struct drm_display_mode *mode, 3567 const struct edid *edid, const u8 *t) 3568{ 3569 int vsync, vmin, vmax; 3570 3571 vmin = t[5]; 3572 if (edid->revision >= 4) 3573 vmin += ((t[4] & 0x01) ? 255 : 0); 3574 vmax = t[6]; 3575 if (edid->revision >= 4) 3576 vmax += ((t[4] & 0x02) ? 255 : 0); 3577 vsync = drm_mode_vrefresh(mode); 3578 3579 return (vsync <= vmax && vsync >= vmin); 3580} 3581 3582static u32 3583range_pixel_clock(const struct edid *edid, const u8 *t) 3584{ 3585 /* unspecified */ 3586 if (t[9] == 0 || t[9] == 255) 3587 return 0; 3588 3589 /* 1.4 with CVT support gives us real precision, yay */ 3590 if (edid->revision >= 4 && t[10] == DRM_EDID_CVT_SUPPORT_FLAG) 3591 return (t[9] * 10000) - ((t[12] >> 2) * 250); 3592 3593 /* 1.3 is pathetic, so fuzz up a bit */ 3594 return t[9] * 10000 + 5001; 3595} 3596 3597static bool mode_in_range(const struct drm_display_mode *mode, 3598 const struct drm_edid *drm_edid, 3599 const struct detailed_timing *timing) 3600{ 3601 const struct edid *edid = drm_edid->edid; 3602 u32 max_clock; 3603 const u8 *t = (const u8 *)timing; 3604 3605 if (!mode_in_hsync_range(mode, edid, t)) 3606 return false; 3607 3608 if (!mode_in_vsync_range(mode, edid, t)) 3609 return false; 3610 3611 if ((max_clock = range_pixel_clock(edid, t))) 3612 if (mode->clock > max_clock) 3613 return false; 3614 3615 /* 1.4 max horizontal check */ 3616 if (edid->revision >= 4 && t[10] == DRM_EDID_CVT_SUPPORT_FLAG) 3617 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3)))) 3618 return false; 3619 3620 if (mode_is_rb(mode) && !drm_monitor_supports_rb(drm_edid)) 3621 return false; 3622 3623 return true; 3624} 3625 3626static bool valid_inferred_mode(const struct drm_connector *connector, 3627 const struct drm_display_mode *mode) 3628{ 3629 const struct drm_display_mode *m; 3630 bool ok = false; 3631 3632 list_for_each_entry(m, &connector->probed_modes, head) { 3633 if (mode->hdisplay == m->hdisplay && 3634 mode->vdisplay == m->vdisplay && 3635 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m)) 3636 return false; /* duplicated */ 3637 if (mode->hdisplay <= m->hdisplay && 3638 mode->vdisplay <= m->vdisplay) 3639 ok = true; 3640 } 3641 return ok; 3642} 3643 3644static int drm_dmt_modes_for_range(struct drm_connector *connector, 3645 const struct drm_edid *drm_edid, 3646 const struct detailed_timing *timing) 3647{ 3648 int i, modes = 0; 3649 struct drm_display_mode *newmode; 3650 struct drm_device *dev = connector->dev; 3651 3652 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 3653 if (mode_in_range(drm_dmt_modes + i, drm_edid, timing) && 3654 valid_inferred_mode(connector, drm_dmt_modes + i)) { 3655 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]); 3656 if (newmode) { 3657 drm_mode_probed_add(connector, newmode); 3658 modes++; 3659 } 3660 } 3661 } 3662 3663 return modes; 3664} 3665 3666/* fix up 1366x768 mode from 1368x768; 3667 * GFT/CVT can't express 1366 width which isn't dividable by 8 3668 */ 3669void drm_mode_fixup_1366x768(struct drm_display_mode *mode) 3670{ 3671 if (mode->hdisplay == 1368 && mode->vdisplay == 768) { 3672 mode->hdisplay = 1366; 3673 mode->hsync_start--; 3674 mode->hsync_end--; 3675 drm_mode_set_name(mode); 3676 } 3677} 3678 3679static int drm_gtf_modes_for_range(struct drm_connector *connector, 3680 const struct drm_edid *drm_edid, 3681 const struct detailed_timing *timing) 3682{ 3683 int i, modes = 0; 3684 struct drm_display_mode *newmode; 3685 struct drm_device *dev = connector->dev; 3686 3687 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 3688 const struct minimode *m = &extra_modes[i]; 3689 3690 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0); 3691 if (!newmode) 3692 return modes; 3693 3694 drm_mode_fixup_1366x768(newmode); 3695 if (!mode_in_range(newmode, drm_edid, timing) || 3696 !valid_inferred_mode(connector, newmode)) { 3697 drm_mode_destroy(dev, newmode); 3698 continue; 3699 } 3700 3701 drm_mode_probed_add(connector, newmode); 3702 modes++; 3703 } 3704 3705 return modes; 3706} 3707 3708static int drm_gtf2_modes_for_range(struct drm_connector *connector, 3709 const struct drm_edid *drm_edid, 3710 const struct detailed_timing *timing) 3711{ 3712 int i, modes = 0; 3713 struct drm_display_mode *newmode; 3714 struct drm_device *dev = connector->dev; 3715 3716 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 3717 const struct minimode *m = &extra_modes[i]; 3718 3719 newmode = drm_gtf2_mode(dev, drm_edid, m->w, m->h, m->r); 3720 if (!newmode) 3721 return modes; 3722 3723 drm_mode_fixup_1366x768(newmode); 3724 if (!mode_in_range(newmode, drm_edid, timing) || 3725 !valid_inferred_mode(connector, newmode)) { 3726 drm_mode_destroy(dev, newmode); 3727 continue; 3728 } 3729 3730 drm_mode_probed_add(connector, newmode); 3731 modes++; 3732 } 3733 3734 return modes; 3735} 3736 3737static int drm_cvt_modes_for_range(struct drm_connector *connector, 3738 const struct drm_edid *drm_edid, 3739 const struct detailed_timing *timing) 3740{ 3741 int i, modes = 0; 3742 struct drm_display_mode *newmode; 3743 struct drm_device *dev = connector->dev; 3744 bool rb = drm_monitor_supports_rb(drm_edid); 3745 3746 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 3747 const struct minimode *m = &extra_modes[i]; 3748 3749 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0); 3750 if (!newmode) 3751 return modes; 3752 3753 drm_mode_fixup_1366x768(newmode); 3754 if (!mode_in_range(newmode, drm_edid, timing) || 3755 !valid_inferred_mode(connector, newmode)) { 3756 drm_mode_destroy(dev, newmode); 3757 continue; 3758 } 3759 3760 drm_mode_probed_add(connector, newmode); 3761 modes++; 3762 } 3763 3764 return modes; 3765} 3766 3767static void 3768do_inferred_modes(const struct detailed_timing *timing, void *c) 3769{ 3770 struct detailed_mode_closure *closure = c; 3771 const struct detailed_non_pixel *data = &timing->data.other_data; 3772 const struct detailed_data_monitor_range *range = &data->data.range; 3773 3774 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE)) 3775 return; 3776 3777 closure->modes += drm_dmt_modes_for_range(closure->connector, 3778 closure->drm_edid, 3779 timing); 3780 3781 if (closure->drm_edid->edid->revision < 2) 3782 return; /* GTF not defined yet */ 3783 3784 switch (range->flags) { 3785 case DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG: 3786 closure->modes += drm_gtf2_modes_for_range(closure->connector, 3787 closure->drm_edid, 3788 timing); 3789 break; 3790 case DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG: 3791 closure->modes += drm_gtf_modes_for_range(closure->connector, 3792 closure->drm_edid, 3793 timing); 3794 break; 3795 case DRM_EDID_CVT_SUPPORT_FLAG: 3796 if (closure->drm_edid->edid->revision < 4) 3797 break; 3798 3799 closure->modes += drm_cvt_modes_for_range(closure->connector, 3800 closure->drm_edid, 3801 timing); 3802 break; 3803 case DRM_EDID_RANGE_LIMITS_ONLY_FLAG: 3804 default: 3805 break; 3806 } 3807} 3808 3809static int add_inferred_modes(struct drm_connector *connector, 3810 const struct drm_edid *drm_edid) 3811{ 3812 struct detailed_mode_closure closure = { 3813 .connector = connector, 3814 .drm_edid = drm_edid, 3815 }; 3816 3817 if (drm_edid->edid->revision >= 1) 3818 drm_for_each_detailed_block(drm_edid, do_inferred_modes, &closure); 3819 3820 return closure.modes; 3821} 3822 3823static int 3824drm_est3_modes(struct drm_connector *connector, const struct detailed_timing *timing) 3825{ 3826 int i, j, m, modes = 0; 3827 struct drm_display_mode *mode; 3828 const u8 *est = ((const u8 *)timing) + 6; 3829 3830 for (i = 0; i < 6; i++) { 3831 for (j = 7; j >= 0; j--) { 3832 m = (i * 8) + (7 - j); 3833 if (m >= ARRAY_SIZE(est3_modes)) 3834 break; 3835 if (est[i] & (1 << j)) { 3836 mode = drm_mode_find_dmt(connector->dev, 3837 est3_modes[m].w, 3838 est3_modes[m].h, 3839 est3_modes[m].r, 3840 est3_modes[m].rb); 3841 if (mode) { 3842 drm_mode_probed_add(connector, mode); 3843 modes++; 3844 } 3845 } 3846 } 3847 } 3848 3849 return modes; 3850} 3851 3852static void 3853do_established_modes(const struct detailed_timing *timing, void *c) 3854{ 3855 struct detailed_mode_closure *closure = c; 3856 3857 if (!is_display_descriptor(timing, EDID_DETAIL_EST_TIMINGS)) 3858 return; 3859 3860 closure->modes += drm_est3_modes(closure->connector, timing); 3861} 3862 3863/* 3864 * Get established modes from EDID and add them. Each EDID block contains a 3865 * bitmap of the supported "established modes" list (defined above). Tease them 3866 * out and add them to the global modes list. 3867 */ 3868static int add_established_modes(struct drm_connector *connector, 3869 const struct drm_edid *drm_edid) 3870{ 3871 struct drm_device *dev = connector->dev; 3872 const struct edid *edid = drm_edid->edid; 3873 unsigned long est_bits = edid->established_timings.t1 | 3874 (edid->established_timings.t2 << 8) | 3875 ((edid->established_timings.mfg_rsvd & 0x80) << 9); 3876 int i, modes = 0; 3877 struct detailed_mode_closure closure = { 3878 .connector = connector, 3879 .drm_edid = drm_edid, 3880 }; 3881 3882 for (i = 0; i <= EDID_EST_TIMINGS; i++) { 3883 if (est_bits & (1<<i)) { 3884 struct drm_display_mode *newmode; 3885 3886 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]); 3887 if (newmode) { 3888 drm_mode_probed_add(connector, newmode); 3889 modes++; 3890 } 3891 } 3892 } 3893 3894 if (edid->revision >= 1) 3895 drm_for_each_detailed_block(drm_edid, do_established_modes, 3896 &closure); 3897 3898 return modes + closure.modes; 3899} 3900 3901static void 3902do_standard_modes(const struct detailed_timing *timing, void *c) 3903{ 3904 struct detailed_mode_closure *closure = c; 3905 const struct detailed_non_pixel *data = &timing->data.other_data; 3906 struct drm_connector *connector = closure->connector; 3907 int i; 3908 3909 if (!is_display_descriptor(timing, EDID_DETAIL_STD_MODES)) 3910 return; 3911 3912 for (i = 0; i < 6; i++) { 3913 const struct std_timing *std = &data->data.timings[i]; 3914 struct drm_display_mode *newmode; 3915 3916 newmode = drm_mode_std(connector, closure->drm_edid, std); 3917 if (newmode) { 3918 drm_mode_probed_add(connector, newmode); 3919 closure->modes++; 3920 } 3921 } 3922} 3923 3924/* 3925 * Get standard modes from EDID and add them. Standard modes can be calculated 3926 * using the appropriate standard (DMT, GTF, or CVT). Grab them from EDID and 3927 * add them to the list. 3928 */ 3929static int add_standard_modes(struct drm_connector *connector, 3930 const struct drm_edid *drm_edid) 3931{ 3932 int i, modes = 0; 3933 struct detailed_mode_closure closure = { 3934 .connector = connector, 3935 .drm_edid = drm_edid, 3936 }; 3937 3938 for (i = 0; i < EDID_STD_TIMINGS; i++) { 3939 struct drm_display_mode *newmode; 3940 3941 newmode = drm_mode_std(connector, drm_edid, 3942 &drm_edid->edid->standard_timings[i]); 3943 if (newmode) { 3944 drm_mode_probed_add(connector, newmode); 3945 modes++; 3946 } 3947 } 3948 3949 if (drm_edid->edid->revision >= 1) 3950 drm_for_each_detailed_block(drm_edid, do_standard_modes, 3951 &closure); 3952 3953 /* XXX should also look for standard codes in VTB blocks */ 3954 3955 return modes + closure.modes; 3956} 3957 3958static int drm_cvt_modes(struct drm_connector *connector, 3959 const struct detailed_timing *timing) 3960{ 3961 int i, j, modes = 0; 3962 struct drm_display_mode *newmode; 3963 struct drm_device *dev = connector->dev; 3964 const struct cvt_timing *cvt; 3965 static const int rates[] = { 60, 85, 75, 60, 50 }; 3966 const u8 empty[3] = { 0, 0, 0 }; 3967 3968 for (i = 0; i < 4; i++) { 3969 int width, height; 3970 3971 cvt = &(timing->data.other_data.data.cvt[i]); 3972 3973 if (!memcmp(cvt->code, empty, 3)) 3974 continue; 3975 3976 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; 3977 switch (cvt->code[1] & 0x0c) { 3978 /* default - because compiler doesn't see that we've enumerated all cases */ 3979 default: 3980 case 0x00: 3981 width = height * 4 / 3; 3982 break; 3983 case 0x04: 3984 width = height * 16 / 9; 3985 break; 3986 case 0x08: 3987 width = height * 16 / 10; 3988 break; 3989 case 0x0c: 3990 width = height * 15 / 9; 3991 break; 3992 } 3993 3994 for (j = 1; j < 5; j++) { 3995 if (cvt->code[2] & (1 << j)) { 3996 newmode = drm_cvt_mode(dev, width, height, 3997 rates[j], j == 0, 3998 false, false); 3999 if (newmode) { 4000 drm_mode_probed_add(connector, newmode); 4001 modes++; 4002 } 4003 } 4004 } 4005 } 4006 4007 return modes; 4008} 4009 4010static void 4011do_cvt_mode(const struct detailed_timing *timing, void *c) 4012{ 4013 struct detailed_mode_closure *closure = c; 4014 4015 if (!is_display_descriptor(timing, EDID_DETAIL_CVT_3BYTE)) 4016 return; 4017 4018 closure->modes += drm_cvt_modes(closure->connector, timing); 4019} 4020 4021static int 4022add_cvt_modes(struct drm_connector *connector, const struct drm_edid *drm_edid) 4023{ 4024 struct detailed_mode_closure closure = { 4025 .connector = connector, 4026 .drm_edid = drm_edid, 4027 }; 4028 4029 if (drm_edid->edid->revision >= 3) 4030 drm_for_each_detailed_block(drm_edid, do_cvt_mode, &closure); 4031 4032 /* XXX should also look for CVT codes in VTB blocks */ 4033 4034 return closure.modes; 4035} 4036 4037static void fixup_detailed_cea_mode_clock(struct drm_connector *connector, 4038 struct drm_display_mode *mode); 4039 4040static void 4041do_detailed_mode(const struct detailed_timing *timing, void *c) 4042{ 4043 struct detailed_mode_closure *closure = c; 4044 struct drm_display_mode *newmode; 4045 4046 if (!is_detailed_timing_descriptor(timing)) 4047 return; 4048 4049 newmode = drm_mode_detailed(closure->connector, 4050 closure->drm_edid, timing); 4051 if (!newmode) 4052 return; 4053 4054 if (closure->preferred) 4055 newmode->type |= DRM_MODE_TYPE_PREFERRED; 4056 4057 /* 4058 * Detailed modes are limited to 10kHz pixel clock resolution, 4059 * so fix up anything that looks like CEA/HDMI mode, but the clock 4060 * is just slightly off. 4061 */ 4062 fixup_detailed_cea_mode_clock(closure->connector, newmode); 4063 4064 drm_mode_probed_add(closure->connector, newmode); 4065 closure->modes++; 4066 closure->preferred = false; 4067} 4068 4069/* 4070 * add_detailed_modes - Add modes from detailed timings 4071 * @connector: attached connector 4072 * @drm_edid: EDID block to scan 4073 */ 4074static int add_detailed_modes(struct drm_connector *connector, 4075 const struct drm_edid *drm_edid) 4076{ 4077 struct detailed_mode_closure closure = { 4078 .connector = connector, 4079 .drm_edid = drm_edid, 4080 }; 4081 4082 if (drm_edid->edid->revision >= 4) 4083 closure.preferred = true; /* first detailed timing is always preferred */ 4084 else 4085 closure.preferred = 4086 drm_edid->edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING; 4087 4088 drm_for_each_detailed_block(drm_edid, do_detailed_mode, &closure); 4089 4090 return closure.modes; 4091} 4092 4093/* CTA-861-H Table 60 - CTA Tag Codes */ 4094#define CTA_DB_AUDIO 1 4095#define CTA_DB_VIDEO 2 4096#define CTA_DB_VENDOR 3 4097#define CTA_DB_SPEAKER 4 4098#define CTA_DB_EXTENDED_TAG 7 4099 4100/* CTA-861-H Table 62 - CTA Extended Tag Codes */ 4101#define CTA_EXT_DB_VIDEO_CAP 0 4102#define CTA_EXT_DB_VENDOR 1 4103#define CTA_EXT_DB_HDR_STATIC_METADATA 6 4104#define CTA_EXT_DB_420_VIDEO_DATA 14 4105#define CTA_EXT_DB_420_VIDEO_CAP_MAP 15 4106#define CTA_EXT_DB_HF_EEODB 0x78 4107#define CTA_EXT_DB_HF_SCDB 0x79 4108 4109#define EDID_BASIC_AUDIO (1 << 6) 4110#define EDID_CEA_YCRCB444 (1 << 5) 4111#define EDID_CEA_YCRCB422 (1 << 4) 4112#define EDID_CEA_VCDB_QS (1 << 6) 4113 4114/* 4115 * Search EDID for CEA extension block. 4116 * 4117 * FIXME: Prefer not returning pointers to raw EDID data. 4118 */ 4119const u8 *drm_find_edid_extension(const struct drm_edid *drm_edid, 4120 int ext_id, int *ext_index) 4121{ 4122 const u8 *edid_ext = NULL; 4123 int i; 4124 4125 /* No EDID or EDID extensions */ 4126 if (!drm_edid || !drm_edid_extension_block_count(drm_edid)) 4127 return NULL; 4128 4129 /* Find CEA extension */ 4130 for (i = *ext_index; i < drm_edid_extension_block_count(drm_edid); i++) { 4131 edid_ext = drm_edid_extension_block_data(drm_edid, i); 4132 if (edid_block_tag(edid_ext) == ext_id) 4133 break; 4134 } 4135 4136 if (i >= drm_edid_extension_block_count(drm_edid)) 4137 return NULL; 4138 4139 *ext_index = i + 1; 4140 4141 return edid_ext; 4142} 4143 4144/* Return true if the EDID has a CTA extension or a DisplayID CTA data block */ 4145static bool drm_edid_has_cta_extension(const struct drm_edid *drm_edid) 4146{ 4147 const struct displayid_block *block; 4148 struct displayid_iter iter; 4149 int ext_index = 0; 4150 bool found = false; 4151 4152 /* Look for a top level CEA extension block */ 4153 if (drm_find_edid_extension(drm_edid, CEA_EXT, &ext_index)) 4154 return true; 4155 4156 /* CEA blocks can also be found embedded in a DisplayID block */ 4157 displayid_iter_edid_begin(drm_edid, &iter); 4158 displayid_iter_for_each(block, &iter) { 4159 if (block->tag == DATA_BLOCK_CTA) { 4160 found = true; 4161 break; 4162 } 4163 } 4164 displayid_iter_end(&iter); 4165 4166 return found; 4167} 4168 4169static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic) 4170{ 4171 BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127); 4172 BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219); 4173 4174 if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1)) 4175 return &edid_cea_modes_1[vic - 1]; 4176 if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193)) 4177 return &edid_cea_modes_193[vic - 193]; 4178 return NULL; 4179} 4180 4181static u8 cea_num_vics(void) 4182{ 4183 return 193 + ARRAY_SIZE(edid_cea_modes_193); 4184} 4185 4186static u8 cea_next_vic(u8 vic) 4187{ 4188 if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1)) 4189 vic = 193; 4190 return vic; 4191} 4192 4193/* 4194 * Calculate the alternate clock for the CEA mode 4195 * (60Hz vs. 59.94Hz etc.) 4196 */ 4197static unsigned int 4198cea_mode_alternate_clock(const struct drm_display_mode *cea_mode) 4199{ 4200 unsigned int clock = cea_mode->clock; 4201 4202 if (drm_mode_vrefresh(cea_mode) % 6 != 0) 4203 return clock; 4204 4205 /* 4206 * edid_cea_modes contains the 59.94Hz 4207 * variant for 240 and 480 line modes, 4208 * and the 60Hz variant otherwise. 4209 */ 4210 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480) 4211 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000); 4212 else 4213 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001); 4214 4215 return clock; 4216} 4217 4218static bool 4219cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode) 4220{ 4221 /* 4222 * For certain VICs the spec allows the vertical 4223 * front porch to vary by one or two lines. 4224 * 4225 * cea_modes[] stores the variant with the shortest 4226 * vertical front porch. We can adjust the mode to 4227 * get the other variants by simply increasing the 4228 * vertical front porch length. 4229 */ 4230 BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 || 4231 cea_mode_for_vic(9)->vtotal != 262 || 4232 cea_mode_for_vic(12)->vtotal != 262 || 4233 cea_mode_for_vic(13)->vtotal != 262 || 4234 cea_mode_for_vic(23)->vtotal != 312 || 4235 cea_mode_for_vic(24)->vtotal != 312 || 4236 cea_mode_for_vic(27)->vtotal != 312 || 4237 cea_mode_for_vic(28)->vtotal != 312); 4238 4239 if (((vic == 8 || vic == 9 || 4240 vic == 12 || vic == 13) && mode->vtotal < 263) || 4241 ((vic == 23 || vic == 24 || 4242 vic == 27 || vic == 28) && mode->vtotal < 314)) { 4243 mode->vsync_start++; 4244 mode->vsync_end++; 4245 mode->vtotal++; 4246 4247 return true; 4248 } 4249 4250 return false; 4251} 4252 4253static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match, 4254 unsigned int clock_tolerance) 4255{ 4256 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 4257 u8 vic; 4258 4259 if (!to_match->clock) 4260 return 0; 4261 4262 if (to_match->picture_aspect_ratio) 4263 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 4264 4265 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) { 4266 struct drm_display_mode cea_mode; 4267 unsigned int clock1, clock2; 4268 4269 drm_mode_init(&cea_mode, cea_mode_for_vic(vic)); 4270 4271 /* Check both 60Hz and 59.94Hz */ 4272 clock1 = cea_mode.clock; 4273 clock2 = cea_mode_alternate_clock(&cea_mode); 4274 4275 if (abs(to_match->clock - clock1) > clock_tolerance && 4276 abs(to_match->clock - clock2) > clock_tolerance) 4277 continue; 4278 4279 do { 4280 if (drm_mode_match(to_match, &cea_mode, match_flags)) 4281 return vic; 4282 } while (cea_mode_alternate_timings(vic, &cea_mode)); 4283 } 4284 4285 return 0; 4286} 4287 4288/** 4289 * drm_match_cea_mode - look for a CEA mode matching given mode 4290 * @to_match: display mode 4291 * 4292 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861 4293 * mode. 4294 */ 4295u8 drm_match_cea_mode(const struct drm_display_mode *to_match) 4296{ 4297 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 4298 u8 vic; 4299 4300 if (!to_match->clock) 4301 return 0; 4302 4303 if (to_match->picture_aspect_ratio) 4304 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 4305 4306 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) { 4307 struct drm_display_mode cea_mode; 4308 unsigned int clock1, clock2; 4309 4310 drm_mode_init(&cea_mode, cea_mode_for_vic(vic)); 4311 4312 /* Check both 60Hz and 59.94Hz */ 4313 clock1 = cea_mode.clock; 4314 clock2 = cea_mode_alternate_clock(&cea_mode); 4315 4316 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) && 4317 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2)) 4318 continue; 4319 4320 do { 4321 if (drm_mode_match(to_match, &cea_mode, match_flags)) 4322 return vic; 4323 } while (cea_mode_alternate_timings(vic, &cea_mode)); 4324 } 4325 4326 return 0; 4327} 4328EXPORT_SYMBOL(drm_match_cea_mode); 4329 4330static bool drm_valid_cea_vic(u8 vic) 4331{ 4332 return cea_mode_for_vic(vic) != NULL; 4333} 4334 4335static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code) 4336{ 4337 const struct drm_display_mode *mode = cea_mode_for_vic(video_code); 4338 4339 if (mode) 4340 return mode->picture_aspect_ratio; 4341 4342 return HDMI_PICTURE_ASPECT_NONE; 4343} 4344 4345static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code) 4346{ 4347 return edid_4k_modes[video_code].picture_aspect_ratio; 4348} 4349 4350/* 4351 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor 4352 * specific block). 4353 */ 4354static unsigned int 4355hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode) 4356{ 4357 return cea_mode_alternate_clock(hdmi_mode); 4358} 4359 4360static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match, 4361 unsigned int clock_tolerance) 4362{ 4363 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 4364 u8 vic; 4365 4366 if (!to_match->clock) 4367 return 0; 4368 4369 if (to_match->picture_aspect_ratio) 4370 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 4371 4372 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 4373 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 4374 unsigned int clock1, clock2; 4375 4376 /* Make sure to also match alternate clocks */ 4377 clock1 = hdmi_mode->clock; 4378 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 4379 4380 if (abs(to_match->clock - clock1) > clock_tolerance && 4381 abs(to_match->clock - clock2) > clock_tolerance) 4382 continue; 4383 4384 if (drm_mode_match(to_match, hdmi_mode, match_flags)) 4385 return vic; 4386 } 4387 4388 return 0; 4389} 4390 4391/* 4392 * drm_match_hdmi_mode - look for a HDMI mode matching given mode 4393 * @to_match: display mode 4394 * 4395 * An HDMI mode is one defined in the HDMI vendor specific block. 4396 * 4397 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one. 4398 */ 4399static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match) 4400{ 4401 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 4402 u8 vic; 4403 4404 if (!to_match->clock) 4405 return 0; 4406 4407 if (to_match->picture_aspect_ratio) 4408 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 4409 4410 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 4411 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 4412 unsigned int clock1, clock2; 4413 4414 /* Make sure to also match alternate clocks */ 4415 clock1 = hdmi_mode->clock; 4416 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 4417 4418 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 4419 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 4420 drm_mode_match(to_match, hdmi_mode, match_flags)) 4421 return vic; 4422 } 4423 return 0; 4424} 4425 4426static bool drm_valid_hdmi_vic(u8 vic) 4427{ 4428 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes); 4429} 4430 4431static int add_alternate_cea_modes(struct drm_connector *connector, 4432 const struct drm_edid *drm_edid) 4433{ 4434 struct drm_device *dev = connector->dev; 4435 struct drm_display_mode *mode, *tmp; 4436 LIST_HEAD(list); 4437 int modes = 0; 4438 4439 /* Don't add CTA modes if the CTA extension block is missing */ 4440 if (!drm_edid_has_cta_extension(drm_edid)) 4441 return 0; 4442 4443 /* 4444 * Go through all probed modes and create a new mode 4445 * with the alternate clock for certain CEA modes. 4446 */ 4447 list_for_each_entry(mode, &connector->probed_modes, head) { 4448 const struct drm_display_mode *cea_mode = NULL; 4449 struct drm_display_mode *newmode; 4450 u8 vic = drm_match_cea_mode(mode); 4451 unsigned int clock1, clock2; 4452 4453 if (drm_valid_cea_vic(vic)) { 4454 cea_mode = cea_mode_for_vic(vic); 4455 clock2 = cea_mode_alternate_clock(cea_mode); 4456 } else { 4457 vic = drm_match_hdmi_mode(mode); 4458 if (drm_valid_hdmi_vic(vic)) { 4459 cea_mode = &edid_4k_modes[vic]; 4460 clock2 = hdmi_mode_alternate_clock(cea_mode); 4461 } 4462 } 4463 4464 if (!cea_mode) 4465 continue; 4466 4467 clock1 = cea_mode->clock; 4468 4469 if (clock1 == clock2) 4470 continue; 4471 4472 if (mode->clock != clock1 && mode->clock != clock2) 4473 continue; 4474 4475 newmode = drm_mode_duplicate(dev, cea_mode); 4476 if (!newmode) 4477 continue; 4478 4479 /* Carry over the stereo flags */ 4480 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK; 4481 4482 /* 4483 * The current mode could be either variant. Make 4484 * sure to pick the "other" clock for the new mode. 4485 */ 4486 if (mode->clock != clock1) 4487 newmode->clock = clock1; 4488 else 4489 newmode->clock = clock2; 4490 4491 list_add_tail(&newmode->head, &list); 4492 } 4493 4494 list_for_each_entry_safe(mode, tmp, &list, head) { 4495 list_del(&mode->head); 4496 drm_mode_probed_add(connector, mode); 4497 modes++; 4498 } 4499 4500 return modes; 4501} 4502 4503static u8 svd_to_vic(u8 svd) 4504{ 4505 /* 0-6 bit vic, 7th bit native mode indicator */ 4506 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192)) 4507 return svd & 127; 4508 4509 return svd; 4510} 4511 4512/* 4513 * Return a display mode for the 0-based vic_index'th VIC across all CTA VDBs in 4514 * the EDID, or NULL on errors. 4515 */ 4516static struct drm_display_mode * 4517drm_display_mode_from_vic_index(struct drm_connector *connector, int vic_index) 4518{ 4519 const struct drm_display_info *info = &connector->display_info; 4520 struct drm_device *dev = connector->dev; 4521 4522 if (!info->vics || vic_index >= info->vics_len || !info->vics[vic_index]) 4523 return NULL; 4524 4525 return drm_display_mode_from_cea_vic(dev, info->vics[vic_index]); 4526} 4527 4528/* 4529 * do_y420vdb_modes - Parse YCBCR 420 only modes 4530 * @connector: connector corresponding to the HDMI sink 4531 * @svds: start of the data block of CEA YCBCR 420 VDB 4532 * @len: length of the CEA YCBCR 420 VDB 4533 * 4534 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB) 4535 * which contains modes which can be supported in YCBCR 420 4536 * output format only. 4537 */ 4538static int do_y420vdb_modes(struct drm_connector *connector, 4539 const u8 *svds, u8 svds_len) 4540{ 4541 struct drm_device *dev = connector->dev; 4542 int modes = 0, i; 4543 4544 for (i = 0; i < svds_len; i++) { 4545 u8 vic = svd_to_vic(svds[i]); 4546 struct drm_display_mode *newmode; 4547 4548 if (!drm_valid_cea_vic(vic)) 4549 continue; 4550 4551 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic)); 4552 if (!newmode) 4553 break; 4554 drm_mode_probed_add(connector, newmode); 4555 modes++; 4556 } 4557 4558 return modes; 4559} 4560 4561/** 4562 * drm_display_mode_from_cea_vic() - return a mode for CEA VIC 4563 * @dev: DRM device 4564 * @video_code: CEA VIC of the mode 4565 * 4566 * Creates a new mode matching the specified CEA VIC. 4567 * 4568 * Returns: A new drm_display_mode on success or NULL on failure 4569 */ 4570struct drm_display_mode * 4571drm_display_mode_from_cea_vic(struct drm_device *dev, 4572 u8 video_code) 4573{ 4574 const struct drm_display_mode *cea_mode; 4575 struct drm_display_mode *newmode; 4576 4577 cea_mode = cea_mode_for_vic(video_code); 4578 if (!cea_mode) 4579 return NULL; 4580 4581 newmode = drm_mode_duplicate(dev, cea_mode); 4582 if (!newmode) 4583 return NULL; 4584 4585 return newmode; 4586} 4587EXPORT_SYMBOL(drm_display_mode_from_cea_vic); 4588 4589/* Add modes based on VICs parsed in parse_cta_vdb() */ 4590static int add_cta_vdb_modes(struct drm_connector *connector) 4591{ 4592 const struct drm_display_info *info = &connector->display_info; 4593 int i, modes = 0; 4594 4595 if (!info->vics) 4596 return 0; 4597 4598 for (i = 0; i < info->vics_len; i++) { 4599 struct drm_display_mode *mode; 4600 4601 mode = drm_display_mode_from_vic_index(connector, i); 4602 if (mode) { 4603 drm_mode_probed_add(connector, mode); 4604 modes++; 4605 } 4606 } 4607 4608 return modes; 4609} 4610 4611struct stereo_mandatory_mode { 4612 int width, height, vrefresh; 4613 unsigned int flags; 4614}; 4615 4616static const struct stereo_mandatory_mode stereo_mandatory_modes[] = { 4617 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 4618 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING }, 4619 { 1920, 1080, 50, 4620 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 4621 { 1920, 1080, 60, 4622 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 4623 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 4624 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING }, 4625 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 4626 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING } 4627}; 4628 4629static bool 4630stereo_match_mandatory(const struct drm_display_mode *mode, 4631 const struct stereo_mandatory_mode *stereo_mode) 4632{ 4633 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 4634 4635 return mode->hdisplay == stereo_mode->width && 4636 mode->vdisplay == stereo_mode->height && 4637 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) && 4638 drm_mode_vrefresh(mode) == stereo_mode->vrefresh; 4639} 4640 4641static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector) 4642{ 4643 struct drm_device *dev = connector->dev; 4644 const struct drm_display_mode *mode; 4645 struct list_head stereo_modes; 4646 int modes = 0, i; 4647 4648 INIT_LIST_HEAD(&stereo_modes); 4649 4650 list_for_each_entry(mode, &connector->probed_modes, head) { 4651 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) { 4652 const struct stereo_mandatory_mode *mandatory; 4653 struct drm_display_mode *new_mode; 4654 4655 if (!stereo_match_mandatory(mode, 4656 &stereo_mandatory_modes[i])) 4657 continue; 4658 4659 mandatory = &stereo_mandatory_modes[i]; 4660 new_mode = drm_mode_duplicate(dev, mode); 4661 if (!new_mode) 4662 continue; 4663 4664 new_mode->flags |= mandatory->flags; 4665 list_add_tail(&new_mode->head, &stereo_modes); 4666 modes++; 4667 } 4668 } 4669 4670 list_splice_tail(&stereo_modes, &connector->probed_modes); 4671 4672 return modes; 4673} 4674 4675static int add_hdmi_mode(struct drm_connector *connector, u8 vic) 4676{ 4677 struct drm_device *dev = connector->dev; 4678 struct drm_display_mode *newmode; 4679 4680 if (!drm_valid_hdmi_vic(vic)) { 4681 drm_err(connector->dev, "[CONNECTOR:%d:%s] Unknown HDMI VIC: %d\n", 4682 connector->base.id, connector->name, vic); 4683 return 0; 4684 } 4685 4686 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]); 4687 if (!newmode) 4688 return 0; 4689 4690 drm_mode_probed_add(connector, newmode); 4691 4692 return 1; 4693} 4694 4695static int add_3d_struct_modes(struct drm_connector *connector, u16 structure, 4696 int vic_index) 4697{ 4698 struct drm_display_mode *newmode; 4699 int modes = 0; 4700 4701 if (structure & (1 << 0)) { 4702 newmode = drm_display_mode_from_vic_index(connector, vic_index); 4703 if (newmode) { 4704 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING; 4705 drm_mode_probed_add(connector, newmode); 4706 modes++; 4707 } 4708 } 4709 if (structure & (1 << 6)) { 4710 newmode = drm_display_mode_from_vic_index(connector, vic_index); 4711 if (newmode) { 4712 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 4713 drm_mode_probed_add(connector, newmode); 4714 modes++; 4715 } 4716 } 4717 if (structure & (1 << 8)) { 4718 newmode = drm_display_mode_from_vic_index(connector, vic_index); 4719 if (newmode) { 4720 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 4721 drm_mode_probed_add(connector, newmode); 4722 modes++; 4723 } 4724 } 4725 4726 return modes; 4727} 4728 4729static bool hdmi_vsdb_latency_present(const u8 *db) 4730{ 4731 return db[8] & BIT(7); 4732} 4733 4734static bool hdmi_vsdb_i_latency_present(const u8 *db) 4735{ 4736 return hdmi_vsdb_latency_present(db) && db[8] & BIT(6); 4737} 4738 4739static int hdmi_vsdb_latency_length(const u8 *db) 4740{ 4741 if (hdmi_vsdb_i_latency_present(db)) 4742 return 4; 4743 else if (hdmi_vsdb_latency_present(db)) 4744 return 2; 4745 else 4746 return 0; 4747} 4748 4749/* 4750 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block 4751 * @connector: connector corresponding to the HDMI sink 4752 * @db: start of the CEA vendor specific block 4753 * @len: length of the CEA block payload, ie. one can access up to db[len] 4754 * 4755 * Parses the HDMI VSDB looking for modes to add to @connector. This function 4756 * also adds the stereo 3d modes when applicable. 4757 */ 4758static int 4759do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len) 4760{ 4761 int modes = 0, offset = 0, i, multi_present = 0, multi_len; 4762 u8 vic_len, hdmi_3d_len = 0; 4763 u16 mask; 4764 u16 structure_all; 4765 4766 if (len < 8) 4767 goto out; 4768 4769 /* no HDMI_Video_Present */ 4770 if (!(db[8] & (1 << 5))) 4771 goto out; 4772 4773 offset += hdmi_vsdb_latency_length(db); 4774 4775 /* the declared length is not long enough for the 2 first bytes 4776 * of additional video format capabilities */ 4777 if (len < (8 + offset + 2)) 4778 goto out; 4779 4780 /* 3D_Present */ 4781 offset++; 4782 if (db[8 + offset] & (1 << 7)) { 4783 modes += add_hdmi_mandatory_stereo_modes(connector); 4784 4785 /* 3D_Multi_present */ 4786 multi_present = (db[8 + offset] & 0x60) >> 5; 4787 } 4788 4789 offset++; 4790 vic_len = db[8 + offset] >> 5; 4791 hdmi_3d_len = db[8 + offset] & 0x1f; 4792 4793 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) { 4794 u8 vic; 4795 4796 vic = db[9 + offset + i]; 4797 modes += add_hdmi_mode(connector, vic); 4798 } 4799 offset += 1 + vic_len; 4800 4801 if (multi_present == 1) 4802 multi_len = 2; 4803 else if (multi_present == 2) 4804 multi_len = 4; 4805 else 4806 multi_len = 0; 4807 4808 if (len < (8 + offset + hdmi_3d_len - 1)) 4809 goto out; 4810 4811 if (hdmi_3d_len < multi_len) 4812 goto out; 4813 4814 if (multi_present == 1 || multi_present == 2) { 4815 /* 3D_Structure_ALL */ 4816 structure_all = (db[8 + offset] << 8) | db[9 + offset]; 4817 4818 /* check if 3D_MASK is present */ 4819 if (multi_present == 2) 4820 mask = (db[10 + offset] << 8) | db[11 + offset]; 4821 else 4822 mask = 0xffff; 4823 4824 for (i = 0; i < 16; i++) { 4825 if (mask & (1 << i)) 4826 modes += add_3d_struct_modes(connector, 4827 structure_all, i); 4828 } 4829 } 4830 4831 offset += multi_len; 4832 4833 for (i = 0; i < (hdmi_3d_len - multi_len); i++) { 4834 int vic_index; 4835 struct drm_display_mode *newmode = NULL; 4836 unsigned int newflag = 0; 4837 bool detail_present; 4838 4839 detail_present = ((db[8 + offset + i] & 0x0f) > 7); 4840 4841 if (detail_present && (i + 1 == hdmi_3d_len - multi_len)) 4842 break; 4843 4844 /* 2D_VIC_order_X */ 4845 vic_index = db[8 + offset + i] >> 4; 4846 4847 /* 3D_Structure_X */ 4848 switch (db[8 + offset + i] & 0x0f) { 4849 case 0: 4850 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING; 4851 break; 4852 case 6: 4853 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 4854 break; 4855 case 8: 4856 /* 3D_Detail_X */ 4857 if ((db[9 + offset + i] >> 4) == 1) 4858 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 4859 break; 4860 } 4861 4862 if (newflag != 0) { 4863 newmode = drm_display_mode_from_vic_index(connector, 4864 vic_index); 4865 4866 if (newmode) { 4867 newmode->flags |= newflag; 4868 drm_mode_probed_add(connector, newmode); 4869 modes++; 4870 } 4871 } 4872 4873 if (detail_present) 4874 i++; 4875 } 4876 4877out: 4878 return modes; 4879} 4880 4881static int 4882cea_revision(const u8 *cea) 4883{ 4884 /* 4885 * FIXME is this correct for the DispID variant? 4886 * The DispID spec doesn't really specify whether 4887 * this is the revision of the CEA extension or 4888 * the DispID CEA data block. And the only value 4889 * given as an example is 0. 4890 */ 4891 return cea[1]; 4892} 4893 4894/* 4895 * CTA Data Block iterator. 4896 * 4897 * Iterate through all CTA Data Blocks in both EDID CTA Extensions and DisplayID 4898 * CTA Data Blocks. 4899 * 4900 * struct cea_db *db: 4901 * struct cea_db_iter iter; 4902 * 4903 * cea_db_iter_edid_begin(edid, &iter); 4904 * cea_db_iter_for_each(db, &iter) { 4905 * // do stuff with db 4906 * } 4907 * cea_db_iter_end(&iter); 4908 */ 4909struct cea_db_iter { 4910 struct drm_edid_iter edid_iter; 4911 struct displayid_iter displayid_iter; 4912 4913 /* Current Data Block Collection. */ 4914 const u8 *collection; 4915 4916 /* Current Data Block index in current collection. */ 4917 int index; 4918 4919 /* End index in current collection. */ 4920 int end; 4921}; 4922 4923/* CTA-861-H section 7.4 CTA Data BLock Collection */ 4924struct cea_db { 4925 u8 tag_length; 4926 u8 data[]; 4927} __packed; 4928 4929static int cea_db_tag(const struct cea_db *db) 4930{ 4931 return db->tag_length >> 5; 4932} 4933 4934static int cea_db_payload_len(const void *_db) 4935{ 4936 /* FIXME: Transition to passing struct cea_db * everywhere. */ 4937 const struct cea_db *db = _db; 4938 4939 return db->tag_length & 0x1f; 4940} 4941 4942static const void *cea_db_data(const struct cea_db *db) 4943{ 4944 return db->data; 4945} 4946 4947static bool cea_db_is_extended_tag(const struct cea_db *db, int tag) 4948{ 4949 return cea_db_tag(db) == CTA_DB_EXTENDED_TAG && 4950 cea_db_payload_len(db) >= 1 && 4951 db->data[0] == tag; 4952} 4953 4954static bool cea_db_is_vendor(const struct cea_db *db, int vendor_oui) 4955{ 4956 const u8 *data = cea_db_data(db); 4957 4958 return cea_db_tag(db) == CTA_DB_VENDOR && 4959 cea_db_payload_len(db) >= 3 && 4960 oui(data[2], data[1], data[0]) == vendor_oui; 4961} 4962 4963static void cea_db_iter_edid_begin(const struct drm_edid *drm_edid, 4964 struct cea_db_iter *iter) 4965{ 4966 memset(iter, 0, sizeof(*iter)); 4967 4968 drm_edid_iter_begin(drm_edid, &iter->edid_iter); 4969 displayid_iter_edid_begin(drm_edid, &iter->displayid_iter); 4970} 4971 4972static const struct cea_db * 4973__cea_db_iter_current_block(const struct cea_db_iter *iter) 4974{ 4975 const struct cea_db *db; 4976 4977 if (!iter->collection) 4978 return NULL; 4979 4980 db = (const struct cea_db *)&iter->collection[iter->index]; 4981 4982 if (iter->index + sizeof(*db) <= iter->end && 4983 iter->index + sizeof(*db) + cea_db_payload_len(db) <= iter->end) 4984 return db; 4985 4986 return NULL; 4987} 4988 4989/* 4990 * References: 4991 * - CTA-861-H section 7.3.3 CTA Extension Version 3 4992 */ 4993static int cea_db_collection_size(const u8 *cta) 4994{ 4995 u8 d = cta[2]; 4996 4997 if (d < 4 || d > 127) 4998 return 0; 4999 5000 return d - 4; 5001} 5002 5003/* 5004 * References: 5005 * - VESA E-EDID v1.4 5006 * - CTA-861-H section 7.3.3 CTA Extension Version 3 5007 */ 5008static const void *__cea_db_iter_edid_next(struct cea_db_iter *iter) 5009{ 5010 const u8 *ext; 5011 5012 drm_edid_iter_for_each(ext, &iter->edid_iter) { 5013 int size; 5014 5015 /* Only support CTA Extension revision 3+ */ 5016 if (ext[0] != CEA_EXT || cea_revision(ext) < 3) 5017 continue; 5018 5019 size = cea_db_collection_size(ext); 5020 if (!size) 5021 continue; 5022 5023 iter->index = 4; 5024 iter->end = iter->index + size; 5025 5026 return ext; 5027 } 5028 5029 return NULL; 5030} 5031 5032/* 5033 * References: 5034 * - DisplayID v1.3 Appendix C: CEA Data Block within a DisplayID Data Block 5035 * - DisplayID v2.0 section 4.10 CTA DisplayID Data Block 5036 * 5037 * Note that the above do not specify any connection between DisplayID Data 5038 * Block revision and CTA Extension versions. 5039 */ 5040static const void *__cea_db_iter_displayid_next(struct cea_db_iter *iter) 5041{ 5042 const struct displayid_block *block; 5043 5044 displayid_iter_for_each(block, &iter->displayid_iter) { 5045 if (block->tag != DATA_BLOCK_CTA) 5046 continue; 5047 5048 /* 5049 * The displayid iterator has already verified the block bounds 5050 * in displayid_iter_block(). 5051 */ 5052 iter->index = sizeof(*block); 5053 iter->end = iter->index + block->num_bytes; 5054 5055 return block; 5056 } 5057 5058 return NULL; 5059} 5060 5061static const struct cea_db *__cea_db_iter_next(struct cea_db_iter *iter) 5062{ 5063 const struct cea_db *db; 5064 5065 if (iter->collection) { 5066 /* Current collection should always be valid. */ 5067 db = __cea_db_iter_current_block(iter); 5068 if (WARN_ON(!db)) { 5069 iter->collection = NULL; 5070 return NULL; 5071 } 5072 5073 /* Next block in CTA Data Block Collection */ 5074 iter->index += sizeof(*db) + cea_db_payload_len(db); 5075 5076 db = __cea_db_iter_current_block(iter); 5077 if (db) 5078 return db; 5079 } 5080 5081 for (;;) { 5082 /* 5083 * Find the next CTA Data Block Collection. First iterate all 5084 * the EDID CTA Extensions, then all the DisplayID CTA blocks. 5085 * 5086 * Per DisplayID v1.3 Appendix B: DisplayID as an EDID 5087 * Extension, it's recommended that DisplayID extensions are 5088 * exposed after all of the CTA Extensions. 5089 */ 5090 iter->collection = __cea_db_iter_edid_next(iter); 5091 if (!iter->collection) 5092 iter->collection = __cea_db_iter_displayid_next(iter); 5093 5094 if (!iter->collection) 5095 return NULL; 5096 5097 db = __cea_db_iter_current_block(iter); 5098 if (db) 5099 return db; 5100 } 5101} 5102 5103#define cea_db_iter_for_each(__db, __iter) \ 5104 while (((__db) = __cea_db_iter_next(__iter))) 5105 5106static void cea_db_iter_end(struct cea_db_iter *iter) 5107{ 5108 displayid_iter_end(&iter->displayid_iter); 5109 drm_edid_iter_end(&iter->edid_iter); 5110 5111 memset(iter, 0, sizeof(*iter)); 5112} 5113 5114static bool cea_db_is_hdmi_vsdb(const struct cea_db *db) 5115{ 5116 return cea_db_is_vendor(db, HDMI_IEEE_OUI) && 5117 cea_db_payload_len(db) >= 5; 5118} 5119 5120static bool cea_db_is_hdmi_forum_vsdb(const struct cea_db *db) 5121{ 5122 return cea_db_is_vendor(db, HDMI_FORUM_IEEE_OUI) && 5123 cea_db_payload_len(db) >= 7; 5124} 5125 5126static bool cea_db_is_hdmi_forum_eeodb(const void *db) 5127{ 5128 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_EEODB) && 5129 cea_db_payload_len(db) >= 2; 5130} 5131 5132static bool cea_db_is_microsoft_vsdb(const struct cea_db *db) 5133{ 5134 return cea_db_is_vendor(db, MICROSOFT_IEEE_OUI) && 5135 cea_db_payload_len(db) == 21; 5136} 5137 5138static bool cea_db_is_vcdb(const struct cea_db *db) 5139{ 5140 return cea_db_is_extended_tag(db, CTA_EXT_DB_VIDEO_CAP) && 5141 cea_db_payload_len(db) == 2; 5142} 5143 5144static bool cea_db_is_hdmi_forum_scdb(const struct cea_db *db) 5145{ 5146 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_SCDB) && 5147 cea_db_payload_len(db) >= 7; 5148} 5149 5150static bool cea_db_is_y420cmdb(const struct cea_db *db) 5151{ 5152 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_CAP_MAP); 5153} 5154 5155static bool cea_db_is_y420vdb(const struct cea_db *db) 5156{ 5157 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_DATA); 5158} 5159 5160static bool cea_db_is_hdmi_hdr_metadata_block(const struct cea_db *db) 5161{ 5162 return cea_db_is_extended_tag(db, CTA_EXT_DB_HDR_STATIC_METADATA) && 5163 cea_db_payload_len(db) >= 3; 5164} 5165 5166/* 5167 * Get the HF-EEODB override extension block count from EDID. 5168 * 5169 * The passed in EDID may be partially read, as long as it has at least two 5170 * blocks (base block and one extension block) if EDID extension count is > 0. 5171 * 5172 * Note that this is *not* how you should parse CTA Data Blocks in general; this 5173 * is only to handle partially read EDIDs. Normally, use the CTA Data Block 5174 * iterators instead. 5175 * 5176 * References: 5177 * - HDMI 2.1 section 10.3.6 HDMI Forum EDID Extension Override Data Block 5178 */ 5179static int edid_hfeeodb_extension_block_count(const struct edid *edid) 5180{ 5181 const u8 *cta; 5182 5183 /* No extensions according to base block, no HF-EEODB. */ 5184 if (!edid_extension_block_count(edid)) 5185 return 0; 5186 5187 /* HF-EEODB is always in the first EDID extension block only */ 5188 cta = edid_extension_block_data(edid, 0); 5189 if (edid_block_tag(cta) != CEA_EXT || cea_revision(cta) < 3) 5190 return 0; 5191 5192 /* Need to have the data block collection, and at least 3 bytes. */ 5193 if (cea_db_collection_size(cta) < 3) 5194 return 0; 5195 5196 /* 5197 * Sinks that include the HF-EEODB in their E-EDID shall include one and 5198 * only one instance of the HF-EEODB in the E-EDID, occupying bytes 4 5199 * through 6 of Block 1 of the E-EDID. 5200 */ 5201 if (!cea_db_is_hdmi_forum_eeodb(&cta[4])) 5202 return 0; 5203 5204 return cta[4 + 2]; 5205} 5206 5207/* 5208 * CTA-861 YCbCr 4:2:0 Capability Map Data Block (CTA Y420CMDB) 5209 * 5210 * Y420CMDB contains a bitmap which gives the index of CTA modes from CTA VDB, 5211 * which can support YCBCR 420 sampling output also (apart from RGB/YCBCR444 5212 * etc). For example, if the bit 0 in bitmap is set, first mode in VDB can 5213 * support YCBCR420 output too. 5214 */ 5215static void parse_cta_y420cmdb(struct drm_connector *connector, 5216 const struct cea_db *db, u64 *y420cmdb_map) 5217{ 5218 struct drm_display_info *info = &connector->display_info; 5219 int i, map_len = cea_db_payload_len(db) - 1; 5220 const u8 *data = cea_db_data(db) + 1; 5221 u64 map = 0; 5222 5223 if (map_len == 0) { 5224 /* All CEA modes support ycbcr420 sampling also.*/ 5225 map = U64_MAX; 5226 goto out; 5227 } 5228 5229 /* 5230 * This map indicates which of the existing CEA block modes 5231 * from VDB can support YCBCR420 output too. So if bit=0 is 5232 * set, first mode from VDB can support YCBCR420 output too. 5233 * We will parse and keep this map, before parsing VDB itself 5234 * to avoid going through the same block again and again. 5235 * 5236 * Spec is not clear about max possible size of this block. 5237 * Clamping max bitmap block size at 8 bytes. Every byte can 5238 * address 8 CEA modes, in this way this map can address 5239 * 8*8 = first 64 SVDs. 5240 */ 5241 if (WARN_ON_ONCE(map_len > 8)) 5242 map_len = 8; 5243 5244 for (i = 0; i < map_len; i++) 5245 map |= (u64)data[i] << (8 * i); 5246 5247out: 5248 if (map) 5249 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420; 5250 5251 *y420cmdb_map = map; 5252} 5253 5254static int add_cea_modes(struct drm_connector *connector, 5255 const struct drm_edid *drm_edid) 5256{ 5257 const struct cea_db *db; 5258 struct cea_db_iter iter; 5259 int modes; 5260 5261 /* CTA VDB block VICs parsed earlier */ 5262 modes = add_cta_vdb_modes(connector); 5263 5264 cea_db_iter_edid_begin(drm_edid, &iter); 5265 cea_db_iter_for_each(db, &iter) { 5266 if (cea_db_is_hdmi_vsdb(db)) { 5267 modes += do_hdmi_vsdb_modes(connector, (const u8 *)db, 5268 cea_db_payload_len(db)); 5269 } else if (cea_db_is_y420vdb(db)) { 5270 const u8 *vdb420 = cea_db_data(db) + 1; 5271 5272 /* Add 4:2:0(only) modes present in EDID */ 5273 modes += do_y420vdb_modes(connector, vdb420, 5274 cea_db_payload_len(db) - 1); 5275 } 5276 } 5277 cea_db_iter_end(&iter); 5278 5279 return modes; 5280} 5281 5282static void fixup_detailed_cea_mode_clock(struct drm_connector *connector, 5283 struct drm_display_mode *mode) 5284{ 5285 const struct drm_display_mode *cea_mode; 5286 int clock1, clock2, clock; 5287 u8 vic; 5288 const char *type; 5289 5290 /* 5291 * allow 5kHz clock difference either way to account for 5292 * the 10kHz clock resolution limit of detailed timings. 5293 */ 5294 vic = drm_match_cea_mode_clock_tolerance(mode, 5); 5295 if (drm_valid_cea_vic(vic)) { 5296 type = "CEA"; 5297 cea_mode = cea_mode_for_vic(vic); 5298 clock1 = cea_mode->clock; 5299 clock2 = cea_mode_alternate_clock(cea_mode); 5300 } else { 5301 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5); 5302 if (drm_valid_hdmi_vic(vic)) { 5303 type = "HDMI"; 5304 cea_mode = &edid_4k_modes[vic]; 5305 clock1 = cea_mode->clock; 5306 clock2 = hdmi_mode_alternate_clock(cea_mode); 5307 } else { 5308 return; 5309 } 5310 } 5311 5312 /* pick whichever is closest */ 5313 if (abs(mode->clock - clock1) < abs(mode->clock - clock2)) 5314 clock = clock1; 5315 else 5316 clock = clock2; 5317 5318 if (mode->clock == clock) 5319 return; 5320 5321 drm_dbg_kms(connector->dev, 5322 "[CONNECTOR:%d:%s] detailed mode matches %s VIC %d, adjusting clock %d -> %d\n", 5323 connector->base.id, connector->name, 5324 type, vic, mode->clock, clock); 5325 mode->clock = clock; 5326} 5327 5328static void drm_calculate_luminance_range(struct drm_connector *connector) 5329{ 5330 struct hdr_static_metadata *hdr_metadata = &connector->hdr_sink_metadata.hdmi_type1; 5331 struct drm_luminance_range_info *luminance_range = 5332 &connector->display_info.luminance_range; 5333 static const u8 pre_computed_values[] = { 5334 50, 51, 52, 53, 55, 56, 57, 58, 59, 61, 62, 63, 65, 66, 68, 69, 5335 71, 72, 74, 75, 77, 79, 81, 82, 84, 86, 88, 90, 92, 94, 96, 98 5336 }; 5337 u32 max_avg, min_cll, max, min, q, r; 5338 5339 if (!(hdr_metadata->metadata_type & BIT(HDMI_STATIC_METADATA_TYPE1))) 5340 return; 5341 5342 max_avg = hdr_metadata->max_fall; 5343 min_cll = hdr_metadata->min_cll; 5344 5345 /* 5346 * From the specification (CTA-861-G), for calculating the maximum 5347 * luminance we need to use: 5348 * Luminance = 50*2**(CV/32) 5349 * Where CV is a one-byte value. 5350 * For calculating this expression we may need float point precision; 5351 * to avoid this complexity level, we take advantage that CV is divided 5352 * by a constant. From the Euclids division algorithm, we know that CV 5353 * can be written as: CV = 32*q + r. Next, we replace CV in the 5354 * Luminance expression and get 50*(2**q)*(2**(r/32)), hence we just 5355 * need to pre-compute the value of r/32. For pre-computing the values 5356 * We just used the following Ruby line: 5357 * (0...32).each {|cv| puts (50*2**(cv/32.0)).round} 5358 * The results of the above expressions can be verified at 5359 * pre_computed_values. 5360 */ 5361 q = max_avg >> 5; 5362 r = max_avg % 32; 5363 max = (1 << q) * pre_computed_values[r]; 5364 5365 /* min luminance: maxLum * (CV/255)^2 / 100 */ 5366 q = DIV_ROUND_CLOSEST(min_cll, 255); 5367 min = max * DIV_ROUND_CLOSEST((q * q), 100); 5368 5369 luminance_range->min_luminance = min; 5370 luminance_range->max_luminance = max; 5371} 5372 5373static uint8_t eotf_supported(const u8 *edid_ext) 5374{ 5375 return edid_ext[2] & 5376 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) | 5377 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) | 5378 BIT(HDMI_EOTF_SMPTE_ST2084) | 5379 BIT(HDMI_EOTF_BT_2100_HLG)); 5380} 5381 5382static uint8_t hdr_metadata_type(const u8 *edid_ext) 5383{ 5384 return edid_ext[3] & 5385 BIT(HDMI_STATIC_METADATA_TYPE1); 5386} 5387 5388static void 5389drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db) 5390{ 5391 u16 len; 5392 5393 len = cea_db_payload_len(db); 5394 5395 connector->hdr_sink_metadata.hdmi_type1.eotf = 5396 eotf_supported(db); 5397 connector->hdr_sink_metadata.hdmi_type1.metadata_type = 5398 hdr_metadata_type(db); 5399 5400 if (len >= 4) 5401 connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4]; 5402 if (len >= 5) 5403 connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5]; 5404 if (len >= 6) { 5405 connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6]; 5406 5407 /* Calculate only when all values are available */ 5408 drm_calculate_luminance_range(connector); 5409 } 5410} 5411 5412/* HDMI Vendor-Specific Data Block (HDMI VSDB, H14b-VSDB) */ 5413static void 5414drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db) 5415{ 5416 u8 len = cea_db_payload_len(db); 5417 5418 if (len >= 6 && (db[6] & (1 << 7))) 5419 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI; 5420 5421 if (len >= 10 && hdmi_vsdb_latency_present(db)) { 5422 connector->latency_present[0] = true; 5423 connector->video_latency[0] = db[9]; 5424 connector->audio_latency[0] = db[10]; 5425 } 5426 5427 if (len >= 12 && hdmi_vsdb_i_latency_present(db)) { 5428 connector->latency_present[1] = true; 5429 connector->video_latency[1] = db[11]; 5430 connector->audio_latency[1] = db[12]; 5431 } 5432 5433 drm_dbg_kms(connector->dev, 5434 "[CONNECTOR:%d:%s] HDMI: latency present %d %d, video latency %d %d, audio latency %d %d\n", 5435 connector->base.id, connector->name, 5436 connector->latency_present[0], connector->latency_present[1], 5437 connector->video_latency[0], connector->video_latency[1], 5438 connector->audio_latency[0], connector->audio_latency[1]); 5439} 5440 5441static void 5442monitor_name(const struct detailed_timing *timing, void *data) 5443{ 5444 const char **res = data; 5445 5446 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_NAME)) 5447 return; 5448 5449 *res = timing->data.other_data.data.str.str; 5450} 5451 5452static int get_monitor_name(const struct drm_edid *drm_edid, char name[13]) 5453{ 5454 const char *edid_name = NULL; 5455 int mnl; 5456 5457 if (!drm_edid || !name) 5458 return 0; 5459 5460 drm_for_each_detailed_block(drm_edid, monitor_name, &edid_name); 5461 for (mnl = 0; edid_name && mnl < 13; mnl++) { 5462 if (edid_name[mnl] == 0x0a) 5463 break; 5464 5465 name[mnl] = edid_name[mnl]; 5466 } 5467 5468 return mnl; 5469} 5470 5471/** 5472 * drm_edid_get_monitor_name - fetch the monitor name from the edid 5473 * @edid: monitor EDID information 5474 * @name: pointer to a character array to hold the name of the monitor 5475 * @bufsize: The size of the name buffer (should be at least 14 chars.) 5476 * 5477 */ 5478void drm_edid_get_monitor_name(const struct edid *edid, char *name, int bufsize) 5479{ 5480 int name_length = 0; 5481 5482 if (bufsize <= 0) 5483 return; 5484 5485 if (edid) { 5486 char buf[13]; 5487 struct drm_edid drm_edid = { 5488 .edid = edid, 5489 .size = edid_size(edid), 5490 }; 5491 5492 name_length = min(get_monitor_name(&drm_edid, buf), bufsize - 1); 5493 memcpy(name, buf, name_length); 5494 } 5495 5496 name[name_length] = '\0'; 5497} 5498EXPORT_SYMBOL(drm_edid_get_monitor_name); 5499 5500static void clear_eld(struct drm_connector *connector) 5501{ 5502 memset(connector->eld, 0, sizeof(connector->eld)); 5503 5504 connector->latency_present[0] = false; 5505 connector->latency_present[1] = false; 5506 connector->video_latency[0] = 0; 5507 connector->audio_latency[0] = 0; 5508 connector->video_latency[1] = 0; 5509 connector->audio_latency[1] = 0; 5510} 5511 5512/* 5513 * drm_edid_to_eld - build ELD from EDID 5514 * @connector: connector corresponding to the HDMI/DP sink 5515 * @drm_edid: EDID to parse 5516 * 5517 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The 5518 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in. 5519 */ 5520static void drm_edid_to_eld(struct drm_connector *connector, 5521 const struct drm_edid *drm_edid) 5522{ 5523 const struct drm_display_info *info = &connector->display_info; 5524 const struct cea_db *db; 5525 struct cea_db_iter iter; 5526 uint8_t *eld = connector->eld; 5527 int total_sad_count = 0; 5528 int mnl; 5529 5530 if (!drm_edid) 5531 return; 5532 5533 mnl = get_monitor_name(drm_edid, &eld[DRM_ELD_MONITOR_NAME_STRING]); 5534 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] ELD monitor %s\n", 5535 connector->base.id, connector->name, 5536 &eld[DRM_ELD_MONITOR_NAME_STRING]); 5537 5538 eld[DRM_ELD_CEA_EDID_VER_MNL] = info->cea_rev << DRM_ELD_CEA_EDID_VER_SHIFT; 5539 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl; 5540 5541 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D; 5542 5543 eld[DRM_ELD_MANUFACTURER_NAME0] = drm_edid->edid->mfg_id[0]; 5544 eld[DRM_ELD_MANUFACTURER_NAME1] = drm_edid->edid->mfg_id[1]; 5545 eld[DRM_ELD_PRODUCT_CODE0] = drm_edid->edid->prod_code[0]; 5546 eld[DRM_ELD_PRODUCT_CODE1] = drm_edid->edid->prod_code[1]; 5547 5548 cea_db_iter_edid_begin(drm_edid, &iter); 5549 cea_db_iter_for_each(db, &iter) { 5550 const u8 *data = cea_db_data(db); 5551 int len = cea_db_payload_len(db); 5552 int sad_count; 5553 5554 switch (cea_db_tag(db)) { 5555 case CTA_DB_AUDIO: 5556 /* Audio Data Block, contains SADs */ 5557 sad_count = min(len / 3, 15 - total_sad_count); 5558 if (sad_count >= 1) 5559 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)], 5560 data, sad_count * 3); 5561 total_sad_count += sad_count; 5562 break; 5563 case CTA_DB_SPEAKER: 5564 /* Speaker Allocation Data Block */ 5565 if (len >= 1) 5566 eld[DRM_ELD_SPEAKER] = data[0]; 5567 break; 5568 case CTA_DB_VENDOR: 5569 /* HDMI Vendor-Specific Data Block */ 5570 if (cea_db_is_hdmi_vsdb(db)) 5571 drm_parse_hdmi_vsdb_audio(connector, (const u8 *)db); 5572 break; 5573 default: 5574 break; 5575 } 5576 } 5577 cea_db_iter_end(&iter); 5578 5579 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT; 5580 5581 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || 5582 connector->connector_type == DRM_MODE_CONNECTOR_eDP) 5583 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP; 5584 else 5585 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI; 5586 5587 eld[DRM_ELD_BASELINE_ELD_LEN] = 5588 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4); 5589 5590 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] ELD size %d, SAD count %d\n", 5591 connector->base.id, connector->name, 5592 drm_eld_size(eld), total_sad_count); 5593} 5594 5595static int _drm_edid_to_sad(const struct drm_edid *drm_edid, 5596 struct cea_sad **sads) 5597{ 5598 const struct cea_db *db; 5599 struct cea_db_iter iter; 5600 int count = 0; 5601 5602 cea_db_iter_edid_begin(drm_edid, &iter); 5603 cea_db_iter_for_each(db, &iter) { 5604 if (cea_db_tag(db) == CTA_DB_AUDIO) { 5605 int j; 5606 5607 count = cea_db_payload_len(db) / 3; /* SAD is 3B */ 5608 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL); 5609 if (!*sads) 5610 return -ENOMEM; 5611 for (j = 0; j < count; j++) { 5612 const u8 *sad = &db->data[j * 3]; 5613 5614 (*sads)[j].format = (sad[0] & 0x78) >> 3; 5615 (*sads)[j].channels = sad[0] & 0x7; 5616 (*sads)[j].freq = sad[1] & 0x7F; 5617 (*sads)[j].byte2 = sad[2]; 5618 } 5619 break; 5620 } 5621 } 5622 cea_db_iter_end(&iter); 5623 5624 DRM_DEBUG_KMS("Found %d Short Audio Descriptors\n", count); 5625 5626 return count; 5627} 5628 5629/** 5630 * drm_edid_to_sad - extracts SADs from EDID 5631 * @edid: EDID to parse 5632 * @sads: pointer that will be set to the extracted SADs 5633 * 5634 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it. 5635 * 5636 * Note: The returned pointer needs to be freed using kfree(). 5637 * 5638 * Return: The number of found SADs or negative number on error. 5639 */ 5640int drm_edid_to_sad(const struct edid *edid, struct cea_sad **sads) 5641{ 5642 struct drm_edid drm_edid; 5643 5644 return _drm_edid_to_sad(drm_edid_legacy_init(&drm_edid, edid), sads); 5645} 5646EXPORT_SYMBOL(drm_edid_to_sad); 5647 5648static int _drm_edid_to_speaker_allocation(const struct drm_edid *drm_edid, 5649 u8 **sadb) 5650{ 5651 const struct cea_db *db; 5652 struct cea_db_iter iter; 5653 int count = 0; 5654 5655 cea_db_iter_edid_begin(drm_edid, &iter); 5656 cea_db_iter_for_each(db, &iter) { 5657 if (cea_db_tag(db) == CTA_DB_SPEAKER && 5658 cea_db_payload_len(db) == 3) { 5659 *sadb = kmemdup(db->data, cea_db_payload_len(db), 5660 GFP_KERNEL); 5661 if (!*sadb) 5662 return -ENOMEM; 5663 count = cea_db_payload_len(db); 5664 break; 5665 } 5666 } 5667 cea_db_iter_end(&iter); 5668 5669 DRM_DEBUG_KMS("Found %d Speaker Allocation Data Blocks\n", count); 5670 5671 return count; 5672} 5673 5674/** 5675 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID 5676 * @edid: EDID to parse 5677 * @sadb: pointer to the speaker block 5678 * 5679 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it. 5680 * 5681 * Note: The returned pointer needs to be freed using kfree(). 5682 * 5683 * Return: The number of found Speaker Allocation Blocks or negative number on 5684 * error. 5685 */ 5686int drm_edid_to_speaker_allocation(const struct edid *edid, u8 **sadb) 5687{ 5688 struct drm_edid drm_edid; 5689 5690 return _drm_edid_to_speaker_allocation(drm_edid_legacy_init(&drm_edid, edid), 5691 sadb); 5692} 5693EXPORT_SYMBOL(drm_edid_to_speaker_allocation); 5694 5695/** 5696 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay 5697 * @connector: connector associated with the HDMI/DP sink 5698 * @mode: the display mode 5699 * 5700 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if 5701 * the sink doesn't support audio or video. 5702 */ 5703int drm_av_sync_delay(struct drm_connector *connector, 5704 const struct drm_display_mode *mode) 5705{ 5706 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); 5707 int a, v; 5708 5709 if (!connector->latency_present[0]) 5710 return 0; 5711 if (!connector->latency_present[1]) 5712 i = 0; 5713 5714 a = connector->audio_latency[i]; 5715 v = connector->video_latency[i]; 5716 5717 /* 5718 * HDMI/DP sink doesn't support audio or video? 5719 */ 5720 if (a == 255 || v == 255) 5721 return 0; 5722 5723 /* 5724 * Convert raw EDID values to millisecond. 5725 * Treat unknown latency as 0ms. 5726 */ 5727 if (a) 5728 a = min(2 * (a - 1), 500); 5729 if (v) 5730 v = min(2 * (v - 1), 500); 5731 5732 return max(v - a, 0); 5733} 5734EXPORT_SYMBOL(drm_av_sync_delay); 5735 5736static bool _drm_detect_hdmi_monitor(const struct drm_edid *drm_edid) 5737{ 5738 const struct cea_db *db; 5739 struct cea_db_iter iter; 5740 bool hdmi = false; 5741 5742 /* 5743 * Because HDMI identifier is in Vendor Specific Block, 5744 * search it from all data blocks of CEA extension. 5745 */ 5746 cea_db_iter_edid_begin(drm_edid, &iter); 5747 cea_db_iter_for_each(db, &iter) { 5748 if (cea_db_is_hdmi_vsdb(db)) { 5749 hdmi = true; 5750 break; 5751 } 5752 } 5753 cea_db_iter_end(&iter); 5754 5755 return hdmi; 5756} 5757 5758/** 5759 * drm_detect_hdmi_monitor - detect whether monitor is HDMI 5760 * @edid: monitor EDID information 5761 * 5762 * Parse the CEA extension according to CEA-861-B. 5763 * 5764 * Drivers that have added the modes parsed from EDID to drm_display_info 5765 * should use &drm_display_info.is_hdmi instead of calling this function. 5766 * 5767 * Return: True if the monitor is HDMI, false if not or unknown. 5768 */ 5769bool drm_detect_hdmi_monitor(const struct edid *edid) 5770{ 5771 struct drm_edid drm_edid; 5772 5773 return _drm_detect_hdmi_monitor(drm_edid_legacy_init(&drm_edid, edid)); 5774} 5775EXPORT_SYMBOL(drm_detect_hdmi_monitor); 5776 5777static bool _drm_detect_monitor_audio(const struct drm_edid *drm_edid) 5778{ 5779 struct drm_edid_iter edid_iter; 5780 const struct cea_db *db; 5781 struct cea_db_iter iter; 5782 const u8 *edid_ext; 5783 bool has_audio = false; 5784 5785 drm_edid_iter_begin(drm_edid, &edid_iter); 5786 drm_edid_iter_for_each(edid_ext, &edid_iter) { 5787 if (edid_ext[0] == CEA_EXT) { 5788 has_audio = edid_ext[3] & EDID_BASIC_AUDIO; 5789 if (has_audio) 5790 break; 5791 } 5792 } 5793 drm_edid_iter_end(&edid_iter); 5794 5795 if (has_audio) { 5796 DRM_DEBUG_KMS("Monitor has basic audio support\n"); 5797 goto end; 5798 } 5799 5800 cea_db_iter_edid_begin(drm_edid, &iter); 5801 cea_db_iter_for_each(db, &iter) { 5802 if (cea_db_tag(db) == CTA_DB_AUDIO) { 5803 const u8 *data = cea_db_data(db); 5804 int i; 5805 5806 for (i = 0; i < cea_db_payload_len(db); i += 3) 5807 DRM_DEBUG_KMS("CEA audio format %d\n", 5808 (data[i] >> 3) & 0xf); 5809 has_audio = true; 5810 break; 5811 } 5812 } 5813 cea_db_iter_end(&iter); 5814 5815end: 5816 return has_audio; 5817} 5818 5819/** 5820 * drm_detect_monitor_audio - check monitor audio capability 5821 * @edid: EDID block to scan 5822 * 5823 * Monitor should have CEA extension block. 5824 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic 5825 * audio' only. If there is any audio extension block and supported 5826 * audio format, assume at least 'basic audio' support, even if 'basic 5827 * audio' is not defined in EDID. 5828 * 5829 * Return: True if the monitor supports audio, false otherwise. 5830 */ 5831bool drm_detect_monitor_audio(const struct edid *edid) 5832{ 5833 struct drm_edid drm_edid; 5834 5835 return _drm_detect_monitor_audio(drm_edid_legacy_init(&drm_edid, edid)); 5836} 5837EXPORT_SYMBOL(drm_detect_monitor_audio); 5838 5839 5840/** 5841 * drm_default_rgb_quant_range - default RGB quantization range 5842 * @mode: display mode 5843 * 5844 * Determine the default RGB quantization range for the mode, 5845 * as specified in CEA-861. 5846 * 5847 * Return: The default RGB quantization range for the mode 5848 */ 5849enum hdmi_quantization_range 5850drm_default_rgb_quant_range(const struct drm_display_mode *mode) 5851{ 5852 /* All CEA modes other than VIC 1 use limited quantization range. */ 5853 return drm_match_cea_mode(mode) > 1 ? 5854 HDMI_QUANTIZATION_RANGE_LIMITED : 5855 HDMI_QUANTIZATION_RANGE_FULL; 5856} 5857EXPORT_SYMBOL(drm_default_rgb_quant_range); 5858 5859/* CTA-861 Video Data Block (CTA VDB) */ 5860static void parse_cta_vdb(struct drm_connector *connector, const struct cea_db *db) 5861{ 5862 struct drm_display_info *info = &connector->display_info; 5863 int i, vic_index, len = cea_db_payload_len(db); 5864 const u8 *svds = cea_db_data(db); 5865 u8 *vics; 5866 5867 if (!len) 5868 return; 5869 5870 /* Gracefully handle multiple VDBs, however unlikely that is */ 5871 vics = krealloc(info->vics, info->vics_len + len, GFP_KERNEL); 5872 if (!vics) 5873 return; 5874 5875 vic_index = info->vics_len; 5876 info->vics_len += len; 5877 info->vics = vics; 5878 5879 for (i = 0; i < len; i++) { 5880 u8 vic = svd_to_vic(svds[i]); 5881 5882 if (!drm_valid_cea_vic(vic)) 5883 vic = 0; 5884 5885 info->vics[vic_index++] = vic; 5886 } 5887} 5888 5889/* 5890 * Update y420_cmdb_modes based on previously parsed CTA VDB and Y420CMDB. 5891 * 5892 * Translate the y420cmdb_map based on VIC indexes to y420_cmdb_modes indexed 5893 * using the VICs themselves. 5894 */ 5895static void update_cta_y420cmdb(struct drm_connector *connector, u64 y420cmdb_map) 5896{ 5897 struct drm_display_info *info = &connector->display_info; 5898 struct drm_hdmi_info *hdmi = &info->hdmi; 5899 int i, len = min_t(int, info->vics_len, BITS_PER_TYPE(y420cmdb_map)); 5900 5901 for (i = 0; i < len; i++) { 5902 u8 vic = info->vics[i]; 5903 5904 if (vic && y420cmdb_map & BIT_ULL(i)) 5905 bitmap_set(hdmi->y420_cmdb_modes, vic, 1); 5906 } 5907} 5908 5909static bool cta_vdb_has_vic(const struct drm_connector *connector, u8 vic) 5910{ 5911 const struct drm_display_info *info = &connector->display_info; 5912 int i; 5913 5914 if (!vic || !info->vics) 5915 return false; 5916 5917 for (i = 0; i < info->vics_len; i++) { 5918 if (info->vics[i] == vic) 5919 return true; 5920 } 5921 5922 return false; 5923} 5924 5925/* CTA-861-H YCbCr 4:2:0 Video Data Block (CTA Y420VDB) */ 5926static void parse_cta_y420vdb(struct drm_connector *connector, 5927 const struct cea_db *db) 5928{ 5929 struct drm_display_info *info = &connector->display_info; 5930 struct drm_hdmi_info *hdmi = &info->hdmi; 5931 const u8 *svds = cea_db_data(db) + 1; 5932 int i; 5933 5934 for (i = 0; i < cea_db_payload_len(db) - 1; i++) { 5935 u8 vic = svd_to_vic(svds[i]); 5936 5937 if (!drm_valid_cea_vic(vic)) 5938 continue; 5939 5940 bitmap_set(hdmi->y420_vdb_modes, vic, 1); 5941 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420; 5942 } 5943} 5944 5945static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db) 5946{ 5947 struct drm_display_info *info = &connector->display_info; 5948 5949 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] CEA VCDB 0x%02x\n", 5950 connector->base.id, connector->name, db[2]); 5951 5952 if (db[2] & EDID_CEA_VCDB_QS) 5953 info->rgb_quant_range_selectable = true; 5954} 5955 5956static 5957void drm_get_max_frl_rate(int max_frl_rate, u8 *max_lanes, u8 *max_rate_per_lane) 5958{ 5959 switch (max_frl_rate) { 5960 case 1: 5961 *max_lanes = 3; 5962 *max_rate_per_lane = 3; 5963 break; 5964 case 2: 5965 *max_lanes = 3; 5966 *max_rate_per_lane = 6; 5967 break; 5968 case 3: 5969 *max_lanes = 4; 5970 *max_rate_per_lane = 6; 5971 break; 5972 case 4: 5973 *max_lanes = 4; 5974 *max_rate_per_lane = 8; 5975 break; 5976 case 5: 5977 *max_lanes = 4; 5978 *max_rate_per_lane = 10; 5979 break; 5980 case 6: 5981 *max_lanes = 4; 5982 *max_rate_per_lane = 12; 5983 break; 5984 case 0: 5985 default: 5986 *max_lanes = 0; 5987 *max_rate_per_lane = 0; 5988 } 5989} 5990 5991static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector, 5992 const u8 *db) 5993{ 5994 u8 dc_mask; 5995 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 5996 5997 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK; 5998 hdmi->y420_dc_modes = dc_mask; 5999} 6000 6001static void drm_parse_dsc_info(struct drm_hdmi_dsc_cap *hdmi_dsc, 6002 const u8 *hf_scds) 6003{ 6004 hdmi_dsc->v_1p2 = hf_scds[11] & DRM_EDID_DSC_1P2; 6005 6006 if (!hdmi_dsc->v_1p2) 6007 return; 6008 6009 hdmi_dsc->native_420 = hf_scds[11] & DRM_EDID_DSC_NATIVE_420; 6010 hdmi_dsc->all_bpp = hf_scds[11] & DRM_EDID_DSC_ALL_BPP; 6011 6012 if (hf_scds[11] & DRM_EDID_DSC_16BPC) 6013 hdmi_dsc->bpc_supported = 16; 6014 else if (hf_scds[11] & DRM_EDID_DSC_12BPC) 6015 hdmi_dsc->bpc_supported = 12; 6016 else if (hf_scds[11] & DRM_EDID_DSC_10BPC) 6017 hdmi_dsc->bpc_supported = 10; 6018 else 6019 /* Supports min 8 BPC if DSC 1.2 is supported*/ 6020 hdmi_dsc->bpc_supported = 8; 6021 6022 if (cea_db_payload_len(hf_scds) >= 12 && hf_scds[12]) { 6023 u8 dsc_max_slices; 6024 u8 dsc_max_frl_rate; 6025 6026 dsc_max_frl_rate = (hf_scds[12] & DRM_EDID_DSC_MAX_FRL_RATE_MASK) >> 4; 6027 drm_get_max_frl_rate(dsc_max_frl_rate, &hdmi_dsc->max_lanes, 6028 &hdmi_dsc->max_frl_rate_per_lane); 6029 6030 dsc_max_slices = hf_scds[12] & DRM_EDID_DSC_MAX_SLICES; 6031 6032 switch (dsc_max_slices) { 6033 case 1: 6034 hdmi_dsc->max_slices = 1; 6035 hdmi_dsc->clk_per_slice = 340; 6036 break; 6037 case 2: 6038 hdmi_dsc->max_slices = 2; 6039 hdmi_dsc->clk_per_slice = 340; 6040 break; 6041 case 3: 6042 hdmi_dsc->max_slices = 4; 6043 hdmi_dsc->clk_per_slice = 340; 6044 break; 6045 case 4: 6046 hdmi_dsc->max_slices = 8; 6047 hdmi_dsc->clk_per_slice = 340; 6048 break; 6049 case 5: 6050 hdmi_dsc->max_slices = 8; 6051 hdmi_dsc->clk_per_slice = 400; 6052 break; 6053 case 6: 6054 hdmi_dsc->max_slices = 12; 6055 hdmi_dsc->clk_per_slice = 400; 6056 break; 6057 case 7: 6058 hdmi_dsc->max_slices = 16; 6059 hdmi_dsc->clk_per_slice = 400; 6060 break; 6061 case 0: 6062 default: 6063 hdmi_dsc->max_slices = 0; 6064 hdmi_dsc->clk_per_slice = 0; 6065 } 6066 } 6067 6068 if (cea_db_payload_len(hf_scds) >= 13 && hf_scds[13]) 6069 hdmi_dsc->total_chunk_kbytes = hf_scds[13] & DRM_EDID_DSC_TOTAL_CHUNK_KBYTES; 6070} 6071 6072/* Sink Capability Data Structure */ 6073static void drm_parse_hdmi_forum_scds(struct drm_connector *connector, 6074 const u8 *hf_scds) 6075{ 6076 struct drm_display_info *info = &connector->display_info; 6077 struct drm_hdmi_info *hdmi = &info->hdmi; 6078 struct drm_hdmi_dsc_cap *hdmi_dsc = &hdmi->dsc_cap; 6079 int max_tmds_clock = 0; 6080 u8 max_frl_rate = 0; 6081 bool dsc_support = false; 6082 6083 info->has_hdmi_infoframe = true; 6084 6085 if (hf_scds[6] & 0x80) { 6086 hdmi->scdc.supported = true; 6087 if (hf_scds[6] & 0x40) 6088 hdmi->scdc.read_request = true; 6089 } 6090 6091 /* 6092 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz. 6093 * And as per the spec, three factors confirm this: 6094 * * Availability of a HF-VSDB block in EDID (check) 6095 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check) 6096 * * SCDC support available (let's check) 6097 * Lets check it out. 6098 */ 6099 6100 if (hf_scds[5]) { 6101 struct drm_scdc *scdc = &hdmi->scdc; 6102 6103 /* max clock is 5000 KHz times block value */ 6104 max_tmds_clock = hf_scds[5] * 5000; 6105 6106 if (max_tmds_clock > 340000) { 6107 info->max_tmds_clock = max_tmds_clock; 6108 } 6109 6110 if (scdc->supported) { 6111 scdc->scrambling.supported = true; 6112 6113 /* Few sinks support scrambling for clocks < 340M */ 6114 if ((hf_scds[6] & 0x8)) 6115 scdc->scrambling.low_rates = true; 6116 } 6117 } 6118 6119 if (hf_scds[7]) { 6120 max_frl_rate = (hf_scds[7] & DRM_EDID_MAX_FRL_RATE_MASK) >> 4; 6121 drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes, 6122 &hdmi->max_frl_rate_per_lane); 6123 } 6124 6125 drm_parse_ycbcr420_deep_color_info(connector, hf_scds); 6126 6127 if (cea_db_payload_len(hf_scds) >= 11 && hf_scds[11]) { 6128 drm_parse_dsc_info(hdmi_dsc, hf_scds); 6129 dsc_support = true; 6130 } 6131 6132 drm_dbg_kms(connector->dev, 6133 "[CONNECTOR:%d:%s] HF-VSDB: max TMDS clock: %d KHz, HDMI 2.1 support: %s, DSC 1.2 support: %s\n", 6134 connector->base.id, connector->name, 6135 max_tmds_clock, str_yes_no(max_frl_rate), str_yes_no(dsc_support)); 6136} 6137 6138static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector, 6139 const u8 *hdmi) 6140{ 6141 struct drm_display_info *info = &connector->display_info; 6142 unsigned int dc_bpc = 0; 6143 6144 /* HDMI supports at least 8 bpc */ 6145 info->bpc = 8; 6146 6147 if (cea_db_payload_len(hdmi) < 6) 6148 return; 6149 6150 if (hdmi[6] & DRM_EDID_HDMI_DC_30) { 6151 dc_bpc = 10; 6152 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_30; 6153 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 30.\n", 6154 connector->base.id, connector->name); 6155 } 6156 6157 if (hdmi[6] & DRM_EDID_HDMI_DC_36) { 6158 dc_bpc = 12; 6159 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_36; 6160 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 36.\n", 6161 connector->base.id, connector->name); 6162 } 6163 6164 if (hdmi[6] & DRM_EDID_HDMI_DC_48) { 6165 dc_bpc = 16; 6166 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_48; 6167 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 48.\n", 6168 connector->base.id, connector->name); 6169 } 6170 6171 if (dc_bpc == 0) { 6172 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] No deep color support on this HDMI sink.\n", 6173 connector->base.id, connector->name); 6174 return; 6175 } 6176 6177 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Assigning HDMI sink color depth as %d bpc.\n", 6178 connector->base.id, connector->name, dc_bpc); 6179 info->bpc = dc_bpc; 6180 6181 /* YCRCB444 is optional according to spec. */ 6182 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) { 6183 info->edid_hdmi_ycbcr444_dc_modes = info->edid_hdmi_rgb444_dc_modes; 6184 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does YCRCB444 in deep color.\n", 6185 connector->base.id, connector->name); 6186 } 6187 6188 /* 6189 * Spec says that if any deep color mode is supported at all, 6190 * then deep color 36 bit must be supported. 6191 */ 6192 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) { 6193 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink should do DC_36, but does not!\n", 6194 connector->base.id, connector->name); 6195 } 6196} 6197 6198/* HDMI Vendor-Specific Data Block (HDMI VSDB, H14b-VSDB) */ 6199static void 6200drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db) 6201{ 6202 struct drm_display_info *info = &connector->display_info; 6203 u8 len = cea_db_payload_len(db); 6204 6205 info->is_hdmi = true; 6206 6207 if (len >= 6) 6208 info->dvi_dual = db[6] & 1; 6209 if (len >= 7) 6210 info->max_tmds_clock = db[7] * 5000; 6211 6212 /* 6213 * Try to infer whether the sink supports HDMI infoframes. 6214 * 6215 * HDMI infoframe support was first added in HDMI 1.4. Assume the sink 6216 * supports infoframes if HDMI_Video_present is set. 6217 */ 6218 if (len >= 8 && db[8] & BIT(5)) 6219 info->has_hdmi_infoframe = true; 6220 6221 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI: DVI dual %d, max TMDS clock %d kHz\n", 6222 connector->base.id, connector->name, 6223 info->dvi_dual, info->max_tmds_clock); 6224 6225 drm_parse_hdmi_deep_color_info(connector, db); 6226} 6227 6228/* 6229 * See EDID extension for head-mounted and specialized monitors, specified at: 6230 * https://docs.microsoft.com/en-us/windows-hardware/drivers/display/specialized-monitors-edid-extension 6231 */ 6232static void drm_parse_microsoft_vsdb(struct drm_connector *connector, 6233 const u8 *db) 6234{ 6235 struct drm_display_info *info = &connector->display_info; 6236 u8 version = db[4]; 6237 bool desktop_usage = db[5] & BIT(6); 6238 6239 /* Version 1 and 2 for HMDs, version 3 flags desktop usage explicitly */ 6240 if (version == 1 || version == 2 || (version == 3 && !desktop_usage)) 6241 info->non_desktop = true; 6242 6243 drm_dbg_kms(connector->dev, 6244 "[CONNECTOR:%d:%s] HMD or specialized display VSDB version %u: 0x%02x\n", 6245 connector->base.id, connector->name, version, db[5]); 6246} 6247 6248static void drm_parse_cea_ext(struct drm_connector *connector, 6249 const struct drm_edid *drm_edid) 6250{ 6251 struct drm_display_info *info = &connector->display_info; 6252 struct drm_edid_iter edid_iter; 6253 const struct cea_db *db; 6254 struct cea_db_iter iter; 6255 const u8 *edid_ext; 6256 u64 y420cmdb_map = 0; 6257 6258 drm_edid_iter_begin(drm_edid, &edid_iter); 6259 drm_edid_iter_for_each(edid_ext, &edid_iter) { 6260 if (edid_ext[0] != CEA_EXT) 6261 continue; 6262 6263 if (!info->cea_rev) 6264 info->cea_rev = edid_ext[1]; 6265 6266 if (info->cea_rev != edid_ext[1]) 6267 drm_dbg_kms(connector->dev, 6268 "[CONNECTOR:%d:%s] CEA extension version mismatch %u != %u\n", 6269 connector->base.id, connector->name, 6270 info->cea_rev, edid_ext[1]); 6271 6272 /* The existence of a CTA extension should imply RGB support */ 6273 info->color_formats = DRM_COLOR_FORMAT_RGB444; 6274 if (edid_ext[3] & EDID_CEA_YCRCB444) 6275 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444; 6276 if (edid_ext[3] & EDID_CEA_YCRCB422) 6277 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422; 6278 if (edid_ext[3] & EDID_BASIC_AUDIO) 6279 info->has_audio = true; 6280 6281 } 6282 drm_edid_iter_end(&edid_iter); 6283 6284 cea_db_iter_edid_begin(drm_edid, &iter); 6285 cea_db_iter_for_each(db, &iter) { 6286 /* FIXME: convert parsers to use struct cea_db */ 6287 const u8 *data = (const u8 *)db; 6288 6289 if (cea_db_is_hdmi_vsdb(db)) 6290 drm_parse_hdmi_vsdb_video(connector, data); 6291 else if (cea_db_is_hdmi_forum_vsdb(db) || 6292 cea_db_is_hdmi_forum_scdb(db)) 6293 drm_parse_hdmi_forum_scds(connector, data); 6294 else if (cea_db_is_microsoft_vsdb(db)) 6295 drm_parse_microsoft_vsdb(connector, data); 6296 else if (cea_db_is_y420cmdb(db)) 6297 parse_cta_y420cmdb(connector, db, &y420cmdb_map); 6298 else if (cea_db_is_y420vdb(db)) 6299 parse_cta_y420vdb(connector, db); 6300 else if (cea_db_is_vcdb(db)) 6301 drm_parse_vcdb(connector, data); 6302 else if (cea_db_is_hdmi_hdr_metadata_block(db)) 6303 drm_parse_hdr_metadata_block(connector, data); 6304 else if (cea_db_tag(db) == CTA_DB_VIDEO) 6305 parse_cta_vdb(connector, db); 6306 else if (cea_db_tag(db) == CTA_DB_AUDIO) 6307 info->has_audio = true; 6308 } 6309 cea_db_iter_end(&iter); 6310 6311 if (y420cmdb_map) 6312 update_cta_y420cmdb(connector, y420cmdb_map); 6313} 6314 6315static 6316void get_monitor_range(const struct detailed_timing *timing, void *c) 6317{ 6318 struct detailed_mode_closure *closure = c; 6319 struct drm_display_info *info = &closure->connector->display_info; 6320 struct drm_monitor_range_info *monitor_range = &info->monitor_range; 6321 const struct detailed_non_pixel *data = &timing->data.other_data; 6322 const struct detailed_data_monitor_range *range = &data->data.range; 6323 const struct edid *edid = closure->drm_edid->edid; 6324 6325 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE)) 6326 return; 6327 6328 /* 6329 * These limits are used to determine the VRR refresh 6330 * rate range. Only the "range limits only" variant 6331 * of the range descriptor seems to guarantee that 6332 * any and all timings are accepted by the sink, as 6333 * opposed to just timings conforming to the indicated 6334 * formula (GTF/GTF2/CVT). Thus other variants of the 6335 * range descriptor are not accepted here. 6336 */ 6337 if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG) 6338 return; 6339 6340 monitor_range->min_vfreq = range->min_vfreq; 6341 monitor_range->max_vfreq = range->max_vfreq; 6342 6343 if (edid->revision >= 4) { 6344 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MIN_VFREQ) 6345 monitor_range->min_vfreq += 255; 6346 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MAX_VFREQ) 6347 monitor_range->max_vfreq += 255; 6348 } 6349} 6350 6351static void drm_get_monitor_range(struct drm_connector *connector, 6352 const struct drm_edid *drm_edid) 6353{ 6354 const struct drm_display_info *info = &connector->display_info; 6355 struct detailed_mode_closure closure = { 6356 .connector = connector, 6357 .drm_edid = drm_edid, 6358 }; 6359 6360 if (drm_edid->edid->revision < 4) 6361 return; 6362 6363 if (!(drm_edid->edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ)) 6364 return; 6365 6366 drm_for_each_detailed_block(drm_edid, get_monitor_range, &closure); 6367 6368 drm_dbg_kms(connector->dev, 6369 "[CONNECTOR:%d:%s] Supported Monitor Refresh rate range is %d Hz - %d Hz\n", 6370 connector->base.id, connector->name, 6371 info->monitor_range.min_vfreq, info->monitor_range.max_vfreq); 6372} 6373 6374static void drm_parse_vesa_mso_data(struct drm_connector *connector, 6375 const struct displayid_block *block) 6376{ 6377 struct displayid_vesa_vendor_specific_block *vesa = 6378 (struct displayid_vesa_vendor_specific_block *)block; 6379 struct drm_display_info *info = &connector->display_info; 6380 6381 if (block->num_bytes < 3) { 6382 drm_dbg_kms(connector->dev, 6383 "[CONNECTOR:%d:%s] Unexpected vendor block size %u\n", 6384 connector->base.id, connector->name, block->num_bytes); 6385 return; 6386 } 6387 6388 if (oui(vesa->oui[0], vesa->oui[1], vesa->oui[2]) != VESA_IEEE_OUI) 6389 return; 6390 6391 if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) { 6392 drm_dbg_kms(connector->dev, 6393 "[CONNECTOR:%d:%s] Unexpected VESA vendor block size\n", 6394 connector->base.id, connector->name); 6395 return; 6396 } 6397 6398 switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) { 6399 default: 6400 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Reserved MSO mode value\n", 6401 connector->base.id, connector->name); 6402 fallthrough; 6403 case 0: 6404 info->mso_stream_count = 0; 6405 break; 6406 case 1: 6407 info->mso_stream_count = 2; /* 2 or 4 links */ 6408 break; 6409 case 2: 6410 info->mso_stream_count = 4; /* 4 links */ 6411 break; 6412 } 6413 6414 if (!info->mso_stream_count) { 6415 info->mso_pixel_overlap = 0; 6416 return; 6417 } 6418 6419 info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso); 6420 if (info->mso_pixel_overlap > 8) { 6421 drm_dbg_kms(connector->dev, 6422 "[CONNECTOR:%d:%s] Reserved MSO pixel overlap value %u\n", 6423 connector->base.id, connector->name, 6424 info->mso_pixel_overlap); 6425 info->mso_pixel_overlap = 8; 6426 } 6427 6428 drm_dbg_kms(connector->dev, 6429 "[CONNECTOR:%d:%s] MSO stream count %u, pixel overlap %u\n", 6430 connector->base.id, connector->name, 6431 info->mso_stream_count, info->mso_pixel_overlap); 6432} 6433 6434static void drm_update_mso(struct drm_connector *connector, 6435 const struct drm_edid *drm_edid) 6436{ 6437 const struct displayid_block *block; 6438 struct displayid_iter iter; 6439 6440 displayid_iter_edid_begin(drm_edid, &iter); 6441 displayid_iter_for_each(block, &iter) { 6442 if (block->tag == DATA_BLOCK_2_VENDOR_SPECIFIC) 6443 drm_parse_vesa_mso_data(connector, block); 6444 } 6445 displayid_iter_end(&iter); 6446} 6447 6448/* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset 6449 * all of the values which would have been set from EDID 6450 */ 6451static void drm_reset_display_info(struct drm_connector *connector) 6452{ 6453 struct drm_display_info *info = &connector->display_info; 6454 6455 info->width_mm = 0; 6456 info->height_mm = 0; 6457 6458 info->bpc = 0; 6459 info->color_formats = 0; 6460 info->cea_rev = 0; 6461 info->max_tmds_clock = 0; 6462 info->dvi_dual = false; 6463 info->is_hdmi = false; 6464 info->has_audio = false; 6465 info->has_hdmi_infoframe = false; 6466 info->rgb_quant_range_selectable = false; 6467 memset(&info->hdmi, 0, sizeof(info->hdmi)); 6468 6469 info->edid_hdmi_rgb444_dc_modes = 0; 6470 info->edid_hdmi_ycbcr444_dc_modes = 0; 6471 6472 info->non_desktop = 0; 6473 memset(&info->monitor_range, 0, sizeof(info->monitor_range)); 6474 memset(&info->luminance_range, 0, sizeof(info->luminance_range)); 6475 6476 info->mso_stream_count = 0; 6477 info->mso_pixel_overlap = 0; 6478 info->max_dsc_bpp = 0; 6479 6480 kfree(info->vics); 6481 info->vics = NULL; 6482 info->vics_len = 0; 6483 6484 info->quirks = 0; 6485} 6486 6487static void update_displayid_info(struct drm_connector *connector, 6488 const struct drm_edid *drm_edid) 6489{ 6490 struct drm_display_info *info = &connector->display_info; 6491 const struct displayid_block *block; 6492 struct displayid_iter iter; 6493 6494 displayid_iter_edid_begin(drm_edid, &iter); 6495 displayid_iter_for_each(block, &iter) { 6496 if (displayid_version(&iter) == DISPLAY_ID_STRUCTURE_VER_20 && 6497 (displayid_primary_use(&iter) == PRIMARY_USE_HEAD_MOUNTED_VR || 6498 displayid_primary_use(&iter) == PRIMARY_USE_HEAD_MOUNTED_AR)) 6499 info->non_desktop = true; 6500 6501 /* 6502 * We're only interested in the base section here, no need to 6503 * iterate further. 6504 */ 6505 break; 6506 } 6507 displayid_iter_end(&iter); 6508} 6509 6510static void update_display_info(struct drm_connector *connector, 6511 const struct drm_edid *drm_edid) 6512{ 6513 struct drm_display_info *info = &connector->display_info; 6514 const struct edid *edid; 6515 6516 drm_reset_display_info(connector); 6517 clear_eld(connector); 6518 6519 if (!drm_edid) 6520 return; 6521 6522 edid = drm_edid->edid; 6523 6524 info->quirks = edid_get_quirks(drm_edid); 6525 6526 info->width_mm = edid->width_cm * 10; 6527 info->height_mm = edid->height_cm * 10; 6528 6529 drm_get_monitor_range(connector, drm_edid); 6530 6531 if (edid->revision < 3) 6532 goto out; 6533 6534 if (!(edid->input & DRM_EDID_INPUT_DIGITAL)) 6535 goto out; 6536 6537 info->color_formats |= DRM_COLOR_FORMAT_RGB444; 6538 drm_parse_cea_ext(connector, drm_edid); 6539 6540 update_displayid_info(connector, drm_edid); 6541 6542 /* 6543 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3? 6544 * 6545 * For such displays, the DFP spec 1.0, section 3.10 "EDID support" 6546 * tells us to assume 8 bpc color depth if the EDID doesn't have 6547 * extensions which tell otherwise. 6548 */ 6549 if (info->bpc == 0 && edid->revision == 3 && 6550 edid->input & DRM_EDID_DIGITAL_DFP_1_X) { 6551 info->bpc = 8; 6552 drm_dbg_kms(connector->dev, 6553 "[CONNECTOR:%d:%s] Assigning DFP sink color depth as %d bpc.\n", 6554 connector->base.id, connector->name, info->bpc); 6555 } 6556 6557 /* Only defined for 1.4 with digital displays */ 6558 if (edid->revision < 4) 6559 goto out; 6560 6561 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) { 6562 case DRM_EDID_DIGITAL_DEPTH_6: 6563 info->bpc = 6; 6564 break; 6565 case DRM_EDID_DIGITAL_DEPTH_8: 6566 info->bpc = 8; 6567 break; 6568 case DRM_EDID_DIGITAL_DEPTH_10: 6569 info->bpc = 10; 6570 break; 6571 case DRM_EDID_DIGITAL_DEPTH_12: 6572 info->bpc = 12; 6573 break; 6574 case DRM_EDID_DIGITAL_DEPTH_14: 6575 info->bpc = 14; 6576 break; 6577 case DRM_EDID_DIGITAL_DEPTH_16: 6578 info->bpc = 16; 6579 break; 6580 case DRM_EDID_DIGITAL_DEPTH_UNDEF: 6581 default: 6582 info->bpc = 0; 6583 break; 6584 } 6585 6586 drm_dbg_kms(connector->dev, 6587 "[CONNECTOR:%d:%s] Assigning EDID-1.4 digital sink color depth as %d bpc.\n", 6588 connector->base.id, connector->name, info->bpc); 6589 6590 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444) 6591 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444; 6592 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) 6593 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422; 6594 6595 drm_update_mso(connector, drm_edid); 6596 6597out: 6598 if (info->quirks & EDID_QUIRK_NON_DESKTOP) { 6599 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Non-desktop display%s\n", 6600 connector->base.id, connector->name, 6601 info->non_desktop ? " (redundant quirk)" : ""); 6602 info->non_desktop = true; 6603 } 6604 6605 if (info->quirks & EDID_QUIRK_CAP_DSC_15BPP) 6606 info->max_dsc_bpp = 15; 6607 6608 if (info->quirks & EDID_QUIRK_FORCE_6BPC) 6609 info->bpc = 6; 6610 6611 if (info->quirks & EDID_QUIRK_FORCE_8BPC) 6612 info->bpc = 8; 6613 6614 if (info->quirks & EDID_QUIRK_FORCE_10BPC) 6615 info->bpc = 10; 6616 6617 if (info->quirks & EDID_QUIRK_FORCE_12BPC) 6618 info->bpc = 12; 6619 6620 /* Depends on info->cea_rev set by drm_parse_cea_ext() above */ 6621 drm_edid_to_eld(connector, drm_edid); 6622} 6623 6624static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev, 6625 struct displayid_detailed_timings_1 *timings, 6626 bool type_7) 6627{ 6628 struct drm_display_mode *mode; 6629 unsigned pixel_clock = (timings->pixel_clock[0] | 6630 (timings->pixel_clock[1] << 8) | 6631 (timings->pixel_clock[2] << 16)) + 1; 6632 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1; 6633 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1; 6634 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1; 6635 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1; 6636 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1; 6637 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1; 6638 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1; 6639 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1; 6640 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1; 6641 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1; 6642 6643 mode = drm_mode_create(dev); 6644 if (!mode) 6645 return NULL; 6646 6647 /* resolution is kHz for type VII, and 10 kHz for type I */ 6648 mode->clock = type_7 ? pixel_clock : pixel_clock * 10; 6649 mode->hdisplay = hactive; 6650 mode->hsync_start = mode->hdisplay + hsync; 6651 mode->hsync_end = mode->hsync_start + hsync_width; 6652 mode->htotal = mode->hdisplay + hblank; 6653 6654 mode->vdisplay = vactive; 6655 mode->vsync_start = mode->vdisplay + vsync; 6656 mode->vsync_end = mode->vsync_start + vsync_width; 6657 mode->vtotal = mode->vdisplay + vblank; 6658 6659 mode->flags = 0; 6660 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 6661 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 6662 mode->type = DRM_MODE_TYPE_DRIVER; 6663 6664 if (timings->flags & 0x80) 6665 mode->type |= DRM_MODE_TYPE_PREFERRED; 6666 drm_mode_set_name(mode); 6667 6668 return mode; 6669} 6670 6671static int add_displayid_detailed_1_modes(struct drm_connector *connector, 6672 const struct displayid_block *block) 6673{ 6674 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block; 6675 int i; 6676 int num_timings; 6677 struct drm_display_mode *newmode; 6678 int num_modes = 0; 6679 bool type_7 = block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING; 6680 /* blocks must be multiple of 20 bytes length */ 6681 if (block->num_bytes % 20) 6682 return 0; 6683 6684 num_timings = block->num_bytes / 20; 6685 for (i = 0; i < num_timings; i++) { 6686 struct displayid_detailed_timings_1 *timings = &det->timings[i]; 6687 6688 newmode = drm_mode_displayid_detailed(connector->dev, timings, type_7); 6689 if (!newmode) 6690 continue; 6691 6692 drm_mode_probed_add(connector, newmode); 6693 num_modes++; 6694 } 6695 return num_modes; 6696} 6697 6698static int add_displayid_detailed_modes(struct drm_connector *connector, 6699 const struct drm_edid *drm_edid) 6700{ 6701 const struct displayid_block *block; 6702 struct displayid_iter iter; 6703 int num_modes = 0; 6704 6705 displayid_iter_edid_begin(drm_edid, &iter); 6706 displayid_iter_for_each(block, &iter) { 6707 if (block->tag == DATA_BLOCK_TYPE_1_DETAILED_TIMING || 6708 block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING) 6709 num_modes += add_displayid_detailed_1_modes(connector, block); 6710 } 6711 displayid_iter_end(&iter); 6712 6713 return num_modes; 6714} 6715 6716static int _drm_edid_connector_add_modes(struct drm_connector *connector, 6717 const struct drm_edid *drm_edid) 6718{ 6719 const struct drm_display_info *info = &connector->display_info; 6720 int num_modes = 0; 6721 6722 if (!drm_edid) 6723 return 0; 6724 6725 /* 6726 * EDID spec says modes should be preferred in this order: 6727 * - preferred detailed mode 6728 * - other detailed modes from base block 6729 * - detailed modes from extension blocks 6730 * - CVT 3-byte code modes 6731 * - standard timing codes 6732 * - established timing codes 6733 * - modes inferred from GTF or CVT range information 6734 * 6735 * We get this pretty much right. 6736 * 6737 * XXX order for additional mode types in extension blocks? 6738 */ 6739 num_modes += add_detailed_modes(connector, drm_edid); 6740 num_modes += add_cvt_modes(connector, drm_edid); 6741 num_modes += add_standard_modes(connector, drm_edid); 6742 num_modes += add_established_modes(connector, drm_edid); 6743 num_modes += add_cea_modes(connector, drm_edid); 6744 num_modes += add_alternate_cea_modes(connector, drm_edid); 6745 num_modes += add_displayid_detailed_modes(connector, drm_edid); 6746 if (drm_edid->edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ) 6747 num_modes += add_inferred_modes(connector, drm_edid); 6748 6749 if (info->quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) 6750 edid_fixup_preferred(connector); 6751 6752 return num_modes; 6753} 6754 6755static void _drm_update_tile_info(struct drm_connector *connector, 6756 const struct drm_edid *drm_edid); 6757 6758static int _drm_edid_connector_property_update(struct drm_connector *connector, 6759 const struct drm_edid *drm_edid) 6760{ 6761 struct drm_device *dev = connector->dev; 6762 int ret; 6763 6764 if (connector->edid_blob_ptr) { 6765 const struct edid *old_edid = connector->edid_blob_ptr->data; 6766 6767 if (old_edid) { 6768 if (!drm_edid_are_equal(drm_edid ? drm_edid->edid : NULL, old_edid)) { 6769 connector->epoch_counter++; 6770 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID changed, epoch counter %llu\n", 6771 connector->base.id, connector->name, 6772 connector->epoch_counter); 6773 } 6774 } 6775 } 6776 6777 ret = drm_property_replace_global_blob(dev, 6778 &connector->edid_blob_ptr, 6779 drm_edid ? drm_edid->size : 0, 6780 drm_edid ? drm_edid->edid : NULL, 6781 &connector->base, 6782 dev->mode_config.edid_property); 6783 if (ret) { 6784 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID property update failed (%d)\n", 6785 connector->base.id, connector->name, ret); 6786 goto out; 6787 } 6788 6789 ret = drm_object_property_set_value(&connector->base, 6790 dev->mode_config.non_desktop_property, 6791 connector->display_info.non_desktop); 6792 if (ret) { 6793 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Non-desktop property update failed (%d)\n", 6794 connector->base.id, connector->name, ret); 6795 goto out; 6796 } 6797 6798 ret = drm_connector_set_tile_property(connector); 6799 if (ret) { 6800 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Tile property update failed (%d)\n", 6801 connector->base.id, connector->name, ret); 6802 goto out; 6803 } 6804 6805out: 6806 return ret; 6807} 6808 6809/** 6810 * drm_edid_connector_update - Update connector information from EDID 6811 * @connector: Connector 6812 * @drm_edid: EDID 6813 * 6814 * Update the connector display info, ELD, HDR metadata, relevant properties, 6815 * etc. from the passed in EDID. 6816 * 6817 * If EDID is NULL, reset the information. 6818 * 6819 * Must be called before calling drm_edid_connector_add_modes(). 6820 * 6821 * Return: 0 on success, negative error on errors. 6822 */ 6823int drm_edid_connector_update(struct drm_connector *connector, 6824 const struct drm_edid *drm_edid) 6825{ 6826 update_display_info(connector, drm_edid); 6827 6828 _drm_update_tile_info(connector, drm_edid); 6829 6830 return _drm_edid_connector_property_update(connector, drm_edid); 6831} 6832EXPORT_SYMBOL(drm_edid_connector_update); 6833 6834/** 6835 * drm_edid_connector_add_modes - Update probed modes from the EDID property 6836 * @connector: Connector 6837 * 6838 * Add the modes from the previously updated EDID property to the connector 6839 * probed modes list. 6840 * 6841 * drm_edid_connector_update() must have been called before this to update the 6842 * EDID property. 6843 * 6844 * Return: The number of modes added, or 0 if we couldn't find any. 6845 */ 6846int drm_edid_connector_add_modes(struct drm_connector *connector) 6847{ 6848 const struct drm_edid *drm_edid = NULL; 6849 int count; 6850 6851 if (connector->edid_blob_ptr) 6852 drm_edid = drm_edid_alloc(connector->edid_blob_ptr->data, 6853 connector->edid_blob_ptr->length); 6854 6855 count = _drm_edid_connector_add_modes(connector, drm_edid); 6856 6857 drm_edid_free(drm_edid); 6858 6859 return count; 6860} 6861EXPORT_SYMBOL(drm_edid_connector_add_modes); 6862 6863/** 6864 * drm_connector_update_edid_property - update the edid property of a connector 6865 * @connector: drm connector 6866 * @edid: new value of the edid property 6867 * 6868 * This function creates a new blob modeset object and assigns its id to the 6869 * connector's edid property. 6870 * Since we also parse tile information from EDID's displayID block, we also 6871 * set the connector's tile property here. See drm_connector_set_tile_property() 6872 * for more details. 6873 * 6874 * This function is deprecated. Use drm_edid_connector_update() instead. 6875 * 6876 * Returns: 6877 * Zero on success, negative errno on failure. 6878 */ 6879int drm_connector_update_edid_property(struct drm_connector *connector, 6880 const struct edid *edid) 6881{ 6882 struct drm_edid drm_edid; 6883 6884 return drm_edid_connector_update(connector, drm_edid_legacy_init(&drm_edid, edid)); 6885} 6886EXPORT_SYMBOL(drm_connector_update_edid_property); 6887 6888/** 6889 * drm_add_edid_modes - add modes from EDID data, if available 6890 * @connector: connector we're probing 6891 * @edid: EDID data 6892 * 6893 * Add the specified modes to the connector's mode list. Also fills out the 6894 * &drm_display_info structure and ELD in @connector with any information which 6895 * can be derived from the edid. 6896 * 6897 * This function is deprecated. Use drm_edid_connector_add_modes() instead. 6898 * 6899 * Return: The number of modes added or 0 if we couldn't find any. 6900 */ 6901int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) 6902{ 6903 struct drm_edid _drm_edid; 6904 const struct drm_edid *drm_edid; 6905 6906 if (edid && !drm_edid_is_valid(edid)) { 6907 drm_warn(connector->dev, "[CONNECTOR:%d:%s] EDID invalid.\n", 6908 connector->base.id, connector->name); 6909 edid = NULL; 6910 } 6911 6912 drm_edid = drm_edid_legacy_init(&_drm_edid, edid); 6913 6914 update_display_info(connector, drm_edid); 6915 6916 return _drm_edid_connector_add_modes(connector, drm_edid); 6917} 6918EXPORT_SYMBOL(drm_add_edid_modes); 6919 6920/** 6921 * drm_add_modes_noedid - add modes for the connectors without EDID 6922 * @connector: connector we're probing 6923 * @hdisplay: the horizontal display limit 6924 * @vdisplay: the vertical display limit 6925 * 6926 * Add the specified modes to the connector's mode list. Only when the 6927 * hdisplay/vdisplay is not beyond the given limit, it will be added. 6928 * 6929 * Return: The number of modes added or 0 if we couldn't find any. 6930 */ 6931int drm_add_modes_noedid(struct drm_connector *connector, 6932 int hdisplay, int vdisplay) 6933{ 6934 int i, count, num_modes = 0; 6935 struct drm_display_mode *mode; 6936 struct drm_device *dev = connector->dev; 6937 6938 count = ARRAY_SIZE(drm_dmt_modes); 6939 if (hdisplay < 0) 6940 hdisplay = 0; 6941 if (vdisplay < 0) 6942 vdisplay = 0; 6943 6944 for (i = 0; i < count; i++) { 6945 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 6946 6947 if (hdisplay && vdisplay) { 6948 /* 6949 * Only when two are valid, they will be used to check 6950 * whether the mode should be added to the mode list of 6951 * the connector. 6952 */ 6953 if (ptr->hdisplay > hdisplay || 6954 ptr->vdisplay > vdisplay) 6955 continue; 6956 } 6957 if (drm_mode_vrefresh(ptr) > 61) 6958 continue; 6959 mode = drm_mode_duplicate(dev, ptr); 6960 if (mode) { 6961 drm_mode_probed_add(connector, mode); 6962 num_modes++; 6963 } 6964 } 6965 return num_modes; 6966} 6967EXPORT_SYMBOL(drm_add_modes_noedid); 6968 6969/** 6970 * drm_set_preferred_mode - Sets the preferred mode of a connector 6971 * @connector: connector whose mode list should be processed 6972 * @hpref: horizontal resolution of preferred mode 6973 * @vpref: vertical resolution of preferred mode 6974 * 6975 * Marks a mode as preferred if it matches the resolution specified by @hpref 6976 * and @vpref. 6977 */ 6978void drm_set_preferred_mode(struct drm_connector *connector, 6979 int hpref, int vpref) 6980{ 6981 struct drm_display_mode *mode; 6982 6983 list_for_each_entry(mode, &connector->probed_modes, head) { 6984 if (mode->hdisplay == hpref && 6985 mode->vdisplay == vpref) 6986 mode->type |= DRM_MODE_TYPE_PREFERRED; 6987 } 6988} 6989EXPORT_SYMBOL(drm_set_preferred_mode); 6990 6991static bool is_hdmi2_sink(const struct drm_connector *connector) 6992{ 6993 /* 6994 * FIXME: sil-sii8620 doesn't have a connector around when 6995 * we need one, so we have to be prepared for a NULL connector. 6996 */ 6997 if (!connector) 6998 return true; 6999 7000 return connector->display_info.hdmi.scdc.supported || 7001 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR420; 7002} 7003 7004static u8 drm_mode_hdmi_vic(const struct drm_connector *connector, 7005 const struct drm_display_mode *mode) 7006{ 7007 bool has_hdmi_infoframe = connector ? 7008 connector->display_info.has_hdmi_infoframe : false; 7009 7010 if (!has_hdmi_infoframe) 7011 return 0; 7012 7013 /* No HDMI VIC when signalling 3D video format */ 7014 if (mode->flags & DRM_MODE_FLAG_3D_MASK) 7015 return 0; 7016 7017 return drm_match_hdmi_mode(mode); 7018} 7019 7020static u8 drm_mode_cea_vic(const struct drm_connector *connector, 7021 const struct drm_display_mode *mode) 7022{ 7023 /* 7024 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes 7025 * we should send its VIC in vendor infoframes, else send the 7026 * VIC in AVI infoframes. Lets check if this mode is present in 7027 * HDMI 1.4b 4K modes 7028 */ 7029 if (drm_mode_hdmi_vic(connector, mode)) 7030 return 0; 7031 7032 return drm_match_cea_mode(mode); 7033} 7034 7035/* 7036 * Avoid sending VICs defined in HDMI 2.0 in AVI infoframes to sinks that 7037 * conform to HDMI 1.4. 7038 * 7039 * HDMI 1.4 (CTA-861-D) VIC range: [1..64] 7040 * HDMI 2.0 (CTA-861-F) VIC range: [1..107] 7041 * 7042 * If the sink lists the VIC in CTA VDB, assume it's fine, regardless of HDMI 7043 * version. 7044 */ 7045static u8 vic_for_avi_infoframe(const struct drm_connector *connector, u8 vic) 7046{ 7047 if (!is_hdmi2_sink(connector) && vic > 64 && 7048 !cta_vdb_has_vic(connector, vic)) 7049 return 0; 7050 7051 return vic; 7052} 7053 7054/** 7055 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with 7056 * data from a DRM display mode 7057 * @frame: HDMI AVI infoframe 7058 * @connector: the connector 7059 * @mode: DRM display mode 7060 * 7061 * Return: 0 on success or a negative error code on failure. 7062 */ 7063int 7064drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 7065 const struct drm_connector *connector, 7066 const struct drm_display_mode *mode) 7067{ 7068 enum hdmi_picture_aspect picture_aspect; 7069 u8 vic, hdmi_vic; 7070 7071 if (!frame || !mode) 7072 return -EINVAL; 7073 7074 hdmi_avi_infoframe_init(frame); 7075 7076 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 7077 frame->pixel_repeat = 1; 7078 7079 vic = drm_mode_cea_vic(connector, mode); 7080 hdmi_vic = drm_mode_hdmi_vic(connector, mode); 7081 7082 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; 7083 7084 /* 7085 * As some drivers don't support atomic, we can't use connector state. 7086 * So just initialize the frame with default values, just the same way 7087 * as it's done with other properties here. 7088 */ 7089 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS; 7090 frame->itc = 0; 7091 7092 /* 7093 * Populate picture aspect ratio from either 7094 * user input (if specified) or from the CEA/HDMI mode lists. 7095 */ 7096 picture_aspect = mode->picture_aspect_ratio; 7097 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) { 7098 if (vic) 7099 picture_aspect = drm_get_cea_aspect_ratio(vic); 7100 else if (hdmi_vic) 7101 picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic); 7102 } 7103 7104 /* 7105 * The infoframe can't convey anything but none, 4:3 7106 * and 16:9, so if the user has asked for anything else 7107 * we can only satisfy it by specifying the right VIC. 7108 */ 7109 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) { 7110 if (vic) { 7111 if (picture_aspect != drm_get_cea_aspect_ratio(vic)) 7112 return -EINVAL; 7113 } else if (hdmi_vic) { 7114 if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic)) 7115 return -EINVAL; 7116 } else { 7117 return -EINVAL; 7118 } 7119 7120 picture_aspect = HDMI_PICTURE_ASPECT_NONE; 7121 } 7122 7123 frame->video_code = vic_for_avi_infoframe(connector, vic); 7124 frame->picture_aspect = picture_aspect; 7125 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; 7126 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN; 7127 7128 return 0; 7129} 7130EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode); 7131 7132/** 7133 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe 7134 * quantization range information 7135 * @frame: HDMI AVI infoframe 7136 * @connector: the connector 7137 * @mode: DRM display mode 7138 * @rgb_quant_range: RGB quantization range (Q) 7139 */ 7140void 7141drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame, 7142 const struct drm_connector *connector, 7143 const struct drm_display_mode *mode, 7144 enum hdmi_quantization_range rgb_quant_range) 7145{ 7146 const struct drm_display_info *info = &connector->display_info; 7147 7148 /* 7149 * CEA-861: 7150 * "A Source shall not send a non-zero Q value that does not correspond 7151 * to the default RGB Quantization Range for the transmitted Picture 7152 * unless the Sink indicates support for the Q bit in a Video 7153 * Capabilities Data Block." 7154 * 7155 * HDMI 2.0 recommends sending non-zero Q when it does match the 7156 * default RGB quantization range for the mode, even when QS=0. 7157 */ 7158 if (info->rgb_quant_range_selectable || 7159 rgb_quant_range == drm_default_rgb_quant_range(mode)) 7160 frame->quantization_range = rgb_quant_range; 7161 else 7162 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 7163 7164 /* 7165 * CEA-861-F: 7166 * "When transmitting any RGB colorimetry, the Source should set the 7167 * YQ-field to match the RGB Quantization Range being transmitted 7168 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB, 7169 * set YQ=1) and the Sink shall ignore the YQ-field." 7170 * 7171 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused 7172 * by non-zero YQ when receiving RGB. There doesn't seem to be any 7173 * good way to tell which version of CEA-861 the sink supports, so 7174 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based 7175 * on CEA-861-F. 7176 */ 7177 if (!is_hdmi2_sink(connector) || 7178 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED) 7179 frame->ycc_quantization_range = 7180 HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 7181 else 7182 frame->ycc_quantization_range = 7183 HDMI_YCC_QUANTIZATION_RANGE_FULL; 7184} 7185EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range); 7186 7187static enum hdmi_3d_structure 7188s3d_structure_from_display_mode(const struct drm_display_mode *mode) 7189{ 7190 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK; 7191 7192 switch (layout) { 7193 case DRM_MODE_FLAG_3D_FRAME_PACKING: 7194 return HDMI_3D_STRUCTURE_FRAME_PACKING; 7195 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE: 7196 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE; 7197 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE: 7198 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE; 7199 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL: 7200 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL; 7201 case DRM_MODE_FLAG_3D_L_DEPTH: 7202 return HDMI_3D_STRUCTURE_L_DEPTH; 7203 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH: 7204 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH; 7205 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM: 7206 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM; 7207 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF: 7208 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF; 7209 default: 7210 return HDMI_3D_STRUCTURE_INVALID; 7211 } 7212} 7213 7214/** 7215 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with 7216 * data from a DRM display mode 7217 * @frame: HDMI vendor infoframe 7218 * @connector: the connector 7219 * @mode: DRM display mode 7220 * 7221 * Note that there's is a need to send HDMI vendor infoframes only when using a 7222 * 4k or stereoscopic 3D mode. So when giving any other mode as input this 7223 * function will return -EINVAL, error that can be safely ignored. 7224 * 7225 * Return: 0 on success or a negative error code on failure. 7226 */ 7227int 7228drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 7229 const struct drm_connector *connector, 7230 const struct drm_display_mode *mode) 7231{ 7232 /* 7233 * FIXME: sil-sii8620 doesn't have a connector around when 7234 * we need one, so we have to be prepared for a NULL connector. 7235 */ 7236 bool has_hdmi_infoframe = connector ? 7237 connector->display_info.has_hdmi_infoframe : false; 7238 int err; 7239 7240 if (!frame || !mode) 7241 return -EINVAL; 7242 7243 if (!has_hdmi_infoframe) 7244 return -EINVAL; 7245 7246 err = hdmi_vendor_infoframe_init(frame); 7247 if (err < 0) 7248 return err; 7249 7250 /* 7251 * Even if it's not absolutely necessary to send the infoframe 7252 * (ie.vic==0 and s3d_struct==0) we will still send it if we 7253 * know that the sink can handle it. This is based on a 7254 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks 7255 * have trouble realizing that they should switch from 3D to 2D 7256 * mode if the source simply stops sending the infoframe when 7257 * it wants to switch from 3D to 2D. 7258 */ 7259 frame->vic = drm_mode_hdmi_vic(connector, mode); 7260 frame->s3d_struct = s3d_structure_from_display_mode(mode); 7261 7262 return 0; 7263} 7264EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode); 7265 7266static void drm_parse_tiled_block(struct drm_connector *connector, 7267 const struct displayid_block *block) 7268{ 7269 const struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block; 7270 u16 w, h; 7271 u8 tile_v_loc, tile_h_loc; 7272 u8 num_v_tile, num_h_tile; 7273 struct drm_tile_group *tg; 7274 7275 w = tile->tile_size[0] | tile->tile_size[1] << 8; 7276 h = tile->tile_size[2] | tile->tile_size[3] << 8; 7277 7278 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30); 7279 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30); 7280 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4); 7281 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4); 7282 7283 connector->has_tile = true; 7284 if (tile->tile_cap & 0x80) 7285 connector->tile_is_single_monitor = true; 7286 7287 connector->num_h_tile = num_h_tile + 1; 7288 connector->num_v_tile = num_v_tile + 1; 7289 connector->tile_h_loc = tile_h_loc; 7290 connector->tile_v_loc = tile_v_loc; 7291 connector->tile_h_size = w + 1; 7292 connector->tile_v_size = h + 1; 7293 7294 drm_dbg_kms(connector->dev, 7295 "[CONNECTOR:%d:%s] tile cap 0x%x, size %dx%d, num tiles %dx%d, location %dx%d, vend %c%c%c", 7296 connector->base.id, connector->name, 7297 tile->tile_cap, 7298 connector->tile_h_size, connector->tile_v_size, 7299 connector->num_h_tile, connector->num_v_tile, 7300 connector->tile_h_loc, connector->tile_v_loc, 7301 tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]); 7302 7303 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id); 7304 if (!tg) 7305 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id); 7306 if (!tg) 7307 return; 7308 7309 if (connector->tile_group != tg) { 7310 /* if we haven't got a pointer, 7311 take the reference, drop ref to old tile group */ 7312 if (connector->tile_group) 7313 drm_mode_put_tile_group(connector->dev, connector->tile_group); 7314 connector->tile_group = tg; 7315 } else { 7316 /* if same tile group, then release the ref we just took. */ 7317 drm_mode_put_tile_group(connector->dev, tg); 7318 } 7319} 7320 7321static bool displayid_is_tiled_block(const struct displayid_iter *iter, 7322 const struct displayid_block *block) 7323{ 7324 return (displayid_version(iter) == DISPLAY_ID_STRUCTURE_VER_12 && 7325 block->tag == DATA_BLOCK_TILED_DISPLAY) || 7326 (displayid_version(iter) == DISPLAY_ID_STRUCTURE_VER_20 && 7327 block->tag == DATA_BLOCK_2_TILED_DISPLAY_TOPOLOGY); 7328} 7329 7330static void _drm_update_tile_info(struct drm_connector *connector, 7331 const struct drm_edid *drm_edid) 7332{ 7333 const struct displayid_block *block; 7334 struct displayid_iter iter; 7335 7336 connector->has_tile = false; 7337 7338 displayid_iter_edid_begin(drm_edid, &iter); 7339 displayid_iter_for_each(block, &iter) { 7340 if (displayid_is_tiled_block(&iter, block)) 7341 drm_parse_tiled_block(connector, block); 7342 } 7343 displayid_iter_end(&iter); 7344 7345 if (!connector->has_tile && connector->tile_group) { 7346 drm_mode_put_tile_group(connector->dev, connector->tile_group); 7347 connector->tile_group = NULL; 7348 } 7349} 7350