162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0 */ 262306a36Sopenharmony_ci/* 362306a36Sopenharmony_ci * ARM HDLCD Controller register definition 462306a36Sopenharmony_ci */ 562306a36Sopenharmony_ci 662306a36Sopenharmony_ci#ifndef __HDLCD_DRV_H__ 762306a36Sopenharmony_ci#define __HDLCD_DRV_H__ 862306a36Sopenharmony_ci 962306a36Sopenharmony_cistruct hdlcd_drm_private { 1062306a36Sopenharmony_ci struct drm_device base; 1162306a36Sopenharmony_ci void __iomem *mmio; 1262306a36Sopenharmony_ci struct clk *clk; 1362306a36Sopenharmony_ci struct drm_crtc crtc; 1462306a36Sopenharmony_ci struct drm_plane *plane; 1562306a36Sopenharmony_ci unsigned int irq; 1662306a36Sopenharmony_ci#ifdef CONFIG_DEBUG_FS 1762306a36Sopenharmony_ci atomic_t buffer_underrun_count; 1862306a36Sopenharmony_ci atomic_t bus_error_count; 1962306a36Sopenharmony_ci atomic_t vsync_count; 2062306a36Sopenharmony_ci atomic_t dma_end_count; 2162306a36Sopenharmony_ci#endif 2262306a36Sopenharmony_ci}; 2362306a36Sopenharmony_ci 2462306a36Sopenharmony_ci#define drm_to_hdlcd_priv(x) container_of(x, struct hdlcd_drm_private, base) 2562306a36Sopenharmony_ci#define crtc_to_hdlcd_priv(x) container_of(x, struct hdlcd_drm_private, crtc) 2662306a36Sopenharmony_ci 2762306a36Sopenharmony_cistatic inline void hdlcd_write(struct hdlcd_drm_private *hdlcd, 2862306a36Sopenharmony_ci unsigned int reg, u32 value) 2962306a36Sopenharmony_ci{ 3062306a36Sopenharmony_ci writel(value, hdlcd->mmio + reg); 3162306a36Sopenharmony_ci} 3262306a36Sopenharmony_ci 3362306a36Sopenharmony_cistatic inline u32 hdlcd_read(struct hdlcd_drm_private *hdlcd, unsigned int reg) 3462306a36Sopenharmony_ci{ 3562306a36Sopenharmony_ci return readl(hdlcd->mmio + reg); 3662306a36Sopenharmony_ci} 3762306a36Sopenharmony_ci 3862306a36Sopenharmony_ciint hdlcd_setup_crtc(struct drm_device *dev); 3962306a36Sopenharmony_civoid hdlcd_set_scanout(struct hdlcd_drm_private *hdlcd); 4062306a36Sopenharmony_ci 4162306a36Sopenharmony_ci#endif /* __HDLCD_DRV_H__ */ 42