162306a36Sopenharmony_ci# SPDX-License-Identifier: MIT 262306a36Sopenharmony_cimenu "Display Engine Configuration" 362306a36Sopenharmony_ci depends on DRM && DRM_AMDGPU 462306a36Sopenharmony_ci 562306a36Sopenharmony_ciconfig DRM_AMD_DC 662306a36Sopenharmony_ci bool "AMD DC - Enable new display engine" 762306a36Sopenharmony_ci default y 862306a36Sopenharmony_ci depends on BROKEN || !CC_IS_CLANG || ARM64 || RISCV || SPARC64 || X86_64 962306a36Sopenharmony_ci select SND_HDA_COMPONENT if SND_HDA_CORE 1062306a36Sopenharmony_ci # !CC_IS_CLANG: https://github.com/ClangBuiltLinux/linux/issues/1752 1162306a36Sopenharmony_ci select DRM_AMD_DC_FP if (X86 || LOONGARCH || (PPC64 && ALTIVEC) || (ARM64 && KERNEL_MODE_NEON && !CC_IS_CLANG)) 1262306a36Sopenharmony_ci help 1362306a36Sopenharmony_ci Choose this option if you want to use the new display engine 1462306a36Sopenharmony_ci support for AMDGPU. This adds required support for Vega and 1562306a36Sopenharmony_ci Raven ASICs. 1662306a36Sopenharmony_ci 1762306a36Sopenharmony_ci calculate_bandwidth() is presently broken on all !(X86_64 || SPARC64 || ARM64) 1862306a36Sopenharmony_ci architectures built with Clang (all released versions), whereby the stack 1962306a36Sopenharmony_ci frame gets blown up to well over 5k. This would cause an immediate kernel 2062306a36Sopenharmony_ci panic on most architectures. We'll revert this when the following bug report 2162306a36Sopenharmony_ci has been resolved: https://github.com/llvm/llvm-project/issues/41896. 2262306a36Sopenharmony_ci 2362306a36Sopenharmony_ciconfig DRM_AMD_DC_FP 2462306a36Sopenharmony_ci def_bool n 2562306a36Sopenharmony_ci help 2662306a36Sopenharmony_ci Floating point support, required for DCN-based SoCs 2762306a36Sopenharmony_ci 2862306a36Sopenharmony_ciconfig DRM_AMD_DC_SI 2962306a36Sopenharmony_ci bool "AMD DC support for Southern Islands ASICs" 3062306a36Sopenharmony_ci depends on DRM_AMDGPU_SI 3162306a36Sopenharmony_ci depends on DRM_AMD_DC 3262306a36Sopenharmony_ci help 3362306a36Sopenharmony_ci Choose this option to enable new AMD DC support for SI asics 3462306a36Sopenharmony_ci by default. This includes Tahiti, Pitcairn, Cape Verde, Oland. 3562306a36Sopenharmony_ci Hainan is not supported by AMD DC and it has no physical DCE6. 3662306a36Sopenharmony_ci 3762306a36Sopenharmony_ciconfig DEBUG_KERNEL_DC 3862306a36Sopenharmony_ci bool "Enable kgdb break in DC" 3962306a36Sopenharmony_ci depends on DRM_AMD_DC 4062306a36Sopenharmony_ci depends on KGDB 4162306a36Sopenharmony_ci help 4262306a36Sopenharmony_ci Choose this option if you want to hit kdgb_break in assert. 4362306a36Sopenharmony_ci 4462306a36Sopenharmony_ciconfig DRM_AMD_SECURE_DISPLAY 4562306a36Sopenharmony_ci bool "Enable secure display support" 4662306a36Sopenharmony_ci depends on DEBUG_FS 4762306a36Sopenharmony_ci depends on DRM_AMD_DC_FP 4862306a36Sopenharmony_ci help 4962306a36Sopenharmony_ci Choose this option if you want to support secure display 5062306a36Sopenharmony_ci 5162306a36Sopenharmony_ci This option enables the calculation of crc of specific region via 5262306a36Sopenharmony_ci debugfs. Cooperate with specific DMCU FW. 5362306a36Sopenharmony_ci 5462306a36Sopenharmony_ciendmenu 55