1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#ifndef __SOC15_H__
25#define __SOC15_H__
26
27#include "nbio_v6_1.h"
28#include "nbio_v7_0.h"
29#include "nbio_v7_4.h"
30
31extern const struct amdgpu_ip_block_version vega10_common_ip_block;
32
33#define SOC15_FLUSH_GPU_TLB_NUM_WREG		6
34#define SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT	3
35
36struct soc15_reg_golden {
37	u32	hwip;
38	u32	instance;
39	u32	segment;
40	u32	reg;
41	u32	and_mask;
42	u32	or_mask;
43};
44
45struct soc15_reg_rlcg {
46	u32	hwip;
47	u32	instance;
48	u32	segment;
49	u32	reg;
50};
51
52struct soc15_reg {
53	uint32_t hwip;
54	uint32_t inst;
55	uint32_t seg;
56	uint32_t reg_offset;
57};
58
59struct soc15_reg_entry {
60	uint32_t hwip;
61	uint32_t inst;
62	uint32_t seg;
63	uint32_t reg_offset;
64	uint32_t reg_value;
65	uint32_t se_num;
66	uint32_t instance;
67};
68
69struct soc15_allowed_register_entry {
70	uint32_t hwip;
71	uint32_t inst;
72	uint32_t seg;
73	uint32_t reg_offset;
74	bool grbm_indexed;
75};
76
77struct soc15_ras_field_entry {
78	const char *name;
79	uint32_t hwip;
80	uint32_t inst;
81	uint32_t seg;
82	uint32_t reg_offset;
83	uint32_t sec_count_mask;
84	uint32_t sec_count_shift;
85	uint32_t ded_count_mask;
86	uint32_t ded_count_shift;
87};
88
89#define SOC15_REG_ENTRY(ip, inst, reg)	ip##_HWIP, inst, reg##_BASE_IDX, reg
90
91#define SOC15_REG_ENTRY_OFFSET(entry)	(adev->reg_offset[entry.hwip][entry.inst][entry.seg] + entry.reg_offset)
92
93#define SOC15_REG_GOLDEN_VALUE(ip, inst, reg, and_mask, or_mask) \
94	{ ip##_HWIP, inst, reg##_BASE_IDX, reg, and_mask, or_mask }
95
96#define SOC15_REG_FIELD(reg, field) reg##__##field##_MASK, reg##__##field##__SHIFT
97
98#define SOC15_REG_FIELD_VAL(val, mask, shift)	(((val) & mask) >> shift)
99
100#define SOC15_RAS_REG_FIELD_VAL(val, entry, field) SOC15_REG_FIELD_VAL((val), (entry).field##_count_mask, (entry).field##_count_shift)
101
102void soc15_grbm_select(struct amdgpu_device *adev,
103		    u32 me, u32 pipe, u32 queue, u32 vmid, int xcc_id);
104void soc15_set_virt_ops(struct amdgpu_device *adev);
105
106void soc15_program_register_sequence(struct amdgpu_device *adev,
107					     const struct soc15_reg_golden *registers,
108					     const u32 array_size);
109
110int vega10_reg_base_init(struct amdgpu_device *adev);
111int vega20_reg_base_init(struct amdgpu_device *adev);
112int arct_reg_base_init(struct amdgpu_device *adev);
113int aldebaran_reg_base_init(struct amdgpu_device *adev);
114void aqua_vanjaram_ip_map_init(struct amdgpu_device *adev);
115u64 aqua_vanjaram_encode_ext_smn_addressing(int ext_id);
116int aqua_vanjaram_init_soc_config(struct amdgpu_device *adev);
117
118void vega10_doorbell_index_init(struct amdgpu_device *adev);
119void vega20_doorbell_index_init(struct amdgpu_device *adev);
120void aqua_vanjaram_doorbell_index_init(struct amdgpu_device *adev);
121#endif
122