162306a36Sopenharmony_ci/* 262306a36Sopenharmony_ci * Copyright (C) 2019 Advanced Micro Devices, Inc. 362306a36Sopenharmony_ci * 462306a36Sopenharmony_ci * Permission is hereby granted, free of charge, to any person obtaining a 562306a36Sopenharmony_ci * copy of this software and associated documentation files (the "Software"), 662306a36Sopenharmony_ci * to deal in the Software without restriction, including without limitation 762306a36Sopenharmony_ci * the rights to use, copy, modify, merge, publish, distribute, sublicense, 862306a36Sopenharmony_ci * and/or sell copies of the Software, and to permit persons to whom the 962306a36Sopenharmony_ci * Software is furnished to do so, subject to the following conditions: 1062306a36Sopenharmony_ci * 1162306a36Sopenharmony_ci * The above copyright notice and this permission notice shall be included 1262306a36Sopenharmony_ci * in all copies or substantial portions of the Software. 1362306a36Sopenharmony_ci * 1462306a36Sopenharmony_ci * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 1562306a36Sopenharmony_ci * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1662306a36Sopenharmony_ci * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1762306a36Sopenharmony_ci * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 1862306a36Sopenharmony_ci * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 1962306a36Sopenharmony_ci * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 2062306a36Sopenharmony_ci */ 2162306a36Sopenharmony_ci#ifndef __AMDGPU_MMHUB_H__ 2262306a36Sopenharmony_ci#define __AMDGPU_MMHUB_H__ 2362306a36Sopenharmony_ci 2462306a36Sopenharmony_cienum amdgpu_mmhub_ras_memory_id { 2562306a36Sopenharmony_ci AMDGPU_MMHUB_WGMI_PAGEMEM = 0, 2662306a36Sopenharmony_ci AMDGPU_MMHUB_RGMI_PAGEMEM = 1, 2762306a36Sopenharmony_ci AMDGPU_MMHUB_WDRAM_PAGEMEM = 2, 2862306a36Sopenharmony_ci AMDGPU_MMHUB_RDRAM_PAGEMEM = 3, 2962306a36Sopenharmony_ci AMDGPU_MMHUB_WIO_CMDMEM = 4, 3062306a36Sopenharmony_ci AMDGPU_MMHUB_RIO_CMDMEM = 5, 3162306a36Sopenharmony_ci AMDGPU_MMHUB_WGMI_CMDMEM = 6, 3262306a36Sopenharmony_ci AMDGPU_MMHUB_RGMI_CMDMEM = 7, 3362306a36Sopenharmony_ci AMDGPU_MMHUB_WDRAM_CMDMEM = 8, 3462306a36Sopenharmony_ci AMDGPU_MMHUB_RDRAM_CMDMEM = 9, 3562306a36Sopenharmony_ci AMDGPU_MMHUB_MAM_DMEM0 = 10, 3662306a36Sopenharmony_ci AMDGPU_MMHUB_MAM_DMEM1 = 11, 3762306a36Sopenharmony_ci AMDGPU_MMHUB_MAM_DMEM2 = 12, 3862306a36Sopenharmony_ci AMDGPU_MMHUB_MAM_DMEM3 = 13, 3962306a36Sopenharmony_ci AMDGPU_MMHUB_WRET_TAGMEM = 19, 4062306a36Sopenharmony_ci AMDGPU_MMHUB_RRET_TAGMEM = 20, 4162306a36Sopenharmony_ci AMDGPU_MMHUB_WIO_DATAMEM = 21, 4262306a36Sopenharmony_ci AMDGPU_MMHUB_WGMI_DATAMEM = 22, 4362306a36Sopenharmony_ci AMDGPU_MMHUB_WDRAM_DATAMEM = 23, 4462306a36Sopenharmony_ci AMDGPU_MMHUB_MEMORY_BLOCK_LAST, 4562306a36Sopenharmony_ci}; 4662306a36Sopenharmony_ci 4762306a36Sopenharmony_cistruct amdgpu_mmhub_ras { 4862306a36Sopenharmony_ci struct amdgpu_ras_block_object ras_block; 4962306a36Sopenharmony_ci}; 5062306a36Sopenharmony_ci 5162306a36Sopenharmony_cistruct amdgpu_mmhub_funcs { 5262306a36Sopenharmony_ci u64 (*get_fb_location)(struct amdgpu_device *adev); 5362306a36Sopenharmony_ci u64 (*get_mc_fb_offset)(struct amdgpu_device *adev); 5462306a36Sopenharmony_ci void (*init)(struct amdgpu_device *adev); 5562306a36Sopenharmony_ci int (*gart_enable)(struct amdgpu_device *adev); 5662306a36Sopenharmony_ci void (*set_fault_enable_default)(struct amdgpu_device *adev, 5762306a36Sopenharmony_ci bool value); 5862306a36Sopenharmony_ci void (*gart_disable)(struct amdgpu_device *adev); 5962306a36Sopenharmony_ci int (*set_clockgating)(struct amdgpu_device *adev, 6062306a36Sopenharmony_ci enum amd_clockgating_state state); 6162306a36Sopenharmony_ci void (*get_clockgating)(struct amdgpu_device *adev, u64 *flags); 6262306a36Sopenharmony_ci void (*setup_vm_pt_regs)(struct amdgpu_device *adev, uint32_t vmid, 6362306a36Sopenharmony_ci uint64_t page_table_base); 6462306a36Sopenharmony_ci void (*update_power_gating)(struct amdgpu_device *adev, 6562306a36Sopenharmony_ci bool enable); 6662306a36Sopenharmony_ci}; 6762306a36Sopenharmony_ci 6862306a36Sopenharmony_cistruct amdgpu_mmhub { 6962306a36Sopenharmony_ci struct ras_common_if *ras_if; 7062306a36Sopenharmony_ci const struct amdgpu_mmhub_funcs *funcs; 7162306a36Sopenharmony_ci struct amdgpu_mmhub_ras *ras; 7262306a36Sopenharmony_ci}; 7362306a36Sopenharmony_ci 7462306a36Sopenharmony_ciint amdgpu_mmhub_ras_sw_init(struct amdgpu_device *adev); 7562306a36Sopenharmony_ci 7662306a36Sopenharmony_ci#endif 7762306a36Sopenharmony_ci 78