1/* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24#ifndef __AMDGPU_MES_H__ 25#define __AMDGPU_MES_H__ 26 27#include "amdgpu_irq.h" 28#include "kgd_kfd_interface.h" 29#include "amdgpu_gfx.h" 30#include "amdgpu_doorbell.h" 31#include <linux/sched/mm.h> 32 33#define AMDGPU_MES_MAX_COMPUTE_PIPES 8 34#define AMDGPU_MES_MAX_GFX_PIPES 2 35#define AMDGPU_MES_MAX_SDMA_PIPES 2 36 37#define AMDGPU_MES_API_VERSION_SHIFT 12 38#define AMDGPU_MES_FEAT_VERSION_SHIFT 24 39 40#define AMDGPU_MES_VERSION_MASK 0x00000fff 41#define AMDGPU_MES_API_VERSION_MASK 0x00fff000 42#define AMDGPU_MES_FEAT_VERSION_MASK 0xff000000 43 44enum amdgpu_mes_priority_level { 45 AMDGPU_MES_PRIORITY_LEVEL_LOW = 0, 46 AMDGPU_MES_PRIORITY_LEVEL_NORMAL = 1, 47 AMDGPU_MES_PRIORITY_LEVEL_MEDIUM = 2, 48 AMDGPU_MES_PRIORITY_LEVEL_HIGH = 3, 49 AMDGPU_MES_PRIORITY_LEVEL_REALTIME = 4, 50 AMDGPU_MES_PRIORITY_NUM_LEVELS 51}; 52 53#define AMDGPU_MES_PROC_CTX_SIZE 0x1000 /* one page area */ 54#define AMDGPU_MES_GANG_CTX_SIZE 0x1000 /* one page area */ 55 56struct amdgpu_mes_funcs; 57 58enum admgpu_mes_pipe { 59 AMDGPU_MES_SCHED_PIPE = 0, 60 AMDGPU_MES_KIQ_PIPE, 61 AMDGPU_MAX_MES_PIPES = 2, 62}; 63 64struct amdgpu_mes { 65 struct amdgpu_device *adev; 66 67 struct mutex mutex_hidden; 68 69 struct idr pasid_idr; 70 struct idr gang_id_idr; 71 struct idr queue_id_idr; 72 struct ida doorbell_ida; 73 74 spinlock_t queue_id_lock; 75 76 uint32_t sched_version; 77 uint32_t kiq_version; 78 79 uint32_t total_max_queue; 80 uint32_t max_doorbell_slices; 81 82 uint64_t default_process_quantum; 83 uint64_t default_gang_quantum; 84 85 struct amdgpu_ring ring; 86 spinlock_t ring_lock; 87 88 const struct firmware *fw[AMDGPU_MAX_MES_PIPES]; 89 90 /* mes ucode */ 91 struct amdgpu_bo *ucode_fw_obj[AMDGPU_MAX_MES_PIPES]; 92 uint64_t ucode_fw_gpu_addr[AMDGPU_MAX_MES_PIPES]; 93 uint32_t *ucode_fw_ptr[AMDGPU_MAX_MES_PIPES]; 94 uint64_t uc_start_addr[AMDGPU_MAX_MES_PIPES]; 95 96 /* mes ucode data */ 97 struct amdgpu_bo *data_fw_obj[AMDGPU_MAX_MES_PIPES]; 98 uint64_t data_fw_gpu_addr[AMDGPU_MAX_MES_PIPES]; 99 uint32_t *data_fw_ptr[AMDGPU_MAX_MES_PIPES]; 100 uint64_t data_start_addr[AMDGPU_MAX_MES_PIPES]; 101 102 /* eop gpu obj */ 103 struct amdgpu_bo *eop_gpu_obj[AMDGPU_MAX_MES_PIPES]; 104 uint64_t eop_gpu_addr[AMDGPU_MAX_MES_PIPES]; 105 106 void *mqd_backup[AMDGPU_MAX_MES_PIPES]; 107 struct amdgpu_irq_src irq[AMDGPU_MAX_MES_PIPES]; 108 109 uint32_t vmid_mask_gfxhub; 110 uint32_t vmid_mask_mmhub; 111 uint32_t compute_hqd_mask[AMDGPU_MES_MAX_COMPUTE_PIPES]; 112 uint32_t gfx_hqd_mask[AMDGPU_MES_MAX_GFX_PIPES]; 113 uint32_t sdma_hqd_mask[AMDGPU_MES_MAX_SDMA_PIPES]; 114 uint32_t aggregated_doorbells[AMDGPU_MES_PRIORITY_NUM_LEVELS]; 115 uint32_t sch_ctx_offs; 116 uint64_t sch_ctx_gpu_addr; 117 uint64_t *sch_ctx_ptr; 118 uint32_t query_status_fence_offs; 119 uint64_t query_status_fence_gpu_addr; 120 uint64_t *query_status_fence_ptr; 121 uint32_t read_val_offs; 122 uint64_t read_val_gpu_addr; 123 uint32_t *read_val_ptr; 124 125 uint32_t saved_flags; 126 127 /* initialize kiq pipe */ 128 int (*kiq_hw_init)(struct amdgpu_device *adev); 129 int (*kiq_hw_fini)(struct amdgpu_device *adev); 130 131 /* MES doorbells */ 132 uint32_t db_start_dw_offset; 133 uint32_t num_mes_dbs; 134 unsigned long *doorbell_bitmap; 135 136 /* ip specific functions */ 137 const struct amdgpu_mes_funcs *funcs; 138}; 139 140struct amdgpu_mes_process { 141 int pasid; 142 struct amdgpu_vm *vm; 143 uint64_t pd_gpu_addr; 144 struct amdgpu_bo *proc_ctx_bo; 145 uint64_t proc_ctx_gpu_addr; 146 void *proc_ctx_cpu_ptr; 147 uint64_t process_quantum; 148 struct list_head gang_list; 149 uint32_t doorbell_index; 150 struct mutex doorbell_lock; 151}; 152 153struct amdgpu_mes_gang { 154 int gang_id; 155 int priority; 156 int inprocess_gang_priority; 157 int global_priority_level; 158 struct list_head list; 159 struct amdgpu_mes_process *process; 160 struct amdgpu_bo *gang_ctx_bo; 161 uint64_t gang_ctx_gpu_addr; 162 void *gang_ctx_cpu_ptr; 163 uint64_t gang_quantum; 164 struct list_head queue_list; 165}; 166 167struct amdgpu_mes_queue { 168 struct list_head list; 169 struct amdgpu_mes_gang *gang; 170 int queue_id; 171 uint64_t doorbell_off; 172 struct amdgpu_bo *mqd_obj; 173 void *mqd_cpu_ptr; 174 uint64_t mqd_gpu_addr; 175 uint64_t wptr_gpu_addr; 176 int queue_type; 177 int paging; 178 struct amdgpu_ring *ring; 179}; 180 181struct amdgpu_mes_queue_properties { 182 int queue_type; 183 uint64_t hqd_base_gpu_addr; 184 uint64_t rptr_gpu_addr; 185 uint64_t wptr_gpu_addr; 186 uint64_t wptr_mc_addr; 187 uint32_t queue_size; 188 uint64_t eop_gpu_addr; 189 uint32_t hqd_pipe_priority; 190 uint32_t hqd_queue_priority; 191 bool paging; 192 struct amdgpu_ring *ring; 193 /* out */ 194 uint64_t doorbell_off; 195}; 196 197struct amdgpu_mes_gang_properties { 198 uint32_t priority; 199 uint32_t gang_quantum; 200 uint32_t inprocess_gang_priority; 201 uint32_t priority_level; 202 int global_priority_level; 203}; 204 205struct mes_add_queue_input { 206 uint32_t process_id; 207 uint64_t page_table_base_addr; 208 uint64_t process_va_start; 209 uint64_t process_va_end; 210 uint64_t process_quantum; 211 uint64_t process_context_addr; 212 uint64_t gang_quantum; 213 uint64_t gang_context_addr; 214 uint32_t inprocess_gang_priority; 215 uint32_t gang_global_priority_level; 216 uint32_t doorbell_offset; 217 uint64_t mqd_addr; 218 uint64_t wptr_addr; 219 uint64_t wptr_mc_addr; 220 uint32_t queue_type; 221 uint32_t paging; 222 uint32_t gws_base; 223 uint32_t gws_size; 224 uint64_t tba_addr; 225 uint64_t tma_addr; 226 uint32_t trap_en; 227 uint32_t skip_process_ctx_clear; 228 uint32_t is_kfd_process; 229 uint32_t is_aql_queue; 230 uint32_t queue_size; 231 uint32_t exclusively_scheduled; 232}; 233 234struct mes_remove_queue_input { 235 uint32_t doorbell_offset; 236 uint64_t gang_context_addr; 237}; 238 239struct mes_unmap_legacy_queue_input { 240 enum amdgpu_unmap_queues_action action; 241 uint32_t queue_type; 242 uint32_t doorbell_offset; 243 uint32_t pipe_id; 244 uint32_t queue_id; 245 uint64_t trail_fence_addr; 246 uint64_t trail_fence_data; 247}; 248 249struct mes_suspend_gang_input { 250 bool suspend_all_gangs; 251 uint64_t gang_context_addr; 252 uint64_t suspend_fence_addr; 253 uint32_t suspend_fence_value; 254}; 255 256struct mes_resume_gang_input { 257 bool resume_all_gangs; 258 uint64_t gang_context_addr; 259}; 260 261enum mes_misc_opcode { 262 MES_MISC_OP_WRITE_REG, 263 MES_MISC_OP_READ_REG, 264 MES_MISC_OP_WRM_REG_WAIT, 265 MES_MISC_OP_WRM_REG_WR_WAIT, 266 MES_MISC_OP_SET_SHADER_DEBUGGER, 267}; 268 269struct mes_misc_op_input { 270 enum mes_misc_opcode op; 271 272 union { 273 struct { 274 uint32_t reg_offset; 275 uint64_t buffer_addr; 276 } read_reg; 277 278 struct { 279 uint32_t reg_offset; 280 uint32_t reg_value; 281 } write_reg; 282 283 struct { 284 uint32_t ref; 285 uint32_t mask; 286 uint32_t reg0; 287 uint32_t reg1; 288 } wrm_reg; 289 290 struct { 291 uint64_t process_context_addr; 292 union { 293 struct { 294 uint32_t single_memop : 1; 295 uint32_t single_alu_op : 1; 296 uint32_t reserved: 29; 297 uint32_t process_ctx_flush: 1; 298 }; 299 uint32_t u32all; 300 } flags; 301 uint32_t spi_gdbg_per_vmid_cntl; 302 uint32_t tcp_watch_cntl[4]; 303 uint32_t trap_en; 304 } set_shader_debugger; 305 }; 306}; 307 308struct amdgpu_mes_funcs { 309 int (*add_hw_queue)(struct amdgpu_mes *mes, 310 struct mes_add_queue_input *input); 311 312 int (*remove_hw_queue)(struct amdgpu_mes *mes, 313 struct mes_remove_queue_input *input); 314 315 int (*unmap_legacy_queue)(struct amdgpu_mes *mes, 316 struct mes_unmap_legacy_queue_input *input); 317 318 int (*suspend_gang)(struct amdgpu_mes *mes, 319 struct mes_suspend_gang_input *input); 320 321 int (*resume_gang)(struct amdgpu_mes *mes, 322 struct mes_resume_gang_input *input); 323 324 int (*misc_op)(struct amdgpu_mes *mes, 325 struct mes_misc_op_input *input); 326}; 327 328#define amdgpu_mes_kiq_hw_init(adev) (adev)->mes.kiq_hw_init((adev)) 329#define amdgpu_mes_kiq_hw_fini(adev) (adev)->mes.kiq_hw_fini((adev)) 330 331int amdgpu_mes_ctx_get_offs(struct amdgpu_ring *ring, unsigned int id_offs); 332 333int amdgpu_mes_init_microcode(struct amdgpu_device *adev, int pipe); 334int amdgpu_mes_init(struct amdgpu_device *adev); 335void amdgpu_mes_fini(struct amdgpu_device *adev); 336 337int amdgpu_mes_create_process(struct amdgpu_device *adev, int pasid, 338 struct amdgpu_vm *vm); 339void amdgpu_mes_destroy_process(struct amdgpu_device *adev, int pasid); 340 341int amdgpu_mes_add_gang(struct amdgpu_device *adev, int pasid, 342 struct amdgpu_mes_gang_properties *gprops, 343 int *gang_id); 344int amdgpu_mes_remove_gang(struct amdgpu_device *adev, int gang_id); 345 346int amdgpu_mes_suspend(struct amdgpu_device *adev); 347int amdgpu_mes_resume(struct amdgpu_device *adev); 348 349int amdgpu_mes_add_hw_queue(struct amdgpu_device *adev, int gang_id, 350 struct amdgpu_mes_queue_properties *qprops, 351 int *queue_id); 352int amdgpu_mes_remove_hw_queue(struct amdgpu_device *adev, int queue_id); 353 354int amdgpu_mes_unmap_legacy_queue(struct amdgpu_device *adev, 355 struct amdgpu_ring *ring, 356 enum amdgpu_unmap_queues_action action, 357 u64 gpu_addr, u64 seq); 358 359uint32_t amdgpu_mes_rreg(struct amdgpu_device *adev, uint32_t reg); 360int amdgpu_mes_wreg(struct amdgpu_device *adev, 361 uint32_t reg, uint32_t val); 362int amdgpu_mes_reg_wait(struct amdgpu_device *adev, uint32_t reg, 363 uint32_t val, uint32_t mask); 364int amdgpu_mes_reg_write_reg_wait(struct amdgpu_device *adev, 365 uint32_t reg0, uint32_t reg1, 366 uint32_t ref, uint32_t mask); 367int amdgpu_mes_set_shader_debugger(struct amdgpu_device *adev, 368 uint64_t process_context_addr, 369 uint32_t spi_gdbg_per_vmid_cntl, 370 const uint32_t *tcp_watch_cntl, 371 uint32_t flags, 372 bool trap_en); 373int amdgpu_mes_flush_shader_debugger(struct amdgpu_device *adev, 374 uint64_t process_context_addr); 375int amdgpu_mes_add_ring(struct amdgpu_device *adev, int gang_id, 376 int queue_type, int idx, 377 struct amdgpu_mes_ctx_data *ctx_data, 378 struct amdgpu_ring **out); 379void amdgpu_mes_remove_ring(struct amdgpu_device *adev, 380 struct amdgpu_ring *ring); 381 382uint32_t amdgpu_mes_get_aggregated_doorbell_index(struct amdgpu_device *adev, 383 enum amdgpu_mes_priority_level prio); 384 385int amdgpu_mes_ctx_alloc_meta_data(struct amdgpu_device *adev, 386 struct amdgpu_mes_ctx_data *ctx_data); 387void amdgpu_mes_ctx_free_meta_data(struct amdgpu_mes_ctx_data *ctx_data); 388int amdgpu_mes_ctx_map_meta_data(struct amdgpu_device *adev, 389 struct amdgpu_vm *vm, 390 struct amdgpu_mes_ctx_data *ctx_data); 391int amdgpu_mes_ctx_unmap_meta_data(struct amdgpu_device *adev, 392 struct amdgpu_mes_ctx_data *ctx_data); 393 394int amdgpu_mes_self_test(struct amdgpu_device *adev); 395 396int amdgpu_mes_doorbell_process_slice(struct amdgpu_device *adev); 397 398/* 399 * MES lock can be taken in MMU notifiers. 400 * 401 * A bit more detail about why to set no-FS reclaim with MES lock: 402 * 403 * The purpose of the MMU notifier is to stop GPU access to memory so 404 * that the Linux VM subsystem can move pages around safely. This is 405 * done by preempting user mode queues for the affected process. When 406 * MES is used, MES lock needs to be taken to preempt the queues. 407 * 408 * The MMU notifier callback entry point in the driver is 409 * amdgpu_mn_invalidate_range_start_hsa. The relevant call chain from 410 * there is: 411 * amdgpu_amdkfd_evict_userptr -> kgd2kfd_quiesce_mm -> 412 * kfd_process_evict_queues -> pdd->dev->dqm->ops.evict_process_queues 413 * 414 * The last part of the chain is a function pointer where we take the 415 * MES lock. 416 * 417 * The problem with taking locks in the MMU notifier is, that MMU 418 * notifiers can be called in reclaim-FS context. That's where the 419 * kernel frees up pages to make room for new page allocations under 420 * memory pressure. While we are running in reclaim-FS context, we must 421 * not trigger another memory reclaim operation because that would 422 * recursively reenter the reclaim code and cause a deadlock. The 423 * memalloc_nofs_save/restore calls guarantee that. 424 * 425 * In addition we also need to avoid lock dependencies on other locks taken 426 * under the MES lock, for example reservation locks. Here is a possible 427 * scenario of a deadlock: 428 * Thread A: takes and holds reservation lock | triggers reclaim-FS | 429 * MMU notifier | blocks trying to take MES lock 430 * Thread B: takes and holds MES lock | blocks trying to take reservation lock 431 * 432 * In this scenario Thread B gets involved in a deadlock even without 433 * triggering a reclaim-FS operation itself. 434 * To fix this and break the lock dependency chain you'd need to either: 435 * 1. protect reservation locks with memalloc_nofs_save/restore, or 436 * 2. avoid taking reservation locks under the MES lock. 437 * 438 * Reservation locks are taken all over the kernel in different subsystems, we 439 * have no control over them and their lock dependencies.So the only workable 440 * solution is to avoid taking other locks under the MES lock. 441 * As a result, make sure no reclaim-FS happens while holding this lock anywhere 442 * to prevent deadlocks when an MMU notifier runs in reclaim-FS context. 443 */ 444static inline void amdgpu_mes_lock(struct amdgpu_mes *mes) 445{ 446 mutex_lock(&mes->mutex_hidden); 447 mes->saved_flags = memalloc_noreclaim_save(); 448} 449 450static inline void amdgpu_mes_unlock(struct amdgpu_mes *mes) 451{ 452 memalloc_noreclaim_restore(mes->saved_flags); 453 mutex_unlock(&mes->mutex_hidden); 454} 455#endif /* __AMDGPU_MES_H__ */ 456