1/* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24#ifndef __AMDGPU_GFX_H__ 25#define __AMDGPU_GFX_H__ 26 27/* 28 * GFX stuff 29 */ 30#include "clearstate_defs.h" 31#include "amdgpu_ring.h" 32#include "amdgpu_rlc.h" 33#include "amdgpu_imu.h" 34#include "soc15.h" 35#include "amdgpu_ras.h" 36#include "amdgpu_ring_mux.h" 37 38/* GFX current status */ 39#define AMDGPU_GFX_NORMAL_MODE 0x00000000L 40#define AMDGPU_GFX_SAFE_MODE 0x00000001L 41#define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L 42#define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L 43#define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L 44 45#define AMDGPU_MAX_GC_INSTANCES 8 46#define KGD_MAX_QUEUES 128 47 48#define AMDGPU_MAX_GFX_QUEUES KGD_MAX_QUEUES 49#define AMDGPU_MAX_COMPUTE_QUEUES KGD_MAX_QUEUES 50 51enum amdgpu_gfx_pipe_priority { 52 AMDGPU_GFX_PIPE_PRIO_NORMAL = AMDGPU_RING_PRIO_1, 53 AMDGPU_GFX_PIPE_PRIO_HIGH = AMDGPU_RING_PRIO_2 54}; 55 56#define AMDGPU_GFX_QUEUE_PRIORITY_MINIMUM 0 57#define AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM 15 58 59enum amdgpu_gfx_partition { 60 AMDGPU_SPX_PARTITION_MODE = 0, 61 AMDGPU_DPX_PARTITION_MODE = 1, 62 AMDGPU_TPX_PARTITION_MODE = 2, 63 AMDGPU_QPX_PARTITION_MODE = 3, 64 AMDGPU_CPX_PARTITION_MODE = 4, 65 AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE = -1, 66 /* Automatically choose the right mode */ 67 AMDGPU_AUTO_COMPUTE_PARTITION_MODE = -2, 68}; 69 70#define NUM_XCC(x) hweight16(x) 71 72enum amdgpu_pkg_type { 73 AMDGPU_PKG_TYPE_APU = 2, 74 AMDGPU_PKG_TYPE_UNKNOWN, 75}; 76 77enum amdgpu_gfx_ras_mem_id_type { 78 AMDGPU_GFX_CP_MEM = 0, 79 AMDGPU_GFX_GCEA_MEM, 80 AMDGPU_GFX_GC_CANE_MEM, 81 AMDGPU_GFX_GCUTCL2_MEM, 82 AMDGPU_GFX_GDS_MEM, 83 AMDGPU_GFX_LDS_MEM, 84 AMDGPU_GFX_RLC_MEM, 85 AMDGPU_GFX_SP_MEM, 86 AMDGPU_GFX_SPI_MEM, 87 AMDGPU_GFX_SQC_MEM, 88 AMDGPU_GFX_SQ_MEM, 89 AMDGPU_GFX_TA_MEM, 90 AMDGPU_GFX_TCC_MEM, 91 AMDGPU_GFX_TCA_MEM, 92 AMDGPU_GFX_TCI_MEM, 93 AMDGPU_GFX_TCP_MEM, 94 AMDGPU_GFX_TD_MEM, 95 AMDGPU_GFX_TCX_MEM, 96 AMDGPU_GFX_ATC_L2_MEM, 97 AMDGPU_GFX_UTCL2_MEM, 98 AMDGPU_GFX_VML2_MEM, 99 AMDGPU_GFX_VML2_WALKER_MEM, 100 AMDGPU_GFX_MEM_TYPE_NUM 101}; 102 103struct amdgpu_mec { 104 struct amdgpu_bo *hpd_eop_obj; 105 u64 hpd_eop_gpu_addr; 106 struct amdgpu_bo *mec_fw_obj; 107 u64 mec_fw_gpu_addr; 108 struct amdgpu_bo *mec_fw_data_obj; 109 u64 mec_fw_data_gpu_addr; 110 111 u32 num_mec; 112 u32 num_pipe_per_mec; 113 u32 num_queue_per_pipe; 114 void *mqd_backup[AMDGPU_MAX_COMPUTE_RINGS * AMDGPU_MAX_GC_INSTANCES]; 115}; 116 117struct amdgpu_mec_bitmap { 118 /* These are the resources for which amdgpu takes ownership */ 119 DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 120}; 121 122enum amdgpu_unmap_queues_action { 123 PREEMPT_QUEUES = 0, 124 RESET_QUEUES, 125 DISABLE_PROCESS_QUEUES, 126 PREEMPT_QUEUES_NO_UNMAP, 127}; 128 129struct kiq_pm4_funcs { 130 /* Support ASIC-specific kiq pm4 packets*/ 131 void (*kiq_set_resources)(struct amdgpu_ring *kiq_ring, 132 uint64_t queue_mask); 133 void (*kiq_map_queues)(struct amdgpu_ring *kiq_ring, 134 struct amdgpu_ring *ring); 135 void (*kiq_unmap_queues)(struct amdgpu_ring *kiq_ring, 136 struct amdgpu_ring *ring, 137 enum amdgpu_unmap_queues_action action, 138 u64 gpu_addr, u64 seq); 139 void (*kiq_query_status)(struct amdgpu_ring *kiq_ring, 140 struct amdgpu_ring *ring, 141 u64 addr, 142 u64 seq); 143 void (*kiq_invalidate_tlbs)(struct amdgpu_ring *kiq_ring, 144 uint16_t pasid, uint32_t flush_type, 145 bool all_hub); 146 /* Packet sizes */ 147 int set_resources_size; 148 int map_queues_size; 149 int unmap_queues_size; 150 int query_status_size; 151 int invalidate_tlbs_size; 152}; 153 154struct amdgpu_kiq { 155 u64 eop_gpu_addr; 156 struct amdgpu_bo *eop_obj; 157 spinlock_t ring_lock; 158 struct amdgpu_ring ring; 159 struct amdgpu_irq_src irq; 160 const struct kiq_pm4_funcs *pmf; 161 void *mqd_backup; 162}; 163 164/* 165 * GFX configurations 166 */ 167#define AMDGPU_GFX_MAX_SE 4 168#define AMDGPU_GFX_MAX_SH_PER_SE 2 169 170struct amdgpu_rb_config { 171 uint32_t rb_backend_disable; 172 uint32_t user_rb_backend_disable; 173 uint32_t raster_config; 174 uint32_t raster_config_1; 175}; 176 177struct gb_addr_config { 178 uint16_t pipe_interleave_size; 179 uint8_t num_pipes; 180 uint8_t max_compress_frags; 181 uint8_t num_banks; 182 uint8_t num_se; 183 uint8_t num_rb_per_se; 184 uint8_t num_pkrs; 185}; 186 187struct amdgpu_gfx_config { 188 unsigned max_shader_engines; 189 unsigned max_tile_pipes; 190 unsigned max_cu_per_sh; 191 unsigned max_sh_per_se; 192 unsigned max_backends_per_se; 193 unsigned max_texture_channel_caches; 194 unsigned max_gprs; 195 unsigned max_gs_threads; 196 unsigned max_hw_contexts; 197 unsigned sc_prim_fifo_size_frontend; 198 unsigned sc_prim_fifo_size_backend; 199 unsigned sc_hiz_tile_fifo_size; 200 unsigned sc_earlyz_tile_fifo_size; 201 202 unsigned num_tile_pipes; 203 unsigned backend_enable_mask; 204 unsigned mem_max_burst_length_bytes; 205 unsigned mem_row_size_in_kb; 206 unsigned shader_engine_tile_size; 207 unsigned num_gpus; 208 unsigned multi_gpu_tile_size; 209 unsigned mc_arb_ramcfg; 210 unsigned num_banks; 211 unsigned num_ranks; 212 unsigned gb_addr_config; 213 unsigned num_rbs; 214 unsigned gs_vgt_table_depth; 215 unsigned gs_prim_buffer_depth; 216 217 uint32_t tile_mode_array[32]; 218 uint32_t macrotile_mode_array[16]; 219 220 struct gb_addr_config gb_addr_config_fields; 221 struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE]; 222 223 /* gfx configure feature */ 224 uint32_t double_offchip_lds_buf; 225 /* cached value of DB_DEBUG2 */ 226 uint32_t db_debug2; 227 /* gfx10 specific config */ 228 uint32_t num_sc_per_sh; 229 uint32_t num_packer_per_sc; 230 uint32_t pa_sc_tile_steering_override; 231 /* Whether texture coordinate truncation is conformant. */ 232 bool ta_cntl2_truncate_coord_mode; 233 uint64_t tcc_disabled_mask; 234 uint32_t gc_num_tcp_per_sa; 235 uint32_t gc_num_sdp_interface; 236 uint32_t gc_num_tcps; 237 uint32_t gc_num_tcp_per_wpg; 238 uint32_t gc_tcp_l1_size; 239 uint32_t gc_num_sqc_per_wgp; 240 uint32_t gc_l1_instruction_cache_size_per_sqc; 241 uint32_t gc_l1_data_cache_size_per_sqc; 242 uint32_t gc_gl1c_per_sa; 243 uint32_t gc_gl1c_size_per_instance; 244 uint32_t gc_gl2c_per_gpu; 245 uint32_t gc_tcp_size_per_cu; 246 uint32_t gc_num_cu_per_sqc; 247 uint32_t gc_tcc_size; 248}; 249 250struct amdgpu_cu_info { 251 uint32_t simd_per_cu; 252 uint32_t max_waves_per_simd; 253 uint32_t wave_front_size; 254 uint32_t max_scratch_slots_per_cu; 255 uint32_t lds_size; 256 257 /* total active CU number */ 258 uint32_t number; 259 uint32_t ao_cu_mask; 260 uint32_t ao_cu_bitmap[4][4]; 261 uint32_t bitmap[AMDGPU_MAX_GC_INSTANCES][4][4]; 262}; 263 264struct amdgpu_gfx_ras { 265 struct amdgpu_ras_block_object ras_block; 266 void (*enable_watchdog_timer)(struct amdgpu_device *adev); 267 bool (*query_utcl2_poison_status)(struct amdgpu_device *adev); 268 int (*rlc_gc_fed_irq)(struct amdgpu_device *adev, 269 struct amdgpu_irq_src *source, 270 struct amdgpu_iv_entry *entry); 271 int (*poison_consumption_handler)(struct amdgpu_device *adev, 272 struct amdgpu_iv_entry *entry); 273}; 274 275struct amdgpu_gfx_shadow_info { 276 u32 shadow_size; 277 u32 shadow_alignment; 278 u32 csa_size; 279 u32 csa_alignment; 280}; 281 282struct amdgpu_gfx_funcs { 283 /* get the gpu clock counter */ 284 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev); 285 void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num, 286 u32 sh_num, u32 instance, int xcc_id); 287 void (*read_wave_data)(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 288 uint32_t wave, uint32_t *dst, int *no_fields); 289 void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 290 uint32_t wave, uint32_t thread, uint32_t start, 291 uint32_t size, uint32_t *dst); 292 void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 293 uint32_t wave, uint32_t start, uint32_t size, 294 uint32_t *dst); 295 void (*select_me_pipe_q)(struct amdgpu_device *adev, u32 me, u32 pipe, 296 u32 queue, u32 vmid, u32 xcc_id); 297 void (*init_spm_golden)(struct amdgpu_device *adev); 298 void (*update_perfmon_mgcg)(struct amdgpu_device *adev, bool enable); 299 int (*get_gfx_shadow_info)(struct amdgpu_device *adev, 300 struct amdgpu_gfx_shadow_info *shadow_info); 301 enum amdgpu_gfx_partition 302 (*query_partition_mode)(struct amdgpu_device *adev); 303 int (*switch_partition_mode)(struct amdgpu_device *adev, 304 int num_xccs_per_xcp); 305 int (*ih_node_to_logical_xcc)(struct amdgpu_device *adev, int ih_node); 306}; 307 308struct sq_work { 309 struct work_struct work; 310 unsigned ih_data; 311}; 312 313struct amdgpu_pfp { 314 struct amdgpu_bo *pfp_fw_obj; 315 uint64_t pfp_fw_gpu_addr; 316 uint32_t *pfp_fw_ptr; 317 318 struct amdgpu_bo *pfp_fw_data_obj; 319 uint64_t pfp_fw_data_gpu_addr; 320 uint32_t *pfp_fw_data_ptr; 321}; 322 323struct amdgpu_ce { 324 struct amdgpu_bo *ce_fw_obj; 325 uint64_t ce_fw_gpu_addr; 326 uint32_t *ce_fw_ptr; 327}; 328 329struct amdgpu_me { 330 struct amdgpu_bo *me_fw_obj; 331 uint64_t me_fw_gpu_addr; 332 uint32_t *me_fw_ptr; 333 334 struct amdgpu_bo *me_fw_data_obj; 335 uint64_t me_fw_data_gpu_addr; 336 uint32_t *me_fw_data_ptr; 337 338 uint32_t num_me; 339 uint32_t num_pipe_per_me; 340 uint32_t num_queue_per_pipe; 341 void *mqd_backup[AMDGPU_MAX_GFX_RINGS]; 342 343 /* These are the resources for which amdgpu takes ownership */ 344 DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 345}; 346 347struct amdgpu_gfx { 348 struct mutex gpu_clock_mutex; 349 struct amdgpu_gfx_config config; 350 struct amdgpu_rlc rlc; 351 struct amdgpu_pfp pfp; 352 struct amdgpu_ce ce; 353 struct amdgpu_me me; 354 struct amdgpu_mec mec; 355 struct amdgpu_mec_bitmap mec_bitmap[AMDGPU_MAX_GC_INSTANCES]; 356 struct amdgpu_kiq kiq[AMDGPU_MAX_GC_INSTANCES]; 357 struct amdgpu_imu imu; 358 bool rs64_enable; /* firmware format */ 359 const struct firmware *me_fw; /* ME firmware */ 360 uint32_t me_fw_version; 361 const struct firmware *pfp_fw; /* PFP firmware */ 362 uint32_t pfp_fw_version; 363 const struct firmware *ce_fw; /* CE firmware */ 364 uint32_t ce_fw_version; 365 const struct firmware *rlc_fw; /* RLC firmware */ 366 uint32_t rlc_fw_version; 367 const struct firmware *mec_fw; /* MEC firmware */ 368 uint32_t mec_fw_version; 369 const struct firmware *mec2_fw; /* MEC2 firmware */ 370 uint32_t mec2_fw_version; 371 const struct firmware *imu_fw; /* IMU firmware */ 372 uint32_t imu_fw_version; 373 uint32_t me_feature_version; 374 uint32_t ce_feature_version; 375 uint32_t pfp_feature_version; 376 uint32_t rlc_feature_version; 377 uint32_t rlc_srlc_fw_version; 378 uint32_t rlc_srlc_feature_version; 379 uint32_t rlc_srlg_fw_version; 380 uint32_t rlc_srlg_feature_version; 381 uint32_t rlc_srls_fw_version; 382 uint32_t rlc_srls_feature_version; 383 uint32_t rlcp_ucode_version; 384 uint32_t rlcp_ucode_feature_version; 385 uint32_t rlcv_ucode_version; 386 uint32_t rlcv_ucode_feature_version; 387 uint32_t mec_feature_version; 388 uint32_t mec2_feature_version; 389 bool mec_fw_write_wait; 390 bool me_fw_write_wait; 391 bool cp_fw_write_wait; 392 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS]; 393 unsigned num_gfx_rings; 394 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS * AMDGPU_MAX_GC_INSTANCES]; 395 unsigned num_compute_rings; 396 struct amdgpu_irq_src eop_irq; 397 struct amdgpu_irq_src priv_reg_irq; 398 struct amdgpu_irq_src priv_inst_irq; 399 struct amdgpu_irq_src cp_ecc_error_irq; 400 struct amdgpu_irq_src sq_irq; 401 struct amdgpu_irq_src rlc_gc_fed_irq; 402 struct sq_work sq_work; 403 404 /* gfx status */ 405 uint32_t gfx_current_status; 406 /* ce ram size*/ 407 unsigned ce_ram_size; 408 struct amdgpu_cu_info cu_info; 409 const struct amdgpu_gfx_funcs *funcs; 410 411 /* reset mask */ 412 uint32_t grbm_soft_reset; 413 uint32_t srbm_soft_reset; 414 415 /* gfx off */ 416 bool gfx_off_state; /* true: enabled, false: disabled */ 417 struct mutex gfx_off_mutex; /* mutex to change gfxoff state */ 418 uint32_t gfx_off_req_count; /* default 1, enable gfx off: dec 1, disable gfx off: add 1 */ 419 struct delayed_work gfx_off_delay_work; /* async work to set gfx block off */ 420 uint32_t gfx_off_residency; /* last logged residency */ 421 uint64_t gfx_off_entrycount; /* count of times GPU has get into GFXOFF state */ 422 423 /* pipe reservation */ 424 struct mutex pipe_reserve_mutex; 425 DECLARE_BITMAP (pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 426 427 /*ras */ 428 struct ras_common_if *ras_if; 429 struct amdgpu_gfx_ras *ras; 430 431 bool is_poweron; 432 433 struct amdgpu_ring sw_gfx_ring[AMDGPU_MAX_SW_GFX_RINGS]; 434 struct amdgpu_ring_mux muxer; 435 436 bool cp_gfx_shadow; /* for gfx11 */ 437 438 uint16_t xcc_mask; 439 uint32_t num_xcc_per_xcp; 440 struct mutex partition_mutex; 441 bool mcbp; /* mid command buffer preemption */ 442}; 443 444struct amdgpu_gfx_ras_reg_entry { 445 struct amdgpu_ras_err_status_reg_entry reg_entry; 446 enum amdgpu_gfx_ras_mem_id_type mem_id_type; 447 uint32_t se_num; 448}; 449 450struct amdgpu_gfx_ras_mem_id_entry { 451 const struct amdgpu_ras_memory_id_entry *mem_id_ent; 452 uint32_t size; 453}; 454 455#define AMDGPU_GFX_MEMID_ENT(x) {(x), ARRAY_SIZE(x)}, 456 457#define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev)) 458#define amdgpu_gfx_select_se_sh(adev, se, sh, instance, xcc_id) ((adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance), (xcc_id))) 459#define amdgpu_gfx_select_me_pipe_q(adev, me, pipe, q, vmid, xcc_id) ((adev)->gfx.funcs->select_me_pipe_q((adev), (me), (pipe), (q), (vmid), (xcc_id))) 460#define amdgpu_gfx_init_spm_golden(adev) (adev)->gfx.funcs->init_spm_golden((adev)) 461#define amdgpu_gfx_get_gfx_shadow_info(adev, si) ((adev)->gfx.funcs->get_gfx_shadow_info((adev), (si))) 462 463/** 464 * amdgpu_gfx_create_bitmask - create a bitmask 465 * 466 * @bit_width: length of the mask 467 * 468 * create a variable length bit mask. 469 * Returns the bitmask. 470 */ 471static inline u32 amdgpu_gfx_create_bitmask(u32 bit_width) 472{ 473 return (u32)((1ULL << bit_width) - 1); 474} 475 476void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se, 477 unsigned max_sh); 478 479int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev, 480 struct amdgpu_ring *ring, 481 struct amdgpu_irq_src *irq, int xcc_id); 482 483void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring); 484 485void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev, int xcc_id); 486int amdgpu_gfx_kiq_init(struct amdgpu_device *adev, 487 unsigned hpd_size, int xcc_id); 488 489int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev, 490 unsigned mqd_size, int xcc_id); 491void amdgpu_gfx_mqd_sw_fini(struct amdgpu_device *adev, int xcc_id); 492int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev, int xcc_id); 493int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev, int xcc_id); 494int amdgpu_gfx_disable_kgq(struct amdgpu_device *adev, int xcc_id); 495int amdgpu_gfx_enable_kgq(struct amdgpu_device *adev, int xcc_id); 496 497void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev); 498void amdgpu_gfx_graphics_queue_acquire(struct amdgpu_device *adev); 499 500int amdgpu_gfx_mec_queue_to_bit(struct amdgpu_device *adev, int mec, 501 int pipe, int queue); 502void amdgpu_queue_mask_bit_to_mec_queue(struct amdgpu_device *adev, int bit, 503 int *mec, int *pipe, int *queue); 504bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev, int xcc_id, 505 int mec, int pipe, int queue); 506bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev, 507 struct amdgpu_ring *ring); 508bool amdgpu_gfx_is_high_priority_graphics_queue(struct amdgpu_device *adev, 509 struct amdgpu_ring *ring); 510int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev, int me, 511 int pipe, int queue); 512void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit, 513 int *me, int *pipe, int *queue); 514bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev, int me, 515 int pipe, int queue); 516void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable); 517int amdgpu_get_gfx_off_status(struct amdgpu_device *adev, uint32_t *value); 518int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block); 519void amdgpu_gfx_ras_fini(struct amdgpu_device *adev); 520int amdgpu_get_gfx_off_entrycount(struct amdgpu_device *adev, u64 *value); 521int amdgpu_get_gfx_off_residency(struct amdgpu_device *adev, u32 *residency); 522int amdgpu_set_gfx_off_residency(struct amdgpu_device *adev, bool value); 523int amdgpu_gfx_process_ras_data_cb(struct amdgpu_device *adev, 524 void *err_data, 525 struct amdgpu_iv_entry *entry); 526int amdgpu_gfx_cp_ecc_error_irq(struct amdgpu_device *adev, 527 struct amdgpu_irq_src *source, 528 struct amdgpu_iv_entry *entry); 529uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg); 530void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v); 531int amdgpu_gfx_get_num_kcq(struct amdgpu_device *adev); 532void amdgpu_gfx_cp_init_microcode(struct amdgpu_device *adev, uint32_t ucode_id); 533 534int amdgpu_gfx_ras_sw_init(struct amdgpu_device *adev); 535int amdgpu_gfx_poison_consumption_handler(struct amdgpu_device *adev, 536 struct amdgpu_iv_entry *entry); 537 538bool amdgpu_gfx_is_master_xcc(struct amdgpu_device *adev, int xcc_id); 539int amdgpu_gfx_sysfs_init(struct amdgpu_device *adev); 540void amdgpu_gfx_sysfs_fini(struct amdgpu_device *adev); 541void amdgpu_gfx_ras_error_func(struct amdgpu_device *adev, 542 void *ras_error_status, 543 void (*func)(struct amdgpu_device *adev, void *ras_error_status, 544 int xcc_id)); 545 546static inline const char *amdgpu_gfx_compute_mode_desc(int mode) 547{ 548 switch (mode) { 549 case AMDGPU_SPX_PARTITION_MODE: 550 return "SPX"; 551 case AMDGPU_DPX_PARTITION_MODE: 552 return "DPX"; 553 case AMDGPU_TPX_PARTITION_MODE: 554 return "TPX"; 555 case AMDGPU_QPX_PARTITION_MODE: 556 return "QPX"; 557 case AMDGPU_CPX_PARTITION_MODE: 558 return "CPX"; 559 default: 560 return "UNKNOWN"; 561 } 562 563 return "UNKNOWN"; 564} 565 566#endif 567