162306a36Sopenharmony_ci/* 262306a36Sopenharmony_ci * Copyright 2017 Advanced Micro Devices, Inc. 362306a36Sopenharmony_ci * 462306a36Sopenharmony_ci * Permission is hereby granted, free of charge, to any person obtaining a 562306a36Sopenharmony_ci * copy of this software and associated documentation files (the "Software"), 662306a36Sopenharmony_ci * to deal in the Software without restriction, including without limitation 762306a36Sopenharmony_ci * the rights to use, copy, modify, merge, publish, distribute, sublicense, 862306a36Sopenharmony_ci * and/or sell copies of the Software, and to permit persons to whom the 962306a36Sopenharmony_ci * Software is furnished to do so, subject to the following conditions: 1062306a36Sopenharmony_ci * 1162306a36Sopenharmony_ci * The above copyright notice and this permission notice shall be included in 1262306a36Sopenharmony_ci * all copies or substantial portions of the Software. 1362306a36Sopenharmony_ci * 1462306a36Sopenharmony_ci * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1562306a36Sopenharmony_ci * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1662306a36Sopenharmony_ci * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1762306a36Sopenharmony_ci * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 1862306a36Sopenharmony_ci * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 1962306a36Sopenharmony_ci * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 2062306a36Sopenharmony_ci * OTHER DEALINGS IN THE SOFTWARE. 2162306a36Sopenharmony_ci * 2262306a36Sopenharmony_ci */ 2362306a36Sopenharmony_ci 2462306a36Sopenharmony_ci#ifndef __AMDGPU_GART_H__ 2562306a36Sopenharmony_ci#define __AMDGPU_GART_H__ 2662306a36Sopenharmony_ci 2762306a36Sopenharmony_ci#include <linux/types.h> 2862306a36Sopenharmony_ci 2962306a36Sopenharmony_ci/* 3062306a36Sopenharmony_ci * GART structures, functions & helpers 3162306a36Sopenharmony_ci */ 3262306a36Sopenharmony_cistruct amdgpu_device; 3362306a36Sopenharmony_cistruct amdgpu_bo; 3462306a36Sopenharmony_ci 3562306a36Sopenharmony_ci#define AMDGPU_GPU_PAGE_SIZE 4096 3662306a36Sopenharmony_ci#define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1) 3762306a36Sopenharmony_ci#define AMDGPU_GPU_PAGE_SHIFT 12 3862306a36Sopenharmony_ci#define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK) 3962306a36Sopenharmony_ci 4062306a36Sopenharmony_ci#define AMDGPU_GPU_PAGES_IN_CPU_PAGE (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE) 4162306a36Sopenharmony_ci 4262306a36Sopenharmony_cistruct amdgpu_gart { 4362306a36Sopenharmony_ci struct amdgpu_bo *bo; 4462306a36Sopenharmony_ci /* CPU kmapped address of gart table */ 4562306a36Sopenharmony_ci void *ptr; 4662306a36Sopenharmony_ci unsigned num_gpu_pages; 4762306a36Sopenharmony_ci unsigned num_cpu_pages; 4862306a36Sopenharmony_ci unsigned table_size; 4962306a36Sopenharmony_ci 5062306a36Sopenharmony_ci /* Asic default pte flags */ 5162306a36Sopenharmony_ci uint64_t gart_pte_flags; 5262306a36Sopenharmony_ci}; 5362306a36Sopenharmony_ci 5462306a36Sopenharmony_ciint amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev); 5562306a36Sopenharmony_civoid amdgpu_gart_table_ram_free(struct amdgpu_device *adev); 5662306a36Sopenharmony_ciint amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev); 5762306a36Sopenharmony_civoid amdgpu_gart_table_vram_free(struct amdgpu_device *adev); 5862306a36Sopenharmony_ciint amdgpu_gart_table_vram_pin(struct amdgpu_device *adev); 5962306a36Sopenharmony_civoid amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev); 6062306a36Sopenharmony_ciint amdgpu_gart_init(struct amdgpu_device *adev); 6162306a36Sopenharmony_civoid amdgpu_gart_dummy_page_fini(struct amdgpu_device *adev); 6262306a36Sopenharmony_civoid amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset, 6362306a36Sopenharmony_ci int pages); 6462306a36Sopenharmony_civoid amdgpu_gart_map(struct amdgpu_device *adev, uint64_t offset, 6562306a36Sopenharmony_ci int pages, dma_addr_t *dma_addr, uint64_t flags, 6662306a36Sopenharmony_ci void *dst); 6762306a36Sopenharmony_civoid amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset, 6862306a36Sopenharmony_ci int pages, dma_addr_t *dma_addr, uint64_t flags); 6962306a36Sopenharmony_civoid amdgpu_gart_invalidate_tlb(struct amdgpu_device *adev); 7062306a36Sopenharmony_ci#endif 71