1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (C) ST-Ericsson SA 2010 4 * 5 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson 6 */ 7 8#include <linux/init.h> 9#include <linux/platform_device.h> 10#include <linux/slab.h> 11#include <linux/gpio/driver.h> 12#include <linux/interrupt.h> 13#include <linux/of.h> 14#include <linux/mfd/stmpe.h> 15#include <linux/seq_file.h> 16#include <linux/bitops.h> 17 18/* 19 * These registers are modified under the irq bus lock and cached to avoid 20 * unnecessary writes in bus_sync_unlock. 21 */ 22enum { REG_RE, REG_FE, REG_IE }; 23 24enum { LSB, CSB, MSB }; 25 26#define CACHE_NR_REGS 3 27/* No variant has more than 24 GPIOs */ 28#define CACHE_NR_BANKS (24 / 8) 29 30struct stmpe_gpio { 31 struct gpio_chip chip; 32 struct stmpe *stmpe; 33 struct device *dev; 34 struct mutex irq_lock; 35 u32 norequest_mask; 36 /* Caches of interrupt control registers for bus_lock */ 37 u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS]; 38 u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS]; 39}; 40 41static int stmpe_gpio_get(struct gpio_chip *chip, unsigned offset) 42{ 43 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip); 44 struct stmpe *stmpe = stmpe_gpio->stmpe; 45 u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB + (offset / 8)]; 46 u8 mask = BIT(offset % 8); 47 int ret; 48 49 ret = stmpe_reg_read(stmpe, reg); 50 if (ret < 0) 51 return ret; 52 53 return !!(ret & mask); 54} 55 56static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val) 57{ 58 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip); 59 struct stmpe *stmpe = stmpe_gpio->stmpe; 60 int which = val ? STMPE_IDX_GPSR_LSB : STMPE_IDX_GPCR_LSB; 61 u8 reg = stmpe->regs[which + (offset / 8)]; 62 u8 mask = BIT(offset % 8); 63 64 /* 65 * Some variants have single register for gpio set/clear functionality. 66 * For them we need to write 0 to clear and 1 to set. 67 */ 68 if (stmpe->regs[STMPE_IDX_GPSR_LSB] == stmpe->regs[STMPE_IDX_GPCR_LSB]) 69 stmpe_set_bits(stmpe, reg, mask, val ? mask : 0); 70 else 71 stmpe_reg_write(stmpe, reg, mask); 72} 73 74static int stmpe_gpio_get_direction(struct gpio_chip *chip, 75 unsigned offset) 76{ 77 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip); 78 struct stmpe *stmpe = stmpe_gpio->stmpe; 79 u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8); 80 u8 mask = BIT(offset % 8); 81 int ret; 82 83 ret = stmpe_reg_read(stmpe, reg); 84 if (ret < 0) 85 return ret; 86 87 if (ret & mask) 88 return GPIO_LINE_DIRECTION_OUT; 89 90 return GPIO_LINE_DIRECTION_IN; 91} 92 93static int stmpe_gpio_direction_output(struct gpio_chip *chip, 94 unsigned offset, int val) 95{ 96 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip); 97 struct stmpe *stmpe = stmpe_gpio->stmpe; 98 u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB + (offset / 8)]; 99 u8 mask = BIT(offset % 8); 100 101 stmpe_gpio_set(chip, offset, val); 102 103 return stmpe_set_bits(stmpe, reg, mask, mask); 104} 105 106static int stmpe_gpio_direction_input(struct gpio_chip *chip, 107 unsigned offset) 108{ 109 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip); 110 struct stmpe *stmpe = stmpe_gpio->stmpe; 111 u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB + (offset / 8)]; 112 u8 mask = BIT(offset % 8); 113 114 return stmpe_set_bits(stmpe, reg, mask, 0); 115} 116 117static int stmpe_gpio_request(struct gpio_chip *chip, unsigned offset) 118{ 119 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip); 120 struct stmpe *stmpe = stmpe_gpio->stmpe; 121 122 if (stmpe_gpio->norequest_mask & BIT(offset)) 123 return -EINVAL; 124 125 return stmpe_set_altfunc(stmpe, BIT(offset), STMPE_BLOCK_GPIO); 126} 127 128static const struct gpio_chip template_chip = { 129 .label = "stmpe", 130 .owner = THIS_MODULE, 131 .get_direction = stmpe_gpio_get_direction, 132 .direction_input = stmpe_gpio_direction_input, 133 .get = stmpe_gpio_get, 134 .direction_output = stmpe_gpio_direction_output, 135 .set = stmpe_gpio_set, 136 .request = stmpe_gpio_request, 137 .can_sleep = true, 138}; 139 140static int stmpe_gpio_irq_set_type(struct irq_data *d, unsigned int type) 141{ 142 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 143 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc); 144 int offset = d->hwirq; 145 int regoffset = offset / 8; 146 int mask = BIT(offset % 8); 147 148 if (type & IRQ_TYPE_LEVEL_LOW || type & IRQ_TYPE_LEVEL_HIGH) 149 return -EINVAL; 150 151 /* STMPE801 and STMPE 1600 don't have RE and FE registers */ 152 if (stmpe_gpio->stmpe->partnum == STMPE801 || 153 stmpe_gpio->stmpe->partnum == STMPE1600) 154 return 0; 155 156 if (type & IRQ_TYPE_EDGE_RISING) 157 stmpe_gpio->regs[REG_RE][regoffset] |= mask; 158 else 159 stmpe_gpio->regs[REG_RE][regoffset] &= ~mask; 160 161 if (type & IRQ_TYPE_EDGE_FALLING) 162 stmpe_gpio->regs[REG_FE][regoffset] |= mask; 163 else 164 stmpe_gpio->regs[REG_FE][regoffset] &= ~mask; 165 166 return 0; 167} 168 169static void stmpe_gpio_irq_lock(struct irq_data *d) 170{ 171 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 172 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc); 173 174 mutex_lock(&stmpe_gpio->irq_lock); 175} 176 177static void stmpe_gpio_irq_sync_unlock(struct irq_data *d) 178{ 179 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 180 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc); 181 struct stmpe *stmpe = stmpe_gpio->stmpe; 182 int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8); 183 static const u8 regmap[CACHE_NR_REGS][CACHE_NR_BANKS] = { 184 [REG_RE][LSB] = STMPE_IDX_GPRER_LSB, 185 [REG_RE][CSB] = STMPE_IDX_GPRER_CSB, 186 [REG_RE][MSB] = STMPE_IDX_GPRER_MSB, 187 [REG_FE][LSB] = STMPE_IDX_GPFER_LSB, 188 [REG_FE][CSB] = STMPE_IDX_GPFER_CSB, 189 [REG_FE][MSB] = STMPE_IDX_GPFER_MSB, 190 [REG_IE][LSB] = STMPE_IDX_IEGPIOR_LSB, 191 [REG_IE][CSB] = STMPE_IDX_IEGPIOR_CSB, 192 [REG_IE][MSB] = STMPE_IDX_IEGPIOR_MSB, 193 }; 194 int i, j; 195 196 /* 197 * STMPE1600: to be able to get IRQ from pins, 198 * a read must be done on GPMR register, or a write in 199 * GPSR or GPCR registers 200 */ 201 if (stmpe->partnum == STMPE1600) { 202 stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_GPMR_LSB]); 203 stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_GPMR_CSB]); 204 } 205 206 for (i = 0; i < CACHE_NR_REGS; i++) { 207 /* STMPE801 and STMPE1600 don't have RE and FE registers */ 208 if ((stmpe->partnum == STMPE801 || 209 stmpe->partnum == STMPE1600) && 210 (i != REG_IE)) 211 continue; 212 213 for (j = 0; j < num_banks; j++) { 214 u8 old = stmpe_gpio->oldregs[i][j]; 215 u8 new = stmpe_gpio->regs[i][j]; 216 217 if (new == old) 218 continue; 219 220 stmpe_gpio->oldregs[i][j] = new; 221 stmpe_reg_write(stmpe, stmpe->regs[regmap[i][j]], new); 222 } 223 } 224 225 mutex_unlock(&stmpe_gpio->irq_lock); 226} 227 228static void stmpe_gpio_irq_mask(struct irq_data *d) 229{ 230 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 231 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc); 232 int offset = d->hwirq; 233 int regoffset = offset / 8; 234 int mask = BIT(offset % 8); 235 236 stmpe_gpio->regs[REG_IE][regoffset] &= ~mask; 237 gpiochip_disable_irq(gc, offset); 238} 239 240static void stmpe_gpio_irq_unmask(struct irq_data *d) 241{ 242 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 243 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc); 244 int offset = d->hwirq; 245 int regoffset = offset / 8; 246 int mask = BIT(offset % 8); 247 248 gpiochip_enable_irq(gc, offset); 249 stmpe_gpio->regs[REG_IE][regoffset] |= mask; 250} 251 252static void stmpe_dbg_show_one(struct seq_file *s, 253 struct gpio_chip *gc, 254 unsigned offset, unsigned gpio) 255{ 256 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc); 257 struct stmpe *stmpe = stmpe_gpio->stmpe; 258 const char *label = gpiochip_is_requested(gc, offset); 259 bool val = !!stmpe_gpio_get(gc, offset); 260 u8 bank = offset / 8; 261 u8 dir_reg = stmpe->regs[STMPE_IDX_GPDR_LSB + bank]; 262 u8 mask = BIT(offset % 8); 263 int ret; 264 u8 dir; 265 266 ret = stmpe_reg_read(stmpe, dir_reg); 267 if (ret < 0) 268 return; 269 dir = !!(ret & mask); 270 271 if (dir) { 272 seq_printf(s, " gpio-%-3d (%-20.20s) out %s", 273 gpio, label ?: "(none)", 274 val ? "hi" : "lo"); 275 } else { 276 u8 edge_det_reg; 277 u8 rise_reg; 278 u8 fall_reg; 279 u8 irqen_reg; 280 281 static const char * const edge_det_values[] = { 282 "edge-inactive", 283 "edge-asserted", 284 "not-supported" 285 }; 286 static const char * const rise_values[] = { 287 "no-rising-edge-detection", 288 "rising-edge-detection", 289 "not-supported" 290 }; 291 static const char * const fall_values[] = { 292 "no-falling-edge-detection", 293 "falling-edge-detection", 294 "not-supported" 295 }; 296 #define NOT_SUPPORTED_IDX 2 297 u8 edge_det = NOT_SUPPORTED_IDX; 298 u8 rise = NOT_SUPPORTED_IDX; 299 u8 fall = NOT_SUPPORTED_IDX; 300 bool irqen; 301 302 switch (stmpe->partnum) { 303 case STMPE610: 304 case STMPE811: 305 case STMPE1601: 306 case STMPE2401: 307 case STMPE2403: 308 edge_det_reg = stmpe->regs[STMPE_IDX_GPEDR_LSB + bank]; 309 ret = stmpe_reg_read(stmpe, edge_det_reg); 310 if (ret < 0) 311 return; 312 edge_det = !!(ret & mask); 313 fallthrough; 314 case STMPE1801: 315 rise_reg = stmpe->regs[STMPE_IDX_GPRER_LSB + bank]; 316 fall_reg = stmpe->regs[STMPE_IDX_GPFER_LSB + bank]; 317 318 ret = stmpe_reg_read(stmpe, rise_reg); 319 if (ret < 0) 320 return; 321 rise = !!(ret & mask); 322 ret = stmpe_reg_read(stmpe, fall_reg); 323 if (ret < 0) 324 return; 325 fall = !!(ret & mask); 326 fallthrough; 327 case STMPE801: 328 case STMPE1600: 329 irqen_reg = stmpe->regs[STMPE_IDX_IEGPIOR_LSB + bank]; 330 break; 331 332 default: 333 return; 334 } 335 336 ret = stmpe_reg_read(stmpe, irqen_reg); 337 if (ret < 0) 338 return; 339 irqen = !!(ret & mask); 340 341 seq_printf(s, " gpio-%-3d (%-20.20s) in %s %13s %13s %25s %25s", 342 gpio, label ?: "(none)", 343 val ? "hi" : "lo", 344 edge_det_values[edge_det], 345 irqen ? "IRQ-enabled" : "IRQ-disabled", 346 rise_values[rise], 347 fall_values[fall]); 348 } 349} 350 351static void stmpe_dbg_show(struct seq_file *s, struct gpio_chip *gc) 352{ 353 unsigned i; 354 unsigned gpio = gc->base; 355 356 for (i = 0; i < gc->ngpio; i++, gpio++) { 357 stmpe_dbg_show_one(s, gc, i, gpio); 358 seq_putc(s, '\n'); 359 } 360} 361 362static const struct irq_chip stmpe_gpio_irq_chip = { 363 .name = "stmpe-gpio", 364 .irq_bus_lock = stmpe_gpio_irq_lock, 365 .irq_bus_sync_unlock = stmpe_gpio_irq_sync_unlock, 366 .irq_mask = stmpe_gpio_irq_mask, 367 .irq_unmask = stmpe_gpio_irq_unmask, 368 .irq_set_type = stmpe_gpio_irq_set_type, 369 .flags = IRQCHIP_IMMUTABLE, 370 GPIOCHIP_IRQ_RESOURCE_HELPERS, 371}; 372 373#define MAX_GPIOS 24 374 375static irqreturn_t stmpe_gpio_irq(int irq, void *dev) 376{ 377 struct stmpe_gpio *stmpe_gpio = dev; 378 struct stmpe *stmpe = stmpe_gpio->stmpe; 379 u8 statmsbreg; 380 int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8); 381 u8 status[DIV_ROUND_UP(MAX_GPIOS, 8)]; 382 int ret; 383 int i; 384 385 /* 386 * the stmpe_block_read() call below, imposes to set statmsbreg 387 * with the register located at the lowest address. As STMPE1600 388 * variant is the only one which respect registers address's order 389 * (LSB regs located at lowest address than MSB ones) whereas all 390 * the others have a registers layout with MSB located before the 391 * LSB regs. 392 */ 393 if (stmpe->partnum == STMPE1600) 394 statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_LSB]; 395 else 396 statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_MSB]; 397 398 ret = stmpe_block_read(stmpe, statmsbreg, num_banks, status); 399 if (ret < 0) 400 return IRQ_NONE; 401 402 for (i = 0; i < num_banks; i++) { 403 int bank = (stmpe_gpio->stmpe->partnum == STMPE1600) ? i : 404 num_banks - i - 1; 405 unsigned int enabled = stmpe_gpio->regs[REG_IE][bank]; 406 unsigned int stat = status[i]; 407 408 stat &= enabled; 409 if (!stat) 410 continue; 411 412 while (stat) { 413 int bit = __ffs(stat); 414 int line = bank * 8 + bit; 415 int child_irq = irq_find_mapping(stmpe_gpio->chip.irq.domain, 416 line); 417 418 handle_nested_irq(child_irq); 419 stat &= ~BIT(bit); 420 } 421 422 /* 423 * interrupt status register write has no effect on 424 * 801/1801/1600, bits are cleared when read. 425 * Edge detect register is not present on 801/1600/1801 426 */ 427 if (stmpe->partnum != STMPE801 && stmpe->partnum != STMPE1600 && 428 stmpe->partnum != STMPE1801) { 429 stmpe_reg_write(stmpe, statmsbreg + i, status[i]); 430 stmpe_reg_write(stmpe, 431 stmpe->regs[STMPE_IDX_GPEDR_MSB] + i, 432 status[i]); 433 } 434 } 435 436 return IRQ_HANDLED; 437} 438 439static void stmpe_init_irq_valid_mask(struct gpio_chip *gc, 440 unsigned long *valid_mask, 441 unsigned int ngpios) 442{ 443 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc); 444 int i; 445 446 if (!stmpe_gpio->norequest_mask) 447 return; 448 449 /* Forbid unused lines to be mapped as IRQs */ 450 for (i = 0; i < sizeof(u32); i++) { 451 if (stmpe_gpio->norequest_mask & BIT(i)) 452 clear_bit(i, valid_mask); 453 } 454} 455 456static void stmpe_gpio_disable(void *stmpe) 457{ 458 stmpe_disable(stmpe, STMPE_BLOCK_GPIO); 459} 460 461static int stmpe_gpio_probe(struct platform_device *pdev) 462{ 463 struct stmpe *stmpe = dev_get_drvdata(pdev->dev.parent); 464 struct device_node *np = pdev->dev.of_node; 465 struct stmpe_gpio *stmpe_gpio; 466 int ret, irq; 467 468 if (stmpe->num_gpios > MAX_GPIOS) { 469 dev_err(&pdev->dev, "Need to increase maximum GPIO number\n"); 470 return -EINVAL; 471 } 472 473 stmpe_gpio = devm_kzalloc(&pdev->dev, sizeof(*stmpe_gpio), GFP_KERNEL); 474 if (!stmpe_gpio) 475 return -ENOMEM; 476 477 mutex_init(&stmpe_gpio->irq_lock); 478 479 stmpe_gpio->dev = &pdev->dev; 480 stmpe_gpio->stmpe = stmpe; 481 stmpe_gpio->chip = template_chip; 482 stmpe_gpio->chip.ngpio = stmpe->num_gpios; 483 stmpe_gpio->chip.parent = &pdev->dev; 484 stmpe_gpio->chip.base = -1; 485 486 if (IS_ENABLED(CONFIG_DEBUG_FS)) 487 stmpe_gpio->chip.dbg_show = stmpe_dbg_show; 488 489 of_property_read_u32(np, "st,norequest-mask", 490 &stmpe_gpio->norequest_mask); 491 492 irq = platform_get_irq(pdev, 0); 493 if (irq < 0) 494 dev_info(&pdev->dev, 495 "device configured in no-irq mode: " 496 "irqs are not available\n"); 497 498 ret = stmpe_enable(stmpe, STMPE_BLOCK_GPIO); 499 if (ret) 500 return ret; 501 502 ret = devm_add_action_or_reset(&pdev->dev, stmpe_gpio_disable, stmpe); 503 if (ret) 504 return ret; 505 506 if (irq > 0) { 507 struct gpio_irq_chip *girq; 508 509 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, 510 stmpe_gpio_irq, IRQF_ONESHOT, 511 "stmpe-gpio", stmpe_gpio); 512 if (ret) { 513 dev_err(&pdev->dev, "unable to get irq: %d\n", ret); 514 return ret; 515 } 516 517 girq = &stmpe_gpio->chip.irq; 518 gpio_irq_chip_set_chip(girq, &stmpe_gpio_irq_chip); 519 /* This will let us handle the parent IRQ in the driver */ 520 girq->parent_handler = NULL; 521 girq->num_parents = 0; 522 girq->parents = NULL; 523 girq->default_type = IRQ_TYPE_NONE; 524 girq->handler = handle_simple_irq; 525 girq->threaded = true; 526 girq->init_valid_mask = stmpe_init_irq_valid_mask; 527 } 528 529 return devm_gpiochip_add_data(&pdev->dev, &stmpe_gpio->chip, stmpe_gpio); 530} 531 532static struct platform_driver stmpe_gpio_driver = { 533 .driver = { 534 .suppress_bind_attrs = true, 535 .name = "stmpe-gpio", 536 }, 537 .probe = stmpe_gpio_probe, 538}; 539 540static int __init stmpe_gpio_init(void) 541{ 542 return platform_driver_register(&stmpe_gpio_driver); 543} 544subsys_initcall(stmpe_gpio_init); 545